Trench schottky diode device and method of making the same
By setting a terminal trench group with gradually varying depth and width and a dielectric metal structure in the trench Schottky diode device, the problem of poor blocking capability under reverse bias is solved, and the reverse breakdown voltage is improved and the electric field distribution is optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES HUAJING MICROELECTRONICS
- Filing Date
- 2024-12-02
- Publication Date
- 2026-06-02
AI Technical Summary
Existing trench MOS Schottky diodes have poor blocking capability due to the barrier reduction effect caused by the image force under reverse bias. Furthermore, improving the breakdown voltage will increase reverse leakage current or sacrifice the forward turn-on voltage.
Design a trench Schottky diode device by setting several cell trenches and multiple terminal trench groups on a substrate, with the depth and width of the terminal trench groups gradually decreasing, and an interlayer dielectric layer covering the substrate and forming a barrier metal layer to adjust the electric field distribution.
Without affecting the forward conduction voltage and leakage current, the reverse breakdown voltage of the device is improved, the electric field distribution is optimized, and the blocking capability of the device is enhanced.
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Figure CN122138418A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a trench Schottky diode device and its fabrication method. Background Technology
[0002] Schottky diodes possess excellent high-frequency characteristics and low forward turn-on voltage, making them highly promising for applications in solar cells, switching power supplies, automobiles, and mobile phones. However, under reverse bias, the barrier reduction effect caused by image force results in poor blocking capability of planar Schottky diodes. To address this issue, trench MOS barrier Schottky diodes (TMBS) were developed. TMBS offer irreplaceable advantages in many fields due to their superior high-frequency characteristics and easily adjustable structural parameters.
[0003] Since the invention of the TMBS structure, many researchers have improved the performance of TMBS devices by modifying their structure or parameters. For example, improving the doping distribution in the active region can improve the breakdown voltage of the device, but this also leads to an increase in reverse leakage current. Another example is to reduce the reverse leakage current of the device by using stepped trenches, but this sacrifices the effective area of the source region and the low forward turn-on voltage (VF) characteristic disappears. Summary of the Invention
[0004] One of the objectives of this invention is to provide a trench Schottky diode device and its fabrication method, which can improve the reverse breakdown voltage of the device without affecting the forward conduction voltage and leakage current.
[0005] To achieve the above objectives, the present invention provides a trench Schottky diode device. The trench Schottky diode device includes a substrate, an interlayer dielectric layer, and a barrier metal layer. The substrate comprises a plurality of cell trenches and a plurality of terminal trench groups disposed outside the plurality of cell trenches; one terminal trench group includes one or more terminal trenches; the terminal trenches within the same terminal trench group are uniformly arranged and have the same trench depth and width; the terminal trenches in different terminal trench groups do not all have the same depth; the interlayer dielectric layer covers the top surface of the substrate and has a contact opening, the contact opening exposing the top surfaces of the plurality of cell trenches and a portion of the top surfaces of the plurality of terminal trench groups; the barrier metal layer is located on the interlayer dielectric layer, covering the bottom surface and sidewalls of the contact opening and a portion of the top surface of the interlayer dielectric layer, and the barrier metal layer forms a Schottky contact with the substrate.
[0006] Optionally, the plurality of cell grooves are evenly arranged, and the width and depth of the grooves are equal.
[0007] Optionally, from the inside out, the width and depth of each terminal trench group gradually decrease, while the trench spacing gradually increases.
[0008] Optionally, the terminal groove group closest to the cell groove is the first terminal groove group; the first terminal groove group surrounds the plurality of cell grooves, and the groove width and depth of the first terminal groove group are consistent with the groove width and depth of the cell grooves, and the contact opening exposes part of the top surface of the first terminal groove group.
[0009] Optionally, the terminal groove can be continuous or discontinuous; the groove shape of the terminal groove can be strip-shaped, circular, or polygonal.
[0010] Optionally, the terminal trench and cell trench include a trench, a gate oxide layer covering the interior of the trench, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench.
[0011] Optionally, the trench Schottky diode device further includes an anode metal layer and a cathode metal layer; the anode metal layer is located on and covers the barrier metal layer; the cathode metal layer is located on the bottom surface of the substrate and covers the bottom surface of the substrate.
[0012] The present invention also provides a method for fabricating a trench Schottky diode device. The method for fabricating the trench Schottky diode device includes: providing a substrate; forming a plurality of cell trenches and a plurality of terminal trench groups disposed outside the plurality of cell trenches on the top of the substrate, wherein each terminal trench group includes one or more terminal trenches, the terminal trenches within the same terminal trench group are uniformly arranged, and the trenches have the same depth and width, while the terminal trenches in different terminal trench groups do not all have the same depth; forming an interlayer dielectric layer on the top surface of the substrate, the interlayer dielectric layer having contact openings, the contact openings exposing the top surfaces of the plurality of cell trenches and a portion of the top surfaces of the plurality of terminal trench groups; and forming a barrier metal layer on the interlayer dielectric layer, the barrier metal layer covering the bottom surface and sidewalls of the contact openings and at least covering a portion of the top surface of the interlayer dielectric layer, the barrier metal layer forming a Schottky contact with the substrate.
[0013] Optionally, forming a plurality of cell trenches on the top of the substrate and a plurality of terminal trench groups disposed outside the plurality of cell trenches includes: forming a patterned mask layer on the top surface of the substrate, and etching the substrate under the mask layer of the patterned mask layer to simultaneously form the plurality of cell trenches and the plurality of terminal trench groups, wherein the plurality of cell trenches have equal width and equal depth, and from the inside to the outside, the trench depth of each terminal trench group gradually decreases, the trench width gradually decreases, and the trench spacing gradually increases.
[0014] Optionally, the formation of a plurality of cell trenches on the top of the substrate and a plurality of terminal trench groups disposed outside the plurality of cell trenches includes: each of the terminal trench groups is formed by etching a separate mask layer.
[0015] Optionally, the terminal groove group closest to the cell groove is the first terminal groove group; the first terminal groove group surrounds the plurality of cell grooves, and the groove width and depth of the first terminal groove group are consistent with the groove width and depth of the cell grooves, and the contact opening exposes part of the top surface of the first terminal groove group.
[0016] Optionally, the method for fabricating the trench Schottky diode device further includes: after forming a plurality of cell trenches and a plurality of terminal trench groups disposed outside the plurality of cell trenches on the top of the substrate, and before forming an interlayer dielectric layer on the top surface of the substrate, forming a gate oxide layer covering the interior of the trenches and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trenches within the plurality of cell trenches and the plurality of terminal trench groups.
[0017] Optionally, the method for fabricating the trench Schottky diode device further includes: after forming a barrier metal layer on the interlayer dielectric layer, performing heat treatment, and within the contact opening, diffusing the metal in the barrier metal layer to the surface of the substrate to form a barrier alloy layer; forming an anode metal layer on the barrier metal layer, the anode metal layer covering the barrier metal layer; and forming a cathode metal layer on the bottom surface of the substrate, the cathode metal layer covering the bottom surface of the substrate.
[0018] The trench Schottky diode device and its fabrication method provided by this invention include a substrate comprising a plurality of cell trenches and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches; a terminal trench group includes one or more terminal trenches; the terminal trenches of the same terminal trench group are uniformly arranged and have the same trench depth and width; the terminal trenches of different terminal trench groups have different depths; an interlayer dielectric layer covers the top surface of the substrate and has a contact opening, the contact opening exposing the top surface of the plurality of cell trenches and part of the top surface of the plurality of terminal trench groups; a barrier metal layer is located on the interlayer dielectric layer, covering the bottom surface and sidewalls of the contact opening and part of the top surface of the interlayer dielectric layer, and the barrier metal layer forms a Schottky contact with the substrate. By setting multiple terminal trench groups with different depths, the electric field coupling effect at different positions of the terminal trenches can be effectively adjusted, thereby effectively adjusting the electric field strength and electric field distribution at different positions of the terminal trenches, and thus improving the reverse breakdown voltage of the device without affecting the forward conduction voltage and leakage current of the device. Attached Figure Description
[0019] Figure 1This is a cross-sectional schematic diagram of a trench Schottky diode device provided in an embodiment of the present invention.
[0020] Figure 2 This is a partial top view of a trench Schottky diode device provided in an embodiment of the present invention.
[0021] Figure 3 A partial top view of a trench Schottky diode device provided in another embodiment of the present invention.
[0022] Figure 4 This is a flowchart illustrating a method for fabricating a trench Schottky diode device according to an embodiment of the present invention.
[0023] Figures 5 to 10 This is a step-by-step structural diagram of a method for fabricating a trench Schottky diode device according to an embodiment of the present invention.
[0024] Figure 11 The electric field distribution diagram of the reverse breakdown of the trench Schottky diode device provided in an embodiment of the present invention is shown in the Sdevice simulation.
[0025] Explanation of reference numerals in the attached figures: 100-substrate; 101-substrate; 102-epitaxy layer; 100a-first region; 100b-second region; 201-cell trench; 202-first gate oxide layer; 203-first polysilicon filling layer; 300a-first terminal trench group; 300b-second terminal trench group; 300c-third terminal trench group; 300d-fourth terminal trench group; 300e-fifth terminal trench group; 301-terminal trench; 302-second gate oxide layer; 303-second polysilicon filling layer; 401-interlayer dielectric layer; 401a-contact opening; 402-barrier metal layer; 403-barrier alloy layer; 404-anode metal layer; 404a-anode metal material layer; 405-cathode metal layer. Detailed Implementation
[0026] In order to improve the reverse breakdown voltage of a trench Schottky diode without affecting its forward conduction voltage and leakage current, the present invention provides a trench Schottky diode device.
[0027] In the trench Schottky diode device, the substrate includes a plurality of cell trenches and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches; a terminal trench group includes one or more terminal trenches; the terminal trenches in the same terminal trench group are evenly arranged and have the same trench depth and width; the terminal trenches in different terminal trench groups do not all have the same depth; the interlayer dielectric layer covers the top surface of the substrate and has a contact opening, the contact opening exposing the top surface of the plurality of cell trenches and part of the top surface of the plurality of terminal trench groups; the barrier metal layer is located on the interlayer dielectric layer, covering the bottom surface and sidewalls of the contact opening and covering part of the top surface of the interlayer dielectric layer, and the barrier metal layer forms a Schottky contact with the substrate.
[0028] Corresponding to the trench Schottky diode device, the present invention also provides a method for manufacturing a trench Schottky diode device, which can manufacture the trench Schottky diode device described above.
[0029] The trench Schottky diode device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0030] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0031] Figure 1 This is a cross-sectional schematic diagram of a trench Schottky diode device provided in an embodiment of the present invention. Figure 2 This is a partial top view of a trench Schottky diode device provided in an embodiment of the present invention. Figure 3 A partial top view of a trench Schottky diode device provided in another embodiment of the present invention.
[0032] refer to Figures 1 to 3As shown, the trench Schottky diode device provided in this application includes a substrate 100, an interlayer dielectric layer 401, and a barrier metal layer 402.
[0033] The substrate 100 includes a plurality of cell trenches 201 and multiple terminal trench groups disposed on the outer side of the plurality of cell trenches 201; a terminal trench group includes one or more terminal trenches 301; the terminal trenches 301 in the same terminal trench group are uniformly arranged and have the same trench depth and width; the depths of the terminal trenches 301 in different terminal trench groups are not all the same. This arrangement of multiple terminal trench groups with varying depths can effectively adjust the electric field coupling at different positions of the terminal trenches 301, thereby effectively adjusting the electric field strength and electric field distribution at different positions of the terminal trenches, and thus improving the reverse breakdown voltage of the device without affecting the forward conduction voltage and leakage current.
[0034] In one embodiment, such as Figure 1 As shown, substrate 100 may include a substrate 101 and an epitaxial layer 102 located on substrate 101. The material of substrate 101 may include silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc. The material of epitaxial layer 102 includes, but is not limited to, silicon. Exemplarily, substrate 101 may be an N+ semiconductor substrate, and epitaxial layer 102 may be an N- epitaxial layer. In other embodiments, substrate 100 may consist only of a semiconductor substrate.
[0035] In this embodiment, both the cell trench 201 and the terminal trench 301 are formed in the epitaxial layer 102. The number of cell trenches 301 in the substrate 100 can be two or more, but is not limited to this.
[0036] For example, the substrate 100 may include a first region 100a and a second region 100b, a plurality of cell trenches 201 are formed in the first region 100a, a plurality of terminal trenches 301 are formed in the second region 100b, and the second region 100b surrounds the first region 100a.
[0037] In the embodiments of this application, both the terminal trench 301 and the cell trench 201 include a trench, a gate oxide layer covering the interior of the trench, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench. Specifically, refer to... Figure 1 As shown, the cell trench 201 has a first gate oxide layer 202 covering the inner surface of the cell trench 201 and a first polysilicon filling layer 203 located on the first gate oxide layer 202 and filling the cell trench 201; the terminal trench 301 has a second gate oxide layer 302 covering the inner surface of the terminal trench 301 and a second polysilicon filling layer 303 located on the second gate oxide layer 302 and filling the terminal trench 301.
[0038] For example, the first gate oxide layer 202 and the second gate oxide layer 302 can be made of the same material and can be formed in the same process. The materials of the first gate oxide layer 202 and the second gate oxide layer 302 include, but are not limited to, silicon oxide. The first polysilicon filling layer 203 and the second polysilicon filling layer 303 can be made of the same material and can be formed in the same process step.
[0039] In this embodiment, the thickness of the first gate oxide layer 202 and the second gate oxide layer 302 can both be greater than or equal to 100 nm and less than or equal to 200 nm. This way, the device surface electric field will not be too high due to the gate oxide layer being too thick, making it difficult to suppress leakage current, and the reverse withstand voltage will not be insufficient due to the gate oxide layer being too thin.
[0040] For example, the multiple cell trenches 201 have equal widths and equal depths, and are evenly arranged, meaning the spacing between adjacent cell trenches 201 is equal. It should be noted that "width" in this specification refers to... Figure 1 The dimension in the X direction, "depth" is Figure 1 The dimension in the Y direction.
[0041] For example, the width of the cell trench 201 can be greater than or equal to 0.5 μm and less than or equal to 2 μm, but is not limited thereto. The depth of the cell trench 201 can be greater than or equal to 1 μm and less than or equal to 3 μm, but is not limited thereto.
[0042] For example, such as Figure 2 and Figure 3 As shown, the multiple cell grooves 201 can all be strip-shaped grooves, and the multiple cell grooves 201 can extend parallel to the top surface of the substrate 100, for example, the cell grooves 201 can extend in the Z direction.
[0043] like Figure 3 As shown, multiple terminal trench groups are arranged sequentially around multiple cell trenches 201 from the inside out, that is, multiple terminal trench groups surround multiple cell trenches 201 on the inner side.
[0044] Specifically, a terminal trench group may include a continuous terminal trench 301, or a group of terminal trenches may include multiple non-continuous terminal trenches 301, with the multiple terminal trenches 301 in the same group arranged around multiple cell trenches 201. Among the multiple terminal trench groups, the terminal trench group closer to the cell trench 201 may include continuous terminal trenches 301, while the terminal trench group farther from the cell trench 201 may include multiple non-continuous terminal trenches.
[0045] For example, refer to Figure 1 and Figure 3 As shown, the terminal trench group closest to cell trench 201 among the multiple terminal trench groups is the first terminal trench group 300a. For example... Figure 3 As shown, multiple terminal trench groups include a first terminal trench group 300a, a second terminal trench group 300b, a third terminal trench group 300c, a fourth terminal trench group 300d, and a fifth terminal trench group 300e arranged in sequence from the inside to the outside. The first terminal trench group 300a, the second terminal trench group 300b, and the third terminal trench group 300c all include continuous annular terminal trenches. The fourth terminal trench group 300d and the fifth terminal trench group 300e include multiple discontinuous terminal trenches, but are not limited thereto.
[0046] Exemplarily, referring to Figure 2 as shown, the opening shape of the terminal trench 301 can be strip-shaped, polygonal, circular, or the like.
[0047] Referring to Figure 1 as shown, the trench width of the terminal trench 301 in the first terminal trench group 300a can be equal to the trench width of the cell trench 201, and the trench depth of the terminal trench 301 corresponding to the first terminal trench group 300a can be equal to the trench depth of the cell trench 201.
[0048] Referring to Figure 1 and Figure 2 as shown, from the inside to the outside (i.e., in the direction from the cell trench 201 to the terminal trench 301), the trench width of each terminal trench group gradually decreases, and the trench depth gradually decreases. For example, W1>W2>W3. The trench spacing between adjacent two terminal trench groups can gradually increase. For example, D1<D2<D3. In this way, the electric field strength and electric field distribution at different positions of the terminal trench can be adjusted more effectively.
[0049] Exemplarily, from the inside to the outside, the pitch increment of each terminal trench group can be greater than or equal to 0.1 μm and less than or equal to 0.3 μm. The decrement of the width and depth of the terminal trench 301 can be determined according to the position of the terminal trench 301 and the depth to be achieved, and it can not be a fixed value.
[0050] Exemplarily, for the terminal trench group including multiple discontinuous terminal trenches 301, the widths and depths of the multiple terminal trenches 301 are equal, the spacing between every two adjacent terminal trenches 301 is equal, and the spacing between adjacent two terminal trenches 301 is less than or equal to the width of the terminal trench 301.
[0051] Referring to Figure 1 as shown, the interlayer dielectric layer 401 is located on the top surface of the substrate 100 and has a contact opening 401a. The contact opening 401a exposes the top surfaces of all cell trenches 201 and part of the top surfaces of multiple groups of terminal trenches.
[0052] Specifically, the contact opening 401a can expose a portion of the top surface of the first terminal trench group 300a near the cell trench 201 and cover another portion of the top surface of the first terminal trench group 300a away from the cell structure, as well as cover the top surface of the remaining terminal trench group.
[0053] For example, the material of the interlayer dielectric layer 401 may include silicon dioxide or other high dielectric constant materials, and the interlayer dielectric layer 401 may also be a composite oxide layer.
[0054] like Figure 1 As shown, the barrier metal layer 402 is located on the interlayer dielectric layer 401, covering the bottom surface and sidewalls of the contact opening 401a and part of the top surface of the interlayer dielectric layer 401. The barrier metal layer 402 forms a Schottky contact with the substrate 100.
[0055] For example, the material of the barrier metal layer 402 includes, but is not limited to, titanium, platinum or molybdenum, to ensure good Schottky properties.
[0056] refer to Figure 1 As shown, the trench Schottky diode device may further include a barrier alloy layer 403, which is located between the barrier metal layer 402 and the substrate 100 and in the region where the contact opening 401a is located. The barrier alloy layer 403 is formed in the contact interface between the barrier metal layer 402 and the substrate 100.
[0057] For example, the barrier alloy layer 403 is an alloy of the metal in the barrier metal layer 402 and the substrate 100. For instance, the barrier metal layer 402 is a titanium layer, the substrate 100 is made of silicon, and the barrier alloy layer 403 is an alloy of titanium and silicon.
[0058] like Figure 1 As shown, the trench Schottky diode device may further include an anode metal layer 404 and a cathode metal layer 405.
[0059] The anode metal layer 404 is located on and covers the barrier metal layer 402. In this embodiment, the sidewalls of the anode metal layer 404 and the barrier metal layer 402 can be aligned, and a portion of the interlayer dielectric layer 401 can extend from under the sidewalls of the anode metal layer 404 and the barrier metal layer 402, that is, the interlayer dielectric layer 401 is not covered by the anode metal layer 404 and the barrier metal layer 402.
[0060] For example, the material of the anode metal layer 404 includes, but is not limited to, Ag, Al or Cu.
[0061] refer to Figure 1As shown, the cathode metal layer 405 is located on the bottom surface of the substrate 100 and covers the bottom surface of the substrate 100. Specifically, the cathode metal layer 405 covers the surface of the substrate 101 in the substrate 100 that is away from the epitaxial layer 102.
[0062] Figure 11 This is an electric field distribution diagram of a trench Schottky diode device under reverse breakdown in Sdevice simulation, provided as an embodiment of the present invention. Figure 11 As shown, the trench Schottky diode device of this application has a relatively uniform electric field distribution during reverse breakdown, which indicates that by setting multiple terminal trench groups with different depths, the electric field distribution of the terminal trenches can be optimized, effectively improving the problem of electric field concentration at the terminal.
[0063] Table 1 is a comparison table of Sdevice simulation DC parameters of traditional trench Schottky diodes and trench Schottky diodes of the present invention.
[0064] Table 1
[0065]
[0066] As shown in Table 1, the reverse breakdown voltage of a conventional trench Schottky diode is 55.8V, the reverse leakage current is 29.4μA, and the forward voltage drop is 459.6mV. The trench Schottky diode device of the present invention has a reverse breakdown voltage of 58.3V, a reverse leakage current of 29.5μA, and a forward voltage drop of 459.8mV. The trench Schottky diode device of the present invention improves the reverse breakdown voltage almost without affecting the reverse leakage current and forward voltage drop.
[0067] This application also provides a method for fabricating a trench Schottky diode device, which can be fabricated using the method described above, but is not limited thereto.
[0068] Figure 4 This is a flowchart illustrating a method for fabricating a trench Schottky diode device according to an embodiment of the present invention. Figure 4 As shown, the method for fabricating the trench Schottky diode device provided in this application includes:
[0069] Step S1, provide the substrate;
[0070] Step S2: A plurality of cell trenches and a plurality of terminal trench groups are formed on the top of the substrate; a terminal trench group includes one or more terminal trenches; the terminal trenches in the same terminal trench group are evenly arranged and have the same trench depth and width; the terminal trenches in different terminal trench groups do not all have the same depth.
[0071] Step S3: An interlayer dielectric layer is formed on the top surface of the substrate. The interlayer dielectric layer has contact openings that expose the top surfaces of the plurality of cell trenches and a portion of the top surfaces of the plurality of terminal trench groups; and
[0072] Step S4: A barrier metal layer is formed on the interlayer dielectric layer. The barrier metal layer covers the bottom surface and sidewalls of the contact opening and part of the top surface of the interlayer dielectric layer. The barrier metal layer forms a Schottky contact with the substrate.
[0073] Figures 5 to 10 This is a step-by-step structural diagram illustrating a method for fabricating a trench Schottky diode device according to an embodiment of the present invention. The following is in conjunction with... Figure 4 , Figures 5 to 10 The fabrication method of the trench Schottky diode device of this application is described.
[0074] refer to Figure 5 As shown, the substrate 100 provided in step S1 may include a substrate 101 and an epitaxial layer 102 formed on the substrate 101, but is not limited thereto. For example, the substrate 101 may be an N+ semiconductor substrate, and the epitaxial layer 102 may be an N- epitaxial layer. The material of the substrate 101 may include silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc. The material of the epitaxial layer 102 includes, but is not limited to, silicon.
[0075] Continue to refer to Figure 5 As shown, in step S2, a plurality of cell trenches 201 and a plurality of terminal trench groups are formed on the top of the substrate 100. A terminal trench group includes one or more terminal trenches 301. The terminal trenches 301 in the same terminal trench group are evenly arranged and have the same trench depth and width. The depth of the terminal trenches in different terminal trench groups is not the same.
[0076] In this embodiment, the plurality of cell trenches 201 includes, but is not limited to, two or more cell trenches 201. Each terminal trench group surrounds the plurality of cell trenches 201 and the terminal trench group inside it. In the direction from the inside to the outside (i.e., from the center of the plurality of cell trenches 201 to the direction away from the plurality of cell trenches 201), the trench depth of the plurality of terminal trench groups gradually decreases.
[0077] In one embodiment, a method for forming a plurality of cell trenches 201 and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches 201 on the top of a substrate 100 may include: forming a patterned mask layer (not shown in the figure) on the top surface of the substrate 100; under the masking of the patterned mask layer, etching the substrate 100 to simultaneously form a plurality of cell trenches 201 and a plurality of terminal trench groups; wherein the plurality of cell trenches 201 have equal width and equal depth; and the trench width of each terminal trench group gradually decreases in the direction from the inside to the outside; and then the patterned mask layer is removed. It should be noted that, since the trench width of the plurality of terminal trench groups is set to gradually decrease in the direction from the inside to the outside, when etching the substrate 100 using the same patterned mask layer, the depth of the formed plurality of terminal trench groups can gradually decrease, thus forming multiple sets of terminal trenches 301 with high efficiency and low cost. In this embodiment, the trench spacing of each of the terminal trench groups can be gradually increased by the pattern definition of the mask layer, but it is not limited to this.
[0078] In another embodiment, each terminal trench group can be formed by etching a separate mask layer. Specifically, a mask layer including a pattern of a terminal trench group is formed on the substrate 100. The substrate 100 is etched using this mask layer as a mask to form a terminal trench group, and then the mask layer is removed. The steps of forming the mask layer, etching the substrate, and removing the mask layer are repeated to form multiple terminal trench groups. When multiple terminal trench groups are formed in this way, the trench depth of each terminal trench group is not limited by the trench width and pattern size, but the cost is higher. In this embodiment, multiple terminal trench groups can be formed before or after forming multiple cellular trenches 201, or even after forming a portion of the terminal trenches 301, multiple cellular trenches 201 can be fabricated before continuing to fabricate terminal trenches 301.
[0079] refer to Figure 5 As shown, in this embodiment, multiple cell trenches 201 and multiple sets of terminal trenches 301 are formed in the epitaxial layer 102. In this application, a set of terminal trenches includes a continuous terminal trench; or, a set of terminal trenches includes multiple non-continuous terminal trenches 301, with the multiple terminal trenches 301 in the same set being evenly arranged and having the same trench depth and width.
[0080] Among the multiple terminal trench groups, the terminal trench groups closer to the multiple cell trenches 201 may include continuous annular terminal trenches, while the terminal trench groups farther away from the multiple cell trenches 201 may include multiple non-continuous terminal trenches.
[0081] For example, the terminal trench group closest to the cell trench 201 is the first terminal trench group; the first terminal trench group surrounds several cell trenches 201, and the trench width and depth of the first terminal trench group are consistent with the trench width and depth of the cell trenches 201. For example, the first terminal trench group 300a corresponds to a continuous annular terminal trench.
[0082] For example, for a terminal trench group including a plurality of non-continuous terminal trenches 301, the plurality of terminal trenches 301 have equal width and depth, the spacing between any two adjacent terminal trenches 301 is equal, and the spacing between any two adjacent terminal trenches 301 is less than or equal to the width of the terminal trenches 301.
[0083] After forming a plurality of cell trenches 201 and a plurality of terminal trench groups, a gate oxide layer covering the interior of the trench and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench are formed in the terminal trenches 301 of the plurality of cell trenches 201 and the plurality of terminal trench groups.
[0084] Specifically, a first gate oxide layer 202 is formed in multiple cell trenches 201 and a second gate oxide layer 302 is formed in multiple terminal trenches 301. The first gate oxide layer 202 covers the inner surface of the cell trenches 201 and the second gate oxide layer 302 covers the inner surface of the terminal trenches 301. The multiple cell trenches 201 are filled with a first polysilicon filling layer 203 and the multiple terminal trenches 301 are filled with a second polysilicon filling layer 303.
[0085] More specifically, the method for forming the first gate oxide layer 202, the second gate oxide layer 302, the first polysilicon filling layer 203, and the second polysilicon filling layer 303 may include: forming an oxide material layer on a substrate 100, the oxide material layer covering the top surface of the substrate 100, the inner surface of the cell trench 201, and the inner surface of the terminal trench 301; forming a polysilicon filling material layer on the substrate 100, the polysilicon filling material layer covering the oxide material layer and filling the cell trench 201 and the terminal trench 301; removing the polysilicon filling material layer and the oxide material layer on the top surface of the substrate 100 by a grinding or etching process, retaining the oxide material layer in the cell trench 201 and the terminal trench 301 as the first gate oxide layer 202 and the second gate oxide layer 302, and retaining the polysilicon filling material layer in the cell trench 201 and the terminal trench 301 as the first polysilicon filling layer 203 and the second polysilicon filling layer 303.
[0086] like Figure 7As shown, in step S3, an interlayer dielectric layer 401 is formed on the top surface of the substrate 100. The interlayer dielectric layer 401 has a contact opening 401a, which exposes the top surfaces of several cell trenches 201 and a portion of the top surfaces of multiple terminal trench groups. Specifically, the contact opening 401a may expose a portion of the top surface of the first terminal trench group 300a, and the interlayer dielectric layer 401 covers another portion of the top surface of the first terminal trench group 300a and the remaining terminal trench groups.
[0087] Specifically, an interlayer dielectric layer 401 covering the substrate 100 can be formed on the top surface of the substrate 100, and then part of the interlayer dielectric layer 401 can be etched away to form a contact opening 401a.
[0088] like Figure 8 As shown, in step S4, a barrier metal layer 402 is formed on the interlayer dielectric layer 401. The barrier metal layer 402 covers the bottom surface and sidewalls of the contact opening 401a and at least covers a portion of the top surface of the interlayer dielectric layer 401. The barrier metal layer 402 forms a Schottky contact with the substrate 100.
[0089] For details, please refer to Figure 8 As shown, in step S4, the barrier metal layer 402 can cover the interlayer dielectric layer 401.
[0090] After the formation of the barrier metal layer 402, as Figure 8 As shown, heat treatment can be performed so that the metal in the barrier metal layer 402 diffuses into the surface of the substrate 100 within the contact opening 401a to form a barrier alloy layer 403.
[0091] like Figure 9 As shown, an anode metal material layer 404a is formed on the barrier metal layer 402, the anode metal material layer 404a covering the barrier metal layer 402 and covering the substrate 100; as Figure 10 As shown, a portion of the anode metal material layer 404a is etched away to form an anode metal layer 404, and the barrier metal layer 402 exposed by the etched anode metal layer 404 is further etched away until a portion of the interlayer dielectric layer 401 is exposed. It should be noted that after etching the barrier metal layer 402, the barrier metal layer 402 covers the bottom surface and sidewalls of the contact opening 401a and a portion of the top surface of the interlayer dielectric layer 401, while the anode metal layer 404 covers the barrier metal layer 402.
[0092] like Figure 1 As shown, a cathode metal layer 405 is formed on the bottom surface of the substrate 100, and the cathode metal layer 405 covers the bottom surface of the substrate 100.
[0093] In the trench Schottky diode device and its fabrication method provided by the present invention, the substrate 100 includes a plurality of cell trenches 201 and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches 201; a terminal trench group includes one or more terminal trenches; the terminal trenches 301 of the same terminal trench group are uniformly arranged and have the same trench depth and width; the terminal trench depths of different terminal trench groups are not all the same; the interlayer dielectric layer 401 covers the top surface of the substrate 100 and has a contact opening 401a, the contact opening 401a exposing the top surface of the plurality of cell trenches 201 and the plurality of terminal trenches. The top surface of the terminal trench group; the barrier metal layer 402 is located on the interlayer dielectric layer 401, covering the bottom surface and sidewalls of the contact opening 401a and covering part of the top surface of the interlayer dielectric layer 401. The barrier metal layer 402 forms a Schottky contact with the substrate 100. By setting multiple terminal trench groups with different depths, the electric field coupling effect at different positions of the terminal trench can be effectively adjusted, thereby effectively adjusting the electric field strength and electric field distribution at different positions of the terminal trench. In this way, the reverse breakdown voltage of the device can be improved without affecting the forward conduction voltage and leakage current of the device.
[0094] It should be noted that this specification adopts a progressive approach. The fabrication methods of trench Schottky diode devices described later focus on the differences from those described earlier. For similarities and similarities between different parts, please refer to each other.
[0095] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A trench Schottky diode device, characterized in that, include: The substrate includes a plurality of cell trenches and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches; One of the terminal trench groups includes one or more terminal trenches; The terminal trenches of the same terminal trench group are evenly arranged, and the trench depth and width are consistent. The depth of the terminal trenches in different terminal trench groups is not the same; An interlayer dielectric layer covers the top surface of the substrate and has a contact opening that exposes part of the top surface of the plurality of cell trenches and the plurality of terminal trench groups. as well as A barrier metal layer, located on the interlayer dielectric layer, covers the bottom surface and sidewalls of the contact opening and a portion of the top surface of the interlayer dielectric layer, and the barrier metal layer forms a Schottky contact with the substrate.
2. The trench Schottky diode device as described in claim 1, characterized in that, The grooves of the cells are evenly arranged, and the width and depth of the grooves are equal.
3. The trench Schottky diode device as described in claim 1, characterized in that, From the inside out, the width and depth of each terminal trench group gradually decrease, while the trench spacing gradually increases.
4. The trench Schottky diode device as described in claim 3, characterized in that, The terminal groove group closest to the cell groove is the first terminal groove group; the first terminal groove group surrounds the plurality of cell grooves, and the groove width and depth of the first terminal groove group are consistent with the groove width and depth of the cell grooves, and the contact opening exposes part of the top surface of the first terminal groove group.
5. The trench Schottky diode device as described in claim 1, 2, or 3, characterized in that, The terminal trench can be continuous or discontinuous; the trench shape can be strip-shaped, circular, or polygonal.
6. The trench Schottky diode device as described in claim 1, 2, 3, or 4, characterized in that, The terminal trench and cell trench include a trench, a gate oxide layer covering the interior of the trench, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench.
7. The trench Schottky diode device as described in claim 1, characterized in that, It also includes an anode metal layer and a cathode metal layer; the anode metal layer is located on and covers the barrier metal layer; the cathode metal layer is located on the bottom surface of the substrate and covers the bottom surface of the substrate.
8. A method for fabricating a trench Schottky diode device, characterized in that, include: Provide a base; A plurality of cell trenches are formed on the top of the substrate and a plurality of terminal trench groups are disposed on the outside of the plurality of cell trenches. A terminal trench group includes one or more terminal trenches; the terminal trenches in the same terminal trench group are evenly arranged and have the same depth and width. The depth of the terminal trenches in different terminal trench groups is not the same; An interlayer dielectric layer is formed on the top surface of the substrate. The interlayer dielectric layer has contact openings that expose the top surfaces of the plurality of cell trenches and a portion of the top surfaces of the plurality of terminal trench groups. as well as A barrier metal layer is formed on the interlayer dielectric layer, the barrier metal layer covering the bottom surface and sidewalls of the contact opening and at least a portion of the top surface of the interlayer dielectric layer, the barrier metal layer forming a Schottky contact with the substrate.
9. The method for fabricating a trench Schottky diode device as described in claim 8, characterized in that, The method of forming a plurality of cell trenches on the top of the substrate and a plurality of terminal trench groups disposed on the outer side of the plurality of cell trenches includes: forming a patterned mask layer on the top surface of the substrate; under the masking of the patterned mask layer, etching the substrate to simultaneously form the plurality of cell trenches and the plurality of terminal trench groups, wherein the plurality of cell trenches have equal width and equal depth, and from the inside to the outside, the trench depth of each terminal trench group gradually decreases, the trench width gradually decreases, and the trench spacing gradually increases.
10. The method for fabricating a trench Schottky diode device as described in claim 8, characterized in that, The method of forming a plurality of cell trenches on the top of the substrate and a plurality of terminal trench groups disposed on the outside of the plurality of cell trenches includes: each of the terminal trench groups is formed by etching a separate mask layer.
11. The method for fabricating a trench Schottky diode device as described in claim 8, characterized in that, The terminal groove group closest to the cell groove is the first terminal groove group; the first terminal groove group surrounds the plurality of cell grooves, and the groove width and depth of the first terminal groove group are consistent with the groove width and depth of the cell grooves, and the contact opening exposes part of the top surface of the first terminal groove group.
12. The method for fabricating a trench Schottky diode device as described in claim 8, characterized in that, Also includes: After forming a plurality of cell trenches on the top of the substrate and a plurality of terminal trench groups disposed outside the plurality of cell trenches, and before forming an interlayer dielectric layer on the top surface of the substrate, a gate oxide layer covering the interior of the trenches and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trenches are formed within the plurality of cell trenches and the plurality of terminal trench groups.
13. The method for fabricating a trench Schottky diode device as described in claim 8, characterized in that, Also includes: After a barrier metal layer is formed on the interlayer dielectric layer, a heat treatment is performed, and the metal in the barrier metal layer diffuses to the surface of the substrate within the contact opening to form a barrier alloy layer. An anode metal layer is formed on the barrier metal layer, and the anode metal layer covers the barrier metal layer. as well as A cathode metal layer is formed on the bottom surface of the substrate, and the cathode metal layer covers the bottom surface of the substrate.