Silicon nanowire-based memristor device and method for producing thereof

Abstract

Disclosed is a memristor device (1) comprising two electrodes (3), each forming or including a Schottky diode (5) having a Schottky barrier, wherein the Schottky diodes are polarized in a back-to-back arrangement, and at least one silicon nanowire (4) connecting the two electrodes, wherein the silicon nanowire is provided with a superficial oxide layer (6). A corresponding fabrication process including an oxidation process for the Si nanowire(s) is also described.

Description

[0001] Description

[0002] Silicon nanowire-based memristor device and method for producing thereof

[0003] Technical field

[0004] The present invention relates to CMOS-compatible memristor devices having a silicon nanowire with improved characteristics. The invention further relates to a method for producing a memristor device using CMOS technology.

[0005] Technical background

[0006] Memristor devices are of increasing interest for different applications. Firstly, memristor devices can be used for a high-density implementation of memories as they exhibit a non-volatile physical state in a dipole arrangement. Due to the high-density storage and low costs, the non-volatile two-terminal memristor technology is a suitable candidate to replace flash memory technology.

[0007] Due to their potential for high connectivity and high density, memristor devices have been used to design cellular neural networks and frame synapses in neuromorphic circuits.

[0008] Furthermore, memristor devices based on silicon nanowires may be applied for biosensing by exploiting the memristive effect in nanoscale 1 D-structures.

[0009] Document A. Mehonic et al., ’’Intrinsic resistance switching in amorphous silicon oxide for high performance SiOx ReRAM devices”, Microelectronic Engineering 178 (2017) 98-103.] discloses a study of intrinsic bipolar resistance switching in metal-oxide-metal silicon oxide ReRAM devices. This paper identifies amorphous SiOx as a promising material for next-generation Resistive Random AccessMemory (ReRAM) devices due to its intrinsic resistance switching (RS) properties. SiOx provides reliable, non-volatile memory storage through RS behavior.

[0010] Document H. Zhou et al., “Design- dependent switching mechanisms of Schottky-barrier-modulated memristors based on 2d semiconductor”, Advanced Electronic Materials (2023) 2201252 discloses Schottky-barrier-modulated memristors based on 2D semiconductors and their potential for next-generation memory devices, with design-dependent switching mechanisms that enable tunable performance and low-power operation. A two-dimensional structure is introduced based on back- to-back Schottky diodes connected through a planar channel semiconductor. The resulting device exhibits both crossing and non-crossing hysteresis loops for varying voltage sweep, which are associated to volatile and non-volatile switching, respectively.

[0011] Document X. Wuet al., “ZnO single- nanowire schottky barrier resistive switching memory assembly with di- electrophoresis”, Journal of Electronic Materials 51 (2022), 7190-7197 discloses a combination of ZnO single nanowires (NWs) with Schottky barrier-based resistive switching for developing high-performance, low-power memory devices.

[0012] Furthermore, application of memristor devices in biosensing is disclosed in S. Carrara, “The birth of a new field: Memristive sensors, a review”, IEEE Sensors Journal 21 (2020) 12370-12378. In the context of biosensing, silicon nanowires (SiNWs) are of particular importance due to their significant aspect ratio and role as a Bio / CMOS interface. SiNW-based biosensors have demonstrated their efficacy in detecting a range of biomolecules, including DNA, proteins, and therapeutic compounds, such as shown in I. Tzouvadaki, N. Aliakbarinodehi, G. De Micheli, S. Carrara, “The memristive effect as a novelty in drug monitoring”, Nanoscale 9 (2017) 9676-9684.

[0013] The devices proposed in the art often lack CMOS compatibility, which limits their integration into existing semiconductor manufacturing processes. Moreover, the reported memristive behavior does not exhibit sufficient robustness, raising concerns about device reliability and reproducibility over extended use.It is an object of the present invention to provide a memristor device addressing key challenges in the field of memristor devices and biosensing. Firstly, the memristor device shall be compatible to CMOS technology making it suitable for integration into modern electronic systems and facilitating large-scale manufacturing. Further, particularly when applied for biosensing application, the detection sensitivity shall be improved by tuning the memristive characteristics of the memristor device to obtain a robust memristor behavior and to induce stable repeatable memristive switching.

[0014] Summary of the invention

[0015] The objectives have been solved by the memristor device according to claim 1 and the process for manufacturing a memristor device according to the further independent claim.

[0016] Further embodiments are indicated in the depending subclaims.

[0017] According to a first aspect, a memristor device is provided, comprising:

[0018] Two electrode bodies each forming or including a Schottky diode having a Schottky barrier, wherein the Schottky diodes are polarized in a back- to-back arrangement;

[0019] - At least one silicon nanowire connecting the two electrode bodies; wherein the silicon nanowire is provided with a superficial oxide layer.

[0020] The above memristor device is formed e.g. on a silicon on insulator substrate with a silicon nanowire arranged between two Schottky diodes which are back-to-back polarized, i.e. electrically serially connected with reversed polarities. The electrical connection of the two Schottky-diodes is made via the silicon nanowire. The silicon nanowire has been applied with a superficial oxide layer e.g. formed by natural oxidation or treated by an oxygen plasma treatment.The nanowire may have a length to width ratio of more than 10, particularly with a length between the electrode bodies of more than 1 m.

[0021] The oxide layer on the nanowire induces a stable and reproducible memristive behavior to the back-to-back Schottky diode arrangement. While the mere Schottky diode arrangement have a current-voltage characteristics with changing conductivities over the voltage applied, a memristive behavior is developed which exploits conductivity changes depending on the history of the electric current or voltage applied to the arrangement. Further, it has a non-volatile memory effect as the conductivity depends on its past electrical history. The memory effect is physically represented by a hysteresis loop in the current-voltage curve.

[0022] The development of the memristive behavior caused by the superficial oxide layer on the nanowire is surprising, as it is conventionally only known that a memristive behavior in a silicon nanowire arrangements can be produced by mechanisms like conductive filament formation or vacancy migration.

[0023] The introduction of superficial oxide appears to play a significant role in modulating the Schottky barrier, thereby enabling robust memristive switching. The provision of the superficial / surface oxide involves a passivation of the nanowire surface which provides a stable state against environmental influences thus improving robustness and providing reliable electrical characteristics.

[0024] Surface oxidation of the silicon nanowire can be achieved by natural oxidation or by means of an oxygen plasma treatment. Oxygen plasma treatment is commonly used to eliminate organic residuals and activate the silicon surface prior to biofunctionalization. During the treatment, the silicon nanowire undergoes substantial ion generation within its bulk region due to absorbed oxygen atoms. This results in the modification of the physical properties of the silicon nanowires so that in the memristor device with back-to-back Schottky diodes, memristive characteristics is achieved.

[0025] By means of the oxygen plasma treatment, the charge carrier concentration in the nanowire can be enhanced. Basically, the superficial oxidation of the siliconnanowire produces an apparent hysteresis having a repeatable volatile memristive characteristics.

[0026] The memristor device may be formed by means of two NiSix electrode bodies connected via the silicon nanowire. The Schottky diodes with their specific characteristics are formed between the NiSix electrodes and the silicon material of the silicon nanowire, thereby defining the Schottky barrier of the Schottky diode.

[0027] According to a further embodiment, the electrode bodies may comprise a silicon base integrally connected with the silicon nanowire, wherein the electrode bodies further have a metal layer separated from the silicon base by means of an intermediate oxide layer, thereby forming the Schottky barrier of the Schottky diode.

[0028] So, the Schottky diodes may be formed by a separated silicon base structure and a metal layer, such as made of nickel. The intermediate oxide layer may have a thickness of between 10 nm and 50 nm.

[0029] The effect of the provision of the intermediate oxide layer is the change of the Schottky barrier height between the metal layer and the silicon nanowire which alters the memristive characteristics of the memristor device. Particularly, the hysteresis loop, the positive voltage region is enlarged compared to the negative voltage region when starting with a voltage in the negative region. By providing the intermediate oxide layer, the Schottky barrier height of the metal silicon junction can be used to control the standard diode-like behavior, and also contributes to the fine modulation of the memristive switching.

[0030] While Schottky barriers in metal silicon interfaces are typically controlled by the choice of the metal material, it was found to be insufficient to produce consistent and controllable memristive switching. This can be overcome by inducing memristive behavior in the metal-silicon nanowire interface by applying an intermediate oxide layer modification which allows for dynamic control of the Schottky barrier. This results in a reliable, tunable switching mechanism without relying on material doping or filament formation. Thus, while Schottky barriers havebeen used for tuning current transport in semiconductor devices, the formation of the oxide layer provides an additional level of control over the switching process allowing for precise set and reset states and low-power operation.

[0031] According to a further aspect, the memristor device can be used for biosensors, as the surface of the silicon nanowire is activated by the oxygen plasma treatment and offers a large surface area for efficient biomolecule capture. By biomodifying the surface with charged molecules, the memristor device can accurately detect target molecules.

[0032] According to a further aspect, a method for manufacturing the memristor device is provided.

[0033] Basically, the process of manufacturing has a high compatibility with a CMOS process. The silicon nanowire and the nickel contacts used in the device are materials that can be integrated into the standard CMOS fabrication process making the memristor devices easy to scale and to integrate into existing semiconductor manufacturing lines. The quasi 1D structure of the silicon nanowires is highly scalable allowing for the production of high-density memory arrays and large-scale biosensor networks.

[0034] According to a further aspect, a method for producing a memristor device is provided, comprising the steps of:

[0035] forming electrode bodies on an insulating substrate of a silicon-on- insulator basis wherein the electrode bodies each forming (with the silicon nanowire) or including a Schottky diode having a Schottky barrier;

[0036] forming at least one silicon nanowire between the electrode bodies; performing an oxidation process on the silicon nanowires, particularly by means of an oxygen plasma treatment.

[0037] The electrode bodies are formed to be electrically connected merely via the silicon nanowire.Moreover, the step of forming electrode bodies may comprise to apply a metal layer, such as a Nickel layer, on a silicon base structure, wherein an intermediate oxide layer with a thickness of between 5 nm and 50 nm, is applied before the application of the metal layer.

[0038] Brief description of the drawings

[0039] Embodiments are described in more detail in conjunction with the accompanying drawings in which:

[0040] Figure 1 shows a cross-sectional view through a memristor device according to an embodiment of the present invention;

[0041] Figure 2 is an illustration of process steps for manufacturing the memristor device of Figure 1;

[0042] Figures 3a and 3b show the electrical behavior of the memristor device before oxygen plasma treatment.

[0043] Figures 4a and 4b show the electrical behavior of the memristor device after oxygen plasma treatment.

[0044] Figure 5 shows a cross-sectional view through a memristor device according to a further embodiment of the present invention; and

[0045] Figure 6 a diagram illustrating the electrical behavior of examples of a memristor device of Figure 5.Detailed description of embodiments

[0046] Figure 1 shows a cross-sectional view through a memristor device 1 according to the present invention. The memristor device 1 is being produced as illustrated in the process flow of Figure 2.

[0047] The memristor device 1 is formed on an SiO2 substrate 2 of a silicon-on-insulator basis with two spaced apart electrode bodies 3, e.g. formed as NiSix electrodes. A plurality of silicon nanowires 4 is arranged between the electrode bodies 3 and is spaced from the SiO2 substrate 2.

[0048] The silicon nanowire 4 has a length of between 0,5 and 3 pm, preferably about 1 to 1,5 pm and a width of between 50 nm and 300 nm, preferably 90 nm, The thickness may be between 50 nm and 200 nm. The nanowires 4 electrically interconnects the electrode bodies 3. Between each of the electrode bodies 3 and the silicon material of the silicon nanowire 4, Schottky diodes 5 are formed which are electrically polarized in a back-to-back configuration. So, when a voltage is applied, one of the Schottky diodes is operated in reverse mode.

[0049] The silicon nanowire 4 forms a quasi-one-dimensional structure. The large aspect ratio of the nanowires 4 is crucial to establish the diode-like structure ensuring that nanowires maintain a large surface for capture biomolecules when used in a biosensor application.

[0050] The mere back-to-back configuration of the Schottky diodes lead to a currentvoltage characteristics as e.g. shown in Figure 3a. It can be seen that the conductivity changes depending on the applied voltage. A substantial hysteresis is not present.

[0051] The silicon nanowire 4 is provided with a surface oxide layer 6. The surface oxide layer may have a thickness of between 1 and 50 nm.

[0052] A standard fabrication process for silicon nanowires begins in step S1 with a top-down, CMOS-compatible technique on a p-type silicon-on-insulator (SOI)substrate with a resistivity range 14-22 Qcm. The substrate basically consists of a thin silicon layer and a buried oxide layer, supported by a thicker silicon wafer.

[0053] To define the pattern for the electrodes, a layer of polymethyl methacrylate (PM MA) is precisely patterned in step S2 using Electron Beam Lithography (EBL) with windows at the locations of the electrode structures.

[0054] Subsequently in step S3, a 50 nm thick layer of Nickel (Ni) is evaporated onto the surface.

[0055] Then in step S4, the excess PMMA layer is removed with acetone, followed by ultrasonic rinsing for 20 minutes. Consequently, the patterned Ni remains on the substrate through the lift-off process.

[0056] The substrates, now carrying the patterned Ni layer, undergo an annealing step in an inert N2 ambient under varying annealing conditions in step S5. The default annealing condition for standard device is at 400 °C for 20 minutes. This annealing process initiates a reaction between Ni and silicon from the substrate, forming Schottky contacts.

[0057] Another Electron Beam Lithography (EBL) process is employed in step S6 using a patterned 100 nm thick layer of Hydrogen SilsesQuioxane (HSQ) as a negative resist to define the space between the electrode bodies. After exposure, the substrate is subjected to Deep Reactive Ion Etching (DRIE), also known as the ’’Bosch Process,” to create the silicon nanowires in the defined space between the electrode structures. This process involves alternating etching and passivation steps using SF6 (etching gas) and C4F8 (passivation gas) in a cyclic manner. As a result, stacked silicon nanowires 4 are formed and remain suspended between the electrode bodies.

[0058] Lastly in step S7, the HSQ resist is stripped in a solution comprising 1% HF for 1 minute. The application of 1% HF serves a dual purpose: it strips the HSQ resist and potentially eliminates oxide layers from the silicon nanowires surface.The so formed silicon nanowires 4 are oxidized in step S8 in a sufficient oxygen plasma atmosphere at 600 W for 15 minutes. On the other hand, Oxygen plasma treatment is also employed to eliminate the organic residuals and activate the silicon surface prior to biofunctionalization. During the oxygen plasma treatment, the silicon nanowires undergo substantial ions generation within its bulk region due to the absorbed oxygen atoms, resulting in the modification of the physical properties of the silicon nanowires. Thus, in real-time operation, high-power oxygen plasma treatment can enhance the charge-carrier concentration in the nanowire.

[0059] Considering the quasi-1 D nature of the device due to the extensive length of silicon nanowires, the impact of the oxygen plasma on bulk silicon is considerably more dominant than its effect on the Schottky contacts.

[0060] Before oxidation of the nanowires, the hysteresis is negligible as presented in current-voltage-diagram of Figure 3a and the corresponding semi-logarithmic curve in figure 3b.

[0061] After Oxygen plasma treatment, a very evident hysteresis comes out, as shown in the current-voltage-diagram of Figure 4a and the corresponding semi-logarithmic curve in figure 4b.

[0062] Figures 4a and 4b show a repeatable volatile memristive behavior within a 4 V voltage window, Figure 4b shows the same anti-clock wise pinched hysteresis which can also be obtained with a natural oxidation process of the silicon nanowires.

[0063] Furthermore, an abrupt resistance change occurs when the sweep starts at -4 V due to the injection of carriers due to the applied voltage as the memristive effect is possible only in the presence of the oxygen in the silicon nanowire. As the voltage increases toward +4V, the current eventually stabilizes at the saturation current I0, constrained by the Schottky contacts.As shown in the cross-sectional view of Figure 5, a memristor device 1 can also be applied with separate Schottky barriers between silicon structures of the silicon-on-insulator base and a metal (nickel) layer 7 applied thereon, as obtained after step S4 of above process. Between metal layer and the silicon structure, an intermediate oxide layer 8 can be applied after step S2, e.g. by sputtering, to modify the Schottky barrier height, thereby providing a further effect on the memristor characteristics.

[0064] The impact of the additional Schottky diodes is illustrated with respect to the diagram of figure 6, and demonstrates the effect of layers of silicon oxide with various thicknesses which were deposited onto the silicon structures of the silicon-on-lnsulator base before the deposition of the metal layer in step S3, The SiO2 layer can e.g. be sputtered with Pfeiffer- Vacuum SPIDER600 or deposited with Atom Layer Deposition Beneq TFS200, or evaporated with Leyhold-Optics LAB600H. in order to ensure the presence of an oxide layer between the Ni and Si. Three characteristics are shown corresponding to a thickness of the intermediate oxide layer of 0 nm, 10 nm, and 20 nm. In the absence of an oxide layer, the memristive behavior, represented by the curve K1 , resembles that shown in figure 4b. The curves K2 and K3 represent the cases of 10 nm and 20 nm oxide layers, respectively. The presence of the oxide layer alters the memristive behavior, notably enlarging the hysteresis loop in the positive voltage region compared to the negative voltage region

Claims

Claims1. Memristor device, comprising:Two electrode bodies each forming or including a Schottky diode having a Schottky barrier, wherein the Schottky diodes are polarized in a back- to-back arrangement;a silicon nanowire electrically connecting the two electrode bodies; wherein the silicon nanowire is provided with a superficial oxide layer.

2. Memristor device according to claim 1 , wherein the nanowire has a length to width ratio of more than 10, particularly with a length between the electrode bodies of more than 0,7, more than 1 pm or more than 1,5 pm, and / or wherein the thickness is particularly between 50 nm and 200 nm.

3. Memristor device according to any of the claims 1 to 2, wherein the superficial oxide layer is formed by natural oxidation or oxygen plasma treatment.

4. Memristor device according to any of the claims 1 to 3, wherein the memristor device is formed on a silicon on insulator substrate.

5. Memristor device according to any of the claims 1 to 4, wherein the electrode bodies comprise NiSix material which forms the Schottky barrier between the electrode bodies and the silicon material of the silicon nanowire.

6. Memristor device according to any of the claims 1 to 4, wherein the electrode bodies comprise a silicon base integrally connected with the silicon nanowire, wherein the electrode bodies further have a metal layer, particularly including Nickel, separated from the silicon base by means ofan intermediate oxide layer, thereby forming the Schottky barrier of the Schottky diode.

7. Memristor device according to claim 5, wherein the intermediate oxide layer has a thickness of between 5 and 50 nm.

8. Method for producing a memristor device, comprising the steps of:forming electrode bodies on an insulating substrate of a silicon-on- insulator basis;- forming at least one silicon nanowire between the electrode bodies;performing an oxidation process on the silicon nanowires, particularly by means of an oxygen plasma treatment.

9. Method according to claim 8, wherein the step of forming electrode bodies comprises to apply a metal layer, such as a Nickel layer, on a silicon base structure, wherein an intermediate oxide layer with a thickness of between 5 nm and 50 nm, is applied before the application of the metal layer.

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