Core-shell structure based knotless transistor and method of manufacturing the same

Abstract

This application provides a junctionless transistor based on a core-shell structure and a method for manufacturing the same, comprising: a substrate, a buried oxide layer, a core layer, a shell layer, a source, a drain, and a gate; the substrate, buried oxide layer, core layer, and shell layer are stacked sequentially, the source, drain, and gate are located on the surface of the shell layer away from the substrate, and the gate is disposed between the source and drain; the core layer has a target defect, which is used to deplete the carriers of the junctionless transistor when it is in the off state. That is, by introducing a target defect in the core layer, the target defect is used to further deplete the carriers when the junctionless transistor based on the core-shell structure is in the off state, thereby reducing the off-state current of the junctionless transistor based on the core-shell structure in the off state and improving the performance of the junctionless transistor based on the core-shell structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a junctionless transistor based on a core-shell structure and its manufacturing method. Background Technology

[0002] With the development of semiconductor-related technologies, core-shell junctionless transistors (CS-JLTs) combine the advantages of conventional junctionless transistors and conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), offering the following additional advantages: normal shutdown operation, high charge carrier mobility, and reduced impact of random doping fluctuations. Therefore, junctionless transistors based on core-shell structures are receiving increasing attention in modern integrated circuit design due to their simple structure, ease of manufacturing, and excellent performance.

[0003] Although junctionless transistors based on core-shell structures offer excellent performance, there are still challenges in reducing off-state current. In core-shell structures, the high carrier concentration in the core layer leads to higher off-state currents in the off state. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a junctionless transistor based on a core-shell structure and a method for manufacturing the same, which can reduce the off-state current of the junctionless transistor based on the core-shell structure in the off-state.

[0005] This application provides a junctionless transistor based on a core-shell structure, comprising:

[0006] The substrate and the buried oxide layer located on one side of the substrate surface;

[0007] A core layer located on the side of the buried oxide layer away from the substrate, the core layer having a target defect designed to deplete the carriers of the junctionless transistor when the junctionless transistor is in the off state;

[0008] A shell layer located on the side of the core layer away from the substrate;

[0009] The shell includes a source, a drain, and a gate, the source, drain, and gate being located on the side surface of the shell away from the substrate, and the gate being disposed between the source and the drain.

[0010] Optionally, the target defect is located on the side of the core layer near the buried oxide layer.

[0011] Optionally, the target defect is located on the side of the core layer near the shell layer.

[0012] Optionally, the target defects are evenly distributed at the location of the core layer.

[0013] Optionally, the concentration of the target defect is less than or equal to a concentration threshold.

[0014] Optionally, when the concentration of the target defect is less than or equal to a concentration threshold, the defect density of the target defect is directly proportional to the concentration of the target defect.

[0015] Optionally, the energy level of the target defect is set at the bottom of the conduction band, the midline of the band gap, or the top of the valence band of the core layer.

[0016] Optionally, the target defect includes acceptor defects and donor defects.

[0017] Optionally, the target defect is the donor defect, and the energy level of the target defect is set at the midline of the bandgap or the top of the valence band of the core layer.

[0018] This application provides a method for manufacturing a junctionless transistor based on a core-shell structure, the method comprising:

[0019] A buried oxide layer and a core layer are sequentially formed on a substrate, wherein the core layer is located on the surface of the buried oxide layer away from the substrate;

[0020] A target defect is introduced into the core layer, which is used to deplete the carriers of the junctionless transistor when the junctionless transistor is in the off state;

[0021] A shell layer is formed on the core layer, the shell layer being located on the side of the core layer away from the substrate;

[0022] A source, a drain, and a gate are formed, the source, drain, and gate being located on the side surface of the shell away from the substrate, and the gate being disposed between the source and the drain.

[0023] This application provides a junctionless transistor based on a core-shell structure, comprising: a substrate, a buried oxide layer, a core layer, a shell layer, a source, a drain, and a gate. The buried oxide layer is located on one side surface of the substrate, the core layer is located on the side surface of the buried oxide layer away from the substrate, the shell layer is located on the side surface of the core layer away from the substrate, the source, drain, and gate are located on the side surface of the shell layer away from the substrate, and the gate is disposed between the source and drain. That is, the substrate, buried oxide layer, core layer, shell layer, source, drain, and gate constitute a planar junctionless transistor based on a core-shell structure, realizing the main performance characteristics of a junctionless transistor based on a core-shell structure. The core layer has a target defect, which is used to deplete the carriers of the junctionless transistor when it is in the off state. In other words, by introducing a target defect in the core layer, the target defect is used to further deplete the carriers when the junctionless transistor based on the core-shell structure is in the off state, thereby reducing the off-state current of the junctionless transistor based on the core-shell structure in the off state and improving the performance of the junctionless transistor based on the core-shell structure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This illustration shows a schematic diagram of a junctionless transistor based on a core-shell structure according to an embodiment of this application.

[0026] Figure 2 This illustration shows a schematic diagram of another junctionless transistor based on a core-shell structure provided in an embodiment of this application.

[0027] Figure 3 This illustration shows a schematic diagram of another junctionless transistor based on a core-shell structure provided in an embodiment of this application;

[0028] Figure 4 This illustration shows a schematic diagram of the relationship between the concentration of different target defects and the defect density of the target defects when the energy level position is the middle of the band gap, according to an embodiment of this application.

[0029] Figure 5 This illustration shows a schematic diagram of energy level-defect density curves for different target defect concentrations provided in an embodiment of this application.

[0030] Figure 6 This illustration shows a schematic diagram of the energy level-defect density curves for another different target defect concentration provided in an embodiment of this application;

[0031] Figure 7 This illustration shows a schematic diagram of the energy level-defect density curves for another type of target defect concentration provided in an embodiment of this application;

[0032] Figure 8 This illustration shows a schematic diagram of the current-voltage curves of a junctionless transistor based on a core-shell structure at different defect concentrations, as provided in an embodiment of this application.

[0033] Figure 9 This illustration shows a flowchart of a method for manufacturing a shortwave infrared image sensor according to an embodiment of this application. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] While junctionless transistors based on core-shell structures offer excellent performance, reducing off-state current remains a challenge. Off-state current refers to the current flowing through the transistor when it is off (i.e., when the gate voltage is below the threshold voltage). Ideally, off-state current should be as low as possible to reduce power consumption and improve the transistor's on / off ratio. In other words, transistors should ideally have extremely low off-state current in the off-state to minimize power consumption.

[0038] However, in junctionless transistors based on core-shell structures, the high carrier concentration in the core layer results in a high off-state current during the off-state.

[0039] Based on this, this application provides a junctionless transistor based on a core-shell structure, comprising: a substrate, a buried oxide layer, a core layer, a shell layer, a source, a drain, and a gate; the buried oxide layer is located on one side surface of the substrate, the core layer is located on the side surface of the buried oxide layer away from the substrate, the shell layer is located on the side surface of the core layer away from the substrate, the source, drain, and gate are located on the side surface of the shell layer away from the substrate, and the gate is disposed between the source and drain. That is, the substrate, buried oxide layer, core layer, shell layer, source, drain, and gate constitute a planar junctionless transistor based on a core-shell structure, realizing the main performance of the junctionless transistor based on the core-shell structure; the core layer has a target defect, which is used to deplete the carriers of the junctionless transistor when it is in the off state. In other words, by introducing a target defect in the core layer, the target defect is used to further deplete the carriers when the junctionless transistor based on the core-shell structure is in the off state, thereby reducing the off-state current of the junctionless transistor based on the core-shell structure in the off state and improving the performance of the junctionless transistor based on the core-shell structure.

[0040] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0041] This application provides a junctionless transistor based on a core-shell structure. Its working principle will be described in detail below with reference to the accompanying drawings. See also... Figure 9 The figure is a schematic diagram of a junctionless transistor based on a core-shell structure provided in an embodiment of this application.

[0042] The junctionless transistor based on a core-shell structure provided in this application includes: a substrate 110, a dielectric 120, a core layer 130, a shell 140, a source 150, a drain 160, and a gate 170.

[0043] The substrate 110 can be a semiconductor substrate, such as a bulk silicon substrate, or it can be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0044] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are N-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a P-well, and the implanted impurities are P-type impurity ions, such as boron (B) ions.

[0045] The buried oxide layer (BOX) 120 is located on one side surface of the substrate 110, that is, the buried oxide layer 120 covers the substrate 110. The material of the buried oxide layer 120 can be silicon oxide (SiO2).

[0046] The core layer 130 is located on the side of the buried oxide layer 120 away from the substrate 110, that is, the core layer 130 covers the buried oxide layer 120, and the core layer 130 is a planar film layer.

[0047] The shell 140 is located on the side of the core layer 130 away from the substrate 110, that is, the shell 140 covers the core layer 130. The shell 140 is a planar film layer, which, together with the core layer 130 which is also a planar film layer, constitutes a planar junctionless transistor based on a core-shell structure.

[0048] The source 150, drain 160, and gate 170 are located on the surface of the shell 140 away from the substrate 110, i.e., the source 150, drain 160, and gate 170 are located on the shell 140. The gate 170 is disposed between the source 150 and the drain 160 so as to control the turn-on and turn-off of the transistor. The source 150, drain 160, and gate 170 can be made of metallic materials.

[0049] In other words, the substrate 110, buried oxide layer 120, core layer 130 and shell layer 140 are stacked sequentially. The substrate 110, buried oxide layer 120, core layer 130, shell layer 140, source 150, drain 160 and gate 170 constitute a planar junctionless transistor based on a core-shell structure, realizing the main performance of a junctionless transistor based on a core-shell structure.

[0050] The core layer 130 has a target defect 131, which is used to deplete the carriers of the junctionless transistor when it is in the off state. In other words, by introducing the target defect 131 into the core layer 130, the target defect 131 is used to further deplete the carriers when the junctionless transistor based on the core shell structure is in the off state, thereby reducing the off-state current of the junctionless transistor based on the core shell structure and improving the performance of the junctionless transistor based on the core shell structure.

[0051] The target defect 131 of the core layer 130 can be an additionally introduced defect or a defect passively introduced by the manufacturing process when manufacturing a junctionless transistor based on a core-shell structure.

[0052] In practical applications, a gate oxide layer 180 is provided between the gate 170 and the shell 140, and an isolation layer 190 is provided between the source 160 and the gate 170 and between the drain 150 and the gate 170, so as to use the isolation layer 190 to provide electrical isolation between the source 160 and the gate 170 and between the drain 150 and the gate 170.

[0053] As one possible implementation, the core layer 130 is a heavily doped film, and the shell layer 140 is an undoped film. During the on-state current, the carriers are mainly supplied by the core layer 130, thus requiring a high doping concentration in the core layer 130. However, during turn-off, the core layer 130 needs to be placed in a depleted state. But in junctionless transistors based on a core-shell structure, the core layer 130 is in a highly doped state, making depletion difficult. To address the challenge of reducing the off-state current, a proposed approach is to introduce a target defect 131 into the core layer 130 to further deplete the carriers during the off-state, thereby reducing the off-state current.

[0054] Junctionless transistors based on a core-shell structure achieve turn-off by depleting the carriers in the channel through the gate work function. Similarly, during turn-off, the electric field lines at the gate edge of a junctionless transistor based on a core-shell structure deplete part of the source and drain, thus exhibiting the same effective channel modulation effect as conventional junctionless transistors.

[0055] The working principle of a junctionless transistor based on a core-shell structure is to combine the dopant-dependent electrons in the heavily doped core layer 130 with the gate-induced electrons in the undoped shell layer 140. The gate 170 turns on the core layer 130 from a fully depleted state to a near-flat band state, and then activates the shell layer 140 like a regular MOSFET.

[0056] In the embodiments of this application, a target defect 131 is set in the core layer 130. The type of the target defect 131 will affect the performance of the junctionless transistor based on the core shell structure, which will be described in detail below.

[0057] Target defect 131 includes acceptor defects and donor defects, where acceptor defects act as positive charge centers to capture electrons, and donor defects act as negative charge centers to donate electrons. Which type of defect, acceptor or donor defect, is used as the introduced defect in a junctionless transistor based on a core-shell structure can be determined according to the specific circumstances.

[0058] In the embodiments of this application, a target defect 131 is set in the core layer 130. The location of the target defect 131 in the core layer 130 will affect the performance of the junctionless transistor based on the core shell structure, which will be described in detail below.

[0059] When a junctionless transistor based on a core-shell structure is in the off-state, the highly doped core layer 130 is not completely depleted. Carriers in the core layer 130 flow through the source 150-core layer 130-drain 160 path or enter the shell 140 through the source 150-shell 140-drain 160 path, forming a leakage current. Therefore, when a junctionless transistor based on a core-shell structure is in the off-state, carriers flow through the core layer 130 or enter the shell 140 from the core layer 130. Thus, introducing defects into the core layer 130 can significantly reduce the off-state current.

[0060] As one possible implementation, the target defect 131 can be located on the side of the core layer 130 near the shell layer 140, that is, the target defect 131 is located in the upper half of the core layer 130, as shown in the reference. Figure 2 As shown. When the target defect 131 is located in the core layer 130 near the interface with the shell layer 140, that is, when the target defect 131 is set in the upper half of the core layer 130, it can effectively block the carriers in the core layer 130 from entering the shell layer 140, thereby reducing the off-state current.

[0061] As another possible implementation, the target defect 131 can be located on the side of the core layer 130 near the buried oxide layer 120, that is, the target defect 131 is located in the lower half of the core layer 130, see reference. Figure 3 As shown. Considering that the core layer 130 is relatively thin in practical applications, placing the target defect 131 in the lower half of the core layer 130 can also achieve the depletion of charge carriers, thereby reducing the off-state current.

[0062] As can be seen from the above description, the location of the target defect 131 in the core layer 130 can be changed. The target defect 131 can be set in the entire core layer 130 which is relatively thin, or it can be set only in some areas, such as the upper half or the lower half of the core layer 130.

[0063] The target defects 131 are evenly distributed in the core layer 130, which can reduce the process difficulty of setting the target defects 131 in the core layer 130, thereby realizing the depletion of the carriers in the core layer 130 by using the evenly distributed target defects 121.

[0064] In the embodiments of this application, a target defect 131 is set in the core layer 130. The concentration of the target defect 131 in the core layer 130 will affect the performance of the junctionless transistor based on the core-shell structure, which will be described in detail below.

[0065] If the concentration of target defect 131 in the core layer 130 is too low, its depletion effect on carriers will be small. If the concentration of target defect 131 in the core layer 130 is too high, it may cause the performance of junctionless transistors based on the core-shell structure to degrade. Therefore, target defect 131 has a preset concentration range.

[0066] As one possible implementation, the concentration of the target defect 131 is less than or equal to a concentration threshold. For example, the concentration threshold could be 1.0E21.

[0067] As another possible implementation, the concentration of target defect 131 is greater than or equal to a minimum threshold. For example, the minimum threshold could be 6.0E18.

[0068] When the concentration of target defect 131 is less than or equal to the concentration threshold, the defect density of target defect 131 is directly proportional to the concentration of target defect 131. That is, the higher the concentration of target defect 131, the higher the defect density of target defect 131 in the core layer 130. Therefore, the defect density of target defect 131 in the core layer 130 can be controlled by controlling the concentration of target defect 131 in the core layer 130, thereby controlling the degree of carrier depletion and ultimately controlling the degree of decrease of the off-state current.

[0069] refer to Figure 4 As shown, Figure 4 The energy level-defect density curves for different concentrations of target defect 131 are illustrated. The horizontal axis of the energy level-defect density curve represents energy, and the vertical axis represents defect density. Figure 4 It can be seen that when the energy level of the target defect 131 is set near the band gap center line of the core layer 130, as the concentration of the target defect 131 increases, the defect density of the target defect 131 at the energy level near the band gap center line in the core layer 130 also increases.

[0070] In the embodiments of this application, a target defect 131 is set in the core layer 130. The energy level position of the target defect 131 in the core layer 130 will affect the performance of the junctionless transistor based on the core-shell structure, which will be described in detail below.

[0071] The energy level distribution of the target defect 131 can be set by combining the energy level distribution of the charge carriers and the energy level distribution of the core layer 130. As one possible approach, the energy level of the target defect 131 can be set near the bottom of the conduction band (Ec), near the midline of the band gap (Eg), or near the top of the valence band (Ev) of the core layer 130. For example, the energy level of the target defect 131 can be set at the bottom of the conduction band, the midline of the band gap, or the top of the valence band of the core layer 130.

[0072] refer to Figures 4-6 As shown, Figures 4-6The diagram illustrates the energy level-defect density curves for different concentrations of target defect 131 when its energy level is set near the midline of the band gap, near the bottom of the conduction band, and near the top of the valence band in the core layer 130. Figures 4-6 It can be seen that setting the energy level of the target defect 131 near the band gap center line, near the bottom of the conduction band, and near the top of the valence band of the core layer 130 can all have the effect of depleting carriers, that is, they can all reduce the off-state current.

[0073] When the target defect 131 is a donor defect, and its energy level is located at the midline of the bandgap or the top of the valence band in the core layer 130, it has a significant effect on reducing the off-state current. In other words, when the target defect 131 is introduced into the core layer 130, its introduction can be controlled by comprehensively considering its type, energy level location, concentration, and placement within the core layer 130. This allows for a reduction in off-state current without compromising the performance of junctionless transistors based on the core-shell structure.

[0074] In the embodiments of this application, junctionless transistors based on core-shell structures with different channel lengths (Lg) can all reduce off-state current after introducing the target defect 131. Here, channel length refers to the length of the gate 170 along the line connecting the source 150 and drain 160.

[0075] refer to Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 The current-voltage curves of junctionless transistors based on core-shell structures with different channel lengths are shown after the introduction of target defect 131. Figure 7 The current-voltage curves of a junctionless transistor with a core-shell structure and a channel length of 200 nm are shown at different concentrations of target defect 131. Figure 8 The current-voltage curves of a junctionless transistor with a core-shell structure and a channel length of 20 nm are illustrated under different concentrations of target defect 131. The horizontal axis of the current-voltage curve represents voltage (Vg), and the vertical axis represents current (Id). Figure 7 and Figure 8 The figure shows four current-voltage curves. The concentration of target defect 131 gradually increases in the four current-voltage curves, and the defect density of target defect 131 also increases accordingly.

[0076] Depend on Figure 7 and Figure 8 It can be observed that as the concentration of target defect 131 gradually increases, the off-state current of the junctionless transistor based on the core-shell structure also gradually decreases. (Reference) Figure 7As shown, in a junctionless transistor based on a core-shell structure with a channel length of 200 nm, the off-state current decreased by up to two orders of magnitude after introducing target defect 131 of four different acceptor types, while the on-state current decreased by only about 6.35%. (Reference) Figure 8 As shown, under the same conditions, in a junctionless transistor based on a core-shell structure with a channel length of 20 nm, the off-state current is reduced by up to two orders of magnitude, while the on-state current is reduced by only 3.92%. The results indicate that by setting the target defect 131 in the core layer 130, the off-state current can be significantly reduced without sacrificing the on-state current, thereby improving the energy efficiency ratio of the junctionless transistor based on the core-shell structure.

[0077] Based on the junctionless transistor with a core-shell structure provided in the above embodiments, this application also provides a method for manufacturing a junctionless transistor with a core-shell structure. Its working principle will be described in detail below with reference to the accompanying drawings. See also... Figure 9 The figure is a schematic flowchart of a method for manufacturing a junctionless transistor based on a core-shell structure according to an embodiment of this application.

[0078] The method for manufacturing junctionless transistors based on a core-shell structure provided in this embodiment includes the following steps:

[0079] S101, a buried oxide layer and a core layer are sequentially formed on the substrate.

[0080] In the embodiments of this application, the substrate may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0081] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate varies depending on the device type. For P-type semiconductor devices, the aforementioned highly doped well region is an N-well, and the implanted impurities are N-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the aforementioned highly doped well region is a P-well, and the implanted impurities are P-type impurity ions, such as boron (B) ions.

[0082] A buried oxide layer is formed on the substrate, and the buried oxide layer is located on one side surface of the substrate.

[0083] After the buried oxide layer is formed, a core layer is formed on the buried oxide layer, and the core layer is located on the side surface of the buried oxide layer away from the substrate.

[0084] S102 introduces the target defect in the core layer.

[0085] In embodiments of this application, a target defect may be introduced in the core layer to deplete the carriers of the junctionless transistor when the junctionless transistor is in the off state.

[0086] The target defect in the core layer can be an additional defect, such as a target defect introduced into the core layer by using a doping process, or a defect passively introduced by the manufacturing process when manufacturing a junctionless transistor based on a core-shell structure.

[0087] S103 forms a shell on the core layer.

[0088] In the embodiments of this application, after introducing a target defect into the core layer, a shell layer can be formed on the core layer, with the shell layer located on the side surface of the core layer away from the substrate.

[0089] One possible implementation involves a heavily doped core layer and an undoped shell layer. During the on-state current, the core layer primarily provides the charge carriers, thus requiring a high doping concentration. However, during turn-off, the core layer needs to be in a depleted state. But in junctionless transistors based on a core-shell structure, the core layer is heavily doped, making depletion difficult. To address this challenge in reducing off-state current, a proposed approach is to introduce targeted defects into the core layer to further deplete the charge carriers during the off-state, thereby reducing the off-state current.

[0090] S104 forms the source, drain, and gate.

[0091] In the embodiments of this application, a source, a drain, and a gate are formed on the shell layer, the source, drain, and gate are located on the side surface of the shell layer away from the substrate, and the gate is disposed between the source and the drain.

[0092] In the embodiments of this application, a gate oxide layer may be formed on the shell before the source, drain and gate are formed, and then the gate is formed on the gate oxide layer, that is, the gate oxide layer is disposed between the gate and the shell.

[0093] In embodiments of this application, an isolation layer may be formed between the source and the gate, and between the drain and the gate, to provide electrical isolation between the source and the gate, and between the drain and the gate.

[0094] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple; relevant parts can be referred to the description of the structural embodiments. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0095] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A junctionless transistor based on a core-shell structure, characterized in that, include: The substrate and the buried oxide layer located on one side of the substrate surface; A core layer located on the side of the buried oxide layer away from the substrate, the core layer having a target defect designed to deplete the carriers of the junctionless transistor when the junctionless transistor is in the off state; A shell layer located on the side of the core layer away from the substrate; The shell includes a source, a drain, and a gate, the source, drain, and gate being located on the side surface of the shell away from the substrate, and the gate being disposed between the source and the drain.

2. The transistor according to claim 1, characterized in that, The target defect is located on the side of the core layer near the buried oxide layer.

3. The transistor according to claim 1, characterized in that, The target defect is located on the side of the core layer near the shell layer.

4. The transistor according to claim 2 or 3, characterized in that, The target defects are evenly distributed at their locations in the core layer.

5. The transistor according to claim 1, characterized in that, The concentration of the target defect is less than or equal to the concentration threshold.

6. The transistor according to claim 5, characterized in that, When the concentration of the target defect is less than or equal to the concentration threshold, the defect density of the target defect is directly proportional to the concentration of the target defect.

7. The transistor according to claim 1, characterized in that, The energy level of the target defect is set at the bottom of the conduction band, the midline of the band gap, or the top of the valence band in the core layer.

8. The transistor according to claim 1, characterized in that, The target defects include acceptor defects and donor defects.

9. The transistor according to claim 8, characterized in that, The target defect is the donor defect, and the energy level of the target defect is set at the midline of the band gap or the top of the valence band of the core layer.

10. A method for manufacturing a junctionless transistor based on a core-shell structure, characterized in that, The method includes: A buried oxide layer and a core layer are sequentially formed on a substrate, wherein the core layer is located on the surface of the buried oxide layer away from the substrate; A target defect is introduced into the core layer, which is used to deplete the carriers of the junctionless transistor when the junctionless transistor is in the off state; A shell layer is formed on the core layer, the shell layer being located on the side of the core layer away from the substrate; A source, a drain, and a gate are formed, the source, drain, and gate being located on the side surface of the shell away from the substrate, and the gate being disposed between the source and the drain.

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