Electronic circuits and circuit elements

Abstract

A method for manufacturing an electronic circuit or circuit module including transistors and resistors. A first device includes a first terminal, a second terminal, and a first semiconductor material body providing a semiconductor path between the first and second terminals. A second device includes a third terminal, a fourth terminal, and a second material body providing a resistive or semiconductor current path between the third and fourth terminals. The method includes: forming the first body; and forming the second body, wherein the first body includes a first amount of metal oxide, and the second body includes a second amount of the metal oxide. A corresponding electronic circuit is disclosed.

Description

[0001] This application is a divisional application of Chinese patent application No. 202080073505.4, filed on August 19, 2020, entitled "Electronic Circuits and Circuit Elements". Technical Field

[0002] This invention relates to electronic circuits (specifically, but not exclusively, to flexible integrated circuits, i.e., flexible ICs), and components (i.e., elements) of such circuits. Some embodiments relate to electronic circuits integrating two or more of the following types of circuit elements: transistors; resistors; and Schottky diodes. Therefore, some embodiments of the invention relate to electronic circuits comprising at least one transistor and at least one resistor, and specifically, but not exclusively, to flexible integrated circuits comprising at least one transistor and at least one resistor. Some embodiments relate to electronic circuits (e.g., flexible ICs) comprising: at least one transistor and at least one Schottky diode; at least one resistor and at least one Schottky diode; and at least one transistor, at least one Schottky diode, and at least one resistor. Some embodiments relate to dual-gate transistors and electronic circuits including such transistors, such as circuits integrating such transistors with at least one Schottky diode and / or at least one resistor. Background Technology

[0003] Although flexible integrated circuits (FlexICs) are well-known, few technologies are capable of manufacturing low-cost FlexICs. Most FlexIC technologies have been developed for displays, rather than digital or analog processing, sensing, and communication. One of the most promising FlexIC technologies is based on thin-film transistors (TFTs) that incorporate metal-oxide-semiconductor semiconductors. The high transmittance of these devices has facilitated their development for displays, but currently commercially viable materials are all n-type semiconductors. This means that metal-oxide-based FlexIC architectures cannot incorporate the silicon-based circuit designs of the past 30 years, which are almost entirely based on complementary semiconductors (i.e., circuits containing both n-type and p-type transistors). These CMOS circuits achieve a level of integration, efficiency, and complexity that has been unattainable to date in any commercially available unipolar (n-type or p-type) technology. Certain aspects and embodiments of the present invention relate to the development of metal-oxide-based flexible ICs for low-cost applications in processing, sensing, communication, and other fields, thus requiring a different approach.

[0004] In the past, silicon-based unipolar integrated circuits (ICs) featured integrated resistors. However, these resistors typically had relatively low resistivity, at most ~50 kΩ / □ (50 kΩ per square ohm). This limited the range of resistors that were economically feasible (i.e., where the IC footprint was small enough). This limitation, in turn, drove the development of circuit architectures using diodes or transistor-loaded transistors, which, compared to contemporary bipolar transistor-based circuits, consumed more power and had slower switching speeds. Furthermore, these resistor technologies were only applicable to bulk crystalline semiconductors. Later IC processes employed thin-film metal or polycrystalline silicon-based resistors in a "back-of-line" (BEOL) layer above the active devices. However, the resistivity of these resistors was even lower, at most approximately 100 Ω / □ (100 Ohms per square ohm).

[0005] Schottky diodes are well-known electronic components that typically provide extremely fast switching between on and off states, making them particularly suitable for rectifying high-frequency signals. Schottky diodes are also widely known for their use in many other electronic applications and circuit configurations. WO 2019 / 116020A1 (the contents of which are incorporated herein by reference) discloses a variety of Schottky diodes suitable for thin and / or flexible electronic circuits that can be integrated into embodiments of the present invention. These Schottky diodes typically include: a first electrode; a second electrode; and a semiconductor material body (e.g., a layer) connected to the first electrode at a first interface (junction) and to the second electrode at a second interface (junction), wherein the first interface includes a first planar region located in a first plane, and the first electrode has a first projection on the first plane along a first direction orthogonal to the first plane; the second interface includes a second planar region located in a second plane, and the second electrode has a second projection on the first plane along the first direction, at least a portion of the second projection being outside the first projection; the second planar region is offset (separated, spaced) relative to the first planar region in the first direction; and one of the first and second interfaces provides a Schottky (rectifying) contact. However, certain embodiments of the invention may incorporate Schottky diodes with other configurations, such as purely lateral or purely longitudinal devices known in the art. Summary of the Invention

[0006] Some aspects and embodiments of the present invention are intended to solve at least one of the problems associated with the prior art. Furthermore, some aspects and embodiments of the present invention address the problem of how to integrate resistors and / or transistors and / or Schottky diodes in electronic circuits, specifically but not exclusively, where the electronic circuits are at least one of the following: capable of mass production; capable of low-cost manufacturing; flexible; transparent; and with a small footprint. Some aspects and embodiments of the present invention also aim to provide resistor geometries, techniques, materials, and methods of manufacturing them, compatible with the combination or integration of any one or more electronic circuits of the types described above. Furthermore, some aspects and embodiments of the present invention address the problem of how to manufacture circuits incorporating resistors, particularly flexible ICs, wherein the resistance of the resistor is within the required range for the resistor to be used as intended in the circuit, and the circuit has a small footprint. Some aspects and embodiments of the present invention also aim to provide dual-gate transistor geometries, techniques, materials, and methods of manufacturing them, compatible with the combination or integration of any one or more electronic circuits of the types described above. Furthermore, certain aspects and embodiments of the present invention address the problem of how to manufacture circuits, particularly flexible ICs, that include resistors (and optionally transistors and / or Schottky diodes), wherein the resistance of the resistors is within the required range so that the resistors are intended for use in the circuit, and the circuit has a small footprint.

[0007] According to a first aspect of the invention, an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a resistor (2) is provided.

[0008] The transistor includes a source terminal (11), a drain terminal (12), a gate terminal (13), and a first material body (10) providing a controllable semiconductor channel between the source and drain terminals.

[0009] The resistor includes a first resistor terminal (21), a second resistor terminal (22), and a second material body (20) that provides a resistive current path between the first resistor terminal and the second resistor terminal.

[0010] The first material body (10) comprises a metal oxide (e.g., a first amount of the metal oxide), and the second material body (20) comprises the metal oxide (e.g., a second amount of the metal oxide).

[0011] Advantageously, since both the first semiconductor body (channel body) 10 and the resistor body 20 are formed of the same metal oxide, they can be formed, for example, by deposition in the same machine, without the need to remove the circuit structure between the formation of the first and second amounts of metal oxide. They can be formed sequentially, but under different conditions, by selecting / arranging the conditions, such that the first body is a semiconductor body and the second body is a resistor body, or the first body is a resistor body and the second body is a semiconductor body. Alternatively, the metal oxide materials of the first and second bodies can be formed simultaneously, for example in a single deposition step, by different doping and / or by different post-processing to achieve differences in electrical properties. Furthermore, combinations of different deposition conditions, different doping, and / or different post-processing can be used to achieve different electrical properties of bodies based on the same metal oxide material.

[0012] In some embodiments, the circuit includes first and second voltage (power) rails (61, 62), and the resistor is a load resistor connected in series between one of the source and drain terminals (11, 12) and one of the voltage (power) rails.

[0013] In some embodiments, the second material body (20) includes dopants. In some such embodiments, the first material body (10) does not include the dopants, and this difference at least partially contributes to the different electrical properties of the two bodies.

[0014] In some alternative embodiments, the first material body (10) comprises dopants in a first concentration range, and the second material body (20) comprises dopants in a second concentration range. In some such embodiments, the second range is higher than the first range, while in other embodiments, the second range is lower than the first range.

[0015] In some embodiments, at least a portion of the second body (20) has been treated (e.g., annealing, laser annealing, thermal annealing, exposure to electromagnetic radiation, doping, implantation, exposure to ion flow) to increase (or decrease) its conductivity.

[0016] In some embodiments, each of the first and second bodies (10, 20) includes a corresponding layer, film, or sheet of the metal oxide. In some such embodiments, each of the layers, films, or sheets has a thickness in the range of 1 to 200 nm (e.g., in the range of 5 to 50 nm).

[0017] In some embodiments, each of the layers, films, or sheets has the same thickness.

[0018] In some embodiments, each of the layers, films, or sheets is flat (planar). In some such embodiments, the first and second bodies are coplanar, although in some alternative embodiments, the first body lies in a first plane and the second body lies in a second plane, the second plane being parallel to the first plane.

[0019] In some embodiments, the second body has a thin-film resistance value in the range of 25 kOhm / sq to 20 MOhm / sq (e.g., in the range of 50 kOhm / sq to 10 MOhm / sq). Advantageously, this allows the resistor to be manufactured within the range required for a wide range of applications, while having a relatively small / compact footprint. In other words, the area of ​​the required resistive material can be suitably small.

[0020] In some embodiments, each of the first and second bodies is substantially transparent to electromagnetic radiation within the visible range.

[0021] In some embodiments, the circuit (or circuit module) includes a substrate (5) arranged to directly or indirectly support each of the transistor (1) and resistor (2). In some embodiments, the substrate is flexible, and the circuit itself may also be flexible.

[0022] In some embodiments, the metal oxide is indium gallium zinc oxide (IGZO).

[0023] In some embodiments, the resistance between the terminals (21, 22) of the resistor (2) is in the range of 10 Ohm to 10 MOhm (e.g., 100 Ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

[0024] In some embodiments, the circuit further includes a second resistor (3) comprising first and second terminals (31, 32) and a third material body (30) providing a resistive current path between the terminals, wherein the third material body comprises the metal oxide (e.g., comprising a third amount of the metal oxide). In some such embodiments, each of the second and third bodies is planar, wherein the second body is located in a second plane and the third body is located in a third plane parallel to the second plane.

[0025] In some embodiments, the first and second resistors exhibit different resistances at room temperature. For example, the second material body may include dopants in a second concentration range, and the third material body may include dopants in a third concentration range, which is different from the second range. Additionally or alternatively, the third body (30) can be processed differently from the second body to obtain different resistances.

[0026] In some embodiments, the transistor includes a second gate terminal (132). The second gate terminal (132) may be disposed on the side of the first body (10) opposite to the first gate terminal (13, 131) and may be separated from the semiconductor material of the first body (10) by another dielectric material layer (42) or other dielectric material body (42).

[0027] Another aspect of the present invention provides a method for manufacturing an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first material body (10) providing a controllable semiconductor channel between the source and drain terminals, and the resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a second material body (20) providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: forming the first body (10); and forming the second body (20), wherein the first body comprises a first amount (100) of metal oxide, and the second body comprises a second amount (200) of the metal oxide.

[0028] In some embodiments, forming the first body includes forming the first amount of the metal oxide, and forming the second body includes forming the second amount of the metal oxide.

[0029] In some embodiments, forming the first amount includes forming the first amount (100) directly or indirectly on a first region (51) of the substrate, and forming the second amount includes forming the second amount (200) directly or indirectly on a second region (52) of the substrate.

[0030] In some embodiments, the formation of the first amount includes forming the first amount (100) using a technique selected from the list of the following: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

[0031] In some embodiments, the formation of the second quantity includes using techniques selected from a list containing the following: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

[0032] In some embodiments, forming the first amount includes depositing the first amount of the metal oxide.

[0033] In some embodiments, forming the second amount includes depositing the metal oxide of the second amount.

[0034] In some embodiments, the formation of the first quantity is performed before the formation of the second quantity.

[0035] In some embodiments, the formation of the first quantity is performed after the formation of the second quantity.

[0036] In some embodiments, the formation of the first amount includes forming (e.g., by deposition or otherwise) a first layer, film, or sheet (1001) of the metal oxide, the first layer, film, or sheet comprising the first amount (100).

[0037] In some embodiments, forming the first body (10) includes patterning the first layer, film, or sheet (1001).

[0038] In some embodiments, the formation of the second amount includes forming (e.g., by deposition or otherwise) a second layer, film, or sheet (2001) of the metal oxide, the second layer, film, or sheet comprising the second amount (200).

[0039] In some embodiments, forming the second body (2) includes patterning the second layer, film, or sheet (2001).

[0040] In some embodiments, the formation of the first quantity (100) is performed simultaneously with the formation of the second quantity (200).

[0041] In some embodiments, the formation of the first amount and the formation of the second amount simultaneously include forming (e.g., by deposition or otherwise) a layer, film or sheet (1200) of the metal oxide, the layer, film or sheet (1200) comprising the first and second amounts (100, 200).

[0042] In some embodiments, forming the first and second bodies (10, 20) includes patterning the sheet (1200).

[0043] In some embodiments, the method further includes doping the first material body (10) with a first dopant to reduce (or increase) the conductivity of the first body.

[0044] In some embodiments, doping the first material body includes forming the first amount (100) on the source (71) of the first dopant.

[0045] In some embodiments, the method further includes providing the source (71) of the first dopant directly or indirectly on the first region (51) of the substrate.

[0046] In some embodiments, doping the first material body includes a source on which the first dopant is formed.

[0047] In some embodiments, the method further includes doping the second material body (20) with a second dopant to increase (or decrease) the conductivity of the second body.

[0048] In some embodiments, doping the second material body includes forming the second amount (200) on the source (72) of the second dopant.

[0049] In some embodiments, the method further includes providing the source (72) of the second dopant directly or indirectly on the second region (52) of the substrate.

[0050] In some embodiments, doping the second material body includes a source on which the second dopant is formed.

[0051] In some embodiments, the method further includes treating the second amount (200) of the metal oxide to increase or decrease the conductivity of the second body.

[0052] In some embodiments, processing the second quantity includes annealing (or otherwise processing) at least a portion of the second quantity to increase or decrease its conductivity.

[0053] In some embodiments, processing the second quantity includes annealing (or other processing) at least a portion of the second quantity to increase or decrease its conductivity.

[0054] In some embodiments, the processing of the second body (e.g., by annealing or other means) includes exposing the at least portion of the body to electromagnetic radiation.

[0055] In some embodiments, the method further includes providing the electromagnetic radiation from a lamp. In some other embodiments, the electromagnetic radiation may be provided from a laser.

[0056] In some embodiments, the method further includes shielding at least a portion of the first amount (100) of the metal oxide from the electromagnetic radiation.

[0057] In some embodiments, the shielding includes using the gate terminal (13) to shield at least a portion of the first amount (100) from the electromagnetic radiation.

[0058] In some embodiments, each of the first and second bodies (10, 20) includes a corresponding layer, film or sheet of the metal oxide, and each of the corresponding layer, film or sheet may have a thickness in the range of 1 to 200 nm (e.g. 5 to 50 nm).

[0059] In some embodiments, each of the respective layers, films, or sheets has the same thickness.

[0060] In some embodiments, each of the respective layers, films, or sheets is flat (planar).

[0061] In some embodiments, the method includes forming the first and second bodies (10, 20) in a common plane.

[0062] In some embodiments, the method includes forming the first body in a first plane and forming the second body in a second plane parallel to the first plane.

[0063] In some embodiments, the second body has a sheet resistance value in the range of 25 kOhm / sq to 20 MOhm / sq (e.g., in the range of 50 kOhm / sq to 10 MOhm / sq).

[0064] In some embodiments, each of the first and second bodies is substantially transparent to electromagnetic radiation within the visible range.

[0065] In some embodiments, the method further includes providing a substrate (5) arranged to directly or indirectly support each of the transistors and resistors, and the formation of the first and second bodies includes forming the first body (10) on or over a first region (51) of the substrate and forming the second body (20) on or over a second region (52) of the substrate.

[0066] In some embodiments, the substrate (5) is flexible.

[0067] In some embodiments, the method further includes forming the source terminal, drain terminal, first resistor terminal, and second resistor terminal after forming the first and second bodies. In some alternative embodiments, the method further includes forming the source terminal, drain terminal, first resistor terminal, and second resistor terminal before forming the first and second bodies, for example, to form a bottom contact device.

[0068] In some embodiments, the metal oxide is indium gallium zinc oxide (IGZO).

[0069] In some embodiments, the resistance between the terminals of the resistor is in the range of 10 Ohm to 10 MOhm (e.g., 100 Ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

[0070] In some embodiments, the circuit further includes a second resistor (3) having first and second terminals (31, 32), and a third material body (30) providing a resistive current path between the terminals, the method comprising forming the third material body (30) comprising a third amount (300) of the metal oxide. For example, the second resistor may be located in a different circuit layer than the first resistor.

[0071] In some embodiments, the method further includes doping or treating the third body in a manner different from that of the second body, such that the first and second resistors exhibit different resistances at room temperature. For example, one of the resistor bodies may be shielded to protect it from radiation (e.g., UV radiation), while the other resistor body is not shielded and thus receives UV radiation, thereby increasing or decreasing its conductivity.

[0072] In some embodiments, the resistor is a load resistor connected in series between one of the source and drain terminals and the voltage (power) rail.

[0073] In some embodiments, the electronic circuitry is flexible.

[0074] Another aspect of the present invention provides a resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a material body (20) providing a resistive current path between the first resistor terminal and the second resistor terminal, wherein the body (20) covers at least a portion of the upper surface of the first resistor terminal (21), and the second resistor terminal (22) covers at least a portion of the upper surface of the second body (20). In other words, the body (20) may at least partially overlap with the first resistor terminal (21), and the second resistor terminal (22) may at least partially overlap with the second body. The resistor may be formed on a substrate or some other support or structure, and the body (20) may comprise a quantity of metal oxide material.

[0075] Another aspect of the present invention provides a method for manufacturing a resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a material body (20) providing a resistive current path between the first resistor terminal and the second resistor terminal. The method includes: forming the body, then forming the first resistor terminal, and then forming the second resistor terminal. Alternatively, the method includes: forming the first resistor terminal (21), then forming the body (20), and then forming the second resistor terminal (22). In another aspect, the method includes: forming the first resistor terminal (21), then forming the second resistor terminal (22), and then forming the body (20). Thus, the resistor terminals are formed at different times (or in the same processing step or sequence of steps).

[0076] Other aspects of the invention provide a resistor as defined in any of the foregoing aspects or embodiments, and a method of manufacturing such a resistor.

[0077] Another aspect of the present invention provides an electronic circuit (or circuit module) (10000) comprising a Schottky diode (3000) and a resistor (2).

[0078] The Schottky diode includes a first electrode (3001), a second electrode (3002), and a first semiconductor material body (3010) (e.g., a layer) connected to the first electrode at a first interface (junction) and connected to the second electrode at a second interface (junction).

[0079] The resistor includes a first resistor terminal (21), a second resistor terminal (22), and a second material body (20) that provides a resistive current path between the first resistor terminal and the second resistor terminal.

[0080] The first semiconductor material body (3010) includes a metal oxide (e.g., including a first amount of the metal oxide), and the second material body (20) includes the metal oxide (e.g., including a second amount of the metal oxide).

[0081] Advantageously, since both the first semiconductor body (channel body) 3010 and the resistor body 20 are formed of the same metal oxide, they can be formed, for example, by deposition in the same machine, without the need to remove the circuit structure between the formation of the first and second amounts of metal oxide. They can be formed sequentially, but under different conditions, by selecting / arranging the conditions, such that the first body is a semiconductor body and the second body is a resistor body. Alternatively, the metal oxide materials of the first and second bodies can be formed simultaneously with each other, for example in a single deposition step, by different doping and / or by different post-processing to achieve differences in electrical properties. Furthermore, combinations of different deposition conditions, different doping, and / or different post-processing can be used to achieve different electrical properties of bodies based on the same metal oxide material.

[0082] Features of any of the foregoing aspects and embodiments of the invention can be incorporated into embodiments of this further aspect (including at least one Schottky diode and at least one resistor) with corresponding advantages.

[0083] For example, in some embodiments, the second material body (20) includes dopants. In some such embodiments, the first semiconductor material body (3010) does not include the dopants, and this difference at least partially contributes to the different electrical properties of the two bodies.

[0084] In some alternative embodiments, the first semiconductor material body (3010) includes dopants in a first concentration range, and the second material body (20) includes said dopants in a second concentration range. In some such embodiments, the second range is higher than the first range, while in other embodiments, the second range is lower than the first range.

[0085] In some embodiments, each of the first and second bodies (3010, 20) includes a corresponding layer, film, or sheet of the metal oxide. In some such embodiments, each of the layers, films, or sheets has a thickness in the range of 1 to 200 nm (e.g., in the range of 5 to 50 nm).

[0086] In some embodiments, the circuit (or circuit module) includes a substrate (5) (also referred to as a support layer, underlayer, or structure) arranged to directly or indirectly support each of the Schottky diode (3000) and the resistor (2). In some embodiments, the substrate is flexible, and the circuit itself may also be flexible.

[0087] Another aspect of the present invention provides a method for manufacturing an electronic circuit (or circuit module) (10000) including a Schottky diode (3000) and a resistor (2), the Schottky diode including a first electrode (3001), a second electrode (3002), and a first semiconductor material body (3010) (e.g., a layer) connected to the first electrode at a first interface (junction) and connected to the second electrode at a second interface (junction), the resistor including a first resistor terminal (21), a second resistor terminal (22), and a second material body (20) providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: forming the first body (3010); and forming the second body (20), wherein the first body comprises a first amount (3100) of metal oxide, and the second body comprises a second amount (200) of the metal oxide.

[0088] Similarly, any of the features of the above aspects and embodiments of the invention can be incorporated into embodiments of this further aspect that have corresponding advantages.

[0089] For example, in some embodiments, forming the first body includes forming the first amount (3100) of the metal oxide, and forming the second body includes forming the second amount (200) of the metal oxide.

[0090] In some embodiments, forming the first amount includes forming the first amount (3100) directly or indirectly on a first region (51) of the substrate, and forming the second amount includes forming the second amount (200) directly or indirectly on a second region (52) of the substrate.

[0091] In some embodiments, the formation of the first amount (3100) includes forming the first amount (3100) using techniques selected from a list including: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

[0092] In some embodiments, the formation of the first quantity (3100) is performed before the formation of the second quantity (200).

[0093] In some embodiments, the formation of the first quantity (3100) is performed after the formation of the second quantity (200).

[0094] In some embodiments, the formation of the first amount (3100) includes forming (e.g., by deposition or otherwise) a layer, film or sheet (1001) of the metal oxide, the layer, film or sheet comprising the first amount (3100).

[0095] In some embodiments, forming the first body (3010) includes patterning the layer, film, or sheet.

[0096] In some embodiments, the formation of the first quantity (3100) is performed simultaneously with the formation of the second quantity (200).

[0097] In some embodiments, the formation of the first quantity (3100) and the formation of the second quantity simultaneously include forming (e.g., by deposition or otherwise) a layer, film, or sheet of the metal oxide, the layer, film, or sheet comprising the first and second quantities (3100, 200). In some embodiments, forming the first and second bodies (3010, 20) includes patterning the sheet.

[0098] In some embodiments, the method further includes doping the first material body (3010) with a first dopant to reduce (or increase) the conductivity of the first body.

[0099] In some embodiments, doping the first material body includes forming the first amount (3100) on the source (71) of the first dopant.

[0100] In some embodiments, the method includes providing the source (71) of the first dopant directly or indirectly on the first region (51) of the substrate.

[0101] In some embodiments, doping the first material body includes a source on which the first dopant is formed.

[0102] In some embodiments, the method further includes doping the second material body (20) with a second dopant to increase (or decrease) the conductivity of the second body.

[0103] In some embodiments, doping the second material body includes forming the second amount (200) on the source (72) of the second dopant.

[0104] In some embodiments, the method further includes providing the source (72) of the second dopant directly or indirectly on the second region (52) of the substrate.

[0105] In some embodiments, doping the second material body includes a source on which the second dopant is formed.

[0106] In some embodiments, the method further includes treating the second amount (200) of the metal oxide to increase or decrease the conductivity of the second body.

[0107] In some embodiments, processing the second quantity includes annealing at least a portion of the second quantity to increase or decrease its conductivity.

[0108] In some embodiments, the annealing includes exposing the at least portion of the material to electromagnetic radiation.

[0109] In some embodiments, the method further includes providing the electromagnetic radiation from the lamp.

[0110] In some embodiments, the method further includes shielding at least a portion of the first amount (3100) of the metal oxide from the electromagnetic radiation.

[0111] In some embodiments, each of the first and second bodies (3010, 20) is substantially transparent to electromagnetic radiation within the visible range.

[0112] In some embodiments, the method further includes a substrate (5) (also referred to as a support layer, underlayer, or structure) arranged to directly or indirectly support each of the Schottky diode and the resistor, and the formation of the first and second bodies includes forming the first body (3010) on or over a first region (51) of the substrate and forming the second body (20) on or over a second region (52) of the substrate.

[0113] In some embodiments, the method further includes forming the first electrode, the second electrode, the first resistor terminal, and the second resistor terminal after forming the first and second bodies (3010, 20). In some alternative embodiments, the method further includes forming the first electrode, the second electrode, the first resistor terminal, and the second resistor terminal before forming the first and second bodies, for example, to form a bottom contact device.

[0114] In some embodiments, the circuit further includes a second resistor (3) having first and second terminals (31, 32) and a third material body (30) providing a resistive current path between the terminals, the method comprising forming the third material body (30) comprising a third amount (300) of the metal oxide. For example, the second resistor may be located in a different circuit layer than the first resistor.

[0115] In some embodiments, the method further includes doping or treating the third body in a manner different from that of the second body, such that the first and second resistors exhibit different resistances at room temperature. For example, one of the resistor bodies may be shielded to protect it from radiation (e.g., UV radiation), while the other resistor body is not shielded and thus receives UV radiation, thereby increasing or decreasing its conductivity.

[0116] Another aspect of the present invention provides an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a Schottky diode (3000).

[0117] The transistor includes a source terminal (11), a drain terminal (12), a gate terminal (13), and a first material body (10) providing a controllable semiconductor channel between the source and the drain terminal.

[0118] The Schottky diode includes a first electrode (3001), a second electrode (3002), and a second semiconductor material body (3010) (e.g., a layer) connected to the first electrode at a first interface (junction) and connected to the second electrode at a second interface (junction), wherein the first material body (10) includes a metal oxide (e.g., including a first amount of the metal oxide) and the second material body (3010) includes the metal oxide (e.g., including a second amount of the metal oxide).

[0119] Advantageously, since both the first semiconductor body (channel body) 10 and the Schottky body 3010 are formed of the same metal oxide, they can be formed, for example, by deposition in the same machine, without the need to remove the circuit structure between the formation of the first and second amounts of metal oxide. They can be formed sequentially (by selecting / arranging conditions under the same or different conditions to produce a semiconductor path with desired characteristics). Alternatively, they can be formed simultaneously with each other, for example, in a single deposition step. If the transistor channel and the Schottky body require different semiconductor properties, the difference in electrical properties can be achieved through different doping and / or through different post-processing. Furthermore, combinations of different deposition conditions, different doping, and / or different post-processing can be used to achieve different electrical properties for bodies based on the same metal oxide material.

[0120] In some embodiments, the circuit includes first and second voltage (power) rails (61, 62), and the Schottky diode is a load connected in series between one of the source and drain terminals (11, 12) and one of the voltage (power) rails.

[0121] Similarly, features of any of the foregoing aspects and embodiments of the invention can be incorporated into embodiments of this further aspect (including at least one transistor and at least one Schottky diode) with corresponding advantages.

[0122] For example, in some embodiments, the second material body (3010) includes dopants. In some such embodiments, the first material body (10) does not include the dopants, and this difference at least partially contributes to the different electrical properties of the two bodies.

[0123] In some alternative embodiments, the first material body (10) includes dopants in a first concentration range, and the second material body (3010) includes said dopants in a second concentration range. In some such embodiments, the second range is higher than the first range, while in other embodiments, the second range is lower than the first range.

[0124] In some embodiments, at least a portion of the second body (20) has been treated (e.g., annealing, laser annealing, thermal annealing, exposure to electromagnetic radiation, doping, implantation, exposure to ion flow) to increase or decrease its conductivity.

[0125] In some embodiments, each of the first and second bodies (10, 3010) includes a corresponding layer, film, or sheet of the metal oxide.

[0126] In some embodiments, the circuit (or circuit module) includes a substrate (5) arranged to directly or indirectly support each of the transistor (1) and the Schottky diode (3000). In some embodiments, the substrate is flexible, and the circuit itself may also be flexible.

[0127] In some embodiments, the circuit further includes at least one resistor (2) including first and second terminals (21, 22) and a resistor material body (20) providing a resistive current path between the terminals (21, 22), wherein the resistor material body includes the metal oxide (e.g., including a third amount of the metal oxide).

[0128] In some embodiments, the circuit includes at least two such resistors, which can be arranged to exhibit different resistances at room temperature, a difference achieved using any of the techniques described above.

[0129] In some embodiments, the transistor includes a second gate terminal (132). The second gate terminal (132) may be disposed on the side of the first body (10) opposite to the first gate terminal (13, 131) and may be separated from the semiconductor material of the first body (10) by another dielectric material layer (42) or other dielectric material body (42).

[0130] Another aspect of the present invention provides a method for manufacturing an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a Schottky diode, the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first material body (10) providing a controllable semiconductor channel between the source and drain terminals, and the Schottky diode comprising a first electrode (3001), a second electrode (3002), and a second semiconductor material body (3010) (e.g., a layer) connected to the first electrode at a first interface (junction) and connected to the second electrode at a second interface (junction), the method comprising: forming the first body (10); and forming the second body (30210), wherein the first body comprises a first amount (100) of metal oxide, and the second body comprises a second amount (3100) of the metal oxide.

[0131] Similarly, any of the features of the above aspects and embodiments of the invention can be incorporated into embodiments of this further aspect that have corresponding advantages.

[0132] For example, in some embodiments, forming the first body includes forming the first amount (100) of the metal oxide, and forming the second body (3010) includes forming the second amount (3100) of the metal oxide.

[0133] In some embodiments, forming the first amount includes forming the first amount (100) directly or indirectly on a first region (51) of the substrate, and forming the second amount includes forming the second amount (3100) directly or indirectly on a second region (52) of the substrate.

[0134] In some embodiments, the formation of the first amount (100) includes forming the first amount (100) using techniques selected from a list containing: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

[0135] In some embodiments, the formation of the second quantity (3100) includes forming the second quantity (200) using techniques selected from a list containing: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

[0136] In some embodiments, the formation of the first quantity (100) is performed before the formation of the second quantity (3100).

[0137] In some embodiments, the formation of the first quantity (100) is performed after the formation of the second quantity (3100).

[0138] In some embodiments, the formation of the first quantity (100) is performed simultaneously with the formation of the second quantity (3100).

[0139] In some embodiments, the formation of the first amount and the formation of the second amount simultaneously include forming (e.g., by deposition or otherwise) a layer, film, or sheet of the metal oxide, the layer, film, or sheet comprising the first and second amounts (100, 3100).

[0140] In some embodiments, the method includes forming a second gate terminal on the side of the first body (10) opposite to the first gate terminal (13, 131).

[0141] In some embodiments, the method further includes providing a substrate (5) arranged to directly or indirectly support each of the transistor and the Schottky diode (3000).

[0142] Another aspect of the present invention provides a transistor (1) comprising: a source terminal (11), a drain terminal (12), a first material body (10) providing a controllable semiconductor channel between the source and drain terminals, a first gate terminal (131) disposed on one side (e.g., below) of the first body (10), and a second gate terminal (132) disposed on the opposite side (e.g., above) of the first body (10).

[0143] Similarly, any of the features of the above aspects and embodiments of the invention can be incorporated into embodiments of this further aspect that have corresponding advantages.

[0144] In some embodiments, the first gate terminal (131), the first body (10), and the second gate terminal (132) are arranged in a stacked manner in a first (i.e., nominal vertical) direction, wherein the first body (10) is disposed above the first gate terminal (131) and spaced apart from the first gate terminal (in the first direction) by a first dielectric layer or dielectric body (41), the second gate terminal (132) is disposed above the first body (10) and spaced apart from the first body (10) by a second dielectric layer or dielectric body (42) (in the first direction), and the source and drain terminals are arranged such that the projection of any gate terminal on a plane orthogonal to the first direction (i.e., a horizontal plane orthogonal to the vertical direction) does not overlap with the projection of the source or drain terminal.

[0145] In some embodiments, the first and second gate terminals are aligned and arranged to have the same projection onto the plane. In some embodiments, the edges of the source and drain terminals are arranged to coincide with the edges of the aligned gate terminals.

[0146] In some embodiments, the first body (10) is provided by a first portion of a metal oxide material layer disposed above the first gate terminal, and the source and drain terminals (11, 12) are provided by corresponding portions of the metal oxide material layer extending beyond the edge of the first gate terminal. In some embodiments, the corresponding portions have a higher conductivity than the first body.

[0147] In some alternative embodiments, both the source and drain terminals are made of metal.

[0148] Another aspect of the present invention provides an integrated circuit comprising a dual-gate transistor according to the foregoing aspects, and at least one resistor and / or at least one Schottky diode (e.g., as described above).

[0149] Another aspect of the present invention provides a method for manufacturing a dual-gate transistor, the method comprising: providing a lower gate terminal supported on a substrate; and using the lower gate terminal as a mask when forming an upper gate terminal aligned with the lower gate terminal.

[0150] In some embodiments, the method further includes using the lower gate terminal as a mask when forming source and drain terminals aligned with the lower gate terminal.

[0151] In some alternative embodiments, the method further includes using the upper gate terminal as a mask when forming source and drain terminals aligned with the lower gate terminal.

[0152] Another aspect of the present invention provides an electronic circuit (or circuit module) (10000) comprising a first device (1, 3000) and a second device (2, 3000).

[0153] The first device includes a first terminal (11, 3001), a second terminal (12, 3002), and a first semiconductor material body (10, 3010) providing a semiconductor path between the first and second terminals.

[0154] The second device (2, 3000) includes a third terminal (21, 3001), a fourth terminal (22, 3002), and a second material body (20, 3010) that provides a resistance or semiconductor current path between the third terminal and the fourth terminal.

[0155] The first material body (10, 3010) includes a metal oxide (e.g., including a first amount (100, 3100) of the metal oxide), and the second material body (20, 3010) includes the metal oxide (e.g., including a second amount (200, 3100) of the metal oxide).

[0156] Advantageously, since the first bodies 10, 3010 and the resistor bodies 20, 3010 are all formed of the same metal oxide, they can be formed, for example, by deposition in the same machine, without having to remove the circuit structure between the formation of the first and second amounts of metal oxide. They can be formed sequentially, but under the same or different conditions, by selecting / arranging the conditions such that the first body is a semiconductor body and the second body is a semiconductor body or a resistor body. Alternatively, the metal oxide materials of the first and second bodies can be formed simultaneously with each other, for example in a single deposition step, by different doping and / or by different post-processing (if desired). Furthermore, combinations of different deposition conditions, different doping, and / or different post-processing can be used to achieve different electrical properties of bodies based on the same metal oxide material.

[0157] For example, the first device may be a transistor (e.g., bottom-gate, top-gate, or dual-gate) or a Schottky diode. The second device may be, for example, a resistor or a Schottky diode. The circuit may also include at least one additional device (e.g., a third device) having a body also formed of the same metal oxide material. This additional device may be, for example, a transistor, a resistor, or a Schottky diode. Similarly, features of any of the foregoing aspects and embodiments of the invention can be incorporated into embodiments of this further aspect with corresponding advantages.

[0158] Another aspect of the present invention provides a method for manufacturing an electronic circuit (or circuit module) (10000) including a first device (1, 3000) and a second device (2, 3000), the first device including a first terminal (11, 3001), a second terminal (12, 3002), and a first semiconductor material body (10, 3010) providing a semiconductor path between the first and second terminals, the second device (2, 3000) including a third terminal (21, 3001), a fourth terminal (22, 3002), and a second material body (20, 3010) providing a resistive or semiconductor current path between the third terminal and the fourth terminal, the method comprising: forming the first body (10, 3010); and forming the second body (20, 3010), wherein the first body includes a first amount (100, 3100) of metal oxide, and the second body includes a second amount (200, 3100) of the metal oxide.

[0159] Similarly, any of the features of the above aspects and embodiments of the invention can be incorporated into embodiments of this further aspect that have corresponding advantages.

[0160] In certain embodiments of any aspect of the invention, at least one of a certain amount of metal oxide can be formed as a semiconductor material under “normally off” conditions (e.g., enhancement mode, n-type or p-type). For such a material, since its conductivity is initially very low (because it is in the normally off state), a process arranged to increase its conductivity can be employed to change its electrical properties to resistance.

[0161] In certain embodiments of any aspect of the invention, a certain amount of at least one of the metal oxides may be formed as a semiconductor material initially under “normally on” conditions (e.g., depletion mode, n-type or p-type). For such a material, since its conductivity is initially relatively high (because it is in the normally on state), a process can be employed to reduce its conductivity in order to change its electrical properties to resistivity.

[0162] In some embodiments, exposure to electromagnetic (e.g., light) radiation can be used to increase the conductivity of at least a portion of a given amount of a metal oxide. For example, a normally-off semiconductor material (e.g., SnO with a negative threshold voltage) can be exposed to radiation to change its properties to essentially resistance. As conductivity increases, NiO can be tuned from p-type to n-type.

[0163] In some embodiments, exposure to electromagnetic (e.g., light) radiation can be used to reduce the conductivity of at least a portion of at least one of a certain amount of a metal oxide. For example, H2 annealing can be used to reduce Sn(IV) from an n-type material (e.g., SnO2) to a p-type material (e.g., SnO). Exposure to light radiation can be used for "normally on" semiconductors, such as p-type devices with a positive threshold voltage. The semiconductor will initially have a relatively high conductivity, and radiation can be arranged to reduce this conductivity, thereby making the material essentially resistive (thus providing a pathway to integrate resistors in p-type processes in some embodiments). This reduction in conductivity (to manufacture resistors) can also be achieved, for example, by using hydrogen to reduce the number of holes.

[0164] In some embodiments, exposure to electromagnetic radiation (photoexcitation) can generate charge carriers (typically to increase rather than decrease their conductivity). In addition to photoexcitation, and for example in the presence of a dielectric layer, laser ablation of a semiconductor film (or other host containing a certain amount of metal oxide material) can also be used to reduce the thickness of the semiconductor material and thus reduce its conductivity.

[0165] In addition to optical processes, in some embodiments, opening windows in the dielectric layer covering the semiconductor substrate (e.g., a layer) allows for the introduction of foreign dopants and / or modification of the metal oxide material by various means to alter its conductivity. In some embodiments, without opening windows, the dielectric layer itself can be designed (e.g., by reducing thickness, altering arrangement / composition, etc.) to facilitate the diffusion of material into layers below or above the semiconductor substrate, thereby reducing (or increasing) the conductivity of that substrate. Attached Figure Description

[0166] Some aspects and embodiments of the invention will now be described with reference to the accompanying drawings, in which;

[0167] Figure 1 This is a schematic cross-sectional view illustrating a portion of the electronic circuitry of the present invention;

[0168] Figure 2 This is a diagram illustrating the inverter circuit of the present invention;

[0169] Figure 3 This is a diagram illustrating another inverter circuit of the present invention;

[0170] Figure 4 and 5 This is a cross-sectional schematic diagram of a portion of two other electronic circuits embodying the present invention;

[0171] Figure 6 The manufacturing steps of another electronic circuit embodying the present invention are shown;

[0172] Figure 7 and 8 The steps in two other methods embodying the present invention are shown;

[0173] Figure 9 This is a schematic cross-sectional view illustrating a portion of another electronic circuit comprising a transistor and two resistors, which embodies the present invention.

[0174] Figure 10 The manufacturing steps of another electronic circuit embodying the present invention are shown;

[0175] Figure 11 This is a schematic cross-sectional view of another embodiment of the present invention;

[0176] Figure 12 The steps in a method of manufacturing another electronic circuit embodying the present invention are shown;

[0177] Figure 13 , 14 15 illustrates steps in three other methods embodying the invention;

[0178] Figure 16-23 A portion of another electronic circuit embodying the present invention is shown;

[0179] Figure 24 The steps in another method of manufacturing an electronic circuit according to the present invention are shown;

[0180] Figure 25 This is a schematic cross-sectional view illustrating another electronic circuit module of the present invention;

[0181] Figure 26 The steps in another method embodying the invention are shown;

[0182] Figure 27 This is a schematic cross-sectional view of another electronic circuit module that embodies the present invention and incorporates a resistor and a bottom-gate transistor.

[0183] Figure 28 The steps in another method embodying the invention are shown;

[0184] Figure 29 This is a schematic cross-sectional view of another electronic circuit module that embodies the present invention and incorporates a resistor, a bottom-gate transistor, and a Schottky diode;

[0185] Figure 30 The steps in another method embodying the invention are shown;

[0186] Figure 31 This is a schematic cross-sectional view of another electronic circuit module that embodies the present invention and incorporates a resistor, a dual-gate transistor, and a Schottky diode;

[0187] Figure 32 This is a schematic cross-sectional view of another electronic circuit module that embodies the present invention and incorporates n-type and p-type transistors and Schottky diodes;

[0188] Figure 33 A diode or gate embodying one aspect of the invention and incorporating a Schottky diode and a resistor is shown;

[0189] Figure 34 A diode AND gate embodying one aspect of the invention and incorporating a Schottky diode and a resistor is shown;

[0190] Figure 35 A diode-load inverter embodying one aspect of the invention and incorporating a Schottky diode and a transistor is shown;

[0191] Figure 36 A CMOS inverter circuit module embodying one aspect of the invention and incorporating n-channel and p-channel transistors is shown.

[0192] Figure 37 This is a schematic cross-sectional view of a dual-gate transistor that embodies the present invention and is suitable for incorporation / integration into circuits and circuit modules embodying the present invention;

[0193] Figure 38 This is a schematic cross-sectional view of another dual-gate transistor that embodies the present invention and is suitable for incorporation / integration into circuits and circuit modules embodying the present invention;

[0194] Figures 39-43 Various methods embodying the present invention for manufacturing self-aligned dual-gate transistors are illustrated;

[0195] Figure 44 Another dual-gate transistor embodying the present invention and suitable for incorporation / integration into circuits and circuit modules embodying the present invention is shown;

[0196] Figure 45 Another circuit module embodying the invention and incorporating a dual-gate transistor and a resistor is shown; and

[0197] Figure 46 Another circuit module embodying the present invention is shown. Detailed Implementation

[0198] Now for reference Figure 1This figure illustrates a portion of an electronic circuit embodying the present invention. Of course, typically, an electronic circuit would include many other components and interconnections between them. However, for clarity and simplicity, this figure shows only one transistor (1) and one resistor (2) of the circuit (also referred to as a circuit module). The transistor (1) is a field-effect transistor (FET) comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first material body (10) providing a controllable semiconductor channel between the source and drain terminals. As will be fully understood, the conductivity of the channel is controlled by applying a suitable voltage to the gate terminal (13). The resistor (2) comprises a first resistor terminal (21), a second resistor terminal (22), and a second material body (20) providing a resistive current path between the first and second resistor terminals. Although in this embodiment the source and drain terminals (11, 12) and resistor terminals (21, 22) are shown in a “top-contact” architecture, i.e., partially covering the ends of the first body (10) and the second body (20), other embodiments of the invention also include circuits employing alternative terminal architectures. Furthermore, although the FET shown is a “top-gate” architecture, with the gate terminal (13) located above the first body (10), other embodiments of the invention also include circuits employing alternative FET architectures. The first material body (10) comprises a first amount of metal oxide, and the second body (20) comprises a second amount of the same metal oxide. Thus, unlike circuits known in the prior art, this circuit includes semiconductor channels and resistors both formed of the same metal oxide. This allows for significant cost and / or time savings during manufacturing, as the amount of materials and methods used to form, pattern, and define the circuit can be minimized. The first amount of metal oxide (100) forming the first body (10) is formed on a first region (51) of a substrate (5), which at least supports the transistors and resistors of the circuit. The first body (10) can therefore be considered to be formed on or above a first region of the surface of the substrate (5). A second amount (200) of metal oxide is formed on a second region (52) of the substrate surface. The figure also shows a dielectric material layer or body (4) formed on the first and second bodies (10, 20), the source and drain terminals, and the resistor terminals, and providing the gate dielectric of the transistor (1). The gate terminal (13) is then formed over the dielectric material layer (4).

[0199] although Figure 1The embodiments illustrate first and second bodies (10, 20), each comprising the same metal oxide, but in amounts (100, 200) of the two metal oxide materials deposited under different conditions, such that the first body (10) exhibits substantially semiconductive behavior, while the second body (20) exhibits substantially resistive behavior. It should be understood that this difference in electrical / electronic properties can be achieved in various ways. For example, one amount of the metal oxide material (100, 200) can be deposited using PVD technology in the presence of oxygen, while the other amount can be deposited using PVD instead of in an oxygen-containing environment. Alternatively, the different electrical / electronic properties of the first and second bodies (10, 20) can be achieved by treating them differently after the initial formation / deposition stages of the first and second amounts (100, 200), and such treatment techniques will be described below. However, embodiments of the invention are linked by a novel concept of transistor channels and resistor bodies comprising the same metal oxide material. In some embodiments, the transistor may be N-type (enhancement-mode or depletion-mode), while in other embodiments it may be P-type (enhancement-mode or depletion-mode). In some embodiments, both the transistor channel and the resistor body comprise organic materials, such as polymers, compound semiconductors, or 2D materials (e.g., graphene or perovskite), instead of metal oxide materials.

[0200] In some embodiments, the resistor (2) may be a load resistor connected in series between one of the source and drain terminals and the voltage rail. Figure 2 One such arrangement is shown. The circuit module (10000) here is a PMOS inverter (or NOT gate) with a resistive load. The resistor (2) is connected in series between the source (11) of the transistor and the grounded low-voltage rail (62). The drain terminal of the transistor (12) is connected to the high-voltage rail (61) (Vdd).

[0201] Figure 3 Another circuit module embodying the invention is shown, wherein a resistor (2) is connected on the high side of the transistor, in series between the voltage rail (61) and the drain terminal (12) of the transistor (1). This circuit can be described as an NMOS inverter circuit or circuit module, or equivalently as a NOT gate with a resistive load.

[0202] Now for reference Figure 4This illustrates a circuit module according to another embodiment, wherein the difference in electrical / electronic properties between the first and second bodies (10, 20) is achieved, at least in part, by depositing a first amount (100) of metal oxide material on a first dopant source (71) formed on a first region (51) of the substrate (5), the dopant source (71) being arranged such that the first amount (100) of metal oxide material can be deposited as a resistive layer, wherein pre-patterned dopants selectively cause the resistive layer deposited on top thereon to become semiconductive. A second amount of metal oxide material (200) has been deposited as a resistive layer on a second region (52) of the substrate (5) where no dopant source is present. Thus, the second amount (200) remains resistive rather than becoming semiconductive.

[0203] Now for reference Figure 5 This illustrates an alternative embodiment in which a second dopant source (72) has been selectively provided over a second region (52) of the substrate (5). The first and second amounts (100, 200) of metal oxide material have each been initially deposited as semiconductor layers. However, the second dopant source (72) has been selected such that the dopant interacts with the second amount (200) to change its electrical properties from essentially semiconducting to essentially resistive, thus creating a second body (20) with resistivity, while the first body (10) remains semiconducting and forms the channel of the transistor (1).

[0204] Despite the above references Figure 4 and Figure 5 Examples discussed include dopant sources (71, 52) beneath the semiconductive and / or resistive bodies (10, 20), but alternatively or additionally, dopant sources may be provided above or to the sides of one or both of these bodies. For example, the dielectric layer (4) may be a dopant source, and / or the source and drain terminals (11, 12) and / or the resistor terminals (21, 22) may be dopant sources. Dopant sources may remain in the final circuit structure or may be removed during processing. For example, the conductive layer used to form the source and drain terminals (11, 12) and / or the resistor terminals (21, 22) may be a dopant source, and doping of the semiconductive and / or resistive bodies (10, 20) may be achieved during terminal formation before partial removal of the conductive layer (e.g., by patterning and etching).

[0205] It should be understood that while selective doping of the deposited amounts of metal oxide materials can be used to achieve their different electrical properties, in some embodiments, this technique can also be used in conjunction with depositing first and second amounts (100, 200) under different conditions. However, in other embodiments, the first and second amounts (100, 200) can be deposited under the same conditions, and their different electrical properties can be achieved entirely through their different post-processing.

[0206] Now for reference Figure 6 This illustrates the steps involved in manufacturing another electronic circuit module embodying the present invention. Here, the structures of the transistor (1) and resistor (2) have been formed initially by depositing first and second quantities (100, 200) of metal oxide material on corresponding portions of the surface of the substrate (5). These first and second quantities (100, 200) are initially semi-conductive. For example, they can be formed to initially be in a semi-conductive "normally off" state (i.e., having low conductivity). However, Figure 6 The steps shown are those in which a second quantity (200) of material is selectively exposed to electromagnetic radiation to alter its conductivity. For example, electromagnetic radiation can be arranged to anneal at least a portion of the second quantity of material and increase its conductivity (e.g., relative to a low conductivity "off" state), such that a resistive, rather than semiconductive, path is provided between terminals. It should be understood that such selective exposure of only one of the metal oxide material bodies (100, 200) can be achieved in a variety of ways. For example, radiation can be directed to a wider portion of the circuit, where the gate terminal (13) acts as a mask to shield the first quantity of metal oxide material (100) (or at least most of it) from the radiation. Alternatively, a separate mask can be used, and / or an electromagnetic radiation source capable of irradiating only a small portion of the circuit can be used (e.g., a laser beam can be used to perform selective annealing / processing). Techniques suitable for increasing the conductivity of one or more bodies in some embodiments are described in US10204683B2.

[0207] Now for reference Figure 7This illustrates two steps in another method embodying the invention. In this method, first (100) and second (200) amounts of metal oxide material have been deposited on different regions of a substrate (5), and both are initially semiconducting. For example, the first and second amounts can be formed to be semiconducting under “normally off” conditions (e.g., for an IGZO device with an n-type enhancement mode / positive threshold voltage). For such materials, since their conductivity is initially very low (because they are in the “off” state), processing is required to increase their conductivity in order to change their electrical properties to resistivity. In some embodiments, a portion of the metal oxide material can be formed as a p-type “normally off” material, such as in SnO with a negative threshold voltage. NiO can also be adjusted from p-type to n-type as conductivity increases. In alternative embodiments, a portion of the metal oxide material can be formed to be semiconducting in the “normally on” state (e.g., for a p-type device with a positive threshold voltage). For such materials, since their conductivity is initially relatively high (because they are in a "connected" state), a process is needed to reduce their conductivity in order to change their electrical properties to resistivity. Returning to the current embodiment, it should be understood that... Figure 7 The individual amounts (100, 200) shown in a can be produced by first depositing a uniform layer, sheet, or other structure of metal oxide material, and then patterning these layers, sheets, or other structures by any suitable means. Alternatively, the individual amounts (100, 200) can be selectively formed on the substrate surface by any suitable technique (e.g., by selective deposition, coating, printing, or other methods). Figure 7 In step a, the second quantity (200) of metal oxide material is selectively exposed to electromagnetic radiation to increase its conductivity and change its electrical properties from essentially semiconductive (“normally off” semiconductor material) to resistive. Following this exposure (which can generally be considered as the second quantity (200) of metal oxide material being treated in a manner different from the first quantity (100)), the following can be obtained: Figure 7 The structure shown in b, wherein a semiconductive metal oxide body (10) occupies a portion of the substrate surface, and a metal oxide material body (20) of the second basic resistor occupies the other portion. It should be understood that the terminals / contacts of the transistor and resistor can then be constructed using suitable processing techniques, and gate dielectrics and gate terminals can also be formed. Therefore, Figure 7 The method shown is a method of treating first and second quantities (100, 200) of metal oxide material in different ways before forming the rest of the transistor and resistor (and...). Figure 6 The method shown here differs from the one in which different processing is performed after the transistor and resistor structures are formed.

[0208] Now for reference Figure 8It illustrates two steps in an alternative method embodying the invention. Here, in Figure 8 In a, an initially uniform semiconductor material layer (1200) has been formed to cover the open surface of the substrate (5). Individual portions of this layer (1200) provide first and second amounts (100, 200) of metal oxide material. Figure 8 a further illustrates that a second amount (200) of the metal oxide is being selectively exposed to electromagnetic radiation to alter its conductivity (e.g., increasing its conductivity and thus decreasing its resistivity, or decreasing its conductivity and increasing its resistivity). It should be understood that such selective exposure can be performed using a variety of suitable techniques, which are readily understood by those skilled in the art based on general knowledge of the art and the remainder of this specification. Thus, in this example, the selective treatment of the second amount (200) of the metal oxide is performed prior to the patterning layer (1200). Figure 8 b illustrates the structure resulting from the patterning of layer (1200), in which the lower portion of the substrate (5) surface is exposed by selectively removing a portion of the layer. Specifically, the metal oxide material has been removed to leave only the first and second bodies (10, 20). The first body (10) corresponds to a first amount (100) of metal oxide deposited as part of the initial layer (1200). The second body (20) comprises a second amount (1200), which has also been exposed to electromagnetic radiation and is now resistive rather than semiconductive. Similarly, in Figure 8 Following the two steps shown, further features of the transistors and resistors will be constructed using appropriate techniques.

[0209] Now for reference Figure 9This illustrates another circuit module embodying the invention. The circuit module includes a transistor (1), a first resistor (2), and a second resistor (3). The transistor channel is provided by a first metal oxide material body (10) formed on a first region (51) of a substrate (5). The first resistor (2) includes a resistor body (20) formed on a second region (52) of the substrate, and the second resistor (3) includes a third body (30) of the same metal oxide material as that used to form the first and second bodies (10, 20), formed on a third portion of the substrate (53). The second resistor also includes resistor terminals (31 and 32). In this embodiment, each of the first, second, and third bodies (10, 20, 30) is formed of the same metal oxide material. However, the first body (10) has been deposited under different conditions than the second body (20), such that the first body (10) is substantially semiconductive, while the second body (20) is substantially resistive. In some embodiments, the third body (30) may have been deposited under the same conditions as the second body (20), and therefore may have the same sheet resistance. However, the geometries of the first and second resistors (2, 3) may be different, causing the first and second resistors to exhibit different resistances. However, in alternative embodiments, the second and third bodies (20, 30) may be deposited under different conditions, causing their resistor bodies (20, 30) to have different sheet resistances. Therefore, different resistances can be obtained even if the geometries of the first and second resistors are not necessarily different. Obviously, in further embodiments, in addition to different deposition techniques, combinations of different resistor geometries (e.g., different resistance path lengths and widths) can be used to fabricate resistors with different values ​​in electronic circuits.

[0210] Now for reference Figure 10 It illustrates the steps for forming another circuit module embodying the invention. In this embodiment, the circuit module also includes a transistor (1) formed on a common substrate (5) and first and second resistors (2, 3). The transistor (1) includes a semiconductor channel provided by a first amount (100) of metal oxide material. This first amount (100) is deposited simultaneously with the deposition of second and third amounts (200, 300) of metal oxide material under the same conditions. Conditions have been selected such that each of these first, second, and third amounts (100, 200, 300) is initially semiconducting. Figure 10The diagram illustrates the changes in conductivity of the second and third quantities (200, 300), while the conductivity of the first quantity (100) remains unchanged from its initial deposition. Specifically, electromagnetic radiation (labeled R) is shown in the illustrated structure, and the gate terminal (13) serves as a mask to shield the metal oxide material of the first quantity (100) from this radiation and its effects. Conversely, the third quantity (300) is fully exposed to radiation R, undergoing annealing (or otherwise being affected) by this exposure, thus transforming the initial semiconductor (e.g., normally off) material of the third quantity (300) into a resistive material (by increasing its conductivity). The diagram also shows a partial mask used to absorb only a portion of the radiation directed at the metal oxide material of the second quantity (200). In other words, the partial mask partially shields the material of the second quantity (200) from radiation R. Therefore, the metal oxide of the second quantity (200) is annealed (or otherwise affected) to a lesser extent than the third quantity (300), resulting in a correspondingly smaller but still significantly increased conductivity. Figure 10 The technology shown is capable of producing circuit modules that include semiconductor transistor channels and first and second resistors with different resistances, all formed of the same metal oxide material but processed in different ways to produce different electrical characteristics.

[0211] Now for reference Figure 11 This illustrates another embodiment combining a transistor (1) with first and second resistors (2, 3). In this example, the semiconductor channel (10) and the second and third resistor bodies (20, 30) are simultaneously deposited under the same deposition conditions from the same metal oxide material, such that the first, second, and third amounts (100, 200, 300) of the metal oxide material are each initially semiconducting. However, the second amount (200) is formed on the second dopant source (72), and the third amount (300) is formed on the third dopant source (73). The dopant material and / or its concentration are selected to cause the second and third bodies (20, 30) to be doped differently and thus exhibit different resistances. No dopant is provided to the first amount of metal oxide material, thus providing the first body (10) of the transistor (1) accordingly.

[0212] Now for reference Figure 12 It illustrates steps in another method embodying the invention, wherein first and second amounts (100) of metal oxide material are deposited at different stages of the manufacturing process and different electrical conductivities of the bodies (10, 20) formed from the same metal oxide material are achieved under different conditions. Figure 12This illustrates how an initial metal oxide material layer (1001) is formed on a substrate (5), which in some embodiments is flexible and in alternative embodiments is rigid. The substantially uniform layer (1001) comprises a first amount (100) of metal oxide material that will form the basis of the transistor channel. It is then patterned by suitable means. Figure 12 The structure shown in a is used to generate Figure 12 The structure shown in b. Therefore, a portion of the layer (1001) has been selectively removed to leave only the first amount (100) of metal oxide material that will form the first body (10). It should be understood that a variety of techniques can be used to perform this patterning, such as those involving one or more of the following: lithography, photolithography, imprinting, nanoimprinting. In the method shown, a conductive material layer (81) is then formed over the first body (10) and the substrate (5). The conductive layer (81) is patterned using a suitable technique to form the source and drain terminals (11 and 12) of the resistor and the first and second terminals (21, 22). A resist material layer (9) is then formed on the terminals / contacts and the semiconductor channel to produce Figure 12 The structure shown in d. Again, by using a suitable technique, windows (90) are formed in the resist layer (9), exposing at least a portion of the resistor terminals (21, 22) and a portion of the substrate surface extending between them. Then, Figure 12 f illustrates the formation (by deposition or other means) of a second layer (2001) having the same metal oxide material as the first layer (1001), but under different conditions, causing the second layer (2001) to exhibit resistive behavior rather than semiconductive behavior. This second layer (2001) comprises a second amount (200) of metal oxide material that forms the second body (20) of the resistor, thereby providing a resistive path between the resistor terminals (21, 22). Thus, in this example, the resistor has bottom contacts, i.e., its terminals are formed directly on the substrate surface, and the resistor body (20) is formed to overlap with those resistor terminals on top. Figure 12 g shows another step in which the remaining resist material of layer (9) has been removed. Figure 12 h shows the result of in Figure 12 The final structure is formed by forming a dielectric layer (4) above the structure shown in g, followed by forming a gate electrode (13) above the transistor channel body (10). Therefore, in Figure 12 In the illustrated embodiment, the channel body (10) and the resistor body (20) are formed of different metal oxide material layers, which are formed under different conditions, such that the channel (10) exhibits semiconductive behavior and the resistor body (20) exhibits resistive behavior.

[0213] In addition, Figure 12In the embodiment shown, the resistor body (20) is formed after the conductive contacts of the transistor and resistor are formed.

[0214] refer to Figure 13 This demonstrates an alternative technique in which the first and second bodies are formed at different times, but before the formation of the conductive contacts. Figure 13 a shows the initial formation of a first layer (1001) of a metal oxide material comprising a first amount (100) on top of a substrate (5). This layer (1001) is patterned using a suitable technique to produce… Figure 13 The structure shown in b includes a first amount (100) of metal oxide material located on a substrate. Then, in Figure 13 In c, after the first amount (100) is formed, a second amount of metal oxide material (200) is formed on different regions of the substrate.

[0215] Now for reference Figure 14 It illustrates an alternative method in which a second amount of metal oxide material (200) is initially formed on the substrate surface. Then, as... Figure 14 As shown in b, after the second quantity (200) is formed, the first quantity (100) is formed on different parts of the substrate.

[0216] Now for reference Figure 15 This illustrates yet another method for forming an electronic circuit module that embodies the present invention. For example... Figure 15 As shown in Figure a, a metal oxide material layer (2001) is first formed on a substrate (5). This layer (2001) includes a second amount of metal oxide material (200) that will form the resistor body. Using a suitable technique, this layer (2001) is patterned to produce... Figure 15 The structure shown in b. This second quantity (200) is formed under conditions that cause the metal oxide material to exhibit resistive behavior. Then, as Figure 15 As shown in c, a resist material layer (9) is formed. Then, as... Figure 15 As shown in d, a window (90) is formed in the resist layer (9), and a metal oxide material layer (1001) is deposited to cover the substrate portion exposed by the window (90) with a first amount of metal oxide material (100). The formation conditions of the layer (1001) make the first amount (100) substantially semi-conductive compared to the resistive second amount (200), even without any subsequent processing. The remaining resist material is then removed by a suitable technique, and a conductive material layer (81) is formed on top of the underlying structure to produce Figure 15 The material shown in e. The conductive layer (81) is then patterned to produce... Figure 15The structure shown in f includes transistor source and drain terminals as well as first and second resistor terminals (21, 22). It should be understood that other components of the circuit module can then be built on top of this structure using appropriate techniques.

[0217] Now for reference Figure 16 This illustrates a portion of another circuit module embodying the invention. In this example, each of the first and second bodies (10, 20) is formed of a layer, sheet, or film of a metal oxide material. In this example, the thickness of the layer, film, or sheet is T. Therefore, the first and second bodies (10, 20) have the same thickness. However, the length of the semiconductor channel provided by the first body (10) is L1, and the length of the resistive path provided by the second body (20) is L2, where L1 and L2 are different. However, in some alternative embodiments, it should be understood that the channel and the resistive path may have the same length.

[0218] Now for reference Figure 17 This illustrates yet another embodiment, in which the first body (10) has a thickness T1, and the second body (20) has a different thickness T2. Similarly, the channel length L1 and the resistor path length L2 are different.

[0219] from Figure 16 and 17 It should be understood that in some embodiments, the first and second bodies (10, 20) are formed on corresponding different areas of the substrate (5) surface, and then contacts or terminals (11, 12, 21, 22) are formed to overlap with the upper surfaces of the first and second bodies (10, 20). Figure 18 An alternative embodiment is shown in which source and drain terminals (11, 12) and first and second resistor terminals (21, 22) are formed on the substrate (5) prior to the formation of the first and second bodies (10, 10, 20). Thus, in this example, the first body (10) partially overlaps with the source and drain terminals (11, 12), and the second body (20) also partially overlaps with the upper surfaces of the resistor terminals (21 and 22). A gate dielectric (4) is formed over the first body (10) and the terminals (11, 12), and a gate terminal (13) is formed over the gate dielectric. Therefore, from... Figure 18 It should be understood that in all embodiments of the present invention, the first body (10) and / or the second body (20) are not necessarily planar. Figure 19This is further illustrated in the figure, which shows a circuit module embodying the invention, wherein a first body (10) is initially formed on the surface of a substrate (5) under conditions that cause it to exhibit semiconductive behavior. Source and drain terminals (11, 12) and a first resistor terminal (21) are then formed simultaneously, wherein the source and drain terminals (11, 12) partially overlap the upper surface of the first body (10). The first resistor terminal (21) is formed directly on a portion of the surface of the substrate (5). A second body (20) is formed in a subsequent step (i.e., after the formation of the first body (10)) under conditions that cause it to exhibit resistive behavior, and the second body (20) covers at least a portion of the upper surface of the first resistor terminal (21) and a portion of the substrate surface (5) adjacent to the first terminal (21). A second resistor terminal (22) is subsequently formed, located above the second body (20). Thus, the resistor body (20) is again not a simple planar surface. In this example, it is stepped, and the first and second resistor terminals (21, 22) are formed in different steps (or different sequence of steps), i.e., formed by different conductive layers. Therefore, in this example, the resistor terminals are formed when they are different from each other (or in the same processing step or sequence of steps).

[0220] Now for reference Figure 20 It illustrates an alternative circuit embodying the invention, wherein the transistor (1) has a bottom-gate structure and the resistor has bottom contacts. It should be understood that... Figure 20 The structure shown can be formed in such a way that the gate and resistor contacts (21 and 22) are formed simultaneously, for example by patterning an initial continuous conductive material layer on the surface of the substrate (5), and then the resistor body (20) is formed with a metal oxide material under conditions that cause the resistor body (20) to exhibit resistive behavior. Next, the gate dielectric can be formed before forming the channel body (10) above the gate, this time under conditions that make the channel body (10) semiconductive rather than resistive. The source and drain contacts (11, 12) can then be formed using suitable techniques. In this example, the first body (10) and the second body (20) are not coplanar, but their respective orientation planes are parallel to each other.

[0221] Now for reference Figure 21 It illustrates an alternative circuit module embodying the invention, wherein the transistor (1) has a bottom-gate structure and the resistor has overlapping top contacts (21, 22). To form Figure 21The structure can first form the gate terminal. Then the resistor body (20) can be formed before or after the gate dielectric. Then the transistor body (10) is formed after the resistor body (20), and the source and drain terminals (11, 12) and resistor terminals (21, 22) can be formed in different steps or simultaneously, for example, by patterning conductive material layers.

[0222] Now for reference Figure 22 This illustrates an alternative embodiment in which first and second amounts (100, 200) of metal oxide material are formed at the same or different times and under the same or different processing conditions. However, the first amount (100) is formed over the first dopant source (71) and the second amount (200) is formed over the second dopant source (72). The dopant material and / or its concentration is selected such that the interaction of the first amount of metal oxide material (100) with the first dopant source (71) results in the first body (10) being semiconductive, and the second amount of metal oxide material (200) interacts with the second dopant source (72) such that the second body (20) provides a resistive current path between the terminals (21, 22).

[0223] Figure 23 A similar embodiment is shown in which the substrate (5) itself has been selectively doped in different regions to provide different dopant sources (71 and 72), which interact with first and second quantities (100, 200) to generate semiconductor channels and resistive bodies, respectively.

[0224] Now for reference Figure 24 It illustrates steps in another method embodying the invention. In step 24a, a metal oxide material layer (1200) is formed on the surface of a substrate (5), the layer (1200) comprising first and second amounts (100, 200) of metal oxide material. The structure is then patterned using a suitable technique to produce Figure 24 The structure shown in b is then used to deposit a conductive material layer (81) on the structure to produce Figure 24 The structure shown in c is then patterned using appropriate techniques (81) to produce Figure 24 In the structure shown in d, portions of the front conductive layer (81) form resistor terminals (21, 22) and source and drain terminals (11 and 12), each of which partially overlaps with the upper surface of a corresponding amount (100, 200) of metal oxide material. A dielectric material layer (4) is then formed to produce... Figure 24 The structure shown in e is formed with a second conductive material layer (82) on top, which includes the material that will form the gate terminal (13). This second layer is then patterned using a suitable technique to produce... Figure 24The structure shown in g, wherein the gate terminal (13) is above the semiconductor channel body (10). Figure 24 In the stage shown in g, each quantity (100, 200) can be a fundamentally semiconducting material (e.g., a "normally off" semiconductor material). Figure 24 h shows where... Figure 24 The structure of g is exposed to electromagnetic radiation R as a subsequent step to thermally anneal (or otherwise affect) only the second amount (200) of the metal oxide material, thereby increasing its conductivity and changing its properties from semi-conductive (normally off) to resistive. The gate (13) acts as a mask or shield and shields the first amount (100) of radiation R, making it substantially unaffected by the radiation, so that the transistor body (10) exhibits semi-conductive behavior rather than resistive behavior. Advantageously, this embodiment is one in which the metal oxide materials for the transistor channel and the resistor body can be deposited simultaneously. The difference in the final electrical characteristics of the channel and the resistor body is achieved through different post-processing.

[0225] It should be understood that while some embodiments provide flexible electronic circuits, such as flexible ICs, and / or low-cost circuits, other embodiments may provide, for example, non-flexible and not necessarily low-cost circuits, such as ICs, fabricated on rigid substrates or partially complete systems.

[0226] Any suitable material can be used as a substrate (5), which can consist of one or more such materials. The substrate (5) may be flexible and includes any one or more materials listed below: glass (rigid or flexible); polymers (e.g., polyethylene naphthalate, polyethylene terephthalate; polymethyl methacrylate; polycarbonate, polyvinyl alcohol; polyvinyl acetate; polyvinylpyrrolidone; polyvinylphenol; polyvinyl chloride; polystyrene; polyethylene naphthalate; polyethylene terephthalate; polyimide, polyamide (e.g., nylon); poly(hydroxy ether); polyurethane; polycarbonate; polysulfone; poly(p-xylene); polyarylate; polyether ether ketone (PEEK); acrylonitrile butadiene styrene; 1-methoxy-2-propyl acetate (SU-8); polyhydroxybenzyl silsesquioxane (HSQ); benzocyclobutene (BCB); Al2O3, SiOxNy; silicon dioxide; Si3N4; UV-curable resin; nanoimprint resist; photoresist; polymer foil; paper; insulating coated metal (e.g., coated stainless steel); cellulose.

[0227] Any suitable material can be used as the dielectric layer (4), which can consist of one or more such materials. Examples of suitable materials include: metal oxides, such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; metal phosphates, such as Al2POx; metal sulfates / sulfites, such as HfSOx; metal nitrides, such as AlN; metal oxynitrides, such as AlOxNy; inorganic insulators, such as SiO2, Si3N4, SiNx; spin-coated glass (such as polyhydroxybenzylsilsesquioxane HSQ), polymers Dielectric materials (such as Cytop, a commercially available amorphous fluoropolymer), 1-methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polyvinyl chloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone; UV-curable resins; nanoimprint resists; or photoresists. Dielectric materials can have relatively low dielectric constants (low K, such as Cytop, HSQ, parylene) or relatively high dielectric constants (high K, such as Ta2O5, HfO2).

[0228] The source, drain, and gate terminals (11, 12, 13) and resistor terminals (21, 22) of the transistor can be formed using any suitable material, any of which can consist of one or more layers of such material. Examples of suitable materials include: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides such as ITO, IZO, AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conductive polymers such as polyaniline, PEDOT:PSS; or semiconductor materials.

[0229] Any suitable material can be used to form the first material body (10) providing a controllable semiconductor channel and the second material body (20) providing a resistive current path, as well as any other further semiconductors and resistors in the circuit. The first body (10) and / or the second body (20) can consist of one or more such materials. Examples of suitable materials include metal oxides such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO), and AlZnO (AZO). Other suitable materials may include organic materials such as polymers, compound semiconductors, and 2D materials such as graphene and perovskite. Suitable materials are those that can be used to form a resistor or semiconductor according to their stoichiometry, deposition, processing, and / or doping. Both the first body (10) and the second body (20) can be composed of the same material. In other embodiments, the first body (10) or the second body (20), or both bodies (10, 20), may each include additional materials taken from the above list or may have different types of materials, such as conductors, insulators, or different types of semiconductors. Therefore, another aspect of the invention provides an electronic circuit (or circuit module) including a transistor and a resistor, the transistor including a source terminal, a drain terminal, a gate terminal, and a first body providing a controllable semiconductor channel between the source and drain terminals, the resistor including a first resistor terminal, a second resistor terminal, and a second body providing a resistive current path between the first and second resistor terminals, wherein the first body includes a first amount of material and the second body includes a second amount of said material. Another aspect provides a method of manufacturing such a circuit, including forming the first body and forming the second body.

[0230] It should also be understood from the above description that certain embodiments of the present invention provide improvements to unipolar (i.e., p-type or n-type semiconductor-based) circuits (e.g., FlexICs) to extend their functionality for low-cost processing, sensing, communication, and other applications. This method is based on integrating resistors along with unipolar transistors into the circuit (e.g., FlexICs). In some embodiments, these resistors have some or all of the following characteristics:

[0231] 1. Used as transistor loads, they enable FlexICs to contain more complex and efficient logic circuits.

[0232] 2. Used in analog circuits, they can, for example, enable timers and other basic functions in RF circuits.

[0233] 3. They exhibit sheet resistance values ​​between approximately 50 kΩ / □ and 10 MΩ / □.

[0234] 4. They can be manufactured using mature thin-film deposition technologies (such as PVD, CVD, etc.).

[0235] 5. They do not require lengthy or energy-intensive post-deposition treatment.

[0236] 6. They have high light transmittance and are essentially transparent.

[0237] 7. The elements of their forming materials are the same as those of the forming materials in the semiconductor channel of transistors (e.g., FlexIC transistors).

[0238] 8. They are formed from metal oxides (e.g., NiO, SnO, IGZO).

[0239] 9. They are formed from indium gallium zinc oxide (IGZO).

[0240] 10. They are located in one or more layers of FlexIC.

[0241] 11. They are located in the same or different layers as the semiconductor channels of the FlexIC transistor.

[0242] The inventors recognized that the electronic properties of metal oxides have recently been studied with considerable intensity. Much of this work has been done in the context of either (i) very low resistivity for applications of transparent conductive oxides (such as indium tin oxide), or (ii) very high resistivity for semiconductor applications. The inventors recognized that electromagnetic radiation, such as from UV lasers or lamps, can reduce the resistivity of metal oxide semiconductor materials from approximately 10... 9 Ω / □ decreased to approximately 10 5 Ω / □. Therefore, some embodiments of the present invention use electromagnetic radiation to change resistance to set the resistance of one or more resistors in a circuit (e.g., an IC).

[0243] The resistors in these embodiments are formed of metal oxides. Their resistivity may depend primarily on the stoichiometry of the metal oxide, the techniques and conditions used for deposition and processing, and the addition of elements from adjacent materials into the IC structure. For example, pre-patterned dopants or dopants present in layers above or beside the resistor can selectively cause the metal oxide semiconductor film to become resistive after deposition and processing.

[0244] By depositing a certain amount of initial semiconductor material on top of a dopant (or the source of the dopant), the dopant can then transform the semiconductor film into a resistive film. This technique is used in some embodiments.

[0245] Dopants can provide atoms, such as O, H, F, N, Y, to the initial semiconductor layer, or they can accept these atoms from the initial semiconductor layer to leave vacancies in the material (and thus increase its conductivity / decrease its resistivity). Alternatively, a metal oxide film can be deposited as a resistive layer with pre-patterned dopants that selectively cause the resistive layer to become semiconductive.

[0246] In another example, a semiconductor film can be formed from a material with one stoichiometry (molar ratio of elements), while a resistive film can be formed from the same material with different stoichiometry.

[0247] Therefore, in order to achieve semiconductor channels and resistors comprising the same metal oxide, corresponding amounts of metal oxide material can exhibit different stoichiometry and / or can be formed / deposited under different conditions and / or can undergo different post-formation processing. Examples of how to distinguish the deposition / processing of resistors and semiconductor channels comprising the same metal oxide material can include the following individually or in combination, and for a body comprising more than one layer of material, the deposition / processing is different for each layer:

[0248] - Deposition via PVD or ALD (atomic layer deposition) (e.g., IGZO) in the presence, absence, or different concentrations of O2, N2, F, and H2.

[0249] - Deposition via PVD and ALD

[0250] - By thermal annealing, for example by annealing only the resistive element or the semiconductor channel, or by annealing the resistive element and the semiconductor channel simultaneously under different temperature conditions and / or in the presence of air, O2, N2, Ar, H2, synthesis gas, etc.

[0251] - Through plasma treatment, such as CF4, Ar, O2, N2, NF3, H2, during or after deposition.

[0252] - By using a UV laser or an excited-state atomic lamp (as described above)

[0253] - By controlling the thickness of the semiconductor channel and the resistive element.

[0254] It should be understood that although the above-described techniques, materials and configurations are used to manufacture circuit modules comprising at least one transistor and at least one resistor, they can also be used, with necessary modifications, to manufacture alternative circuit modules comprising at least one resistor and at least one Schottky diode, at least one transistor and at least one Schottky diode, or at least one of a resistor, a transistor and a Schottky diode.

[0255] Now for reference Figure 25This illustrates another circuit module embodying one aspect of the invention and incorporating transistor 1 and resistor 2. The transistor in this example is a top-gate transistor, and the resistor is top-contact, meaning the upper surfaces of its terminals 21, 22 are exposed for further connections. This structure is similar to... Figure 1 The illustrated embodiments are largely the same. The substrate 5 is referred to herein as the bottom layer, and it should be understood that this may include one or more layers, or in fact may include a complex structure (e.g., including additional electronic components and / or circuitry) on which the resistor 2 and transistor 1 are formed. In this example, the gate 13 is stepped and partially fills the groove in the dielectric layer 4 above the body 10, which forms the semiconductor channel (an n-type semiconductor in this example).

[0256] Figure 26 It shows the manufacturing process as follows Figure 25 The steps in the method of the circuit module shown. Figure 26 A illustrates the first step, in which a certain amount of metal oxide material 200 is formed on the bottom layer 5, the formation conditions being such that the electrical behavior of the metal oxide material is typically resistive. This amount 200 thus forms the resistor body 20. Next, as... Figure 26 As shown in Figure B, an additional 100 units of metal oxide material are deposited on the upper surface of the substrate. The formation conditions are such that the metal oxide material is semi-conductive, and this forms the body 10 of the transistor. Next, as... Figure 26 As shown in Figure C, a conductive material layer 81 is formed on the upper surfaces of the first and second bodies 10, 20 and the substrate 5, and then the conductive layer 81 is patterned using a suitable technique to produce... Figure 26 The structure shown in D includes transistor and resistor terminals 11, 12, 21, and 22. Next, a dielectric material layer 4 is formed on top of the underlying structure, as shown in Figure D. Figure 26 As shown in E, a gate terminal 13 is then formed above the semiconductor channel 10, as follows: Figure 26 As shown in F. In addition, the dielectric layer 4 was treated to expose the upper surfaces of the resistor terminals 21 and 22.

[0257] While this top-contact, top-gate structure is suitable for certain embodiments, patterning multiple metal oxide (e.g., IGZO) layers can be problematic, and it may be necessary to fabricate the semiconductor body 10 and resistor body 20 separately. Furthermore, in some examples, the semiconductor material 10 may interact with the underlying layer, which is undesirable. Additionally, some applications require the integration of Schottky devices into circuit modules that include resistors and / or transistors, which may require providing a bottom electrode. Integrating Schottky devices into circuit modules embodying certain aspects of the invention is desirable to create near-field communication (NFC) circuits with smaller footprints, lower power circuits, higher speed circuits (e.g., circuits capable of operating at UHF frequencies), and also takes into account ESD protection factors.

[0258] Based on these considerations, Figure 27 Another circuit module embodying one aspect of the invention is shown. This can be viewed as a top-contact, bottom-gate module. Here, the transistor gate 13 is formed on the upper surface of the substrate 5, as is the resistor body 20. The resistor body can be formed before or after the bottom gate 13, which minimizes processing of the resistor body. A first dielectric layer 41 has been formed over the gate 13, and this layer 41 also covers the upper surface of the resistor body 20. The semiconductor body 10 of the transistor 1 has been formed on the first dielectric layer 41, and then the source and drain terminals 11, 12 of the transistor are formed to partially overlap the upper surface of the semiconductor body 10. Another dielectric layer 42 has been formed, but the upper surfaces of the transistor and resistor terminals 11, 12, 21, 22 are exposed for further connections.

[0259] Although the n-type semiconductor channel 10 in the figure is shown as a single body, it should be understood that in some embodiments, the semiconductor body 10 may be designed to include, for example, a gradient channel or multiple different layers (e.g., high and low resistance layers, etc.). In other words, in this embodiment and indeed in other embodiments, the semiconductor body 10 may consist of two or more semiconductor layers, each with customized conductivity, mobility, carrier concentration, etc.

[0260] The source and drain terminals 11, 12 of the transistor can be fabricated using various suitable techniques, such as masking and etching, or patterning a resist layer to form a window, depositing a conductive material within the window, and then stripping away the remaining resist material. Various suitable techniques can be used to pattern the second dielectric material. Furthermore, although a simple lateral resistor 2 is shown in the figure, other forms of resistors can be incorporated into alternative circuit modules embodying the invention (e.g., vertical resistors, resistors with horizontally and vertically offset terminals, etc.).

[0261] Figure 28 It shows the formation of such as Figure 27 Some steps of the circuit module shown. Figure 28 A shows a quantity 200 of metal oxide material provided (by deposition or otherwise) on the nominal upper surface of substrate 5. This quantity 200 can be provided in its initial state, where it typically exhibits semiconductive behavior. Figure 28 A, indicated by a large arrow, shows the initial semiconductor material body 200 being exposed to electromagnetic radiation of a suitable frequency to change the electrical properties of the body from semiconducting to resistive, as described above regarding other embodiments. Then, Figure 28 B illustrates another stage of the method, in which resistor terminals 21, 22 are formed simultaneously with the formation of the bottom gate electrode 13. Thus, in this example, resistor terminals 21, 22 and gate terminal 13 are formed of the same conductive material (e.g., metal).

[0262] Figure 28 C illustrates a later stage of the method, in which a first dielectric layer 41 is formed over the resistor and gate electrode, a semiconductor body 10 is formed over the first dielectric layer 41, then the source and drain electrodes 11, 12 of the transistor are formed, followed by the formation of a second dielectric layer 42 over the underlying structure. In some examples, the upper dielectric layer 42 may remain in this form, or it may be patterned to expose the surface of one or more terminals previously located below.

[0263] As described above, for certain applications, it is necessary to integrate Schottky diodes into integrated circuits that include at least one transistor and / or at least one resistor, as described above. It should be understood that the above teachings regarding the manufacture of electronic circuit modules including at least one resistor can be applied, with appropriate modifications, to the manufacture of circuit modules embodying other aspects of the invention and incorporating Schottky diodes and at least one transistor and / or at least one resistor.

[0264] Figure 29 An example of such a circuit module embodying the present invention is shown. This circuit module is similar to... Figure 27The circuit module shown is a top-contact, bottom-gate module, but additionally incorporates a Schottky diode 3000. This Schottky diode includes a first electrode 3001, formed in this example from the upper surface of substrate 5, similar to the bottom gate 13 of transistor 1. The diode includes a semiconductor material body 2010 connecting the first electrode 3001 and the second electrode 3002. The interface or junction between the first electrode 3001 and the diode body 3010 is arranged to provide a Schottky (rectifying) contact, and the interface or junction between the diode body 3010 and the upper electrode 3002 is arranged to be resistive. However, it should be understood that in alternative embodiments, the upper contact may be a rectifying contact, while the lower contact may be resistive, to meet requirements. Again, the circuit module includes a first dielectric layer 41 and a second dielectric layer 42, the second dielectric layer 42 being arranged such that the upper surface of either transistor body 10 or diode body 3010 is not exposed.

[0265] Now for reference Figure 30 It demonstrates the manufacturing process such as Figure 29 The steps of the circuit shown. Figure 30 In step A, the resistor body 20 is formed on the upper surface of the substrate 5, and a conductive layer 81 is formed on top. This conductive layer is then patterned to create resistor terminals 21 and 22, gate terminal 13, and the lower diode electrode 3001. Then, in... Figure 30 In C, a first dielectric layer is formed above the underlying structure and patterned to form a window exposing a portion of the upper surface of the lower electrode 3001 of the diode. In this example, the conductive layer 81 is composed of titanium (Ti). Figure 30 In step C, the exposed upper surface of the Ti electrode 3001 is oxidized by baking in air at 200°C to produce TiOx. This TiOx layer is shown as 3011 in the figure. Figure 30 D illustrates another stage in the manufacturing process, in which the diode body 3010 is formed by depositing an additional amount 3100 of metal oxide material to fill windows in the dielectric layer 41 and extending along the upper surface of the layer 41. The interface between the metal oxide material of the diode body 3010 and the oxide surface of the lower electrode 3001 provides a rectified Schottky contact. Another conductive material layer 810 is formed over this structure and then patterned to produce Figure 30In the structure shown in E, the remainder of the other conductive layer 810 provides transistor terminals 11, 12 and the upper terminal 3002 of the Schottky diode. Therefore, in this embodiment, the diode body 3010 is formed at a different time than the resistor body 20 (in this case, formed later). The diode body 3010 can be formed simultaneously with the transistor body 10 (e.g., under the same process conditions), or it can be formed at a different time than the transistor body (e.g., under different process conditions if the diode and transistor body need to have different electrical characteristics, or if separate formation is advantageous / desirable for other reasons).

[0266] from Figure 29 and 30 It should be understood that some embodiments of the present invention include Schottky diodes with vertical and horizontal offsets between their terminals, but it should also be understood that some alternative embodiments may include Schottky diodes having purely vertical or purely horizontal structures known in the art. In some embodiments, resistive TIOX on the electrode surface can be repaired, for example, by etching using CF4 / O2 or Cl.

[0267] Now for reference Figure 31 It illustrates another circuit module embodying the invention, this time including a top contact, a dual-gate transistor 1, a Schottky diode 3000, and a resistor 2. It is similar to... Figure 29 The illustrated embodiment, however, includes an additional top gate 132 (the previous gate is now labeled as the lower gate 131). Therefore, the conductivity characteristics of the semiconductor body 10 can be controlled by applying appropriate voltages to both the lower gate 131 and the upper gate 132. Such an embodiment is particularly suitable for analog circuits and provides additional control over the transistor threshold voltage by providing an additional gate. In use, the circuit can be arranged such that the same voltage is applied simultaneously to the lower gate 131 and the upper gate 132, or that separate voltages can be applied to the top and bottom gates. Providing a dual-gate transistor allows for higher mobility and enables the transistor to conduct larger currents.

[0268] Now for reference Figure 32This illustrates yet another circuit module embodying the invention, comprising a Schottky diode 3000, a first transistor 1A having an n-type semiconductor / channel 10A, and a second transistor 1B having a p-type semiconductor / channel 10B. Although the illustrated module combines transistors each with only a single gate, it should be understood that additional gates can be employed in one or both of transistors 1A and 1B, thus making them dual-gate transistors. In this example, the p-type semiconductor layer 10B is formed to partially contact terminals 11B and 12B that partially overlap with the upper surface of the substrate 5 and the second transistor 1B. The gate 13A of the first transistor 1A is also formed on the upper surface of the substrate 5, similar to the first electrode 3001 of the diode 3000. These various electrodes can all be formed simultaneously, for example from a common conductive material sheet, or they can be formed in different steps (e.g., if the conductive material required for the diode's first electrode 3001 is different from the material required for the transistor electrode). It should be understood that... Figure 32 The circuit module shown represents the integration of CMOS technology and Schottky diodes in an integrated circuit.

[0269] Figure 33-35 Various electronic circuits or circuit modules embodying the present invention and incorporating different combinations of Schottky diodes and / or resistors and / or transistors are shown.

[0270] Now for reference Figure 33 Up to 35, it should be understood that various circuits and circuit modules embodying the present invention may include combinations of at least one transistor and / or at least one resistor and / or at least one Schottky diode, for example, in the form of flexible integrated circuits / modules. Such circuits / modules include logic gates. Such logic gates may include one or more diodes, either as the sole active element (e.g., in "diode logic") or in combination with a transistor ("diode-transistor logic"). Two diode logic examples embodying the present invention and incorporating Schottky diodes are provided in... Figure 33 and 34 As shown in the image. Figure 33 A diode or gate embodying one aspect of the invention is shown, comprising two diodes, each having a corresponding anode connected to a corresponding input terminal and a corresponding cathode connected to an output terminal. The output terminal is grounded via a resistor. Figure 34 A diode AND gate embodying one aspect of the invention is shown, comprising two diodes, each having a corresponding cathode connected to a corresponding input terminal and a corresponding anode connected to an output terminal. The output terminal is connected to a positive power rail 1000 via a resistor. Using Schottky diodes in logic gates (e.g., in these embodiments) can provide advantages such as fast response and small voltage drop, among other benefits.

[0271] Another circuit module embodying the present invention is a diode load inverter, such as... Figure 35 As shown. A traditional unipolar inverter typically places a transistor switch and a resistive load between the high-voltage and low-voltage references. The inverter input is connected to the transistor gate terminal, and the inverter output is connected to the junction of the transistor and the resistor. In a diode-loaded inverter, the resistive load is replaced by a diode, for example... Figure 35 As shown in Figure 3535, using Schottky diodes as loads in diode load inverters can provide advantages such as fast switching, low voltage drop, and low power consumption.

[0272] Now for reference Figure 36 It shows a basic CMOS inverter that can operate with features such as Figure 32 The structure of the first and second transistors 1A and 1B shown is implemented in an integrated circuit.

[0273] As can be understood from the above, certain circuit modules embodied in this invention include dual-gate transistors, wherein a top gate and a bottom gate are provided on either side of the semiconductor channel or the body 10. In fact, another aspect of the invention provides a dual-gate transistor, and embodiments of this aspect are described below. Figure 37As shown in the diagram, transistor 1 includes a bottom gate 131 formed on the upper surface of the underlying substrate of structure 5. In some embodiments, the bottom gate 131 may be a conductive feature already present on the underlying structure. A first dielectric material layer or body 41 is formed over the bottom gate 131, and then an initial semiconductor material layer or body is formed over the first dielectric layer. The central portion of the semiconductor material layer forms the body or channel 10 of the transistor. Furthermore, a suitably processed portion of this initial semiconducting layer extending beyond the edge of the underlying lower gate terminal 131 provides the source and drain terminals 11, 12 of the device. In other words, the edge of the semiconductor channel 10 (and therefore the edges of the source and drain terminals 11, 12) coincides with the edge of the underlying lower gate terminal 131, such that when viewed from above, there is no overlap between the source or drain terminals 11, 12 and the lower gate 131, thereby minimizing any parasitic capacitance between the source and drain terminals and the gate 131. In other words, the projections of the source and drain terminals 11, 12 on the nominal horizontal plane (which typically corresponds to the plane of the upper surface of substrate 5 in this figure) do not overlap with the projection of the lower gate terminal 131 on that horizontal plane. In this embodiment, the source and drain terminals 11, 12 are extended by providing contacts 111 and 121 formed of a metallic material that partially overlap with each of the source and drain terminals 11, 12. A second dielectric layer 42 is formed over the semiconductor channel 10 and the extended source and drain electrodes, and the upper gate terminal 132 is formed over the second dielectric layer 42. The upper gate 132 is aligned with both the edge of the semiconductor channel 10 and the edge of the lower gate 131, and has the same projection on the horizontal plane as the projection of the lower gate electrode 131. In other words, the upper and lower gates are aligned and have the same footprint on the horizontal plane. Furthermore, when the source and drain terminals 11, 12 do not overlap with the lower gate terminal 131, they also do not overlap with the upper gate terminal 132. Therefore, any parasitic capacitance between the upper gate electrode 132 and the source and drain terminals is also reduced.

[0274] Therefore, it should be understood that Figure 37The dual-gate transistor shown is aligned such that its lower gate electrode 131, semiconductor channel 10, and upper gate electrode 132 form an aligned stack, with no overlap between the source and drain terminals and either gate terminal when viewed from a direction perpendicular to the nominal horizontal plane. This alignment can be achieved in various ways. In some embodiments, this alignment between the source and drain terminals 11 and 12 and the lower gate electrode 131 is achieved by forming the source and drain electrodes 11 and 12 from the corresponding portions of the initial semiconductor layer by irradiating them with electromagnetic radiation of an appropriate frequency (i.e., through the substrate 5, such that the radiation affects those irradiated portions, but the central portion forming the semiconductor channel 10 is shielded from radiation by the lower gate terminal 131, which must, of course, be opaque to radiation of the desired wavelength / frequency).

[0275] Now for reference Figure 38 It illustrates another dual-gate transistor embodying one aspect of the invention. This transistor has the same... Figure 37 A similar structure is shown, but here the underlying substrate 5 is a multilayer structure, and the lower gate electrode 131 is again disposed on the nominal upper surface of this structure 5. An initial amount of semiconductor material 100 is deposited over the lower dielectric layer 41 and the lower gate electrode 131, and portions of the layer extending laterally beyond the edge of the lower gate electrode 131 are again appropriately processed to change their electrical properties from semiconductive to resistive, thereby forming the source and drain terminals 11, 12. In this example, a second dielectric layer 42 partially covers the source and drain terminals 11, 12 and all of the semiconductor channels 10, and an upper gate electrode 132 is formed over this second dielectric layer 42, which is again aligned with the lower gate terminal 131 to reduce parasitic capacitance.

[0276] Now for reference Figure 39 It illustrates steps in a method suitable for manufacturing a dual-gate transistor embodying the present invention, which also embodies one aspect of the invention. Figure 39 In A, a substrate / structure 5 is provided, having a nominal upper surface 51 on which a lower gate terminal, for example formed of a suitable metal, is provided, and then as follows: Figure 39As shown in Figure B, a layer stack is formed above the lower gate terminal 131, comprising a first dielectric layer 41, a semiconductor material layer 100 (e.g., formed of metal oxide), and an upper dielectric material layer 42. This structure is then exposed to electromagnetic radiation (e.g., UV radiation) of an appropriate frequency from below. For this technique to work, the substrate 5 must, of course, be at least partially transparent to the radiation, and the lower gate terminal 131 should be opaque. By irradiating the structure from below, the lower gate electrode 131 shields the central portion of the semiconductor layer 100 from the radiation, while exposing portions of the semiconductor layer extending beyond the edges of the lower gate terminal 131. In other words, the lower gate 131 acts as a mask, and the interface between the exposed portion and the unexposed central portion of the semiconductor material is precisely aligned with the edges of the lower gate terminal 131. In other words, this technique enables “self-alignment” between the lower gate terminal and the source and drain terminals 11, 12 (which are respectively provided by corresponding portions of the initial semiconductor material exposed to radiation from below through the substrate). Appropriate selection of the radiation frequency and dose to cause the electrical properties of the previously exposed portion of the semiconductor material to change from semiconducting to conductive, because, as Figure 39 As shown in Figure C, these exposed portions form aligned source and drain terminals 11, 12 relative to the lower gate terminal 131.

[0277] Then, as Figure 39 As shown in Figure D, a resist material layer 9 is formed above this structure, and the resulting structure is again exposed to electromagnetic radiation from below, such that the lower gate 131 shields a portion of the resist layer 91 from radiation, but portions 92 on either side of the layer 9 are exposed. The frequency and dose of this radiation are again appropriately selected to produce the desired variation in the resist material 9, enabling it to be subsequently developed and processed to form a window W in the resist layer, which is aligned with the lower gate 131. It should be understood that the frequency and / or dose of this radiation used in the second reverse exposure step is generally different from the radiation used when converting portions of the semiconductor material into source and drain terminals 11, 12.

[0278] refer to Figure 39 E, This illustrates the subsequent steps, where after forming a window W in the resist layer 9 (which is precisely aligned with the lower gate 131), a conductive material 81 is deposited to form an aligned upper gate terminal 132 within the window W, wherein the remainder of the conductive material 81 covers the exposed portion 92 of the material on either side of the window W. The structure is then processed to remove or strip the remaining portion 92 of the resist material, leaving... Figure 39 F shows a structure including a self-aligned dual-gate transistor. In this example, the lower gate 131 serves as a mask in forming aligned source and drain terminals 11, 12 and in forming aligned upper gate terminal 132.

[0279] from Figure 39 As should be understood from the above description, the material used to form the upper electrode 132 in this example does not need to be radiotransparent to the radiation used in any exposure step.

[0280] Now for reference Figure 40 It illustrates an alternative technique embodying the present invention and used in the manufacture of self-aligned dual-gate transistors embodying the present invention. Figure 40 In A, a lower gate 131 is again provided on the upper surface of the substrate 5, and a stack of dielectric layers and an initial semiconductor material interlayer are formed above the lower gate 131. Figure 40 As shown in A (with arrow), this structure is exposed to suitable electromagnetic radiation from below, such that the lower gate 131 shields the central portion of the semiconductor material aligned with the lower gate 131 from the radiation and keeps it semiconducting. However, portions of the initial semiconductor material 100 on either side of the shielded portion are exposed to this radiation, and due to this radiation, its electrical conductivity typically becomes resistive. Figure 40 As shown in Figure B, these exposed portions form source and drain terminals 11 and 12. A conductive material layer 1320 is then formed over the underlying structure, and a resist material layer 9 is formed over the conductive material 1320. The structure is then exposed to electromagnetic radiation from below, such that the lower gate 131 again acts as a mask. The material for the conductive layer 1320 and the radiation in this second exposure step are selected such that the radiation can penetrate the conductive material layer 1320 and expose portions of the conductive material 1320 on either side of the lower gate 131. However, the lower gate 131 acts as a mask so that the radiation in the second exposure step does not expose the central portion 91 of the etchant material layer 9. The resist material is then processed such that only the exposed portions 92 are removed, leaving the central portion 91 covering the central portion of the conductive material layer 1320 aligned with the lower gate 131, as shown. Figure 40 As shown in C. Then, as Figure 40 As shown in D, the remaining portion 91 of the resist material is used as an etching mask to remove portions of the conductive material layer 1320 on either side of the etching mask 91, producing an upper gate 132 that is precisely aligned with the lower gate 131 and the source and drain 11, 12 (which, by producing, form portions of the initial semiconductor layer 100).

[0281] It should be understood that, in this embodiment, the material used for the top gate (i.e., the material of the conductive layer 1320) must be transparent to the radiation used in the second exposure step. However, the lower gate 131 is used as a mask when forming the source and drain terminals 11, 12 aligned with the lower gate and when forming the upper gate terminal 132 aligned with the lower gate terminal 131.

[0282] Now for reference Figure 41 It illustrates steps in another method embodying the invention for manufacturing a dual-gate transistor embodying the invention. For example... Figure 41 As shown in Figure A, the lower gate 131 is again disposed on another surface of the substrate 5, above which a series of layers are formed, including a first dielectric layer 41, an initial semiconductor material layer 100, a second dielectric layer 42, a conductive material layer 1320, and a resist material layer 9. The structure is then exposed to suitable radiation from below, such that the lower gate 131 shields the central portion of each of these layers aligned above the lower gate 131 from the radiation. Of course, in this example, except for the lower gate 131, it is required that each layer of the stack including the substrate 5 should be transparent to the radiation used in the first exposure. The radiation frequency and dose are selected so that it interacts appropriately with the exposed portion 92 of the resist layer 9, so that the resist layer can be subsequently processed to remove the exposed portion 92 and leave only the central shielding portion 91 as an etch mask. The central portion 91 is then used as an etch mask to remove a portion of the conductive material layer 1320, leaving only the aligned central portion forming the upper gate 132 (which has the same projection on the horizontal plane as the lower gate 131). Then, as Figure 41 As shown in C, the structure is again exposed to suitable radiation from below (i.e., through substrate 5), causing the unshielded portion of the initial semiconductor layer 100 to transform into a fundamentally resistive behavior, becoming the source and drain terminals 11, 12 aligned with the lower gate. The central portion of the previously semiconducting layer 100 is shielded by the lower gate 131, which acts as a mask, and becomes the semiconductor channel or body 10 of the dual-gate transistor.

[0283] Now for reference Figure 42 It illustrates alternative methods embodying the invention and steps for manufacturing a dual-gate transistor embodying the invention. Here, as... Figure 42 As shown in Figure A, a lower gate is again provided on the nominal upper surface of substrate 5. A dielectric material layer 41 is formed over the gate, and an initial semiconductor material layer 100 is formed over this dielectric layer. A resist material layer 9 is then formed over the semiconductor layer, and the structure is irradiated with suitable electron radiation from below the substrate, such that the central portion 91 of the resist layer is shielded from radiation by the gate 131, which serves as a mask, and a portion 92 on either side of the central portion is exposed to radiation. The radiation is arranged to have the desired effect on the resist material, thereby allowing the resist layer to be processed to remove the exposed portion 92 and leave the central portion 91 in place, aligned with the lower gate 131. This structure in Figure 42Figure B shows a conductive material layer 1320 formed, a portion of which covers the central portion of the resist material 91 aligned with the lower gate 131 and other portions of the conductive material on either side of the resist material 91 covering multiple portions of the semiconductor layer 100. The structure is then processed to strip away the remaining portion 91 of the resist material, while removing portions of the conductive layer formed on top of it, thus leaving only portions of the conductive material 1320 on either side of the bottom gate (i.e., whose edges are aligned with the edges of the bottom gate) and accordingly providing the source and drain terminals 11, 12. Therefore, in this example, the source and drain terminals are not formed from portions of the initial semiconductor layer, but are provided by portions of the conductive material self-aligned with the lower gate 131 using a technique that again uses the lower gate 131 as a mask. Then, as... Figure 42 As shown in Figure C, another dielectric material layer 42 is formed above the underlying structure, and another resist material layer 9 is formed above the second dielectric layer 42. The structure is then exposed again to electromagnetic radiation of appropriate frequency and dose from below to expose a portion 92 of the resist layer 9, but not the central portion 91. It should be understood that in this technique, the conductive material 1320 used to form the source and drain terminals 11, 12 must be suitable for… Figure 42 Radiation transparency is used in the second exposure step of C. This time, the resist material is treated to leave the exposed portion 92 in place, but a window W aligned with the lower gate 131 is formed by removing the exposed portion 91. Then as... Figure 42 As shown in Figure D, another conductive material layer 1320 is formed above the structure. This conductive material forms a conductive top grid 1320 within the window W, and a portion of the conductive material also covers the remaining portion 92 of the resist material on either side. The resist material is then further processed to peel off these portions 92, leaving... Figure 42 The structure shown in E. It should be understood that in this embodiment, a transparent conductive material is required to fabricate the source and drain terminals, but unlike other embodiments, these source and drain terminals are not fabricated from a portion of the initial semiconductor layer. However, the conductive material used to form the top gate 132 does not need to be transparent, as it is deposited within a window W formed by self-alignment with the lower gate 131.

[0284] Now for reference Figure 43 This illustrates another method embodying the invention and applicable to the manufacture of dual-gate transistors that also embody the invention. For example... Figure 43As shown in Figure A, a lower gate 131 is provided on substrate 5, and a three-layer stack is formed above the lower gate 131, comprising a first dielectric layer 41, a semiconductor material layer 100, and a second dielectric layer 42. A resist material layer 9 is formed above the underlying structure and then exposed to appropriate radiation from below (through substrate 5), such that the lower gate 131 shields the central portion 91 of the resist material from this radiation, exposing portions 92 on either side. The resist material is then appropriately processed to remove the unexposed portions 91, forming a window W in the resist layer 9. This window W is self-aligned to the lower gate 131, as the lower gate acts as a mask when forming the window. Then, as... Figure 43 As shown in Figure B, a conductive material layer 1320 has been formed, and a portion of this layer within the window forms the upper gate 132. The remaining portion and resist material 92 are then removed to produce... Figure 43 The structure shown in C. In this embodiment, the conductive material used for layer 1320 is... Figure 43 The radiation used in the second exposure step shown in Figure C is opaque. In this figure, the structure is exposed to radiation from above, such that the top gate 132 now acts as a mask, shielding the central portion 10 of the initial semiconducting layer 100 from the radiation from above, but exposing portions on either side whose conductivity increases with the effect of radiation, typically becoming conductive and forming the source and drain electrodes 11, 12. Therefore, in this example, an opaque lower gate 131 is used as a mask when fabricating the self-aligned upper gate 132, and then the upper gate 132 is used as a mask when fabricating the self-aligned gate and drain terminals 11, 12. Although Figure 43 C illustrates the use of the top gate as a mask in the fabrication of the source and drain terminals 11, 12; however, it should be understood that in alternative embodiments, the lower gate 131 can again be used as a mask for such purposes, wherein the substrate 5 is illuminated from below rather than above.

[0285] Now for reference Figure 44 As should be understood from the above description, certain thin-film transistor (TFT) devices embodying one aspect of the present invention can employ dual-gate electrodes. They may also employ a split-channel design. Such devices can also be integrated with resistors, Schottky diodes, and even more single-gate transistors. Figure 44In the illustrated embodiment, a bottom gate 131 is formed (or provided) on the nominal upper surface of the underlying structure (or substrate) 5. A dielectric material layer 41 covers the gate 131, and an initial semiconductor material body 100 is formed thereon. A second dielectric material layer 42 covers the underlying stacked structure, and a top gate 132 aligned with the bottom gate 131 has been formed using a suitable technique as described above, wherein the bottom gate serves as a mask. In this example, the top gate material is opaque to the radiation used in subsequent exposure steps, as described below. Also in this example, the initial semiconductor material body (e.g., comprising metal oxides) is not homogeneous but has a substructure comprising multiple layers. This separated or hierarchical channel feature can also be used in single-gate transistors, as described above with respect to alternative embodiments. Figure 44 In one embodiment, the channel provided by the central portion 10 of the initial semiconductor material body 100 comprises three layers 10(1), 10(2), and 10(3). Figure 44 As indicated by the arrows, by exposing the structure to suitable electromagnetic radiation from above, self-aligned (i.e., self-aligned to the gate) source and drain terminals 11, 12 are formed from portions of the initial semiconductor body 100. The top gate 132 shields (i.e., masks) this radiation from the central portion 10, maintaining the electrical properties of its three layers unchanged, while exposing the unmasked portion of the material 100 to the radiation alters its electrical properties to be substantially conductive rather than semiconductive. In other words, the radiation is arranged to permanently increase the conductivity of the exposed portion. Figure 44 The invention illustrates the device stacking and the self-alignment principle using optical radiation.

[0286] Further details regarding the discrete channels that can be used in embodiments of the present invention for bottom-gate, top-gate, or dual-gate transistors are as follows:

[0287] Separated channels typically consist of two or more layers of semiconductor, each with customized conductivity, mobility, carrier concentration, etc. These layers can be fabricated using different deposition conditions, such as different oxygen partial pressures during PVD, different PVD targets, such as different stoichiometric IGZO, and / or doping measures as described above. In self-aligned methods, the ends of the layered semiconductor body (e.g., Figure 44 (As shown) is irradiated to become conductive; these layers do not merge or diffuse, and their conductivity will differ from one another, but they are all conductive. Additional metal source / drain contacts can be arranged to electrically connect to these ends near the device (which themselves define the source and drain terminal portions that are in direct contact with the channel body 10). In a dual-gate three-layer channel device, as... Figure 44As shown, the two interface layers (i.e., 10(1) and 10(3)) in direct contact with either side of the dielectric layer (i.e., above and below the channel portion 10) can be arranged with a lower conductivity than the bulk (intermediate) layer 10(2), so that conduction mainly occurs at one (or both) clean interfaces between the three layers (in other words, at the interface between 10(1) and 10(2), and at the interface between 10(2) and 10(3)). This provides improved conduction characteristics, including higher current, higher mobility, etc. Alternatively, in a dual-gate 3-layer channel device, the conductivity of the two interface layers can be higher than that of the bulk (intermediate) layer, so conduction occurs in two essentially independent channels, each controlled by its respective gate. In a single-gate 2-layer channel device, the conductivity of the upper interface layer may be lower than that of the lower (bulk) layer, so conduction mainly occurs at the clean interface between the two layers. With the advantages described above, this separated (dual)-channel approach makes integration with Schottky and single-gate TFTs (and resistors) possible.

[0288] It should be understood that certain embodiments are applicable to the process of constructing FlexICs on a pre-existing structure rather than on a conventional (e.g., glass) carrier. Such a pre-existing structure may include an array of devices, components, or features having conductive surface layers to which the FlexIC devices need to be connected.

[0289] Some embodiments include at least one dual-gate TFT comprising a stack of gate terminals / gate insulators / semiconductors / source-drain terminals / gate insulators / gate terminals. The characteristics of the TFT can be better controlled by influencing the electric field in the semiconductor channel from opposite directions. For example, if the two gates are electrically connected to each other, the effective TFT on-current may be doubled because two channels are created at the two interfaces between the semiconductor and the respective gate dielectric.

[0290] When placing a FlexIC onto an existing structure, such as onto a partially completed substrate, conductive features or elements on the surface of the existing structure can be used as functional elements during device integration onto the partially completed substrate as described herein. This provides an opportunity to generate a self-aligned FlexIC containing a dual-gate TFT, for example, using conductive features on the surface of the partially completed substrate as the bottom gate of such a dual-gate TFT.

[0291] Advantageously, this can be achieved by connecting the two gates to achieve an effective 2 x Ion (i.e., doubling the “on” current), as described above. Alternatively, the dual gates can be independently controlled to move the threshold voltage (Vt) or create depletion-type / similar devices. Conventional lithography methods would imply a large gate on top to address coverage issues, while the self-aligned techniques described herein can fabricate a top gate with the same footprint as the bottom gate and precisely aligned with it. In some embodiments, further complexity can be added, for example, to a semiconductor stack, such as using multiple layers including highly doped / undoped layers. This can be arranged at only one semiconductor / gate dielectric interface or two such interfaces. Similar to the self-aligned top gate structure, the properties of the interface layers can be used to selectively dope / increase the conductivity of semiconductor regions (optionally included in the channel region). This approach can also be used to fabricate resistors. In some embodiments, the bottom gate can be used to align a second (top) gate (or a second gate and a second gate dielectric) using back-side exposure, creating a window (for “stripping”) or etch-mask aligned with the first gate. If integrated onto a partially completed substrate that emits radiation or provides other ways to activate the channel, the bottom gate can protect or prevent the channel from being illuminated by the LED / light source / other sources below. In practice, this also means that if the partially completed substrate below excites or temporarily or permanently dops an unprotected channel that extends laterally beyond the bottom gate, the system will "self-align" to the bottom gate. Device stacks can be designed so that the source and drain electrodes do not overlap with the gate (or either gate).

[0292] The same effect can be achieved by irradiating the device stack with UV light (e.g., from an excimer laser) from above or below to create self-aligned source-drain contacts (i.e., aligned with one or both gates). The top gate can also be aligned with the bottom gate electrode from the bottom of the substrate. Gate-source / drain overlap, rather than gate-gate overlap, is particularly important (in terms of reducing parasitic capacitance, but this approach allows for similar positional accuracy of the two gates relative to the SD).

[0293] In some embodiments, using a doped substrate (e.g., formed via ALD) can allow the creation of doped resistors. Suitable resistors include those with lateral or vertical orientations or a combination of both.

[0294] In some embodiments, the bottom layer may be formed as part of the bottom gate process (i.e., it may already be set on a partially completed substrate).

[0295] In some embodiments, the dual-gate architecture also provides the opportunity to form vertically stacked lateral capacitors integrated into the stack. This can provide more capacitance per unit area of ​​the FlexIC.

[0296] In some embodiments, the dual-gate TFT stack includes at least two ALD layers with the following electrodes: bottom gate / dielectric 1 / source-drain / dielectric 2 / top gate. The two ALD layers may be arranged to provide dopant to one or more channel layers.

[0297] Now for reference Figure 45 This illustrates another circuit module embodying the invention and including a self-aligned dual-gate transistor and a resistor. An initial semiconductor material layer (e.g., in an initial "normally off" state) has been formed over the bottom gate and the first dielectric layer 41. An aligned top gate 132 has been formed using the bottom gate as a mask, and the top gate is then used as a mask to shield the channel portion 10 from processing (exposed by radiation), thereby making a portion of the initial semiconductor layer resistive (to form the resistor body 20) and another portion conductive (to form the drain terminal 12). The resistor body 20 is thus directly connected to the semiconductor channel, effectively combining the transistor source and the second terminals 11, 22 of the resistor.

[0298] Now for reference Figure 46This illustrates another circuit module embodying the invention and including a resistor, a top-gate transistor, and a Schottky diode. This circuit module thus integrates three distinct devices, each comprising a corresponding material body comprising a corresponding amount of the same metal oxide. The module is based on a top-gate TFT structure, and the resistor is raised to be coplanar with the diode semiconductor layer, and / or formed directly or indirectly on the same dielectric layer as the diode semiconductor layer. One of the source / drain terminals of the transistor and one of the Schottky terminals are provided by a common terminal. This common terminal can therefore be described as the source / drain, interconnect, and Schottky diode electrode, provided by a single common conductive material body. In this example, the common terminal / body is formed to partially overlap with adjacent portions of the nominal upper surface of the transistor body and the underlying substrate. In this example, the transistor body can be formed first, for example directly on the substrate, and then the source / drain terminals of the transistor, one of which is the common electrode / interconnect of the Schottky diode, can be formed. A dielectric material layer or other body can then be formed over the transistor body and source / drain terminals, and a window or via can be formed down through the dielectric layer to expose a portion of the upper surface of the common electrode. A certain amount of metal oxide material for the diode and resistor bodies can then be formed / deposited / provided simultaneously or in separate processes. If provided in separate processes, the process conditions can be adjusted such that the amount of metal oxide material forming the diode body is formed in a semiconductor state (e.g., a "normally off" state), while the amount forming the resistor body is formed in a resistive state (i.e., having a higher conductivity than the diode body in a non-on (i.e., off) state). The diode body at least partially fills the window through the dielectric, contacts the common terminal, and also covers a portion of the upper surface of the dielectric, which also directly or indirectly supports the resistor body. The resistor terminals, transistor gate terminals, and upper terminals of the diode can be formed simultaneously, for example by selective deposition, printing, forming, and then patterning of the conductive material layer, or by any other suitable technique.

Claims

1. A method of manufacturing an electronic circuit or circuit module including a transistor and a resistor, the transistor including a source terminal, a drain terminal, a gate terminal, and a first material body providing a controllable semiconductor channel between the source terminal and the drain terminal, and the resistor including a first resistor terminal, a second resistor terminal, and a second material body providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: The first subject is formed; as well as Forming the second subject, The first body comprises a first amount of metal oxide, and the second body comprises a second amount of the metal oxide. The formation of the first body includes forming the first amount of the metal oxide, and the formation of the second body includes forming the second amount of the metal oxide. The formation of the first quantity is performed before or after the formation of the second quantity.

2. The method of claim 1, wherein forming the first amount comprises forming the first amount directly or indirectly on a first region of the substrate, and forming the second amount comprises forming the second amount directly or indirectly on a second region of the substrate.

3. The method of claim 1, wherein the formation of the first quantity comprises forming the first quantity using a technique selected from the list comprising: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

4. The method of claim 1, wherein the formation of the second quantity comprises forming the second quantity using a technique selected from the list of the following: physical deposition; physical vapor deposition (PVD); chemical deposition; chemical vapor deposition (CVD); atomic layer deposition (ALD); physicochemical deposition; vapor deposition; sputtering; sol-gel technology; chemical bath deposition; spray pyrolysis; electroplating technology; pulsed laser deposition (PLD); solution treatment; and spin coating.

5. The method of claim 1, wherein the formation of the first amount comprises forming a first layer, film, or sheet of the metal oxide, the first layer, film, or sheet comprising the first amount.

6. The method of claim 5, wherein the formation of the first body comprises patterning the first layer, film, or sheet.

7. The method of claim 1, wherein the formation of the second amount comprises forming a second layer, film, or sheet of the metal oxide, the second layer, film, or sheet comprising the second amount.

8. The method of claim 7, wherein the formation of the second body comprises patterning the second layer, film, or sheet.

9. The method of claim 1, further comprising doping the first material body with a first dopant to reduce or increase the electrical conductivity of the first body.

10. The method of claim 9, wherein doping the first material body comprises forming the first amount on a source of the first dopant.

11. The method of claim 10, further comprising providing the source of the first dopant directly or indirectly on the first region of the substrate.

12. The method of claim 9, wherein doping the first material body includes a source for forming the first dopant on the first material body.

13. The method of claim 1, further comprising doping the second material body with a second dopant to increase or decrease the electrical conductivity of the second body.

14. The method of claim 13, wherein doping the second material body includes forming the second amount on the source of the second dopant.

15. The method of claim 14, further comprising providing the source of the second dopant directly or indirectly on the second region of the substrate.

16. The method of claim 13, wherein doping the second material body includes a source for forming the second dopant on the second material body.

17. The method of claim 1, further comprising processing the second body to increase or decrease the conductivity of the second body.

18. The method of claim 17, wherein processing the second body comprises annealing at least a portion of the second body to increase or decrease its electrical conductivity.

19. The method of claim 17, wherein, The treatment of the second body includes exposing at least a portion of the second body to electromagnetic radiation.

20. The method of claim 19, further comprising providing the electromagnetic radiation from at least one of the lamps or lasers.

21. The method of claim 19, further comprising shielding at least a portion of the first body from the electromagnetic radiation.

22. The method of claim 21, wherein the shielding comprises shielding the electromagnetic radiation of at least a portion of the first body or at least a portion of the first amount using the gate terminal.

23. The method of claim 1, wherein forming the first amount comprises depositing the first amount of the metal oxide.

24. The method of claim 1, wherein forming the second amount comprises depositing the metal oxide of the second amount.

25. The method according to claim 1, wherein the first body and the second body are formed under different conditions.

26. The method of claim 1, wherein the different conditions cause the first body to have different electrical characteristics than the second body.

27. The method of claim 1, wherein forming the first amount comprises performing physical vapor deposition in the presence of oxygen.

28. The method of claim 1, wherein forming the second amount comprises physical vapor deposition in the presence of oxygen.

29. The method according to claim 1, wherein: Forming the first quantity includes physical vapor deposition in the presence of oxygen; The formation of the second quantity includes physical vapor deposition in the presence of oxygen; and The partial pressure of oxygen during the formation of the first quantity is different from the partial pressure of oxygen during the formation of the second quantity.

30. The method of claim 1, wherein the electronic circuit or circuit module is an inverter circuit or a NOT gate.

31. The method of claim 1, wherein the electronic circuit or circuit module further comprises a first voltage power rail and a second voltage power rail, and wherein the resistor is a load resistor connected in series between one of the source terminal and one of the drain terminal and one of the voltage power rails.

32. The method of claim 1, wherein the electronic circuit or the circuit module is flexible.

33. The method of claim 1, further comprising providing a substrate arranged to directly or indirectly support each of the transistor and the resistor, and the formation of the first body and the second body comprising forming the first body on or over a first region of the substrate and forming the second body on or over a second region of the substrate, wherein the substrate is flexible.

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