Process method for controlling gate height of NFET and PFET
By forming an etch stop layer on top of the polysilicon gate to protect the hard mask layer, the problem of inconsistent gate heights between NFETs and PFETs caused by germanium-silicon processes is solved, achieving gate height consistency and cost savings.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-02
AI Technical Summary
In existing high-dielectric-constant metal gate processes, the germanium-silicon process reduces the gate height of PFETs, leading to inconsistencies in gate heights between NFETs and PFETs, and increasing process complexity and cost.
An etch stop layer is formed on top of the polysilicon gate. After the gate region is defined by photolithography, the etch stop layer protects the hard mask layer, prevents loss during the device enhancement process, maintains the gate height consistency of NFET and PFET, and removes the etch stop layer by wet etching to save costs.
This achieves consistency in gate height between NFET and PFET, simplifies the process flow, reduces photomask and process costs, and avoids device characteristic anomalies caused by gate height differences.
Smart Images
Figure CN122138451A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a process method for controlling the gate height of NFETs and PFETs. Background Technology
[0002] In existing high-kJ metal gate (HKMG) processes, a dummy gate structure is used before gate replacement. This dummy gate structure typically consists of a gate dielectric layer, a polysilicon gate, and a silicon nitride hard mask (HM) layer and a silicon oxide hard mask layer stacked on top of the polysilicon gate. To improve device performance, device enhancement processes are often introduced. For example, to improve the carrier mobility of a PFET (P-type MOSFET), a germanium-silicon (SiGe) process is used to form embedded germanium-silicon epitaxial layers on both sides of the dummy gate structure. However, the germanium-silicon process causes losses in the silicon oxide hard mask layer, reducing the gate height of the PFET and resulting in a height difference between the gates of an NFET (N-type MOSFET) and a PFET. A photoresist etch-back (PREB) process is then introduced to eliminate this height difference, effectively improving device characteristic anomalies caused by gate height drift. Adopting simpler and more efficient processes to reduce process steps and save production costs has become another research direction. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a process method for controlling the gate height of NFET and PFET, which can prevent the enhancement process from having an adverse effect on the gate height, thereby making the gate height of NFET and PFET consistent and saving process costs.
[0004] To solve the above-mentioned technical problems, the present invention provides a process method for controlling the gate height of NFETs and PFETs, comprising: Step 1: Provide a semiconductor substrate, and sequentially form a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate.
[0005] Step 2: Form a hard mask layer on the surface of the polysilicon gate.
[0006] Step 3: Form an etching stop layer on the surface of the hard mask layer.
[0007] Step 4: Photolithography defines the formation region of the gate, and then the etch stop layer is etched for the first time to remove the etch stop layer outside the formation region of the gate.
[0008] Step 5: Using the etch stop layer as a mask, perform a second etching on the hard mask layer and the polysilicon gate to transfer the pattern of the etch stop layer into the hard mask layer and the polysilicon gate to form a gate structure; the gate structure is formed by superimposing the gate dielectric layer, the patterned polysilicon gate, and the hard mask layer; the gate structure includes a first gate structure of an NFET and a second gate structure of a PFET.
[0009] Step 6: Perform component enhancement process. In the component enhancement process, the etch stop layer is used to protect the hard mask layer, prevent the hard mask layer from being damaged, and thus make the height of the first gate structure and the second gate structure consistent.
[0010] Step 7: Remove the etching stop layer.
[0011] A further improvement is that the hard mask layer is composed of a first silicon nitride layer and a second silicon oxide layer stacked together.
[0012] A further improvement is that the etch stop layer includes a first TiN layer.
[0013] A further improvement is that a second silicon nitride layer is formed on the surface of the first TiN layer.
[0014] A further improvement is that the first etching includes etching of the second silicon nitride layer and etching of the first TiN layer.
[0015] The first TiN layer was etched using a wet etching process.
[0016] A further improvement is that SC1 is used as the etching solution for etching the first TiN layer. SC1 is also known as solution number one.
[0017] A further improvement is that the etching of the second silicon nitride layer includes dry etching.
[0018] A further improvement is that the second silicon nitride layer retained after the first etching is consumed during the second etching process.
[0019] A further improvement is that, in step six, the element enhancement process includes forming an embedded germanium-silicon epitaxial layer on both sides of the second gate structure, and the source and drain regions of the PFET are formed in the embedded germanium-silicon epitaxial layer.
[0020] A further improvement is that, in step seven, the etching stop layer is removed by wet etching.
[0021] A further improvement is that, after step six and before step seven, the following is also included: The first metal layer and the second TiN layer are formed sequentially.
[0022] A metal silicide reaction is performed to form metal silicides on the semiconductor substrate surfaces on both sides of each gate structure through self-alignment.
[0023] Then, step seven, wet etching, is performed to simultaneously remove the second TiN layer, the remaining first metal layer, and the first TiN layer.
[0024] A further improvement is that the material of the first metal layer includes NiPt, and the metal silicide is NiSi.
[0025] A further improvement is that the wet etching in step seven includes sequential etching of SPM and SC1.
[0026] A further improvement is that, after step six and before the formation of the first metal layer, the following is also included: Sidewalls are formed on the sides of each of the gate structures.
[0027] The N+ doped source / drain regions of the NFET are formed on the side of each of the first gate structures, and the P+ doped source / drain regions of the PFET are formed on the side of each of the second gate structures.
[0028] A further improvement is that the semiconductor substrate simultaneously includes a core region and an input / output region, wherein the core region includes a core NFET and a core PFET, and the input / output region includes an input / output NFET and an input / output PFET.
[0029] This invention, after forming the hard mask layer on top of the polysilicon gate, does not directly perform photolithography. Instead, it first forms an etch stop layer, then performs photolithography to define the gate formation region. Subsequently, the etch stop layer, hard mask layer, and polysilicon gate are etched sequentially. The addition of the etch stop layer does not affect the etching of the polysilicon gate and does not require an additional photomask. It also saves on adjusting the photomask due to inconsistent gate heights and the introduction of other associated processes. Because the hard mask layer has an etch stop layer on top, after the gate structure is formed, during device enhancement processes such as the formation of the embedded germanium-silicon epitaxial layer for PFETs, the etch stop layer on the surface of the hard mask layer protects the hard mask layer, preventing it from being damaged. This maintains the gate structure height and ensures consistency between the gate heights of NFETs and PFETs. Therefore, this invention prevents the device enhancement process from adversely affecting the gate height, thus ensuring consistency between the gate heights of NFETs and PFETs.
[0030] In addition, in this invention, the etching stop layer can be TiN, and the photolithography during patterning directly uses the photomask that defines the formation area of the gate. Sharing the photomask can reduce the process cost, so this invention can also save process costs.
[0031] In addition, in this invention, the etching stop layer can be removed by a wet etching process, which is beneficial for process integration and can further reduce costs. Attached Figure Description
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of a process method for controlling the gate height of NFET and PFET according to an embodiment of the present invention; Figures 2-8 This is a schematic diagram of the device structure in each step of the process method for controlling the gate height of NFET and PFET according to an embodiment of the present invention. Detailed Implementation
[0033] like Figure 1 The diagram shown is a flowchart of a process method for controlling the gate height of NFETs and PFETs according to an embodiment of the present invention; as shown... Figures 2 to 8 The diagram shown is a schematic representation of the device structure in each step of the process method for controlling the gate height of NFET and PFET according to an embodiment of the present invention. The process method for controlling the gate height of NFET and PFET according to an embodiment of the present invention includes: Step 1, such as Figure 2 As shown, a semiconductor substrate 101 is provided, and a gate dielectric layer (not shown) and a polysilicon gate 103 are sequentially formed on the surface of the semiconductor substrate 101.
[0034] In this embodiment of the invention, the semiconductor substrate 101 includes both a core region and an input / output (IO) region. The core region includes a core NFET and a core PFET, and the input / output region includes an input / output NFET and an input / output PFET. Figure 2 In the diagram, region 101a is the formation region of the core NFET, region 101b is the formation region of the core PFET, region 101c is the formation region of the IO NFET, and region 101d is the formation region of the IO PFET.
[0035] In some embodiments, the semiconductor substrate 101 is a silicon substrate. Shallow trench isolation 102 is also formed in the semiconductor substrate 101.
[0036] Step 2: Form a hard mask layer 104 on the surface of the polysilicon gate 103.
[0037] In this embodiment of the invention, the hard mask layer 104 is formed by stacking a first silicon nitride layer 104a and a second silicon oxide layer 104b.
[0038] Figure 2 In the diagram, the plane corresponding to the dashed line AA is the top surface of the hard mask layer 104.
[0039] Step 3: Form an etching stop layer on the surface of the hard mask layer 104.
[0040] In this embodiment of the invention, the etching stop layer includes a first TiN layer 105.
[0041] A second silicon nitride layer 106 is also formed on the surface of the first TiN layer 105.
[0042] Step 4, as follows Figure 3 As shown, photolithography forms a photoresist pattern 107 that defines the formation area of the gate. At this time, the photomask used in photolithography is the photomask corresponding to the gate, that is, the polysilicon gate, so that the formation area of the gate can be defined.
[0043] The etch stop layer is then etched for the first time to remove the etch stop layer outside the formation region of the gate.
[0044] In this embodiment of the invention, the first etching includes, for example: Figure 4 The etching of the second silicon nitride layer 106 shown and as follows Figure 5 The etching of the first TiN layer 105 is shown.
[0045] The etching of the second silicon nitride layer 106 includes dry etching.
[0046] The first TiN layer 105 is etched using a wet etching process. In some embodiments, the etching solution used for etching the first TiN layer 105 is SC1.
[0047] Step 5, as follows Figure 6 As shown, the hard mask layer 104 and the polysilicon gate 103 are sequentially etched a second time using the etch stop layer as a mask to transfer the pattern of the etch stop layer into the hard mask layer 104 and the polysilicon gate 103 to form a gate structure; the gate structure is formed by superimposing the gate dielectric layer and the patterned polysilicon gate 103 and the hard mask layer 104; the gate structure includes a first gate structure of NFET and a second gate structure of PFET.
[0048] In this embodiment of the invention, the second silicon nitride layer 106 retained after the first etching will be consumed during the second etching process.
[0049] Step Six, as Figure 6 As shown, a component enhancement process is performed. In this process, the etch stop layer is used to protect the hard mask layer 104, preventing the hard mask layer 104 from being damaged and thus ensuring that the heights of the first gate structure and the second gate structure are consistent.
[0050] In this embodiment of the invention, the component enhancement process includes forming an embedded germanium-silicon epitaxial layer 108 on both sides of the second gate structure, and the source and drain regions of the PFET are formed in the embedded germanium-silicon epitaxial layer 108. Due to the protection of the etch stop layer, i.e., the first TiN layer 105, the second silicon oxide layer 104b is not damaged during the formation of the embedded germanium-silicon epitaxial layer 108; therefore, the top surface of the second silicon oxide layer 104b remains at the position indicated by the dashed line AA.
[0051] Step 7, as follows Figure 8 As shown, the etching stop layer is removed.
[0052] In this embodiment of the invention, in step seven, the etching stop layer is removed by wet etching.
[0053] In this embodiment of the invention, after step six and before step seven, the following steps are also included: like Figure 7 As shown, sidewalls 109 are formed on the sides of each of the gate structures. In some embodiments, the material of the sidewalls 109 includes SiN.
[0054] The N+ doped source / drain regions of the NFET are formed on the side of each of the first gate structures, and the P+ doped source / drain regions of the PFET are formed on the side of each of the second gate structures.
[0055] A first metal layer 110 and a second TiN layer 111 are formed sequentially.
[0056] A metal silicide reaction is performed to form metal silicides 110a on the surface of the semiconductor substrate 101 on both sides of each gate structure by self-alignment.
[0057] like Figure 8 As shown, step seven, wet etching, is then performed to simultaneously remove the second TiN layer 111, the remaining first metal layer 110, and the first TiN layer 105. That is, in this embodiment of the invention, it is not necessary to perform separate wet etching to remove the etching stop layer. Instead, the etching stop layer is simultaneously removed by wet etching, which removes the second TiN layer 111 and the remaining first metal layer 110 during the formation of the metal silicide 110a. This saves process steps and costs.
[0058] In some embodiments, the material of the first metal layer 110 includes NiPt, and the metal silicide 110a is NiSi.
[0059] Step seven, wet etching, includes sequential etching of SPM and SC1.
[0060] Depend on Figure 8 As shown, the gate structures of Core NFET, Core PFET, IO NFET and IO PFET have the same height, eliminating the influence of the component enhancement process on the different gate structure heights of the devices in the existing methods.
[0061] In this embodiment of the invention, after forming the hard mask layer 104 on top of the polysilicon gate 103, photolithography is not performed directly. Instead, an etch stop layer is formed first, followed by photolithography to define the gate formation region. Then, the etch stop layer, hard mask layer 104, and polysilicon gate 103 are etched sequentially. The addition of the etch stop layer does not affect the etching of the polysilicon gate 103 and does not require an additional photomask. Because the hard mask layer 104 has an etch stop layer on top, after the gate structure is formed, a device enhancement process such as PFE is performed. During the formation process of the embedded germanium-silicon epitaxial layer 108 of T, since an etch stop layer is formed on the surface of the hard mask layer 104, the etch stop layer protects the hard mask layer 104 during the device enhancement process, thereby preventing the hard mask layer 104 from being damaged. This allows the height of the gate structure to be maintained and the gate heights of the NFET and PFET to be kept consistent. Therefore, the embodiments of the present invention can prevent the device enhancement process from having an adverse effect on the gate height, thereby ensuring that the gate heights of the NFET and PFET are kept consistent.
[0062] In addition, in this embodiment of the invention, the etching stop layer can be TiN, and the photolithography during patterning directly uses the photomask that defines the formation area of the gate. Sharing the photomask can reduce the process cost, so this embodiment of the invention can also save process cost.
[0063] In addition, in this embodiment of the invention, the etching stop layer can be removed by a wet etching process, which is beneficial for process integration and can further reduce costs.
[0064] To avoid gate height drift caused by gate height difference due to SiGe process, which leads to abnormal device characteristics, this embodiment of the invention utilizes the original poly mask to grow an etch stop layer protecting the gate structure of N / PPET (NFET and PFET) before gate etching. After adjusting the PFET, the etch stop layer is cleaned by wet etching (WET) to ultimately achieve a consistent gate height across different devices.
[0065] Since the embodiments of the present invention utilize a poly mask as a mask layer and complete the process through simple film growth and wet cleaning, it can achieve consistent gate height while reducing production costs.
[0066] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A process method for controlling the gate height of NFETs and PFETs, characterized in that, include: Step 1: Provide a semiconductor substrate, and sequentially form a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate; Step 2: Form a hard mask layer on the surface of the polysilicon gate; Step 3: Form an etching stop layer on the surface of the hard mask layer; Step 4: Photolithography defines the formation region of the gate, and then the etch stop layer is etched for the first time to remove the etch stop layer outside the formation region of the gate; Step 5: Using the etch stop layer as a mask, perform a second etching on the hard mask layer and the polysilicon gate to transfer the pattern of the etch stop layer into the hard mask layer and the polysilicon gate to form a gate structure; the gate structure is formed by stacking the gate dielectric layer, the patterned polysilicon gate, and the hard mask layer; the gate structure includes a first gate structure of an NFET and a second gate structure of a PFET; Step 6: Perform component enhancement process. In the component enhancement process, the etch stop layer is used to protect the hard mask layer, prevent the hard mask layer from being damaged, and thus make the height of the first gate structure and the second gate structure consistent. Step 7: Remove the etching stop layer.
2. The process method for controlling the gate height of NFET and PFET as described in claim 1, characterized in that: The hard mask layer is composed of a first silicon nitride layer and a second silicon oxide layer stacked together.
3. The process method for controlling the gate height of NFET and PFET as described in claim 1, characterized in that: The etch stop layer includes a first TiN layer.
4. The process method for controlling the gate height of NFET and PFET as described in claim 3, characterized in that: A second silicon nitride layer is also formed on the surface of the first TiN layer.
5. The process method for controlling the gate height of NFET and PFET as described in claim 4, characterized in that: The first etching includes etching the second silicon nitride layer and etching the first TiN layer; The first TiN layer was etched using a wet etching process.
6. The process method for controlling the gate height of NFET and PFET as described in claim 5, characterized in that: The etching solution used for etching the first TiN layer is SC1.
7. The process method for controlling the gate height of NFET and PFET as described in claim 5, characterized in that: The etching of the second silicon nitride layer includes dry etching.
8. The process method for controlling the gate height of NFET and PFET as described in claim 5, characterized in that: The second silicon nitride layer retained after the first etching will be consumed during the second etching process.
9. The process method for controlling the gate height of NFET and PFET as described in claim 1, characterized in that: In step six, the element enhancement process includes forming an embedded germanium-silicon epitaxial layer on both sides of the second gate structure, and the source and drain regions of the PFET are formed in the embedded germanium-silicon epitaxial layer.
10. The process method for controlling the gate height of NFET and PFET as described in claim 8, characterized in that: In step seven, the etching stop layer is removed by wet etching.
11. The process method for controlling the gate height of NFET and PFET as described in claim 10, characterized in that: After step six and before step seven, the following is also included: The first metal layer and the second TiN layer are formed sequentially; Metal silicide is formed on the surface of the semiconductor substrate on both sides of each gate structure by self-alignment through a metal silicide reaction. Then, step seven, wet etching, is performed to simultaneously remove the second TiN layer, the remaining first metal layer, and the first TiN layer.
12. The process method for controlling the gate height of NFET and PFET as described in claim 11, characterized in that: The material of the first metal layer includes NiPt, and the metal silicide is NiSi.
13. The process method for controlling the gate height of NFET and PFET as described in claim 11, characterized in that: Step seven, wet etching, includes sequential etching of SPM and SC1.
14. The process method for controlling the gate height of NFET and PFET as described in claim 11, characterized in that: The process includes the following steps after step six and before the formation of the first metal layer: Sidewalls are formed on the sides of each of the gate structures; The N+ doped source / drain regions of the NFET are formed on the side of each of the first gate structures, and the P+ doped source / drain regions of the PFET are formed on the side of each of the second gate structures.
15. The process method for controlling the gate height of NFET and PFET as described in claim 1, characterized in that: The semiconductor substrate includes a core region and an input / output region. The core region includes a core NFET and a core PFET, and the input / output region includes an input / output NFET and an input / output PFET.