Complementary field effect transistor and method of manufacturing the same, electronic device

Abstract

This application provides a complementary field-effect transistor (CFPT) and its fabrication method, as well as an electronic device. The fabrication method includes: forming a first active structure and a second active structure stacked sequentially on a substrate; depositing a first dummy gate structure and a second dummy gate structure stacked sequentially on the substrate; removing the first active structure and the second active structure located in the source / drain region; forming a bottom source / drain structure based on the second active structure in the gate region, and forming a top source / drain structure above the bottom source / drain structure based on the first active structure in the gate region; removing the first dummy gate structure and depositing a first metal material above the second dummy gate structure to form a top metal gate; flipping the top transistor and removing the substrate to expose the second dummy gate structure; removing the second dummy gate structure and depositing a second metal material above the top metal gate to form a bottom metal gate; the work function value of the top metal gate and the work function value of the bottom metal gate are different.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a complementary field-effect transistor, its fabrication method, and electronic devices. Background Technology

[0002] With Moore's Law continuously evolving, especially after the gate-all-around (GAA) technology node, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, which helps to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] In the implementation scheme of related stacked transistors, since the N-channel metal-oxide-semiconductor (NMOS) and the P-channel metal-oxide-semiconductor (PMOS) are stacked vertically in the vertical direction, this brings about a unique work-function metal (WFM) filling problem. Summary of the Invention

[0004] This application provides a complementary field-effect transistor and its fabrication method, as well as an electronic device, which can achieve a low aspect ratio gate work function metal filling process by filling and removing a pseudo-gate structure, thereby flexibly adjusting the threshold voltage of N-type transistors and P-type transistors.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a method for fabricating a complementary field-effect transistor (CFPT). The method includes: forming a first active structure and a second active structure stacked sequentially on a substrate, wherein the first active structure is farther from the substrate than the second active structure; depositing a first dummy gate structure and a second dummy gate structure stacked sequentially on the substrate, wherein the first dummy gate structure is opposite to the first active structure, and the second dummy gate structure is opposite to the second active structure; the first dummy gate structure and the second dummy gate structure are located in a gate region; removing the first active structure and the second active structure located in a source-drain region; forming a bottom source-drain structure based on the second active structure in the gate region; and above the bottom source-drain structure, forming a first active structure based on the first active structure in the gate region... An active structure is formed to create a top source / drain structure; a first dummy gate structure is removed, and a first metal material is deposited over a second dummy gate structure to form a top metal gate, wherein the top metal gate and the top source / drain structure are contained within a top transistor; the top transistor is flipped and the substrate is removed to expose the second dummy gate structure; the second dummy gate structure is removed, and a second metal material is deposited over the top metal gate to form a bottom metal gate, wherein the bottom metal gate and the bottom source / drain structure are contained within a bottom transistor, and the top transistor and the bottom transistor have different polarities; the work function value of the top metal gate and the work function value of the bottom metal gate are different.

[0007] This application provides a complementary field-effect transistor (CFAT) fabricated using the above method, comprising: a top transistor and a bottom transistor stacked together; wherein the top transistor and the bottom transistor have different polarities; the top metal gate of the top transistor is formed by deposition of a first metal material, and the bottom metal gate of the bottom transistor is formed by deposition of a second metal material; the work function values ​​of the first metal material and the second metal material are different.

[0008] This application provides an electronic device, including: a circuit board and the aforementioned complementary field-effect transistor located on the circuit board.

[0009] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0010] In this embodiment, a first pseudo-gate structure opposite to the first active structure and a second pseudo-gate structure opposite to the second active structure can be formed in the gate region of the complementary field-effect transistor. These independent first and second pseudo-gate structures separate the gate regions of the top and bottom transistors. This allows for the independent implementation of the replacement metal gate (RMG) process for the top transistor by removing the first pseudo-gate structure alone, and the independent implementation of the bottom transistor's RMG process by removing the second pseudo-gate structure alone after a single wafer flip. Here, the RMG process only requires a low aspect ratio gate work function metal filling process to fill the gate region corresponding to each transistor, thus forming a metal gate structure. This significantly reduces the complexity of using a high aspect ratio gate work function metal filling process to fill the gate region of the bottom transistor in related technologies, thereby enabling more flexible adjustment of the threshold voltage of the complementary field-effect transistor.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0013] Figure 1 This is a flowchart illustrating a method for fabricating a complementary field-effect transistor according to an exemplary embodiment.

[0014] Figure 2 This is a top view of a complementary field-effect transistor according to an exemplary embodiment.

[0015] Figures 3 to 21 This is a schematic diagram illustrating the fabrication process of a first type of complementary field-effect transistor according to an exemplary embodiment.

[0016] Figures 22 to 25 This is a schematic diagram illustrating the fabrication process of a second complementary field-effect transistor according to an exemplary embodiment.

[0017] Figure 26 This is a schematic diagram of a complementary field-effect transistor according to an exemplary embodiment.

[0018] The reference numerals and names in the figure are as follows:

[0019] 20. Substrate; 21. Initial stacked structure; 22. First active structure; 23. First sacrificial layer; 24. Second active structure; 25. Second sacrificial layer; 26. Shallow trench isolation structure; 27. First dummy gate structure; 28. Intermediate dielectric layer; 29. ​​Second dummy gate structure; 30. Dummy gate sidewall; 31. Intermediate isolation dielectric layer; 32. Barrier layer; 33. Bottom source / drain structure; 34. Bottom interlayer dielectric structure; 35. Insulating layer; 36. Top source / drain structure; 37. Top interlayer dielectric structure; 38. Gate dielectric layer; 39. Top metal gate; 40. Top source / drain metal; 41. Diffusion barrier structure; 42. Top metal interconnect layer; 43. Carrier wafer; 44. Bottom metal gate; 45. Bottom source / drain metal; 46. Bottom metal interconnect layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] In the following description, the terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] In related technologies, N-type and P-type transistors in stacked transistors are vertically stacked in the same vertical direction. This presents significant technological challenges for realizing the metal gate of the transistors, such as high aspect ratios and the difficulty of etching the metal. Complementary field-effect transistors (CFETs), in particular, require high aspect ratio processes to deposit the bottom gate material within a single gate trench, remove the bottom gate material covering the top active structure through etching, and finally re-deposit the top gate material around the top active structure using a gate trench. It is evident that the high aspect ratio processes in these technologies limit the thickness selection of the work function metal, and the thickness of the WFM limits the range of work function control, making it difficult to achieve multiple degrees of freedom in controlling threshold voltages.

[0024] To address the aforementioned technical problems, embodiments of this application provide a complementary field-effect transistor and its fabrication method, as well as an electronic device, which can achieve a low aspect ratio gate work function metal filling process by filling and removing a pseudo-gate structure, thereby flexibly adjusting the threshold voltages of the N-type and P-type transistors in the complementary field-effect transistor.

[0025] In a first aspect, embodiments of this application provide a method for fabricating a complementary field-effect transistor. Figure 1 This is a flowchart illustrating a method for fabricating a complementary field-effect transistor according to an exemplary embodiment. See also... Figure 1 As shown, the fabrication method of a complementary field-effect transistor may include steps 101 to 107.

[0026] Step 101: Form a first active structure and a second active structure stacked sequentially on the substrate, wherein the first active structure is farther away from the substrate than the second active structure.

[0027] Step 102: Deposit a first pseudo-gate structure and a second pseudo-gate structure stacked sequentially on the substrate, wherein the first pseudo-gate structure is opposite to the first active structure and the second pseudo-gate structure is opposite to the second active structure; the first pseudo-gate structure and the second pseudo-gate structure are located in the gate region.

[0028] Step 103: Remove the first and second active structures located in the source-drain region.

[0029] Step 104: A bottom source / drain structure is formed based on the second active structure within the gate region, and a top source / drain structure is formed above the bottom source / drain structure based on the first active structure within the gate region.

[0030] Step 105: Remove the first dummy gate structure and deposit a first metal material over the second dummy gate structure to form a top metal gate, wherein the top metal gate and the top source / drain structure are contained in the top transistor.

[0031] Step 106: Flip the top transistor and remove the substrate to expose the second pseudo-gate structure.

[0032] Step 107: Remove the second pseudo-gate structure and deposit a second metal material over the top metal gate to form a bottom metal gate, wherein the bottom metal gate and the bottom source / drain structure are contained in the bottom transistor, the top transistor and the bottom transistor have different polarities, and the work function value of the top metal gate is different from that of the bottom metal gate.

[0033] In the embodiments of this application, the substrate is used to support the entire device structure. The substrate can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a structure formed from a bulk silicon substrate, an SOI substrate, or other substrates. The embodiments of this application do not limit this.

[0034] In some embodiments, the substrate may be a bulk silicon substrate. An initial stacked structure can be formed by depositing semiconductor material on the bulk silicon substrate; subsequently, an active structure can be formed by etching the initial stacked structure. The active structure includes at least a first active structure and a second active structure.

[0035] In some embodiments, the substrate can be a structure formed from a bulk silicon substrate. An active structure can be formed by etching the upper portion of the bulk silicon substrate to a predetermined depth. Simultaneously, the lower portion of the bulk silicon substrate forms the substrate.

[0036] In some embodiments, the substrate can be a structure formed from an SOI substrate. An active structure can be formed by sequentially etching the top silicon layer and buried oxide layer in the SOI substrate, followed by etching the upper portion of the bottom silicon layer. Simultaneously, the lower portion of the bottom silicon layer forms the substrate.

[0037] In some embodiments, the active structure and the substrate are stacked sequentially along a stacking direction, with the first active structure being farther from the substrate than the second active structure. In some embodiments, the first active structure is used to fabricate the top source / drain structure and the top metal gate in the top transistor. The second active structure is used to fabricate the bottom source / drain structure and the bottom metal gate in the bottom transistor.

[0038] In some embodiments, the morphology of the active structure may differ depending on the type of transistor formed. For example, when the transistor is a fin field-effect transistor, the morphology of the active structure may be a fin-like structure. When the transistor is a gate-all-around field-effect transistor, the morphology of the active structure may be a nanosheet stacked structure.

[0039] In some embodiments, the first active structure and the second active structure may be isolated by a dielectric layer. In some embodiments, the dielectric layer may be a buried oxide layer in SOI. In some embodiments, a sacrificial layer is formed between the first active structure and the second active structure. The dielectric layer can be formed by removing the sacrificial layer and depositing a dielectric material at the location where the sacrificial layer is removed. This dielectric layer formed based on the sacrificial layer may also be referred to as an intermediate isolation dielectric layer (MDI).

[0040] In some embodiments, the dielectric material may include silicon oxide, silicon nitride, low dielectric constant materials (such as organosilicon, silicon fluoride, etc.), high dielectric constant materials (such as hafnium oxide, zirconium oxide, etc.).

[0041] In some embodiments, after forming the active structure, a dummy gate material such as polycrystalline silicon or amorphous silicon can be deposited over the substrate to form a dummy gate structure spanning the active structure. Here, the dummy gate structure can be located in the gate region of the complementary field-effect transistor. The dummy gate structure can be removed in a subsequent step. Furthermore, at the location where the dummy gate structure is removed, a metal gate can be formed by depositing a metal material.

[0042] In some embodiments, the pseudo-gate structure in this application may include a first pseudo-gate structure and a second pseudo-gate structure. The first pseudo-gate structure is a pseudo-gate structure corresponding to the first active structure. The second pseudo-gate structure is a pseudo-gate structure corresponding to the second active structure.

[0043] In some embodiments, the first pseudo-gate structure and the second pseudo-gate structure can be deposited in a single step using the same deposition process. In some embodiments, the first pseudo-gate structure and the second pseudo-gate structure can be deposited in multiple steps using a multi-step deposition process. In some embodiments, when the pseudo-gate structure is formed in multiple steps using a multi-step deposition process, the second pseudo-gate structure can be deposited first, followed by the deposition of the first pseudo-gate structure.

[0044] In some embodiments, step 102 may include: depositing a dummy gate material over a substrate to form a second dummy gate structure; depositing an insulating material over the second dummy gate structure to form a dielectric layer, wherein the dielectric layer is located at the junction of the first active structure and the second active structure; and depositing a dummy gate material over the dielectric layer to form a first dummy gate structure.

[0045] Understandably, the dielectric layer (also known as the intermediate dielectric layer) is located between the first and second pseudo-gate structures, thus separating them. In subsequent steps, the presence of the dielectric layer can be used to determine whether the removal of either the first or second pseudo-gate structure has been completed.

[0046] In some embodiments, the dummy gate structure spans across the gate region. After the dummy gate structure is formed, the active structures not covered by the dummy gate structure in the source / drain region can be removed to open up space in the source / drain region. In some embodiments, using the first dummy gate structure as a mask, the first active structure and the second active structure are etched sequentially to remove the active structures not covered by the dummy gate structure.

[0047] In some embodiments, when a sacrificial layer exists between the first active structure and the second active structure, after removing the first active structure not covered by the dummy gate structure, the sacrificial layer between the first and second active structures (including the sacrificial layer in the gate region and the sacrificial layer in the source / drain region) can be removed. Then, dielectric material is deposited at the location where the sacrificial layer was removed to form a dielectric layer. Subsequently, the dielectric layer and the second active structure in the source / drain region are removed, thereby removing the active structure not covered by the dummy gate structure.

[0048] In some embodiments, after removing the first and second active structures in the source / drain regions, a bottom source / drain structure can be spatially epitaxially grown in the source / drain regions based on the second active structure in the gate region, and a top source / drain structure can be spatially epitaxially grown in the source / drain regions above the bottom source / drain structure based on the first active structure in the gate region.

[0049] In some embodiments, step 104 may include: forming a bottom source / drain structure in the space of the source / drain region based on a second active structure in the gate region, and then depositing a dielectric material around the bottom source / drain structure to form a bottom interlayer dielectric structure. An insulating material is then deposited over the bottom interlayer dielectric structure to form an insulating layer. A top source / drain structure may then be formed in the space of the source / drain region based on a first active structure in the gate region. Here, one side of the insulating layer is connected to the bottom interlayer dielectric structure, and the other side is connected to the top source / drain structure. The top and bottom source / drain structures are stacked along a stacking direction. The top and bottom source / drain structures are oriented in the same direction. The top and bottom source / drain structures have different polarities.

[0050] In some embodiments, the insulating material may include materials such as silicon oxide, hafnium oxide, and silicon oxynitride, but this application does not limit this.

[0051] In some embodiments, after forming the bottom source-drain structure and the top source-drain structure, the source structure and drain structure in the complementary field-effect transistor can be formed. Subsequently, only the fabrication of the metal gate is required to complete the transistor fabrication.

[0052] In some embodiments, after forming the bottom source / drain structure and the top source / drain structure, the first dummy gate structure can be removed. Then, a first metal material is deposited at the location where the first dummy gate structure was removed, i.e., above the second dummy gate structure, to form the top metal gate. Thus, the top metal gate and the top source / drain structure together constitute the top transistor. Here, the first metal material can be a gate work function metal.

[0053] Understandably, since the first dummy gate structure is opposite to the first active structure, and the first active structure is located on top of the stacked transistors (i.e., including the top and bottom transistors), the top gate can be fabricated simply by removing the first dummy gate structure and depositing the gate work function metal at the location where the dummy gate structure is removed using a low aspect ratio process. Compared to the process of filling the gate work function metal using a high aspect ratio process in related technologies, this effectively reduces the fabrication difficulty, while broadening the range of selectable gate work function metals and improving process flexibility.

[0054] In some embodiments, when a dielectric layer is formed between the first dummy gate structure and the second dummy gate structure, step 105 may include: removing the first dummy gate structure to expose the dielectric layer above the second dummy gate structure; and depositing a first metal material above the dielectric layer to form a top metal gate.

[0055] Understandably, when a dielectric layer is formed between the first and second dummy gate structures, the first dummy gate structure can be removed to expose the dielectric layer and the first active structure within the gate region. Here, the dielectric layer is located above the second dummy gate structure and at the junction of the top and bottom transistors. A first metal material can then be deposited over the dielectric layer to form a top metal gate covering the first active structure within the gate region.

[0056] In some embodiments, forming a top metal gate may include: depositing a gate dielectric material on the outer surface of a first active structure within the gate region to form a gate dielectric layer; and then depositing a first metal material on the outer surface of the gate dielectric layer to form a gate electrode layer. Here, the gate dielectric layer and the gate electrode layer together form the top gate structure.

[0057] In some embodiments, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the top transistor. In some embodiments, the first metal material may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0058] In some embodiments, forming the top metal gate may further include forming a top source / drain metal over the top source / drain structure. Here, the top source / drain metal is used to connect the top source / drain structure to the back-end interconnect layer. The top metal interconnect layer can then be formed over the top metal gate and the top source / drain metal using back-end processes (such as inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc.).

[0059] In some embodiments, after forming the top metal gate, the top transistor can be flipped and the substrate removed to expose the second pseudo-gate structure.

[0060] Understandably, after the top transistor is completed, it can be bonded to the carrier wafer and then flipped. For example, an insulating layer for bonding can be formed by depositing an insulating material (such as silicon oxide) over the top transistor. The insulating layer is then bonded to the carrier wafer, achieving bonding between the top transistor and the carrier wafer. The carrier wafer is then flipped to flip the top transistor. After flipping, the top transistor is located at the bottom, and the second active structure is located at the top, facilitating the subsequent fabrication of the bottom transistor based on the second active structure.

[0061] In some embodiments, after exposing the second dummy gate structure, the second dummy gate structure can be removed, and then the bottom metal gate in the bottom transistor can be fabricated using the same process as forming the top metal gate in the top transistor. Similarly, when a dielectric layer is formed between the first and second dummy gate structures, the bottom metal gate can be formed above the dielectric layer. For the sake of brevity, the fabrication of the bottom metal gate will not be described in detail here.

[0062] Understandably, the bottom metal gate and the bottom source / drain structure together constitute the bottom transistor. Here, the bottom metal gate is formed by depositing a second metal material, which can be a gate work function metal. In some embodiments, the work function value of the top metal gate formed by depositing a first metal material is different from the work function value of the bottom metal gate formed by depositing a second metal material. This completes the realization of a multi-work function metal gate for a complementary field-effect transistor.

[0063] In some embodiments, after forming the bottom metal gate, a bottom source / drain metal layer and a bottom metal interconnect layer may be formed sequentially. This completes the fabrication of the complementary field-effect transistor.

[0064] In this embodiment, a first pseudo-gate structure opposite to the first active structure and a second pseudo-gate structure opposite to the second active structure can be formed in the gate region of the complementary field-effect transistor. These independent first and second pseudo-gate structures separate the gate regions of the top and bottom transistors, allowing for independent RMG (Reverse Metal Gate) processes of the top transistor by removing the first pseudo-gate structure alone, and independent RMG processes of the bottom transistor by removing the second pseudo-gate structure alone after a single wafer flip. Here, the RMG process only requires a low aspect ratio gate work function metal filling process to fill the gate region corresponding to each transistor, thus forming a metal gate structure. This significantly reduces the complexity of filling the gate region of the bottom transistor using a high aspect ratio gate work function metal filling process in related technologies, thereby enabling more flexible adjustment of the threshold voltage of the complementary field-effect transistor.

[0065] In some embodiments, a complementary field-effect transistor may include: a first semiconductor unit and a second semiconductor unit, the first semiconductor unit and the second semiconductor unit being disposed adjacent to each other in a first direction; the first direction is perpendicular to the stacking direction of the top transistor and the bottom transistor.

[0066] Understandably, a complementary field-effect transistor (CFPT) may include multiple semiconductor cells arranged in a first direction. Here, the first direction may be perpendicular to the stacking direction of the top and bottom transistors. That is, the first direction may be... Figure X The direction can also be the Y-direction of the layout. Multiple semiconductor cells arranged in the first direction may include first and second semiconductor cells arranged adjacent to each other.

[0067] In some embodiments, the first semiconductor unit is used to fabricate at least one complementary field-effect transistor (CFT) unit. In some embodiments, when the at least one CTF unit comprises multiple CTF units, the multiple CTF units can be arranged along a first direction. Alternatively, the multiple CTF units can be arranged along a second direction. Alternatively, the multiple CTF units can be arrayed within the plane containing the first and second directions. Here, the second direction is perpendicular to the stacking direction of the top and bottom transistors, and the second direction is perpendicular to the first direction.

[0068] In some embodiments, the second semiconductor unit is used to fabricate at least one complementary field-effect transistor (CFT) unit. The arrangement of the CTF units in the second semiconductor unit may be the same as or different from the arrangement of the CTF units in the first semiconductor unit; this application does not limit this arrangement.

[0069] It should be noted that each complementary field-effect transistor unit can be a single transistor.

[0070] In some embodiments, step 105 may further include: removing the dielectric layer in the first semiconductor cell after removing the first dummy gate structure, while retaining the dielectric layer in the second semiconductor cell.

[0071] Understandably, when a complementary field-effect transistor (CFPT) includes a first semiconductor unit and a second semiconductor unit, and a dielectric layer is disposed between the first and second dummy gate structures, the first dummy gate structure can be removed first, followed by the dielectric layer in the first semiconductor unit, while retaining the dielectric layer in the second semiconductor unit. This results in a common-gate structure where the top and bottom metal gates are connected in the first semiconductor unit, and a separate-gate structure where the top and bottom metal gates are isolated by the dielectric layer in the second semiconductor unit. This achieves both separate-gate and common-gate CFPT units, meeting the circuit connection requirements of different application scenarios.

[0072] In some embodiments, when multiple semiconductor cells are arranged adjacent to each other along a first direction, step 105 may further include: removing the first pseudo-gate structure to expose the second pseudo-gate structure; selectively depositing a metal material with a target work function value above the second pseudo-gate structure of the multiple semiconductor cells to form a top metal gate corresponding to each semiconductor cell, wherein the metal materials in different semiconductor cells have the same or different target work function values.

[0073] Understandably, removing the first dummy gate structure in multiple semiconductor cells can expose the second dummy gate structure in multiple semiconductor cells. It should be noted that when no dielectric layer is disposed between the first and second dummy gate structures, removing the first dummy gate structure directly exposes the second dummy gate structure. When a dielectric layer is disposed between the first and second dummy gate structures, removing both the first and dielectric layers exposes the second dummy gate structure. In some embodiments, depending on actual usage requirements, only the first dummy gate structure may be removed without removing the dielectric layer. Therefore, step 105 may include: removing the first dummy gate structure to expose the dielectric layer; selectively depositing a metal material with a target work function value above the dielectric layer of the multiple semiconductor cells to form a top metal gate corresponding to each semiconductor cell.

[0074] Understandably, after exposing the second dummy gate structure, a metal material with a target work function value can be selectively deposited in each semiconductor cell above the second dummy gate structure to form a top metal gate corresponding to each semiconductor cell. Here, the work function value of the top metal gate corresponding to each semiconductor cell can be different, that is, the target work function value of the metal material corresponding to each semiconductor cell can be different, or the target work function value of the metal material corresponding to each semiconductor cell can be the same, but the structure of the top metal gate corresponding to each semiconductor cell is different.

[0075] In some embodiments, by selectively forming mask structures such as photoresist layers and insulating dielectric layers over different semiconductor cells, metal material can be deposited in semiconductor cells not covered by the mask structure to form a metal gate. The mask structure is then removed, allowing the metal gate to be fabricated in a portion of the semiconductor cell. Repeating the steps of selectively depositing the mask structure and forming the metal gate in the unmasked areas allows for the deposition of metal gates with different work function values ​​in different semiconductor cells. Similarly, the above steps allow for the deposition of metal gates with different work function values ​​over the dielectric layer in different semiconductor cells.

[0076] In some embodiments, step 105 may further include: depositing a barrier layer over a second dummy gate structure in a third semiconductor cell, wherein the third semiconductor cell is one or more of a plurality of semiconductor cells; depositing a first material over a second dummy gate structure not covered by the barrier layer to form a first sub-gate structure; removing the barrier layer and depositing a second material over the exposed second dummy gate structure to form a second sub-gate structure, wherein the work function value of the first material and the work function value of the second material are contained in a first metal material; the work function value of the first material and the work function value of the second material are different.

[0077] In some embodiments, step 105 may include: removing the first dummy gate structure and the second dummy gate structure to simultaneously expose the first active structure and the second active structure; depositing gate dielectric material on the surfaces of the first active structure and the second active structure to form a gate dielectric layer; redepositing the second dummy gate structure over the substrate and depositing a first metal material over the second dummy gate structure to form a top metal gate.

[0078] Understandably, by simultaneously exposing the first and second active structures, and depositing gate dielectric material on the exposed surfaces of both structures, the gate dielectric layers of both the top and bottom transistors can be formed simultaneously. This significantly simplifies the process flow, improves manufacturing efficiency, and ensures highly consistent physical and electrical properties between the gate dielectric layers of the top and bottom transistors. Furthermore, defining the exposure windows of both active structures in a single photolithography and etching process avoids overlay errors caused by multiple alignments, which is beneficial for improving device integration density and electrical consistency. After forming the gate dielectric layer, a second dummy gate structure can be redeposited on the substrate, and based on the special morphology of the second dummy gate structure, a low aspect ratio gate work function metal filling process can be achieved.

[0079] In some embodiments, the method may further include: after forming a bottom metal gate, forming a bottom metal interconnect layer communicating with the bottom source-drain structure and the bottom metal gate, wherein the bottom metal interconnect layer is included in the bottom transistor; flipping the bottom transistor; and forming a top metal interconnect layer communicating with the top source-drain structure and the top metal gate, wherein the top metal interconnect layer is included in the top transistor.

[0080] Understandably, through steps 101 to 107, a single flip-flop process—that is, completing the top metal gate and top metal interconnect layer followed by the bottom metal gate and bottom metal interconnect layer—can fabricate a complementary field-effect transistor (CFPT). Alternatively, a two-stage flip-flop process can be used: after completing the top metal gate of the top transistor, flip-flop directly to complete the bottom metal gate and bottom metal interconnect layer of the bottom transistor, and then flip-flop again to fabricate the top metal interconnect layer of the top transistor. This approach, which fabricates the metal interconnect layer after all metal gates are fabricated, completely solves the problems of metal contamination control and thermal budget control.

[0081] The following will describe the fabrication method of the complementary field-effect transistor in the embodiments of this application with specific examples.

[0082] Figure 2 A top view of a complementary field-effect transistor according to an exemplary embodiment is shown below. Figure 2 As shown in the top view, only the fin structure, gate structure, and source-drain structure of the complementary field-effect transistor (CFPT) are displayed. Specifically, the AA' section is a cross-section of the CFPT along the length of the gate region (perpendicular to the channel direction); the BB' section is a cross-section of the CFPT along the length of the source-drain region (perpendicular to the channel direction); and the CC' section is a cross-section of the CFPT along the channel direction.

[0083] Figures 3 to 21 This is a schematic diagram illustrating the fabrication process of a first type of complementary field-effect transistor according to an exemplary embodiment. For ease of understanding, Figures 3 to 21 (a) in the diagram shows the path along Figure 2 A cross-sectional view along the AA' direction. Figures 3 to 21 (b) shows the path along Figure 2 A cross-sectional view along the BB' direction. Figures 3 to 21 (c) in the diagram shows the path along Figure 2 A sectional view along the CC' direction. The following is in conjunction with... Figures 1 to 21 As shown, the fabrication method of a complementary field-effect transistor may include the following steps:

[0084] Step 1: Epitaxial growth of silicon-germanium and silicon is performed on the original substrate 20 (formed from silicon) to form an initial stacked structure 21, resulting in the following... Figure 3 The structure shown.

[0085] Understandably, the initial stacked structure 21 was formed by alternating deposition of silicon germanium and silicon.

[0086] Step 2: Using photolithography, a stacked structure is formed through a single etching process, resulting in... Figure 4 The structure shown.

[0087] Understandably, in Figure 4 (a) and Figure 4 In (b), it can be seen that the initial stacked structure 21 forms a fin-like structure after etching. This fin-like structure includes a stacked structure (nanosheet stacked structure) used to fabricate a fully surround gate field-effect transistor.

[0088] In some embodiments, silicon-germanium forms a support layer in the stacked structure, and silicon forms a channel layer in the stacked structure. See also Figure 4 As shown, the stacked structure may include a first active structure 22, a first sacrificial layer 23, a second active structure 24, and a second sacrificial layer 25. Here, the percentage of germanium atoms in the silicon-germanium forming the sacrificial layers (including the first sacrificial layer 23 and the second sacrificial layer 25) is different from the percentage of germanium atoms in the silicon-germanium forming the stacked structure.

[0089] The third step involves depositing oxide material on substrate 20 to form a shallow trench isolation structure 26, resulting in... Figure 5 The structure shown.

[0090] Here, the shallow trench isolation structure 26 is opposite to the second sacrificial layer 25.

[0091] In the fourth step, a dummy gate material, a dielectric material, and another dummy gate material are sequentially deposited on the substrate 20 to form a second dummy gate structure 29, an intermediate dielectric layer 28, and a first dummy gate structure 27, respectively. After the first dummy gate structure 27 is formed, sidewall material is deposited to form dummy gate sidewalls 30, resulting in... Figure 6 The structure shown.

[0092] Here, the first dummy gate structure 27 and the second dummy gate structure 29 can be formed of polysilicon, and the intermediate dielectric layer 28 can be formed of silicon oxide. Here, the first dummy gate structure 27 and the second dummy gate structure 29 are self-aligned. The intermediate dielectric layer 28 is located between the first dummy gate structure 27 and the second dummy gate structure 29. The second dummy gate structure 29 is opposite to the second active structure 24, the intermediate dielectric layer 28 is opposite to the first sacrificial layer 23, and the first dummy gate structure 27 is opposite to the first active structure 22.

[0093] Fifth step: Using the dummy gate structure as a mask, the first active structure 22 and the first sacrificial layer 23 in the source / drain regions are etched using an etching process to expose the first sacrificial layer 23 in the gate region. Then, according to the standard fabrication process for intermediate dielectric layer (MDI) forming, the intermediate dielectric layer 31 is formed, resulting in... Figure 7 The structure shown.

[0094] Here, by removing the first sacrificial layer 23 and depositing dielectric material at the location of the first sacrificial layer 23, an intermediate isolation dielectric layer 31 can be formed. Both the intermediate isolation dielectric layer 31 and the intermediate dielectric layer 28 are types of dielectric layers mentioned in the embodiments of this application. The intermediate dielectric layer 28 is the dielectric layer between the top gate structure and the bottom gate structure. When forming the top gate structure and the bottom gate structure, metal material can be deposited only on the intermediate dielectric layer 28.

[0095] Step 6: A barrier layer material is deposited on the sidewalls of the first active structure 22 and the first sacrificial layer 23 within the gate region to form a barrier layer 32, resulting in... Figure 8 The structure shown.

[0096] Here, the barrier layer 32 is used to ensure that the first active structure 22 in the top transistor is not affected when the bottom source / drain structure is subsequently fabricated through epitaxial growth. The barrier layer material can be silicon nitride, tantalum nitride, or other materials.

[0097] Step 7: Etch the support layer in the second active structure 24 to a predetermined depth. Deposit insulating materials such as silicon nitride at the locations where the support layer is removed to form the internal sidewalls of the bottom transistor. Then, based on the second active structure 24 in the gate region, epitaxially form the bottom source / drain structure 33 in the source / drain region. Next, remove the barrier layer 32 and deposit dielectric material in the source / drain region to form the bottom interlayer dielectric structure 34 in the bottom transistor, resulting in... Figure 9 The structure shown.

[0098] Step 8: An insulating material is deposited on top of the bottom interlayer dielectric structure 34 to form an insulating layer 35, resulting in... Figure 10 The structure shown.

[0099] Step 9: Laterally etch the support layer in the first active structure 22 to a predetermined depth. Deposit insulating materials such as silicon nitride at the locations where the support layer is removed to form the internal sidewalls of the top transistor; then, based on the first active structure 22 in the gate region, epitaxially form a top source / drain structure 36 in the source / drain region; deposit dielectric materials in the source / drain region to form the top interlayer dielectric structure 37 in the top transistor, resulting in... Figure 11 The structure shown.

[0100] Here, the top source / drain structure 36 is connected to the insulating layer 35.

[0101] Step 10: Remove the first dummy gate structure 27 to expose the first active structure 22 within the gate region, resulting in... Figure 12 The structure shown.

[0102] In the eleventh step, the first semiconductor unit is exposed by selective photolithography, and the intermediate dielectric layer 28 and the second dummy gate structure 29 within the first semiconductor unit are etched to obtain the following... Figure 13 The structure shown.

[0103] Here, in Figure 13 (a) and Figure 13 In (b) of the diagram, the first semiconductor unit is located to the right of the second semiconductor unit.

[0104] Step 12: Using an isotropic etching process, the second dummy gate structure 29 within the second semiconductor unit is removed, resulting in the following... Figure 14 The structure shown.

[0105] Step 13: Remove the support layers in the first active structure 22 and the second active structure 24 within the gate region, retaining the channel layer; then deposit gate dielectric material on the surface of the retained channel layer to form the gate dielectric layer 38, resulting in... Figure 15 The structure shown.

[0106] Here, the gate dielectric layer 38 in both the top and bottom transistors is fabricated simultaneously, which allows for a better balance in the electrical performance of the complementary field-effect transistor. In the first semiconductor unit, the gate dielectric layer 38 only wraps the intermediate isolation dielectric layer 31, while in the second semiconductor unit, the gate dielectric layer 38 wraps both the intermediate dielectric layer 28 and the intermediate isolation dielectric layer 31.

[0107] Step fourteen: Deposit dummy gate material on substrate 20 to reform the second dummy gate structure 29, resulting in... Figure 16 The structure shown.

[0108] Step 15: Deposit a first metal material over the second pseudo-gate structure 29 and the intermediate dielectric layer 28 to form the top metal gate 39 in the top transistor, resulting in... Figure 17 The structure shown.

[0109] Step sixteen: Following the standard back-end fabrication process in semiconductor manufacturing, the top source / drain metal 40, diffusion barrier structure 41, and top metal interconnect layer 42 are sequentially fabricated to obtain the desired result. Figure 18 The structure shown.

[0110] Step seventeen: Bond the top metal interconnect layer 42 to the carrier wafer 43, then flip the carrier wafer 43 and remove the substrate 20, the second sacrificial layer 25, and the shallow trench isolation structure 26 to obtain the following... Figure 19 The structure shown.

[0111] Step 18: Remove the second dummy gate structure 29, then deposit a second metal material over the top metal gate 39 and the intermediate dielectric layer 28 to form the bottom metal gate 44 in the bottom transistor, resulting in... Figure 20 The structure shown.

[0112] Here, the work function value of the top metal gate 39 and the work function value of the bottom metal gate 44 in this embodiment may be different.

[0113] Step nineteen: Following the standard back-end fabrication process in semiconductor manufacturing, the bottom source / drain metal 45, the diffusion barrier structure 41, and the bottom metal interconnect layer 46 are sequentially fabricated to obtain the following... Figure 21 The structure shown.

[0114] Thus, the complementary field-effect transistor in the embodiments of this application has been fabricated.

[0115] In this embodiment, after the top transistor is fabricated, a single wafer flipping process can be used to continue fabricating the bottom transistor. Based on this single wafer flipping, selective photolithography is used to simultaneously fabricate complementary field-effect transistors with separate gate structures and complementary field-effect transistors with common gate structures within two adjacent semiconductor cells on the same wafer. This brings more flexible design methods and the possibility of further miniaturization of standard circuit cells. At the same time, the process complexity and device failure rate are reduced by integrally molding the gate dielectric layer and depositing the gate filling structure.

[0116] Figures 22 to 25 This is a schematic diagram illustrating the fabrication process of a second complementary field-effect transistor according to an exemplary embodiment. For ease of understanding, Figures 22 to 25 (a) in the diagram shows the path along Figure 2 A cross-sectional view along the AA' direction. Figures 22 to 25 (b) shows the path along Figure 2 A cross-sectional view along the BB' direction. Figures 22 to 25 (c) in the diagram shows the path along Figure 2 A sectional view along the CC' direction. The following is in conjunction with... Figures 1 to 25 As shown, the fabrication method of a complementary field-effect transistor may include the following steps:

[0117] The first step, similar to steps one through fifteen in the fabrication process of the first type of complementary field-effect transistor described above, yields the following result: Figure 17 The structure shown.

[0118] The fabrication process can be found in the description of the fabrication process of the first type of complementary field-effect transistor. For the sake of brevity, it will not be repeated here.

[0119] The second step, in Figure 17 Based on the structure shown, the top metal gate 39 is bonded to the carrier wafer 43. Then, the carrier wafer 43 is flipped, and the substrate 20, the second sacrificial layer 25, and the shallow trench isolation structure 26 are removed to obtain the structure shown. Figure 22 The structure shown.

[0120] The third step involves removing the second dummy gate structure 29, followed by depositing a second metal material over the top metal gate 39 and the intermediate dielectric layer 28 to form the bottom metal gate 44 in the bottom transistor, resulting in... Figure 23 The structure shown.

[0121] The fourth step involves sequentially fabricating the bottom source / drain metal 45, the diffusion barrier structure 41, and the bottom metal interconnect layer 46 according to standard back-end semiconductor fabrication processes, resulting in the following: Figure 24 The structure shown.

[0122] Fifth, the bottom metal interconnect layer 46 is bonded to the carrier wafer 43. Then, the carrier wafer 43 is flipped, and the original carrier wafer 43 connected to the top metal gate 39 is removed. Following standard back-end semiconductor fabrication processes, the top source / drain metal 40, diffusion barrier structure 41, and top metal interconnect layer 42 are sequentially fabricated to obtain the desired result. Figure 25 The structure shown.

[0123] Thus, the complementary field-effect transistor in the embodiments of this application has been fabricated.

[0124] In this embodiment, after the top metal gate of the top transistor is fabricated, a first wafer flip can be performed to continue fabricating the bottom transistor. After the bottom transistor is fabricated, a second wafer flip can be performed to continue fabricating the top metal interconnect layer of the top transistor. Compared to the first wafer flip in the fabrication process, the problems of metal contamination and thermal budget control can be completely solved.

[0125] It should be noted that the above process schematically illustrates the fabrication process of forming complementary stacked transistors based on a fully all-around gate structure. This complementary stacked transistor is a transistor with a multifunctional metal gate. This invention is also applicable to other types of stacked transistors such as FinFETs and GAA Forksheets. Furthermore, the MDI method presented in this example is one way to achieve top- and bottom transistor isolation, and specific implementations are not limited to this. Other MDI process implementations or isolation methods using SOI, bulk materials, etc., are also compatible with the two methods proposed in this solution.

[0126] For example, Figure 26See the schematic diagram of a complementary field-effect transistor according to an embodiment of this application. Figure 26 The diagram illustrates the structure of a complementary field-effect transistor (CFFET) formed based on a FinFET. The structural composition of the CFFET-based CFFET is consistent with that of the CFFET-based CFFET, except that the active structure in the FinFET-based CFFET is a fin-like structure.

[0127] Secondly, embodiments of this application provide a complementary field-effect transistor (CFPT), which is fabricated by the method shown in any of the embodiments of the first aspect. See also Figure 21 and Figure 25 As shown, the complementary field-effect transistor may include: a top transistor and a bottom transistor stacked together; wherein the top transistor and the bottom transistor have different polarities; the top metal gate in the top transistor is formed by deposition of a first metal material, and the bottom metal gate in the bottom transistor is formed by deposition of a second metal material; the work function values ​​of the first metal material and the second metal material are different.

[0128] In some embodiments, the complementary field-effect transistor may further include a dielectric layer located between a top metal gate and a bottom metal gate.

[0129] In some embodiments, the complementary field-effect transistor may further include: a first semiconductor unit and a second semiconductor unit, the first semiconductor unit and the second semiconductor unit being disposed adjacent to each other in a first direction; the first direction being perpendicular to the stacking direction of the top transistor and the bottom transistor; wherein, the top metal gate and the bottom metal gate in the first semiconductor unit are connected, and a dielectric layer is disposed in the second semiconductor unit.

[0130] It is understood that the specific structure of the complementary field-effect transistor in the embodiments of this application can be found in the description of any embodiment in the first aspect, and will not be repeated here for the sake of brevity.

[0131] Understandably, compared to ordinary flip-chip stacked transistors that independently adjust the work function metal by separately fabricating the front and back transistors, the embodiments of this application can avoid the thermal budget problem by only one flip-chip process. That is, the gate metal of this solution is formed after the source and drain epitaxial steps, which has a better process effect and provides new directions and possibilities for the design and performance optimization of stacked transistors.

[0132] Finally, the embodiments of this application can be applied to next-generation integrated circuit manufacturing processes to achieve multi-threshold voltage regulation of N-type and P-type transistors, and have great potential for advanced node unit design and power consumption performance optimization.

[0133] Furthermore, the complementary field-effect transistors provided in the embodiments of this application can be detected using detection and analysis instruments, such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM).

[0134] Taking TEM as an example, the embodiments of this application can use TEM slicing to detect the aforementioned complementary field-effect transistors. It can be seen that the complementary field-effect transistors proposed in these embodiments differ from traditional complementary field-effect transistors in that the top and bottom transistors each have multiple different work function metals, allowing for independent and relatively free adjustment of the transistor's threshold voltage. The fabrication process does not require etching the metal to adjust the work function metal, making the process relatively simple. Furthermore, the source-drain structures in the top and bottom transistors have a certain spacing, similar to the morphology of a complementary stacked transistor, rather than the "back-to-back" type of a flip-chip stacked transistor. The metal contacts of the source-drain structures are formed on the front and back sides of the wafer, respectively, effectively suppressing crosstalk and parasitic capacitance between the source and drain, achieving independent source-drain contacts and low contact resistance.

[0135] Thirdly, embodiments of this application provide an electronic device, including: a circuit board and a complementary field-effect transistor (CFPT) as described in the above embodiments, wherein the CFPT is disposed on the circuit board. The specific structure of the CFPT can be found in the description of any embodiment of the first aspect, and will not be repeated here.

[0136] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a complementary field-effect transistor, characterized in that, The method includes: A first active structure and a second active structure are formed in sequence on a substrate, wherein the first active structure is farther away from the substrate than the second active structure; A first dummy gate structure and a second dummy gate structure are deposited and stacked sequentially on the substrate, wherein the first dummy gate structure is opposite to the first active structure, and the second dummy gate structure is opposite to the second active structure; the first dummy gate structure and the second dummy gate structure are located in the gate region; Remove the first active structure and the second active structure located within the source-drain region; A bottom source / drain structure is formed based on the second active structure within the gate region, and a top source / drain structure is formed above the bottom source / drain structure based on the first active structure within the gate region. The first dummy gate structure is removed, and a first metal material is deposited over the second dummy gate structure to form a top metal gate, wherein the top metal gate and the top source / drain structure are contained in a top transistor; Flip the top transistor and remove the substrate to expose the second dummy gate structure; The second dummy gate structure is removed, and a second metal material is deposited over the top metal gate to form the bottom metal gate, wherein the bottom metal gate and the bottom source / drain structure are included in the bottom transistor, the top transistor and the bottom transistor have different polarities, and the work function value of the top metal gate and the work function value of the bottom metal gate are different.

2. The method according to claim 1, characterized in that, The deposition of a first dummy gate structure and a second dummy gate structure stacked sequentially on the substrate includes: A pseudo-gate material is deposited over the substrate to form the second pseudo-gate structure; An insulating material is deposited over the second pseudo-gate structure to form a dielectric layer, wherein the dielectric layer is located at the junction of the first active structure and the second active structure; A pseudo-gate material is deposited over the dielectric layer to form the first pseudo-gate structure; The step of removing the first dummy gate structure and depositing a first metal material over the second dummy gate structure to form a top metal gate includes: Remove the first pseudo-gate structure to expose the dielectric layer above the second pseudo-gate structure; A first metal material is deposited over the dielectric layer to form the top metal gate; The step of removing the second dummy gate structure and depositing a second metal material over the top metal gate to form the bottom metal gate includes: Remove the second dummy gate structure to expose the dielectric layer above the top metal gate; A second metal material is deposited over the dielectric layer to form the bottom metal gate.

3. The method according to claim 2, characterized in that, The complementary field-effect transistor includes: a first semiconductor unit and a second semiconductor unit, wherein the first semiconductor unit and the second semiconductor unit are disposed adjacent to each other in a first direction; the first direction is perpendicular to the stacking direction of the top transistor and the bottom transistor; The step of removing the first dummy gate structure and depositing a first metal material over the second dummy gate structure to form a top metal gate further includes: After removing the first pseudo-gate structure, the dielectric layer in the first semiconductor cell is removed, while the dielectric layer in the second semiconductor cell is retained.

4. The method according to claim 1, characterized in that, The step of removing the first dummy gate structure and depositing a first metal material over the second dummy gate structure to form a top metal gate includes: Remove the first pseudo-gate structure and the second pseudo-gate structure to simultaneously expose the first active structure and the second active structure; A gate dielectric material is deposited on the surfaces of the first active structure and the second active structure to form a gate dielectric layer; The second dummy gate structure is redeposited over the substrate, and a first metal material is deposited over the second dummy gate structure to form the top metal gate.

5. The method according to claim 1, characterized in that, The method further includes: After forming the bottom metal gate, a bottom metal interconnect layer is formed that communicates with the bottom source / drain structure and the bottom metal gate, wherein the bottom metal interconnect layer is included in the bottom transistor; The bottom transistor is flipped; A top metal interconnect layer is formed that communicates with the top source / drain structure and the top metal gate, wherein the top metal interconnect layer is contained within the top transistor.

6. The method according to claim 1, characterized in that, The complementary field-effect transistor includes: a plurality of semiconductor units; the plurality of semiconductor units are arranged adjacent to each other along a first direction; The step of removing the first dummy gate structure and depositing a first metal material over the second dummy gate structure to form a top metal gate includes: Remove the first pseudo-gate structure to expose the second pseudo-gate structure; Above the second pseudo-gate structure of the plurality of semiconductor cells, a metal material having a target work function value is selectively deposited to form a top metal gate corresponding to each semiconductor cell, wherein the metal materials in different semiconductor cells have the same or different target work function values.

7. A complementary field-effect transistor, characterized in that, The transistor is fabricated using the method described in any one of claims 1 to 6, comprising: a top transistor and a bottom transistor stacked together. The top transistor and the bottom transistor have different polarities; the top metal gate of the top transistor is formed by deposition of a first metal material, and the bottom metal gate of the bottom transistor is formed by deposition of a second metal material; the work function values ​​of the first metal material and the second metal material are different.

8. The complementary field-effect transistor according to claim 7, characterized in that, The complementary field-effect transistor further includes a dielectric layer located between the top metal gate and the bottom metal gate.

9. The complementary field-effect transistor according to claim 8, characterized in that, The complementary field-effect transistor further includes: a first semiconductor unit and a second semiconductor unit, wherein the first semiconductor unit and the second semiconductor unit are disposed adjacent to each other in a first direction; the first direction is perpendicular to the stacking direction of the top transistor and the bottom transistor; In the first semiconductor unit, the top metal gate and the bottom metal gate are connected, and the second semiconductor unit is provided with the dielectric layer.

10. An electronic device, characterized in that, include: The circuit board and the complementary field-effect transistor as described in any one of claims 7 to 9.

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