Semiconductor structure and method of forming the same

Abstract

This application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: an isolation layer and an insulating layer, wherein the top and bottom surfaces of the isolation layer and the insulating layer are flush; a first fin located on the bottom surface of the isolation layer, the first fin including a plurality of first trenches; a first ion implantation region located in the first fin at the bottom of the plurality of first trenches; a second fin located on the top surface of the isolation layer, the second fin including a plurality of second trenches; and a second ion implantation region located in the second fin at the bottom of the plurality of second trenches. This application provides a semiconductor structure and a method for forming the same, enabling the fins below the source and drain of an FFET to conduct, increasing the effective height of the fins, and suppressing short-channel effects.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] The Flip-FET (FFET) was first proposed at the 2024 VLSI conference (reference: First Experimental Demonstration of Self-aligned Flip FET (FFET): a Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-side Active and Interconnects, Haoran Lu, 2024 IEEE VLSI Symposium on Technology and Circuits, T11-4). It combines the self-alignment advantages of the popular monolithic CFET, the low aspect ratio of sequentially stacked CFETs, back-side signal transmission, and back-side stacked field-effect transistor technology, consisting of a pair of back-to-back FinFETs. FFETs are compatible with FinFET processes and offer significant advantages in power consumption and area, making them a promising candidate for next-generation logic transistors.

[0003] In current FFET-based inverters, one side is an NMOS and the other is a PMOS. An isolation layer separates the N and PMOS components. During the source / drain formation process of an FFET, a portion of the fins at the bottom of the source / drain trench needs to be retained as a seed layer for epitaxial growth. Due to the high resistance of this seed layer, the fins at the bottom of the source / drain cannot conduct current, resulting in a reduction in the effective current-carrying fin height. Even with in-situ heavy doping of the source / drain to allow the dopant ions to diffuse downwards to the bottom fins, the lateral diffusion will also be the same length, leading to a short-channel effect.

[0004] Therefore, it is necessary to provide a more efficient and reliable technical solution to enable the fins below the source and drain of the FFET to conduct, increase the effective height of the fins, and suppress the short-channel effect. Summary of the Invention

[0005] This application provides a semiconductor structure and its formation method, which enables the fins below the source and drain of an FFET to conduct, increases the effective height of the fins, and suppresses the short-channel effect.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first fin, an isolation layer located on top of the first fin, and a second fin located on top of the isolation layer are sequentially formed on the surface of the semiconductor substrate; forming an insulating layer covering the semiconductor substrate on the surface of the semiconductor substrate, wherein the top surface of the insulating layer is flush with the top surface of the isolation layer; forming a plurality of second trenches in the second fin; forming second ion implantation regions in the second fins at the bottom of the plurality of second trenches; removing the semiconductor substrate and etching the insulating layer so that the bottom surface of the insulating layer is flush with the bottom surface of the isolation layer; forming a plurality of first trenches in the first fin; and forming first ion implantation regions in the first fins at the bottom of the plurality of first trenches.

[0007] In some embodiments of this application, before forming a plurality of first trenches in the first fin, the method further includes: forming a plurality of first gate structures on the top surface and sidewall of the first fin, wherein the plurality of first trenches are located between adjacent first gate structures.

[0008] In some embodiments of this application, the method of forming a first ion implantation region in the first fins at the bottom of the plurality of first trenches includes: forming a first shielding layer at the bottom and sidewalls of the plurality of first trenches; forming a second ion implantation region in the second fins at the bottom of the plurality of second trenches using an ion implantation process; and removing the first shielding layer.

[0009] In some embodiments of this application, the thickness of the first shielding layer is 3-5 nanometers.

[0010] In some embodiments of this application, the width of the first ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

[0011] In some embodiments of this application, after forming a first ion implantation region in the first fin at the bottom of the plurality of first trenches, the method further includes: forming a first doped layer that fills the plurality of first trenches using an epitaxial growth process.

[0012] In some embodiments of this application, the first doped layer includes: a first undoped layer located at the bottom and sidewalls of the plurality of first trenches; a first low-doped layer located on the surface of the first undoped layer; and a first high-doped layer located on the surface of the first low-doped layer.

[0013] In some embodiments of this application, before forming a plurality of second trenches in the second fin, the method further includes: forming a plurality of second gate structures on the top surface and sidewalls of the second fin, wherein the plurality of second trenches are located between adjacent second gate structures.

[0014] In some embodiments of this application, the method of forming a second ion implantation region in the first fin at the bottom of the plurality of second trenches includes: forming a second shielding layer at the bottom and sidewalls of the plurality of second trenches; forming a second ion implantation region in the first fin at the bottom of the plurality of first trenches using an ion implantation process; and removing the second shielding layer.

[0015] In some embodiments of this application, the thickness of the second shielding layer is 3-5 nanometers.

[0016] In some embodiments of this application, the width of the second ion implantation region is 30 to 60 nanometers; the distance between the second ion implantation region and the isolation layer is 1 to 5 nanometers.

[0017] In some embodiments of this application, after forming a second ion implantation region in the second fins at the bottom of the plurality of second trenches, the method further includes: forming a second doped layer that fills the plurality of second trenches using an epitaxial growth process.

[0018] In some embodiments of this application, the second doped layer includes: a second undoped layer located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer located on the surface of the second undoped layer; and a second high-doped layer located on the surface of the second low-doped layer.

[0019] Another aspect of this application provides a semiconductor structure, comprising: an isolation layer and an insulating layer, wherein the top and bottom surfaces of the isolation layer and the insulating layer are flush; a first fin located on the bottom surface of the isolation layer, the first fin including a plurality of first trenches; a first ion implantation region located in the first fin at the bottom of the plurality of first trenches; a second fin located on the top surface of the isolation layer, the second fin including a plurality of second trenches; and a second ion implantation region located in the second fin at the bottom of the plurality of second trenches.

[0020] In some embodiments of this application, the top surface and sidewall of the first fin are formed with a plurality of first gate structures, and the plurality of first trenches are located between adjacent first gate structures.

[0021] In some embodiments of this application, the width of the first ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

[0022] In some embodiments of this application, a first doped layer is formed in the plurality of first trenches, filling the plurality of first trenches.

[0023] In some embodiments of this application, the first doped layer includes: a first undoped layer located at the bottom and sidewalls of the plurality of first trenches; a first low-doped layer located on the surface of the first undoped layer; and a first high-doped layer located on the surface of the first low-doped layer.

[0024] In some embodiments of this application, the top surface and sidewalls of the second fin are formed with a plurality of second gate structures, and the plurality of second trenches are located between adjacent second gate structures.

[0025] In some embodiments of this application, the width of the second ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

[0026] In some embodiments of this application, a second doped layer is formed in the plurality of second trenches, filling the plurality of second trenches.

[0027] In some embodiments of this application, the second doped layer includes: a second undoped layer located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer located on the surface of the second undoped layer; and a second high-doped layer located on the surface of the second low-doped layer.

[0028] This application provides a semiconductor structure and its formation method, which enables the fins below the source and drain of an FFET to conduct, increases the effective height of the fins, and suppresses the short-channel effect. Attached Figure Description

[0029] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0030] in:

[0031] Figures 1 to 17 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0032] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0033] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0034] Figures 1 to 17 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 1 , Figure 2 and Figure 3 As shown, where, Figure 1 This is a top view. Figure 2 For along Figure 1 Longitudinal section view at point AA (middle dashed line). Figure 3 For along Figure 1 A longitudinal cross-sectional view at the dashed line BB. A semiconductor substrate 100 is provided, the semiconductor substrate 100 including mutually perpendicular x-directions and y-directions, the surface of the semiconductor substrate 100 having a first fin 110 extending along the x-direction, an isolation layer 130 located on the top surface of the first fin 110, and a second fin 120 located on the top surface of the isolation layer 130 sequentially formed. The projections of the first fin 110, the isolation layer 130, and the second fin 120 in the vertical direction (perpendicular to the surface of the semiconductor substrate 100) coincide, and the first fin 110, the isolation layer 130, and the second fin 120 are formed simultaneously in a single etching process.

[0036] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.

[0037] refer to Figure 2 and Figure 3 As shown, in some embodiments of this application, the semiconductor structure described herein is, for example, an FFET, where the first fin 110 and the second fin 120 are used to fabricate different types of field-effect transistors. The methods for forming the front and back fins of the FFET can be found in the prior art, and will not be elaborated upon here.

[0038] In some embodiments of this application, a plurality of first fins 110, isolation layers 130 and second fins 120 may be formed on the semiconductor substrate 100. For the purpose of simplicity, only two are shown in this embodiment as an example.

[0039] In some embodiments of this application, the materials of the first fin 110 and the second fin 120 may be the same or different. The materials of the first fin 110 and the second fin 120 may be common channel materials in the art, such as silicon, silicon-germanium, etc. The first fin 110 and the second fin 120 may contain corresponding doped ions depending on the type of device to be formed. The isolation layer 130 is used to insulate and isolate the first fin 110 and the second fin 120. The material of the isolation layer 130 may include insulating dielectric materials such as silicon oxide.

[0040] In some embodiments of this application, the method of forming the first fin 110, the isolation layer 130, and the second fin 120 on the surface of the semiconductor substrate 100 includes: sequentially forming a first fin material layer, an isolation material layer, and a second fin material layer on the surface of the semiconductor substrate 100; and etching the first fin material layer, the isolation material layer, and the second fin material layer to form the first fin 110, the isolation layer 130, and the second fin 120.

[0041] refer to Figure 4 and Figure 5 As shown, where, Figure 4 This is a top view. Figure 5 For along Figure 4 A longitudinal cross-sectional view at the dashed line BB. An insulating layer 140 is formed on the surface of the semiconductor substrate 100, covering the semiconductor substrate 100. The top surface of the insulating layer 140 is flush with the top surface of the isolation layer 130. The insulating layer 140 is used to cover and fill the space between the first fin 110 and the sidewall of the isolation layer 130, facilitating the subsequent fabrication of a field-effect transistor structure on the second fin 120.

[0042] In some embodiments of this application, the material of the insulating layer 140 includes insulating dielectric materials such as silicon oxide.

[0043] Next, a field-effect transistor is fabricated on the second fin 120 using the second fin 120 as the channel. The field-effect transistor on the second fin 120 can be a PMOS or an NMOS, which is not limited here.

[0044] refer to Figure 6 , Figure 7 and Figure 8 As shown, where, Figure 6 This is a top view. Figure 7 For along Figure 6 Longitudinal section view at point AA (middle dashed line). Figure 8 For along Figure 6 Longitudinal cross-section at the dashed line BB. Several second gate structures 121 are formed on the top surface and sidewalls of the second fin 120.

[0045] refer to Figure 6 As shown, the plurality of second gate structures 121 extend along the y-direction.

[0046] In some embodiments of this application, the second gate structure 121 includes a gate oxide layer, a gate layer, and a sidewall layer.

[0047] refer to Figure 9 As shown, Figure 9 for Figure 7 The following is a schematic diagram of the subsequent steps. A plurality of second trenches 122 are formed in the second fin 120, the plurality of second trenches 122 being located between adjacent second gate structures 121. The plurality of second trenches 122 are used for epitaxial growth of source and drain doped layers.

[0048] refer to Figure 10 , Figure 11 and Figure 12 As shown, a second ion implantation region 123 is formed in the second fin 120 at the bottom of the plurality of second trenches 122.

[0049] In some embodiments of this application, the method of forming a second ion implantation region 123 in the second fin 120 at the bottom of the plurality of second trenches 122 includes: referring to Figure 10 As shown, a second shielding layer 124 is formed at the bottom and sidewalls of the plurality of second trenches 122; Reference Figure 11 As shown, a second ion implantation region 123 is formed in the second fins 120 at the bottom of the plurality of second trenches 122 using an ion implantation process; Reference Figure 12 As shown, the second shielding layer 124 is removed.

[0050] In some embodiments of this application, the thickness of the second shielding layer 124 is 3-5 nanometers. The second shielding layer 124 can protect the surface of the second fin 120 from damage. The thickness of the second shielding layer 124 can control the width and depth of the second ion implantation region 123. For example, increasing the thickness of the second shielding layer 124 can reduce the width and depth of the second ion implantation region 123.

[0051] In some embodiments of this application, the width W of the second ion implantation region 123 is 30 to 60 nanometers; the distance D between the second ion implantation region 123 and the isolation layer 120 is 1 to 5 nanometers.

[0052] In some embodiments of this application, the doped ion type of the second ion implantation region 123 is determined according to the transistor type formed by the second fin 120, and the doped ion type of the second ion implantation region 123 is the same as the doping type of the second fin 120. The doping concentration of the second ion implantation region 123 is greater than the doping concentration of the second fin 120.

[0053] In some embodiments of this application, the doping concentration of the second ion implantation region 123 is 1e20 to 1e21 cm⁻¹. -2 .

[0054] In the technical solution of this application, before the epitaxial growth of the source and drain layer, the ion implantation region 123 is pre-formed in the second fin 120 below the second trench 122. This does not affect the subsequent epitaxial growth process, and the second fin 120 at the bottom of the second trench 122 can be utilized, effectively increasing the effective height of the second fin 120 and achieving higher performance.

[0055] In the technical solution of this application, by controlling the thickness of the second shielding layer 124, the width and depth of the second ion implantation region 123 can be within a suitable range, thereby improving the effective height of the second fin 120 while improving the short-channel effect.

[0056] refer to Figure 13 As shown, a second doped layer 125 is formed in the plurality of second trenches 122 using an epitaxial growth process, filling the plurality of second trenches 122. The doping type of the second doped layer 125 is determined according to the type of field-effect transistor on the second fin 120. The material of the second doped layer 125 includes silicon or silicon-germanium.

[0057] In some embodiments of this application, the second doped layer 125 includes: a second undoped layer 125a located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer 125b located on the surface of the second undoped layer 125a; and a second high-doped layer 125c located on the surface of the second low-doped layer 125b.

[0058] In the technical solution of this application, to prevent dopant ions in the second doped layer 125 from diffusing into the second ion implantation region 123 and changing its size, the second doped layer 125 adopts a multilayer structure with varying doping concentration. The second undoped layer 125a is undoped, the second low-doped layer 125b has a lower doping concentration, and the second high-doped layer 125c has a higher doping concentration than the second low-doped layer 125b. This structure can further improve the short-channel effect.

[0059] In some embodiments of this application, the doping concentration of the second low-doped layer 125b is 1e20 to 1e21 cm. -2 The doping concentration of the second highly doped layer 125c is 5e20 to 1e21 cm. -2 .

[0060] In some embodiments of this application, the process of fabricating field-effect transistors on the second fin 120 further includes processes such as forming an interlayer dielectric layer and fabricating back-end metal interconnects. These aspects, which are not the focus of this application, are omitted herein.

[0061] After the field-effect transistors on the second fin 120 are fabricated, the wafer is flipped to begin fabricating the field-effect transistors on the first fin 110. It should be noted that the field-effect transistors on the first fin 110 may be of the same or different type as those on the second fin 120; for example, they may be PMOS or NMOS.

[0062] refer to Figure 14 and Figure 15 As shown, the semiconductor substrate 100 is removed and the insulating layer 140 is etched so that the bottom surface of the insulating layer 140 is flush with the bottom surface of the isolation layer 130. The purpose of this is to expose the first fin 110, which facilitates the fabrication of a field-effect transistor on the first fin 110.

[0063] refer to Figure 16 and Figure 17 As shown, fabricating a field-effect transistor on the first fin 110 includes: forming a plurality of first gate structures 111 on the top surface and sidewalls of the first fin 110; forming a plurality of first trenches in the first fin 110, the plurality of first trenches being located between adjacent first gate structures 111; forming a first ion implantation region 113 in the first fin 110 at the bottom of the plurality of first trenches; and forming a first doped layer 115 filling the plurality of first trenches using an epitaxial growth process.

[0064] In some embodiments of this application, the method of forming a first ion implantation region 113 in the first fins 110 at the bottom of the plurality of first trenches includes: forming a first shielding layer at the bottom and sidewalls of the plurality of first trenches; forming a second ion implantation region in the second fins at the bottom of the plurality of second trenches using an ion implantation process; and removing the first shielding layer.

[0065] In some embodiments of this application, the thickness of the first shielding layer is 3-5 nanometers.

[0066] In some embodiments of this application, the width of the first ion implantation region 113 is 30 to 60 nanometers; the distance between the first ion implantation region 113 and the isolation layer 130 is 1 to 5 nanometers.

[0067] In some embodiments of this application, the first doped layer 115 includes: a first undoped layer 115a located at the bottom and sidewalls of the plurality of first trenches; a first low-doped layer 115b located on the surface of the first undoped layer 115a; and a first high-doped layer 115c located on the surface of the first low-doped layer 115b.

[0068] It should be noted that the process for fabricating a field-effect transistor on the first fin 110 is the same as the process for fabricating a field-effect transistor on the second fin 120. Therefore, this application only briefly describes the process of fabricating a field-effect transistor on the first fin 110 and omits a detailed description of its process steps. Those skilled in the art should be able to understand the process of fabricating a field-effect transistor on the first fin 110 in this application by referring to the process of fabricating a field-effect transistor on the second fin 120. In addition, the corresponding structures on the first fin 110 and the second fin 120 can be identical in terms of shape or parameters, except for the different doping types due to different field-effect transistor types.

[0069] This application provides a method for forming a semiconductor structure, enabling the fins below the source and drain of an FFET to conduct, increasing the effective height of the fins, and suppressing the short-channel effect.

[0070] Embodiments of this application also provide a semiconductor structure, referencing Figure 16 and Figure 17 As shown, it includes: an isolation layer 130 and an insulating layer 140, the top and bottom surfaces of the isolation layer 130 and the insulating layer 140 being flush; a first fin 110 located on the bottom surface of the isolation layer 130, the first fin 110 including a plurality of first trenches; a first ion implantation region 113 located in the first fin 110 at the bottom of the plurality of first trenches; a second fin 120 located on the top surface of the isolation layer 130, the second fin 120 including a plurality of second trenches; and a second ion implantation region 123 located in the second fin 120 at the bottom of the plurality of second trenches.

[0071] In some embodiments of this application, the projections of the first fin 110, the isolation layer 130, and the second fin 120 in the vertical direction coincide.

[0072] In some embodiments of this application, the semiconductor structure described herein is, for example, an FFET, wherein the first fin 110 and the second fin 120 are used to fabricate different types of field-effect transistors.

[0073] In some embodiments of this application, the field-effect transistors on the first fin 110 and the second fin 120 can be PMOS or NMOS, and this application does not limit them. The types of field-effect transistors on the first fin 110 and the second fin 120 can be the same or different.

[0074] In some embodiments of this application, the number of the first fin 110, the isolation layer 130, and the second fin 120 may be multiple. For the sake of simplicity, only two are shown in this embodiment as an example.

[0075] In some embodiments of this application, the materials of the first fin 110 and the second fin 120 may be the same or different. The materials of the first fin 110 and the second fin 120 may be common channel materials in the art, such as silicon, silicon-germanium, etc. The first fin 110 and the second fin 120 may contain corresponding doped ions depending on the type of device to be formed. The isolation layer 130 is used to insulate and isolate the first fin 110 and the second fin 120. The material of the isolation layer 130 may include insulating dielectric materials such as silicon oxide.

[0076] In some embodiments of this application, the material of the insulating layer 140 includes insulating dielectric materials such as silicon oxide.

[0077] In some embodiments of this application, the second gate structure 121 includes a gate oxide layer, a gate layer, and a sidewall layer.

[0078] In some embodiments of this application, the width W of the second ion implantation region 123 is 30 to 60 nanometers; the distance D between the second ion implantation region 123 and the isolation layer 120 is 1 to 5 nanometers.

[0079] In some embodiments of this application, the doped ion type of the second ion implantation region 123 is determined according to the transistor type formed by the second fin 120, and the doped ion type of the second ion implantation region 123 is the same as the doping type of the second fin 120. The doping concentration of the second ion implantation region 123 is greater than the doping concentration of the second fin 120.

[0080] In some embodiments of this application, the doping concentration of the second ion implantation region 123 is 1e20 to 1e21 cm⁻¹. -2 .

[0081] In the technical solution of this application, the ion implantation region 123 is formed in the second fin 120 below the second trench, which does not affect the subsequent epitaxial growth process, and can make use of the second fin 120 at the bottom of the second trench, effectively increasing the effective height of the second fin 120 and achieving higher performance.

[0082] In the technical solution of this application, the width and depth of the second ion implantation region 123 are within a suitable range, which improves the effective height of the second fin 120 while improving the short channel effect.

[0083] In some embodiments of this application, the doping type of the second doped layer 125 is determined according to the type of field-effect transistor on the second fin 120. The material of the second doped layer 125 includes silicon or silicon-germanium.

[0084] In some embodiments of this application, the second doped layer 125 includes: a second undoped layer 125a located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer 125b located on the surface of the second undoped layer 125a; and a second high-doped layer 125c located on the surface of the second low-doped layer 125b.

[0085] In the technical solution of this application, to prevent dopant ions in the second doped layer 125 from diffusing into the second ion implantation region 123 and changing its size, the second doped layer 125 adopts a multilayer structure with varying doping concentration. The second undoped layer 125a is undoped, the second low-doped layer 125b has a lower doping concentration, and the second high-doped layer 125c has a higher doping concentration than the second low-doped layer 125b. This structure can further improve the short-channel effect.

[0086] In some embodiments of this application, the doping concentration of the second low-doped layer 125b is 1e20 to 1e21 cm. -2 The doping concentration of the second highly doped layer 125c is 5e20 to 1e21 cm. -2 .

[0087] It should be noted that the structure of the field-effect transistor on the first fin 110 is the same as the structure of the field-effect transistor on the second fin 120. Therefore, a detailed description of the structure of the field-effect transistor on the first fin 110 is omitted here. Those skilled in the art should be able to understand the structure of the field-effect transistor on the first fin 110 in this application by referring to the structure of the field-effect transistor on the second fin 120. In addition, the corresponding structures on the first fin 110 and the second fin 120 may be identical except for the different doping types due to different types of field-effect transistors, such as shape or parameters.

[0088] This application provides a semiconductor structure and its formation method, which enables the fins below the source and drain of an FFET to conduct, increases the effective height of the fins, and suppresses the short-channel effect.

[0089] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0090] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be an intermediate element present.

[0091] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0092] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first fin, an isolation layer located on the top surface of the first fin, and a second fin located on the top surface of the isolation layer are sequentially formed on the surface of the semiconductor substrate; An insulating layer is formed on the surface of the semiconductor substrate to cover the semiconductor substrate, wherein the top surface of the insulating layer is flush with the top surface of the isolation layer; Several second grooves are formed in the second fin; A second ion implantation region is formed in the second fins at the bottom of the plurality of second trenches; Remove the semiconductor substrate and etch the insulating layer so that the bottom surface of the insulating layer is flush with the bottom surface of the isolation layer; A plurality of first grooves are formed in the first fin; A first ion implantation region is formed in the first fin at the bottom of the plurality of first trenches.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming a plurality of first trenches in the first fin, the method further includes: forming a plurality of first gate structures on the top surface and sidewall of the first fin, wherein the plurality of first trenches are located between adjacent first gate structures.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming a first ion implantation region in a first fin at the bottom of a plurality of first trenches includes: forming a first shielding layer at the bottom and sidewalls of the plurality of first trenches; forming a second ion implantation region in a second fin at the bottom of a plurality of second trenches using an ion implantation process; and removing the first shielding layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The thickness of the first shielding layer is 3-5 nanometers.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The width of the first ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming a first ion implantation region in the first fin at the bottom of the plurality of first trenches, the method further includes: forming a first doped layer that fills the plurality of first trenches using an epitaxial growth process.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first doped layer includes: a first undoped layer located at the bottom and sidewalls of the plurality of first trenches; a first low-doped layer located on the surface of the first undoped layer; and a first high-doped layer located on the surface of the first low-doped layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming a plurality of second trenches in the second fin, the method further includes: forming a plurality of second gate structures on the top surface and sidewalls of the second fin, wherein the plurality of second trenches are located between adjacent second gate structures.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming a second ion implantation region in the second fins at the bottom of the plurality of second trenches includes: forming a second shielding layer at the bottom and sidewalls of the plurality of second trenches; forming a second ion implantation region in the first fins at the bottom of the plurality of first trenches using an ion implantation process; and removing the second shielding layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The thickness of the second shielding layer is 3-5 nanometers.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The width of the second ion implantation region is 30 to 60 nanometers; the distance between the second ion implantation region and the isolation layer is 1 to 5 nanometers.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming a second ion implantation region in the second fins at the bottom of the plurality of second trenches, the method further includes: forming a second doped layer that fills the plurality of second trenches using an epitaxial growth process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The second doped layer includes: a second undoped layer located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer located on the surface of the second undoped layer; and a second high-doped layer located on the surface of the second low-doped layer.

14. A semiconductor structure, characterized in that, include: An isolation layer and an insulating layer, wherein the top and bottom surfaces of the isolation layer and the insulating layer are flush; A first fin is located on the bottom surface of the isolation layer, and the first fin includes a plurality of first grooves; The first ion implantation region is located in the first fin at the bottom of the plurality of first trenches; The second fin is located on the top surface of the isolation layer, and the second fin includes a plurality of second grooves; The second ion implantation region is located in the second fin at the bottom of the plurality of second trenches.

15. The semiconductor structure as described in claim 14, characterized in that, The top surface and sidewalls of the first fin are formed with a plurality of first gate structures, and the plurality of first trenches are located between adjacent first gate structures.

16. The semiconductor structure as claimed in claim 14, characterized in that, The width of the first ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

17. The semiconductor structure as claimed in claim 14, characterized in that, A first doped layer is formed in the plurality of first trenches, filling the plurality of first trenches.

18. The semiconductor structure as claimed in claim 17, characterized in that, The first doped layer includes: a first undoped layer located at the bottom and sidewalls of the plurality of first trenches; a first low-doped layer located on the surface of the first undoped layer; and a first high-doped layer located on the surface of the first low-doped layer.

19. The semiconductor structure as claimed in claim 14, characterized in that, The top surface and sidewalls of the second fin are formed with a plurality of second gate structures, and the plurality of second trenches are located between adjacent second gate structures.

20. The semiconductor structure as claimed in claim 14, characterized in that, The width of the second ion implantation region is 30 to 60 nanometers; the distance between the first ion implantation region and the isolation layer is 1 to 5 nanometers.

21. The semiconductor structure as described in claim 14, characterized in that, A second doped layer is formed in the plurality of second trenches, filling the plurality of second trenches.

22. The semiconductor structure as claimed in claim 21, characterized in that, The second doped layer includes: a second undoped layer located at the bottom and sidewalls of the plurality of second trenches; a second low-doped layer located on the surface of the second undoped layer; and a second high-doped layer located on the surface of the second low-doped layer.

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