Semiconductor structure, method of manufacturing the same, chip and circuit

Abstract

This invention provides a semiconductor structure, its fabrication method, chip, and circuit, relating to the field of semiconductor technology. The transistor includes: a substrate; and a transistor unit formed on the substrate. The transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers using a synchronous process. The n+1 functional structure layers and n polysilicon layers are stacked alternately. The oxide dielectric layer is formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, along with adjacent functional structure layers and the oxide dielectric layer between them, constitutes a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit. Each lateral double-diffused field-effect transistor has a three-dimensional cross configuration. Each functional structure layer includes: a body region, a drift region, a source, and a drain. This invention can increase the total operating current of the semiconductor structure and reduce the transistor area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a semiconductor structure, a method for fabricating a semiconductor structure, a chip, and a circuit. Background Technology

[0002] Lateral double-diffused MOSFETs (LDMOS) are a type of lateral power device whose electrodes are all located on the device surface. They are easy to integrate with low-voltage signal circuits and other devices through internal connections. At the same time, they have advantages such as high voltage withstand capability, high gain, good linearity, high efficiency, and good broadband matching performance. They are now widely used in power integrated circuits, especially power management chips.

[0003] In the prior art, the operating current provided by the lateral double-diffused field-effect transistor is relatively small, and the transistor area is relatively large. Summary of the Invention

[0004] To address the technical problems of low operating current and large transistor area in existing semiconductor structures, this invention provides a semiconductor structure, a semiconductor structure fabrication method, a chip, and a circuit. Using this semiconductor structure can increase the total operating current, reduce the on-resistance, increase the output power of the semiconductor structure, reduce the device area, and simultaneously form multiple transistors, simplifying the process flow and improving economic efficiency.

[0005] To achieve the above objectives, a first aspect of the present invention provides a semiconductor structure comprising: a substrate; wherein the substrate comprises, from bottom to top, a base substrate and an oxide isolation layer; A transistor cell is formed on a substrate. The transistor cell is vertically stacked using a synchronous process, consisting of n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers. The n+1 functional structure layers and n polysilicon layers are stacked alternately. The oxide dielectric layers are formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, its adjacent functional structure layer, and the oxide dielectric layer between them together constitute a lateral double-diffused field-effect transistor, thus forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor cell; where n is a positive integer greater than 1. Each lateral double-diffused field-effect transistor has a three-dimensional cross-shaped configuration, with a structural doped part and two protrusions. The structural doped part extends along a first horizontal direction, and the two protrusions extend from both sides of the structural doped part along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other. Each functional structure layer includes: a body region and a drift region, which are sequentially formed in the structure doped portion along a second horizontal direction; a source electrode, which is formed in a protrusion adjacent to the body region and forms an ohmic contact with the body region; and a drain electrode, which is formed in a protrusion adjacent to the drift region and forms an ohmic contact with the drift region.

[0006] Furthermore, the semiconductor structure further includes: an isolation structure formed on the substrate, the isolation structure being in contact with the structural doped portion and / or at least one of the two protrusions of each lateral double-diffused field-effect transistor, the isolation structure serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

[0007] Furthermore, the isolation structure includes two U-shaped isolation structures, both formed horizontally on the outside of the two protrusions, with their openings facing the structure-doped portion. The two U-shaped isolation structures, together with the structure-doped portion and the two protrusions, constitute a cubic configuration.

[0008] Furthermore, the source and drain of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source and drain in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

[0009] Furthermore, the semiconductor structure further includes: a first metal electrode, which is led upward from the region of the functional structure layer where the source electrode is not covered to the upper surface of the semiconductor structure along the vertical stacking direction; and a second metal electrode, which is led upward from the region of the functional structure layer where the drain electrode is not covered to the upper surface of the semiconductor structure along the vertical stacking direction.

[0010] Furthermore, in the first horizontal direction, the two ends of the polycrystalline silicon layer exhibit a stepped, symmetrically decreasing distribution as the vertical stacking height increases.

[0011] Furthermore, the semiconductor structure also includes a third metal electrode, which extends upward from the uncovered areas at both ends of the polycrystalline silicon layer to the upper surface of the semiconductor structure along the vertical stacking direction.

[0012] A second aspect of the present invention provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; wherein the substrate comprises, from bottom to top, a base substrate and an oxide isolation layer; A transistor unit is formed on the substrate; wherein, the transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers using a synchronous process, with the n+1 functional structure layers and n polysilicon layers stacked alternately, and the oxide dielectric layers formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, its adjacent functional structure layer, and the oxide dielectric layer between its adjacent functional structure layers together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit; wherein, n The value is a positive integer greater than 1; each lateral double-diffused field-effect transistor has a three-dimensional cross configuration, with a structural doped portion and two protrusions. The structural doped portion extends along a first horizontal direction, and the two protrusions protrude from both sides of the structural doped portion along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other; each functional structure layer includes: a body region and a drift region, which are formed sequentially in the structural doped portion along the second horizontal direction; a source electrode, which is formed in the protrusion adjacent to the body region and forms an ohmic contact with the body region; and a drain electrode, which is formed in the protrusion adjacent to the drift region and forms an ohmic contact with the drift region.

[0013] Furthermore, the substrate may be provided by an SOI substrate; wherein the SOI substrate comprises, from bottom to top, the base substrate, the oxide isolation layer and the top substrate.

[0014] Furthermore, before forming transistor cells on the substrate, the method further includes: forming an isolation structure on the substrate, the isolation structure contacting the structural doped portion and / or at least one of two protrusions of each lateral double-diffused field-effect transistor, the isolation structure serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

[0015] Further, forming the isolation structure on the substrate includes: removing part of the top substrate using an etching process to form a cross-shaped top substrate; forming an isolation oxide layer on the surface of the SOI substrate, the isolation oxide layer covering the exposed oxide isolation layer and the cross-shaped top substrate; removing the isolation oxide layer on the upper surface of the cross-shaped top substrate to form two U-shaped isolation structures on the substrate, both U-shaped isolation structures being formed horizontally outside the two protrusions to be formed, and both openings facing the structure doped portion to be formed, the two U-shaped isolation structures together with the structure doped portion to be formed and the two protrusions forming a cubic configuration.

[0016] Further, the step of forming transistor units on the substrate includes: vertically and alternately stacking n monocrystalline silicon layers and n germanium-silicon layers on the upper surface of a top substrate with a cross-shaped configuration; forming n+1 functional structure layers using the top substrate and n monocrystalline silicon layers; removing the n germanium-silicon layers to form n clearance spaces between the n+1 functional structure layers; forming an oxide layer on the surface of the functional structure layer adjacent to the clearance spaces to obtain 2n oxide dielectric layers; and depositing polycrystalline silicon in the clearance spaces between two adjacent oxide dielectric layers to obtain n polycrystalline silicon layers.

[0017] Further, the method of forming an n+1 functional structure layer using a top substrate and an n-layer monocrystalline silicon layer includes: simultaneously performing ion implantation of a first conductivity type on the top substrate, the n-layer monocrystalline silicon layer, and the n-layer germanium-silicon layer, and simultaneously performing ion implantation of a second conductivity type on the top substrate, the n-layer monocrystalline silicon layer, and the n-layer germanium-silicon layer, forming an initial body region and an initial drift region on both the top substrate and the n-layer monocrystalline silicon layer; wherein the initial body region and the initial drift region are arranged along a second horizontal direction; the first conductivity type is opposite to the second conductivity type; simultaneously performing heavy doping ion implantation of the second conductivity type on the top substrate, the n-layer monocrystalline silicon layer, and the n-layer germanium-silicon layer located at the two protrusions, forming a heavy doped region in the initial body region and the initial drift region of the two protrusions, using the initial body region of the structural doped part as the body region, the initial drift region of the structural doped part as the drift region, using the heavy doped region of the protrusion adjacent to the body region as the source, and using the heavy doped region of the protrusion adjacent to the drift region as the drain, thereby forming an n+1 functional structure layer on the top substrate and the n-layer monocrystalline silicon layer.

[0018] Furthermore, the removal of the n-layer germanium-silicon layer to form n clearance spaces between the n+1 functional structural layers includes: oxidizing the n-layer germanium-silicon layer into n-layer germanium-silicon oxide layer using an oxidation process; and removing the n-layer germanium-silicon oxide layer using wet etching to form n clearance spaces between the n+1 functional structural layers.

[0019] Furthermore, the method further includes: etching the functional structure layer sequentially from bottom to top, such that the source and drain of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source and drain in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

[0020] Furthermore, the method further includes: etching the polysilicon layer sequentially from bottom to top, such that in the first horizontal direction, the two ends of the polysilicon layer are distributed in a stepped symmetrical decreasing pattern as the vertical stacking height increases.

[0021] Furthermore, the method further includes: forming a dielectric layer on the upper surface of the semiconductor structure; forming a first metal electrode, a second metal electrode, and a third metal electrode on the dielectric layer, wherein the first metal electrode is led upward from the region of the functional structure layer where the source electrode is not covered along the vertical stacking direction to the upper surface of the semiconductor structure, the second metal electrode is led upward from the region of the functional structure layer where the drain electrode is not covered along the vertical stacking direction to the upper surface of the semiconductor structure, and the third metal electrode is led upward from the regions of the two ends of the polysilicon layer where they are not covered along the vertical stacking direction to the upper surface of the semiconductor structure.

[0022] A third aspect of the present invention provides a chip comprising the semiconductor structure described above.

[0023] A fourth aspect of the present invention provides a circuit comprising the semiconductor structure described above.

[0024] The present invention has at least the following technical effects through the technical solution provided by the present invention: The semiconductor structure of this invention includes a substrate, which comprises a base substrate and an oxide isolation layer from bottom to top. A transistor unit is formed on the substrate, and the transistor unit is vertically stacked using a simultaneous process consisting of n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers. The n+1 functional structure layers and n polysilicon layers are stacked alternately, and the oxide dielectric layer is formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, its adjacent functional structure layer, and the oxide dielectric layer between them together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit. This increases the total operating current of the semiconductor structure, reduces the on-resistance, improves the output power of the semiconductor structure, reduces the device area, and allows for the simultaneous formation of multiple transistors, simplifying the process flow and improving economic efficiency. Each lateral double-diffused field-effect transistor has a three-dimensional cross configuration, with a structural doped portion and two protrusions. The structural doped portion extends along a first horizontal direction, and the two protrusions protrude from both sides of the structural doped portion along a second horizontal direction. Each functional structural layer includes: a body region and a drift region, sequentially formed along a second horizontal direction in the structure doped region; a source electrode, formed on a protrusion adjacent to the body region, forming an ohmic contact with the body region; and a drain electrode, formed on a protrusion adjacent to the drift region, forming an ohmic contact with the drift region. The semiconductor structure provided by this invention can increase the total operating current of the semiconductor structure, reduce on-resistance, increase the output power of the semiconductor structure, reduce device area, and simultaneously form multiple transistors, simplifying the process flow and improving economic efficiency.

[0025] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 A cross-sectional view of the substrate formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 2A This is a top view of the isolation structure formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 2B A cross-sectional view of the isolation structure formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the AA' direction; Figure 2C A cross-sectional view of the isolation structure formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 3A A top view of the n-layer single-crystal silicon layer and the n-layer germanium-silicon layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 3B A cross-sectional view of the n-layer single-crystal silicon layer and the n-layer germanium-silicon layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention along the AA' direction; Figure 3C A cross-sectional view of the n-layer single-crystal silicon layer and the n-layer germanium-silicon layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 4A This is a top view of the initial body region and the initial drift region formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 4B A cross-sectional view of the initial bulk region and initial drift region formed in the semiconductor structure fabrication method provided in the embodiments of the present invention along the AA' direction; Figure 4C A cross-sectional view of the initial body region and initial drift region formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 5A This is a top view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 5B A cross-sectional view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention along the AA' direction; Figure 5C A cross-sectional view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 6AThis is a top view of the semiconductor structure fabrication method provided in this embodiment of the invention after removing n germanium-silicon layers; Figure 6B A cross-sectional view along the AA' direction after removing n germanium-silicon layers in the semiconductor structure fabrication method provided in this embodiment of the invention; Figure 6C A cross-sectional view in the BB' direction after removing the n-layer germanium-silicon layer in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 7A This is a top view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 7B A cross-sectional view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention along the AA' direction; Figure 7C A cross-sectional view of the body region, drift region, source, and drain formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 8A This is a top view of the stepped source and drain electrodes formed after etching the functional structure layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 8B A cross-sectional view of the stepped source and drain electrodes formed after etching the functional structure layer in the semiconductor structure fabrication method provided in the embodiment of the present invention in the BB' direction; Figure 9A This is a top view of the stepped body region and drift region formed after etching the polysilicon layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 9B A cross-sectional view of the stepped body region and drift region formed after etching the polysilicon layer in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 10A A cross-sectional view of the dielectric layer and the third metal electrode formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the AA' direction; Figure 10B A cross-sectional view of the dielectric layer, the first metal electrode, and the second metal electrode formed in the semiconductor structure fabrication method provided in the embodiments of the present invention in the BB' direction; Figure 11 A flowchart illustrating a semiconductor structure fabrication method provided in an embodiment of the present invention.

[0027] Explanation of reference numerals in the attached figures 1-Base substrate; 2-Oxide isolation layer; 3-Top substrate; 4-Isolation structure; 5-Single crystal silicon layer; 6-Germanium silicon layer; 7-Initial bulk region; 8-Initial drift region; 9-Bulk region; 10-Drift region; 11-Source; 12-Drain; 13-Oxide dielectric layer; 14-Polycrystalline silicon layer; 15-Dielectric layer; 16-First metal electrode; 17-Second metal electrode; 18-Third metal electrode. Detailed Implementation

[0028] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0030] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Please refer to Figure 10A and Figure 10B The first aspect of the present invention provides a semiconductor structure, the semiconductor structure comprising: a substrate; wherein the substrate comprises, from bottom to top, a base substrate 1 and an oxide isolation layer 2; A transistor cell is formed on a substrate. The transistor cell is formed by vertically stacking n+1 functional structure layers, n polysilicon layers 14, and 2n oxide dielectric layers 13 using a synchronous process. The n+1 functional structure layers and n polysilicon layers 14 are stacked alternately. The oxide dielectric layers 13 are formed between adjacent functional structure layers and polysilicon layers 14. Each polysilicon layer 14, its adjacent functional structure layer, and the oxide dielectric layer 13 between its adjacent functional structure layers together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor cell; where n is a positive integer greater than 1. Each lateral double-diffused field-effect transistor has a three-dimensional cross-shaped configuration, with a structural doped part and two protrusions. The structural doped part extends along a first horizontal direction, and the two protrusions extend from both sides of the structural doped part along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other. Each functional structure layer includes: a body region 9 and a drift region 10, which are formed sequentially in the structure doped portion along the second horizontal direction; a source 11, which is formed in the protrusion adjacent to the body region 9 and forms an ohmic contact with the body region 9; and a drain 12, which is formed in the protrusion adjacent to the drift region 10 and forms an ohmic contact with the drift region 10.

[0033] Specifically, in this embodiment of the invention, the semiconductor structure includes a substrate, which comprises a base substrate 1 and an oxide isolation layer 2 from bottom to top. A transistor unit is formed on the substrate, and the transistor unit includes multiple laterally diffused field-effect transistors. The transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers 14, and 2n oxide dielectric layers 13 using a synchronous process. The n+1 functional structure layers and n polysilicon layers 14 are stacked alternately, and the oxide dielectric layer 13 is formed between adjacent functional structure layers and polysilicon layers 14.

[0034] Please refer to Figure 9A Each lateral double-diffused field-effect transistor (LDFET) has a three-dimensional cross-shaped configuration, with a structural doped region and two protrusions. The structural doped region extends along a first horizontal direction, and the two protrusions extend from both sides of the structural doped region along a second horizontal direction. Each functional structure layer includes a body region 9, a drift region 10, a source 11, and a drain 12. The body region 9 and the drift region 10 are formed sequentially in the structural doped region along the second horizontal direction. The source 11 is formed in the protrusion adjacent to the body region 9 and forms an ohmic contact with the body region 9. The drain 12 is formed in the protrusion adjacent to the drift region 10 and forms an ohmic contact with the drift region 10.

[0035] Please refer to Figure 10A and Figure 10B The figure uses two different line types to identify the two transistors. The bottom polysilicon layer 14, the bottom functional structure layer, and the oxide dielectric layer 13 between them together constitute the first transistor. The bottom polysilicon layer 14, the penultimate functional structure layer, and the oxide dielectric layer 13 between them together constitute the second transistor. Through this layer-by-layer stacking method, each polysilicon layer 14 forms two new transistors with the adjacent upper and lower functional structure layers and the oxide dielectric layer 13 between them. This results in 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit, increasing the total operating current of the semiconductor structure, reducing the on-resistance, and increasing the output power of the semiconductor structure. It also reduces the device area while requiring the same operating current. In this embodiment, multiple transistors can be stacked simultaneously, simplifying the process flow, improving economic efficiency, and allowing for unlimited stacking of transistors as needed.

[0036] The semiconductor structure provided by the present invention can increase the total operating current, reduce the on-resistance, increase the output power of the semiconductor structure, reduce the device area, and simultaneously form multiple transistors, simplifying the process flow and improving economic efficiency.

[0037] Furthermore, the semiconductor structure further includes: an isolation structure 4 formed on the substrate, the isolation structure 4 being in contact with the structural doped portion and / or at least one of the two protrusions of each lateral double-diffused field-effect transistor, the isolation structure 4 serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

[0038] Furthermore, the isolation structure 4 includes two U-shaped isolation structures, both formed horizontally on the outside of the two protrusions, and their openings face the structure doped portion. The two U-shaped isolation structures, together with the structure doped portion and the two protrusions, constitute a cubic configuration.

[0039] Specifically, in this embodiment of the invention, an isolation structure 4 is formed on the substrate. The isolation structure 4 protrudes from the oxide isolation layer 2 of the substrate and contacts the structural doped portion of each lateral double-diffused field-effect transistor, or contacts at least one of the two protrusions, or contacts both the structural doped portion and at least one of the two protrusions. This serves as electrical isolation between the semiconductor structure and adjacent devices, preventing semiconductor structure breakdown or short circuits, improving the reliability of the semiconductor structure, avoiding noise interference or signal distortion from adjacent devices, and protecting the semiconductor structure. During the semiconductor structure fabrication process, a clearance layer is formed between two adjacent functional structure layers to replace the oxide dielectric layer and the polysilicon layer, facilitating the fabrication of the functional structure layer. After the functional structure layer is formed, the clearance layer is removed to create a clearance space, within which the oxide dielectric layer and the polysilicon layer are formed. After removing the clearance layer, the functional structure layer is temporarily suspended. The isolation structure 4 contacts the structural doped portion or the protrusion, or both, providing mechanical support for the suspended functional structure layer, preventing collapse, and protecting the structural integrity and reliability of the lateral double-diffused field-effect transistor.

[0040] The isolation structure 4 includes two U-shaped isolation structures with openings facing the structure doped portion. The two U-shaped isolation structures are formed horizontally on the outside of the two protrusions, and together with the middle structure doped portion and the two protrusions, they form a cubic configuration.

[0041] The semiconductor structure provided by the present invention can improve the reliability of the semiconductor structure, avoid noise interference or signal distortion from adjacent devices, protect the semiconductor structure, and protect the structural integrity and reliability of the lateral double-diffused field-effect transistor.

[0042] Furthermore, the source electrode 11 and drain electrode 12 of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source electrode 11 and drain electrode 12 in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

[0043] Furthermore, the semiconductor structure further includes: a first metal electrode 16, which is led upward from the uncovered area of ​​the source electrode 11 of the functional structure layer to the upper surface of the semiconductor structure along the vertical stacking direction; and a second metal electrode 17, which is led upward from the uncovered area of ​​the drain electrode 12 of the functional structure layer to the upper surface of the semiconductor structure along the vertical stacking direction.

[0044] Specifically, in this embodiment of the invention, the source electrode 11 and drain electrode 12 of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source electrode 11 and drain electrode 12 in the second horizontal direction decrease sequentially with the increase of the vertical stacking height. A first metal electrode 16 is formed in the uncovered area of ​​the source electrode 11, and the first metal electrode 16 is led upward from the source electrode 11 to the upper surface of the semiconductor structure along the vertical stacking direction. A second metal electrode 17 is formed in the uncovered area of ​​the drain electrode 12, and the second metal electrode 17 is led upward from the drain electrode 12 to the upper surface of the semiconductor structure along the vertical stacking direction. The first metal electrode 16 and the second metal electrode 17 can provide a controllable current path for the semiconductor structure.

[0045] Furthermore, in the first horizontal direction, the two ends of the polysilicon layer 14 are distributed in a stepped symmetrical decrease as the vertical stacking height increases.

[0046] Furthermore, the semiconductor structure also includes a third metal electrode 18, which is extended upward along the vertical stacking direction from the uncovered areas at both ends of the polycrystalline silicon layer 14 to the upper surface of the semiconductor structure.

[0047] Specifically, in this embodiment of the invention, the two ends of the polysilicon layer 14 are distributed in a stepped symmetrical decrease as the vertical stacking height increases. A third metal electrode 18 is formed in the area where the two ends of the polysilicon layer 14 are not covered. The third metal electrode 18 is led out from the polysilicon layer 14 to the upper surface of the semiconductor structure, providing a controllable current switching path for the semiconductor structure.

[0048] Please refer to Figure 11 The second aspect of the present invention provides a method for fabricating a semiconductor structure, the method comprising: S101: providing a substrate; wherein the substrate comprises, from bottom to top, a base substrate 1 and an oxide isolation layer 2; S102: A transistor unit is formed on the substrate; wherein, the transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers 14, and 2n oxide dielectric layers 13 using a synchronous process, the n+1 functional structure layers and n polysilicon layers 14 are stacked alternately, and the oxide dielectric layers 13 are formed between adjacent functional structure layers and polysilicon layers 14. Each polysilicon layer 14, its adjacent functional structure layer, and the oxide dielectric layer 13 between its adjacent functional structure layers together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit; In this context, n is a positive integer greater than 1; each lateral double-diffused field-effect transistor has a three-dimensional cross configuration, with a structural doped portion and two protrusions. The structural doped portion extends along a first horizontal direction, and the two protrusions protrude from both sides of the structural doped portion along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other; each functional structure layer includes: a body region 9 and a drift region 10, which are formed sequentially in the structural doped portion along the second horizontal direction; a source 11, which is formed in the protrusion adjacent to the body region 9 and forms an ohmic contact with the body region 9; and a drain 12, which is formed in the protrusion adjacent to the drift region 10 and forms an ohmic contact with the drift region 10.

[0049] Specifically, step S101 is performed first: a substrate is provided; wherein the substrate comprises a base substrate 1 and an oxide isolation layer 2 from bottom to top.

[0050] Furthermore, the substrate may be provided by an SOI substrate; wherein the SOI substrate comprises, from bottom to top, the base substrate 1, the oxide isolation layer 2, and the top substrate 3.

[0051] Furthermore, before forming transistor units on the substrate, the method further includes: forming an isolation structure 4 on the substrate, the isolation structure 4 contacting the structure doped portion and / or at least one of the two protrusions to be formed in each lateral double-diffused field-effect transistor, the isolation structure 4 serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

[0052] Further, the formation of the isolation structure 4 on the substrate includes: removing part of the top substrate 3 using an etching process to form a cross-shaped top substrate 3; forming an isolation oxide layer on the surface of the SOI substrate, the isolation oxide layer covering the exposed oxide isolation layer 2 and the cross-shaped top substrate 3; removing the isolation oxide layer on the upper surface of the cross-shaped top substrate 3 to form two U-shaped isolation structures on the substrate, both U-shaped isolation structures being formed horizontally outside the two protrusions to be formed, and both openings facing the structure doped portion to be formed, the two U-shaped isolation structures together with the structure doped portion to be formed and the two protrusions forming a cubic configuration.

[0053] Finally, step S102 is executed: a transistor unit is formed on the substrate; wherein, the transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers 14, and 2n oxide dielectric layers 13 using a synchronous process, the n+1 functional structure layers and n polysilicon layers 14 are stacked alternately, and the oxide dielectric layers 13 are formed between adjacent functional structure layers and polysilicon layers 14. Each polysilicon layer 14, its adjacent functional structure layer, and the oxide dielectric layer 13 between its adjacent functional structure layers together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit. The transistor is a lateral double-diffused field-effect transistor (LDFET) with a three-dimensional cross-shaped configuration. It has a structural doped region and two protrusions. The structural doped region extends along a first horizontal direction, and the two protrusions protrude from both sides of the structural doped region along a second horizontal direction. The first horizontal direction and the second horizontal direction are orthogonal to each other. Each functional structure layer includes a body region 9 and a drift region 10, which are formed sequentially in the structural doped region along the second horizontal direction. A source 11 is formed in the protrusion adjacent to the body region 9 and forms an ohmic contact with the body region 9. A drain 12 is formed in the protrusion adjacent to the drift region 10 and forms an ohmic contact with the drift region 10.

[0054] Further, the formation of transistor units on the substrate includes: vertically and alternately stacking n monocrystalline silicon layers 5 and n germanium-silicon layers 6 on the upper surface of a top substrate 3 with a cross-shaped configuration; forming n+1 functional structure layers using the top substrate 3 and the n monocrystalline silicon layers 5; removing the n germanium-silicon layers 6 to form n clearance spaces between the n+1 functional structure layers; forming an oxide layer on the surface of the functional structure layer adjacent to the clearance spaces to obtain 2n oxide dielectric layers 13; and depositing polycrystalline silicon in the clearance spaces between two adjacent oxide dielectric layers 13 to obtain n polycrystalline silicon layers 14.

[0055] Further, the formation of n+1 functional structure layers using the top substrate 3 and n-layer monocrystalline silicon 5 includes: simultaneously performing ion implantation of the top substrate 3, n-layer monocrystalline silicon 5, and n-layer germanium-silicon 6 with a first conductivity type, and simultaneously performing ion implantation of the top substrate 3, n-layer monocrystalline silicon 5, and n-layer germanium-silicon 6 with a second conductivity type, forming an initial body region 7 and an initial drift region 8 in both the top substrate 3 and n-layer monocrystalline silicon 5; wherein the initial body region 7 and the initial drift region 8 are arranged along a second horizontal direction; the first conductivity type is opposite to the second conductivity type; for the layers located at... The top substrate 3, n-layer single-crystal silicon layer 5, and n-layer germanium-silicon layer 6 of the two protrusions are simultaneously implanted with heavily doped ions of the second conductivity type to form heavily doped regions in the initial body region 7 and initial drift region 8 of the two protrusions. The initial body region 7 of the structural doped part is used as the body region 9, the initial drift region 8 of the structural doped part is used as the drift region 10, the heavily doped region of the protrusion adjacent to the body region 9 is used as the source 11, and the heavily doped region of the protrusion adjacent to the drift region 10 is used as the drain 12, thereby forming an n+1 functional structure layer on the top substrate 3 and the n-layer single-crystal silicon layer 5.

[0056] Furthermore, the removal of the n-layer germanium-silicon layer 6 to form n clearance spaces between the n+1 functional structural layers includes: oxidizing the n-layer germanium-silicon layer into n-layer germanium-silicon oxide layer using an oxidation process; and removing the n-layer germanium-silicon oxide layer using wet etching to form n clearance spaces between the n+1 functional structural layers.

[0057] Furthermore, the method further includes: etching the functional structure layer sequentially from bottom to top, such that the source 11 and drain 12 of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source 11 and drain 12 in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

[0058] Furthermore, the method further includes etching the polysilicon layer 14 sequentially from bottom to top, such that in the first horizontal direction, the two ends of the polysilicon layer 14 are distributed in a stepped symmetrical decreasing pattern as the vertical stacking height increases.

[0059] Furthermore, the method further includes: forming a dielectric layer 15 on the upper surface of the semiconductor structure; forming a first metal electrode 16, a second metal electrode 17, and a third metal electrode 18 on the dielectric layer 15, wherein the first metal electrode 16 is led upward from the uncovered area of ​​the source electrode 11 of the functional structure layer along the vertical stacking direction to the upper surface of the semiconductor structure, the second metal electrode 17 is led upward from the uncovered area of ​​the drain electrode 12 of the functional structure layer along the vertical stacking direction to the upper surface of the semiconductor structure, and the third metal electrode 18 is led upward from the uncovered areas at both ends of the polysilicon layer 14 along the vertical stacking direction to the upper surface of the semiconductor structure.

[0060] Specifically, in the embodiments of the present invention, the provided semiconductor structure can be either an N-type semiconductor structure or a P-type semiconductor structure. When the lateral double-diffused field-effect transistor in the semiconductor structure is an N-type lateral double-diffused field-effect transistor, the first doping type is P-type and the second doping type is N-type; when the lateral double-diffused field-effect transistor in the semiconductor structure is a P-type lateral double-diffused field-effect transistor, the first doping type is N-type and the second doping type is P-type. The present invention does not impose any limitations on this, and the following embodiments only use an N-type lateral double-diffused field-effect transistor as an example for explanation.

[0061] First provide Figure 1 The substrate shown comprises, from bottom to top, a base substrate 1 and an oxide isolation layer 2. The substrate can be omitted, and an SOI substrate can be used directly. The lower substrate serves as the base substrate 1, the middle oxide layer as the oxide isolation layer 2, and the top substrate 3 is used to fabricate the functional structure layer. Photoresist is formed on the SOI substrate. An etching window is created in the photoresist using exposure and development processes. The top substrate 3 is etched through the etching window to remove a portion of the top substrate 3, forming a cross-shaped top substrate 3. An isolation oxide layer is formed on the surface of the SOI substrate using chemical vapor deposition. This isolation oxide layer covers the exposed oxide isolation layer 2 and the cross-shaped top substrate 3. Photoresist is formed on the surface of the isolation oxide layer. An etching window is created in the photoresist using exposure and development processes. The isolation oxide layer is etched through the etching window to remove the isolation oxide layer from the surface of the cross-shaped top substrate 3. Figures 2A-2C The two U-shaped isolation structures are formed horizontally on the outside of the two protrusions to be formed, and their openings face the structure doped part to be formed. The two U-shaped isolation structures 4 together with the structure doped part to be formed and the two protrusions form a cubic configuration.

[0062] Please refer to Figures 3A-3C Using epitaxial growth, n layers of single-crystal silicon (SiGe) and n layers of germanium-silicon (SiGe) are vertically and alternately stacked on the surface of a top substrate 3 with a cross-shaped configuration. Photoresist is formed on the surface of the top single-crystal silicon layer 5. Through exposure and development, a bulk ion implantation window is formed on the photoresist. P-type lightly doped ions are simultaneously implanted into the top substrate 3, the n-layer single-crystal silicon (SiGe) layer 5, and the n-layer germanium-silicon (SiGe) layer 6 through the bulk ion implantation window. The photoresist is then removed. Photoresist is formed again. Through exposure and development, a drift region ion implantation window is formed on the photoresist. N-type lightly doped ions are simultaneously implanted into the top substrate 3, the n-layer single-crystal silicon (SiGe) layer 5, and the n-layer germanium-silicon (SiGe) layer 6 through the drift region ion implantation window. The photoresist is then removed, and high-temperature propagation is performed to form a layer... Figures 4A-4C The initial body region 7 and the initial drift region 8 are shown, and the initial body region 7 and the initial drift region 8 are arranged along the second horizontal direction.

[0063] Photoresist is formed again, and source / drain ion implantation windows are formed on the photoresist through exposure and development. N-type heavily doped ions are simultaneously implanted into the top substrate 3, n-layer single-crystal silicon layer 5, and n-layer germanium-silicon layer 6 located at the two protrusions through these source / drain ion input windows, forming heavily doped regions in the initial bulk region 7 and initial drift region 8 of the two protrusions. Figures 5A-5C As shown, the initial body region 7 of the structural doped region is designated as body region 9, the initial drift region 8 of the structural doped region is designated as drift region 10, the heavily doped region of the protrusion adjacent to body region 9 is designated as source 11, and the heavily doped region of the protrusion adjacent to drift region 10 is designated as drain 12, thereby forming an n+1 functional structure layer on the top substrate 3 and the n-layer single-crystal silicon layer 5. The germanium-silicon layer 6 is doped simultaneously during ion implantation. Since it will be removed in subsequent processes, the labels in the schematic diagram remain unchanged.

[0064] The germanium-silicon layer 6 is oxidized using thermal oxidation or plasma oxidation processes. Since germanium-silicon oxidizes much faster than silicon, it is completely oxidized to form a germanium-silicon oxide layer. The germanium-silicon oxide layer is then removed by wet etching, forming a layer between the n+1 functional structural layers. Figures 6A-6C The n clearance spaces are shown. At this time, the functional structure layer is temporarily suspended. The isolation structure 4 is in contact with the doped part or the protrusion of the structure, or both. It can provide mechanical support for the suspended functional structure layer, prevent collapse, and protect the structural integrity and reliability of the lateral double-diffused field-effect transistor.

[0065] Next, the semiconductor structure undergoes thermal oxidation to form an oxide layer on the surface of the functional structure layer adjacent to the clearance space, thereby obtaining a 2n-layer oxide dielectric layer 13. N-type heavily doped polycrystalline silicon is then deposited between the two opposing oxide dielectric layers 13 using low-pressure chemical vapor deposition to form… Figures 7A-7B The n-layer polysilicon layer 14 is shown. Each polysilicon layer 14, its adjacent functional structure layer, and the oxide dielectric layer 13 between them together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit.

[0066] A layer of silicon dioxide is chemically vapor deposited on the surface of the semiconductor structure. Starting from the outermost end of the two protrusions in the second horizontal direction, the etching proceeds vertically downwards, sequentially etching the silicon dioxide, the source 11 and drain 12 of the functional structure layer, the oxide dielectric layer 13, the polysilicon layer 14, and so on, until the source 11 and drain 12 of the last functional structure layer are exposed. Another layer of silicon dioxide is deposited, and the above etching steps are repeated until the source 11 and drain 12 of the penultimate functional structure layer are exposed. This process is repeated until all functional structure layers are etched. Figure 8A and Figure 8BThe source electrode 11 and drain electrode 12 are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source electrode 11 and drain electrode 12 in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

[0067] A layer of silicon dioxide is chemically vapor deposited on the surface of the semiconductor structure. Starting from the two outermost ends of the doped region in the first horizontal direction, the etching proceeds vertically downwards, sequentially etching the silicon dioxide, the body region 9 and drift region 10 of the functional structure layer, the oxide dielectric layer 13, the polysilicon layer 14, and so on, until the last polysilicon layer 14 is exposed. Another layer of silicon dioxide is deposited, and the above etching steps are repeated until the penultimate polysilicon layer 14 is exposed. This process is repeated until all functional structure layers are etched. Figure 9A and Figure 9B The polycrystalline silicon layer 14 shown is distributed in a stepped symmetrical manner with increasing vertical stacking height at both ends.

[0068] A dielectric layer 15 is formed on the upper surface of the semiconductor structure. The dielectric layer 15 is etched to form multiple contact holes. Metal is then physically vapor-deposited within the contact holes to form… Figure 10A and Figure 10B The first metal electrode 16, the second metal electrode 17, and the third metal electrode 18 are shown. Figure 10A and Figure 10B The cross-sectional direction is the same as that in the aforementioned figures ( Figure 1 -9) Maintain complete consistency. The first metal electrode 16 is led upward from the uncovered area of ​​the source electrode 11 of the functional structure layer to the upper surface of the semiconductor structure along the vertical stacking direction. The second metal electrode 17 is led upward from the uncovered area of ​​the drain electrode 12 of the functional structure layer to the upper surface of the semiconductor structure along the vertical stacking direction. The third metal electrode 18 is led upward from the uncovered areas at both ends of the polysilicon layer 14 to the upper surface of the semiconductor structure along the vertical stacking direction.

[0069] In this embodiment, taking two polysilicon layers 14, three functional structure layers, and four oxide dielectric layers 13 as an example, the figure uses two different line shapes to identify the two transistors. The bottom polysilicon layer 14, the bottom functional structure layer, and the oxide dielectric layer 13 between them together constitute the first transistor. The bottom polysilicon layer 14, the penultimate functional structure layer, and the oxide dielectric layer 13 between them together constitute the second transistor. The upper polysilicon layer, together with the two adjacent functional structure layers and the oxide dielectric layer 13 between them, constitute two lateral double-diffused field-effect transistors.

[0070] A third aspect of the present invention provides a chip comprising the semiconductor structure described above.

[0071] A fourth aspect of the present invention provides a circuit comprising the semiconductor structure described above.

[0072] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0073] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0074] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; wherein, from bottom to top, the substrate comprises a base substrate and an oxide isolation layer; A transistor cell is formed on a substrate. The transistor cell is vertically stacked using a synchronous process, consisting of n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers. The n+1 functional structure layers and n polysilicon layers are stacked alternately. The oxide dielectric layers are formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, its adjacent functional structure layer, and the oxide dielectric layer between them together constitute a lateral double-diffused field-effect transistor, thus forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor cell; where n is a positive integer greater than 1. Each lateral double-diffused field-effect transistor has a three-dimensional cross-shaped configuration, with a structural doped part and two protrusions. The structural doped part extends along a first horizontal direction, and the two protrusions extend from both sides of the structural doped part along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other. Each functional structure layer includes: a body region and a drift region, which are sequentially formed in the structure doped portion along a second horizontal direction; a source electrode, which is formed in a protrusion adjacent to the body region and forms an ohmic contact with the body region; and a drain electrode, which is formed in a protrusion adjacent to the drift region and forms an ohmic contact with the drift region.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An isolation structure is formed on the substrate, the isolation structure being in contact with the structural doped portion and / or at least one of the two protrusions of each lateral double-diffused field-effect transistor, the isolation structure serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

3. The semiconductor structure according to claim 2, characterized in that, The isolation structure includes two U-shaped isolation structures, both formed horizontally on the outside of the two protrusions, with their openings facing the structure doped portion. The two U-shaped isolation structures, together with the structure doped portion and the two protrusions, constitute a cubic configuration.

4. The semiconductor structure according to claim 1, characterized in that, The source and drain of the functional structure layer are arranged in a stepped manner along the vertical stacking direction, and the lengths of the source and drain in the second horizontal direction decrease sequentially with the increase of the vertical stacking height.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: The first metal electrode is led upward along the vertical stacking direction from the region of the functional structure layer where the source electrode is not covered to the upper surface of the semiconductor structure. The second metal electrode is led upwards along the vertical stacking direction from the region of the functional structure layer where the drain electrode is not covered to the upper surface of the semiconductor structure.

6. The semiconductor structure according to claim 1, characterized in that, In the first horizontal direction, the two ends of the polycrystalline silicon layer decrease symmetrically in a step-like manner as the vertical stacking height increases.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: The third metal electrode is led upwards from the uncovered areas at both ends of the polycrystalline silicon layer to the upper surface of the semiconductor structure along the vertical stacking direction.

8. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure fabrication method includes: A substrate is provided; wherein, from bottom to top, the substrate comprises a base substrate and an oxide isolation layer; A transistor unit is formed on the substrate; wherein, the transistor unit is formed by vertically stacking n+1 functional structure layers, n polysilicon layers, and 2n oxide dielectric layers using a synchronous process, with the n+1 functional structure layers and n polysilicon layers stacked alternately, and the oxide dielectric layers formed between adjacent functional structure layers and polysilicon layers. Each polysilicon layer, its adjacent functional structure layer, and the oxide dielectric layer between its adjacent functional structure layers together constitute a lateral double-diffused field-effect transistor, thereby forming 2n vertically stacked lateral double-diffused field-effect transistors within the transistor unit; wherein, n The value is a positive integer greater than 1; each lateral double-diffused field-effect transistor has a three-dimensional cross configuration, with a structural doped portion and two protrusions. The structural doped portion extends along a first horizontal direction, and the two protrusions protrude from both sides of the structural doped portion along a second horizontal direction; wherein the first horizontal direction and the second horizontal direction are orthogonal to each other; each functional structure layer includes: a body region and a drift region, which are formed sequentially in the structural doped portion along the second horizontal direction; a source electrode, which is formed in the protrusion adjacent to the body region and forms an ohmic contact with the body region; and a drain electrode, which is formed in the protrusion adjacent to the drift region and forms an ohmic contact with the drift region.

9. The semiconductor structure fabrication method according to claim 8, characterized in that, The substrate may be provided by an SOI substrate; wherein the SOI substrate comprises, from bottom to top, the base substrate, the oxide isolation layer and the top substrate.

10. The semiconductor structure fabrication method according to claim 9, characterized in that, Before forming transistor cells on the substrate, the method further includes: An isolation structure is formed on the substrate, the isolation structure being in contact with the doped portion of the structure to be formed for each lateral double-diffused field-effect transistor and / or at least one of the two protrusions to be formed, the isolation structure serving as electrical isolation between the semiconductor structure and adjacent devices, and supporting 2n lateral double-diffused field-effect transistors during the fabrication of the semiconductor structure.

11. The semiconductor structure fabrication method according to claim 10, characterized in that, The formation of the isolation structure on the substrate includes: A portion of the top substrate is removed using an etching process to form a cross-shaped top substrate; An isolation oxide layer is formed on the surface of the SOI substrate, which covers the exposed oxide isolation layer and the top substrate with a cross-shaped configuration; Remove the isolation oxide layer on the upper surface of the top substrate with a cross-shaped configuration, and form two U-shaped isolation structures on the substrate. Both U-shaped isolation structures are formed in the horizontal direction outside the two protrusions to be formed, and their openings face the structure doped portion to be formed. The two U-shaped isolation structures, together with the structure doped portion to be formed and the two protrusions, constitute a cubic configuration.

12. The semiconductor structure fabrication method according to claim 11, characterized in that, The formation of transistor units on the substrate includes: n layers of single-crystal silicon and n layers of germanium-silicon are vertically and alternately stacked on the top surface of the top substrate with a cross-shaped configuration; An n+1 functional structure layer is formed using a top substrate and n single-crystal silicon layers; By removing n germanium-silicon layers, n clearance spaces are formed between n+1 functional structural layers; An oxide layer is formed on the surface of the functional structure layer adjacent to the clearance space, thereby obtaining 2n oxide media layers; Polycrystalline silicon is deposited in the space between two adjacent oxide dielectric layers to obtain n polycrystalline silicon layers.

13. The semiconductor structure fabrication method according to claim 12, characterized in that, The method of forming an n+1 functional structure layer using a top substrate and n single-crystal silicon layers includes: The top substrate, n-layer single-crystal silicon, and n-layer germanium-silicon are simultaneously implanted with ions of the first conductivity type, and the top substrate, n-layer single-crystal silicon, and n-layer germanium-silicon are simultaneously implanted with ions of the second conductivity type, forming an initial body region and an initial drift region in both the top substrate and the n-layer single-crystal silicon; wherein the initial body region and the initial drift region are arranged along a second horizontal direction; the first conductivity type and the second conductivity type are opposite. Simultaneously perform heavy doping ion implantation of the second conductivity type on the top substrate, n-layer single-crystal silicon layer, and n-layer germanium-silicon layer located at the two protrusions to form heavily doped regions in the initial body region and initial drift region of the two protrusions. The initial body region of the structural doped part is used as the body region, the initial drift region of the structural doped part is used as the drift region, the heavily doped region of the protrusion adjacent to the body region is used as the source, and the heavily doped region of the protrusion adjacent to the drift region is used as the drain, thereby forming n+1 functional structure layers in the top substrate and n-layer single-crystal silicon layer.

14. The semiconductor structure fabrication method according to claim 12, characterized in that, The removal of the n-layer germanium-silicon layer, forming n clearance spaces between the n+1 functional structural layers, includes: An oxidation process is used to oxidize n-layer germanium-silicon layers into n-layer germanium-silicon oxide layers; By using wet etching to remove n layers of germanium-silicon oxide, n clearance spaces are formed between n+1 functional structure layers.

15. The semiconductor structure fabrication method according to claim 8, characterized in that, The method further includes: The functional structure layers are etched sequentially from bottom to top, so that the source and drain of the functional structure layers are arranged in a stepped manner along the vertical stacking direction, and the length of the source and drain in the second horizontal direction decreases sequentially with the increase of the vertical stacking height.

16. The semiconductor structure fabrication method according to claim 15, characterized in that, The method further includes: The polysilicon layers are etched sequentially from bottom to top, so that in the first horizontal direction, the two ends of the polysilicon layers decrease symmetrically in a step-like manner as the vertical stacking height increases.

17. The semiconductor structure fabrication method according to claim 16, characterized in that, The method further includes: A dielectric layer is formed on the surface of a semiconductor structure; A first metal electrode, a second metal electrode, and a third metal electrode are formed in the dielectric layer. The first metal electrode is led upward from the region of the source of the functional structure layer that is not covered along the vertical stacking direction to the upper surface of the semiconductor structure. The second metal electrode is led upward from the region of the drain of the functional structure layer that is not covered along the vertical stacking direction to the upper surface of the semiconductor structure. The third metal electrode is led upward from the regions of both ends of the polysilicon layer that are not covered along the vertical stacking direction to the upper surface of the semiconductor structure.

18. A chip, characterized in that, The chip comprises the semiconductor structure described in any one of claims 1-7.

19. A circuit, characterized in that, The circuit comprises the semiconductor structure of any one of claims 1-7.

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