Semiconductor structure, method of manufacturing the same, chip and circuit

Abstract

This invention provides a semiconductor structure, its fabrication method, chip, and circuit, relating to the field of semiconductor technology. The transistor includes: a substrate; a columnar transistor unit comprising, from the inside out: a source layer, a body layer, a drift region layer, and a drain layer; m gate vias, uniformly spaced in a ring between the source and drain layers, each penetrating from the top to the bottom surface along the axial direction of the columnar transistor unit, and penetrating the body layer and the drift region layer; m oxide layers, each formed on the walls of the m gate vias; and m polysilicon layers, each filling one of the m gate vias. The polysilicon layers, together with the oxide layer, source layer, body layer, drift region layer, and drain layer on one side in the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors within the columnar transistor unit. This invention can improve the current driving capability per unit area of ​​the semiconductor structure, increase the total operating current and output power, and optimize the electric field distribution.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a semiconductor structure, a method for fabricating a semiconductor structure, a chip, and a circuit. Background Technology

[0002] Lateral double-diffused MOSFETs (LDMOS) are a type of lateral power device whose electrodes are all located on the device surface. They are easy to integrate with low-voltage signal circuits and other devices through internal connections. At the same time, they have advantages such as high voltage withstand capability, high gain, good linearity, high efficiency, and good broadband matching performance. They are now widely used in power integrated circuits, especially power management chips.

[0003] In existing technologies, traditional LDMOS devices have limited current drive capability per unit area, resulting in a relatively low total operating current. This directly limits the output power of the power amplifier. To compensate for the insufficient output power, the operating voltage of the device is sometimes increased. However, higher operating voltages place more stringent requirements on the device's breakdown voltage and the overall system's heat dissipation design. This not only increases the design difficulty and cost but may also reduce the overall efficiency and reliability of the device.

[0004] Therefore, how to effectively improve the total operating current and current drive capability of LDMOS devices, thereby breaking through the bottleneck of their output power, is a key technical problem that those skilled in the art are constantly exploring and urgently need to solve. Summary of the Invention

[0005] To address the technical problems of limited current driving capability per unit area, low total operating current, and low output power in existing semiconductor devices, this invention provides a semiconductor structure, a semiconductor structure fabrication method, a chip, and a circuit. These technologies can improve the current driving capability per unit area of ​​the semiconductor structure, increase the total operating current and output power, optimize the electric field distribution, effectively improve the breakdown voltage of the device, and improve heat dissipation efficiency, ensuring stable operation of the device at higher power levels.

[0006] To achieve the above objectives, a first aspect of the present invention provides a semiconductor structure comprising: a substrate; wherein the substrate comprises, from bottom to top, a base substrate and an oxide isolation layer; a columnar transistor unit formed on the substrate, having a layered encapsulation structure, comprising, from inside to outside, a source layer, a body layer, a drift region layer and a drain layer; m gate holes, uniformly spaced in a ring between the source layer and the drain layer, and all penetrating from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and penetrating the body layer and the drift region layer; wherein m is a positive integer; m oxide layers, respectively formed on the walls of the m gate holes; m polysilicon layers, respectively filling the m gate holes; wherein the polysilicon layers, together with the oxide layer, source layer, body layer, drift region layer and drain layer on one side in the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors within the columnar transistor unit.

[0007] Furthermore, the layers of the columnar transistor unit are in a concentric layered structure.

[0008] Furthermore, each gate aperture has an annular sector configuration in a cross section perpendicular to the axial direction.

[0009] Furthermore, the thickness of the oxide layer located in the drift region layer is greater than the thickness of the oxide layer located in the bulk region layer.

[0010] Furthermore, the semiconductor structure also includes a heat dissipation layer formed on the outer surface of the drain layer.

[0011] Furthermore, the semiconductor structure further includes: a first metal electrode embedded in the source layer and extending from the top surface of the source layer to the bottom surface along the axial direction of the columnar transistor unit; a second metal electrode embedded in the drain layer and extending from the top surface of the drain layer to the bottom surface along the axial direction of the columnar transistor unit; and m third metal electrodes, each embedded in m polysilicon layers and extending from the top surface of the corresponding polysilicon layer to the bottom surface along the axial direction of the columnar transistor unit.

[0012] A second aspect of the present invention provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; wherein the substrate comprises, from bottom to top, a base substrate and an oxide isolation layer; forming a columnar transistor unit, m gate holes, m oxide layers and m polysilicon layers on the substrate; wherein m is a positive integer; the columnar transistor unit has a layered encapsulation structure, comprising, from the inside to the outside, a source layer, a body layer, a drift region layer and a drain layer; the m gate holes are uniformly spaced in a ring between the source layer and the drain layer, and each extends from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and extends through the body layer and the drift region layer; the m oxide layers are respectively formed on the walls of the m gate holes; the m polysilicon layers are respectively filled in the m gate holes; the polysilicon layers, together with the oxide layer, source layer, body layer, drift region layer and drain layer on one side in the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors within the columnar transistor unit.

[0013] Further, the formation of a columnar transistor unit, m gate vias, m oxide layers, and m polysilicon layers on the substrate includes: forming an initial body region layer and an initial drift region layer on the substrate, the initial body region layer and the initial drift region layer having a layered encapsulation structure, the initial drift region layer encapsulating the outer surface of the initial body region layer; forming m gate vias, the m gate vias being evenly spaced in a ring between the source layer to be formed and the drain layer to be formed, and all of them penetrating from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and penetrating the initial body region layer and the initial drift region layer; forming m oxide layers on the walls of the m gate vias respectively; filling the m gate vias with m polysilicon layers respectively; forming a source layer at the center of the initial body region layer, and forming a drain layer outside the initial drift region layer, the remaining initial body region layer region serving as the body region layer, and the remaining initial drift region layer region serving as the drift region layer.

[0014] Furthermore, the layers of the columnar transistor unit are in a concentric layered structure.

[0015] Furthermore, each gate aperture has an annular sector configuration in a cross section perpendicular to the axial direction.

[0016] Furthermore, the thickness of the oxide layer located in the drift region layer is greater than the thickness of the oxide layer located in the bulk region layer.

[0017] Furthermore, the method further includes forming a heat dissipation layer on the outer surface of the drain layer.

[0018] Furthermore, the method further includes: forming a first metal electrode in the source layer, the first metal electrode extending from the top surface to the bottom surface of the source layer along the axial direction of the columnar transistor unit; forming a second metal electrode in the drain layer, the second metal electrode extending from the top surface to the bottom surface of the drain layer along the axial direction of the columnar transistor unit; and forming m third metal electrodes in m polysilicon layers, the third metal electrodes extending from the top surface to the bottom surface of the corresponding polysilicon layer along the axial direction of the columnar transistor unit.

[0019] A third aspect of the present invention provides a chip comprising the semiconductor structure described above.

[0020] A fourth aspect of the present invention provides a circuit comprising the semiconductor structure described above.

[0021] The present invention has at least the following technical effects through the technical solution provided by the present invention: The semiconductor structure of this invention includes a substrate, which comprises a base substrate and an oxide isolation layer from bottom to top. A columnar transistor unit is formed on the substrate, the columnar transistor unit having a layered encapsulation structure, comprising, from the inside to the outside: a source layer, a body layer, a drift region layer, and a drain layer. m gate vias are uniformly spaced in a ring between the source layer and the drain layer, and each gate via penetrates from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and penetrates the body layer and the drift region layer. An oxide layer is formed on the wall of each gate via, and a polysilicon layer is filled within the gate via. The semiconductor structure provided by this invention can improve the current driving capability per unit area of ​​the semiconductor structure, increase the total operating current and output power, while optimizing the electric field distribution, effectively improving the breakdown voltage of the device, and improving heat dissipation efficiency, ensuring stable operation of the device at higher power levels.

[0022] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 A cross-sectional view of the substrate formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 2 This is a top view of the initial bulk region layer and the initial drift region layer formed in the semiconductor structure fabrication method provided in the embodiment of the present invention. Figure 3 This is a top view of the gate hole formed in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 4This is a top view of the oxide layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 5 This is a top view of the polycrystalline silicon layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 6 This is a top view of the bulk layer, drift layer, source layer, and drain layer formed in the semiconductor structure fabrication method provided in the embodiments of the present invention. Figure 7 A top view of the first metal electrode, the second metal electrode, and the third metal electrode formed in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 8 This is a top view of the heat dissipation layer formed in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 9 A flowchart illustrating a semiconductor structure fabrication method provided in an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures 1-Base substrate; 2-Oxide isolation layer; 3-Top substrate; 4-Initial bulk region layer; 5-Initial drift region layer; 6-Gate via; 7-Oxide layer; 8-Polysilicon layer; 9-Source layer; 10-Drain layer; 11-Bulk region layer; 12-Drift region layer; 13-First metal electrode; 14-Second metal electrode; 15-Third metal electrode; 16-Heat dissipation layer. Detailed Implementation

[0025] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0027] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0028] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] Please refer to Figure 8The first aspect of this invention provides a semiconductor structure comprising: a substrate; wherein the substrate comprises, from bottom to top, a base substrate 1 and an oxide isolation layer 2; a columnar transistor unit formed on the substrate, having a layered encapsulation structure, comprising, from inside to outside, a source layer 9, a body layer 11, a drift region layer 12 and a drain layer 10; and m gate holes 6, uniformly spaced in a ring between the source layer 9 and the drain layer 10, and all extending from the top surface along the axial direction of the columnar transistor unit. The process extends to the bottom surface and penetrates the body layer 11 and the drift layer 12; where m is a positive integer; m oxide layers 7 are formed on the walls of m gate holes 6; m polysilicon layers 8 are filled in the m gate holes 6; wherein the polysilicon layers 8, together with the oxide layer 7, source layer 9, body layer 11, drift layer 12 and drain layer 10 on one side of the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors in the columnar transistor unit.

[0030] Specifically, in this embodiment of the invention, the semiconductor structure includes a substrate, which includes a base substrate 1 and an oxide isolation layer 2 from bottom to top. A columnar transistor unit is formed on the oxide isolation layer 2. The columnar transistor unit has a layered wrapping structure and includes, from the inside to the outside, a source layer 9, a body layer 11, a drift region layer 12 and a drain layer 10.

[0031] m gate holes 6 are formed between the source layer 9 and the drain layer 10. The gate holes 6 are evenly spaced in a ring. Each gate hole 6 penetrates from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and also penetrates the body layer 11 and the drift layer 12. Its two ends contact the source layer 9 and the drain layer 10, respectively. There are dozens or even hundreds of gate holes 6. Figure 8 Only three are shown as an example. The uniform distribution of the gate holes 6 ensures a uniform electric field distribution within the semiconductor structure, effectively avoiding localized high electric field regions caused by electric field concentration. This optimized electric field distribution can significantly improve the device's breakdown voltage, reduce leakage current under high voltage operation, and ultimately enhance the device's power handling capability and long-term operational reliability. m oxide layers 7 are formed on the walls of each of the m gate holes 6, and m polysilicon layers 8 are filled within each of the m gate holes 6.

[0032] Please refer to Figure 8The polysilicon layer 8, together with the oxide layer 7, source layer 9, body layer 11, drift region layer 12, and drain layer 10 on one side of the circumferential direction, constitutes the first transistor. Body layer 11 serves as the body region, drift region layer 12 as the drift region, source layer 9 as the source, and drain layer 10 as the drain. The oxide layer 7 and polysilicon layer 8 within body layer 11 serve as the gate, and the oxide layer 7 and polysilicon layer 8 within drift region layer 12 serve as the field plate. The polysilicon layer 8, together with the oxide layer 7, source layer 9, body layer 11, drift region layer 12, and drain layer 10 on the opposite side of the circumferential direction, constitutes the second transistor. Thus, a total of 2m laterally double-diffused field-effect transistors can be formed within the columnar transistor unit. This significantly improves the current drive capability per unit area of ​​the semiconductor structure, increasing the total operating current and output power. Furthermore, by adjusting the height of the columnar transistor unit, the channel width can be controlled, thereby regulating the output current.

[0033] The semiconductor structure provided by the present invention can improve the current driving capability per unit area of ​​the semiconductor structure, increase the total operating current and output power, optimize the electric field distribution, effectively improve the breakdown voltage of the device, and improve the heat dissipation efficiency, ensuring the stable operation of the device at higher power.

[0034] Furthermore, the layers of the columnar transistor unit are in a concentric layered structure.

[0035] Specifically, in this embodiment of the invention, the layers of the columnar transistor unit are arranged in a concentric layered structure, which optimizes the distribution of the electric field in the radial direction and improves the breakdown voltage. Current flows vertically along the axial direction, and heat can be directly dissipated from the drain located on the outer side, reducing thermal resistance and improving self-heating effect.

[0036] The semiconductor structure provided by the present invention can optimize the electric field distribution of the device and improve heat dissipation efficiency.

[0037] Furthermore, each gate hole 6 has an annular sector configuration in a cross section perpendicular to the axial direction.

[0038] Specifically, in this embodiment of the invention, each gate aperture 6 has a trapezoidal cross-section perpendicular to the axial direction, with the length of the upper base near the center being shorter than the length of the lower base away from the center. Furthermore, each gate aperture 6 has a ring-shaped sector configuration within the cross-section perpendicular to the axial direction. This optimizes the electric field distribution within the semiconductor structure, thereby improving the device's breakdown voltage and current handling capability. This design disperses the electric field across multiple sector edges, preventing excessive concentration of the electric field in a single region and effectively suppressing breakdown caused by localized high electric fields. In addition, the ring-shaped sector configuration improves the uniformity of the current path, reduces on-resistance, and enhances the gate's control efficiency over the channel, further optimizing the device's high-frequency performance and switching speed.

[0039] Furthermore, the thickness of the oxide layer 7 located in the drift region layer 12 is greater than the thickness of the oxide layer 7 located in the body region layer 11.

[0040] Specifically, in this embodiment of the invention, the thickness of the oxide layer 7 located in the drift region layer 12 is greater than the thickness of the oxide layer 7 located in the body region layer 11. The oxide layer 7 and the polysilicon layer 8 located in the drift region layer 12 can serve as a field plate, while the oxide layer 7 and the polysilicon layer 8 located in the body region layer 11 serve as a gate. This field plate effectively shields the electric field influence of the drain high voltage on the drift region, allowing the depletion layer to expand more uniformly within the drift region. This achieves a higher breakdown voltage within a limited chip area, maximizing the device's withstand voltage capability. The thin oxide layer allows for more concentrated and effective electric field control of the channel by the gate, and also reduces the contact resistance of the source itself. Simultaneously, optimized electric field control reduces unnecessary charge storage, indirectly helping to reduce parasitic effects at high frequencies and improving the device's switching speed and operating frequency.

[0041] Furthermore, the semiconductor structure also includes a heat dissipation layer 16 formed on the outer surface of the drain layer 10.

[0042] Specifically, in this embodiment of the invention, the heat dissipation layer 16 provides a high-efficiency, low-thermal-resistance heat dissipation channel. During the operation of the power device, a large amount of heat generated by conduction and switching losses is mainly concentrated in core areas such as the channel and drift region. This heat is first transferred to the drain layer via thermal conduction, and then efficiently conducted to the external heat dissipation system or packaging substrate through the heat dissipation layer. The heat dissipation layer preferably uses materials with extremely high thermal conductivity, such as metallic materials (e.g., copper, aluminum and their alloys), thermally conductive and insulating materials (e.g., alumina, aluminum nitride, and other ceramics), carbon-based materials (e.g., diamond and diamond-like materials), or composite materials composed of metals and ceramics, carbon-based materials, etc., thereby significantly reducing the overall thermal resistance of the device and keeping the chip temperature within a safe range. Through the above structural design, the present invention not only significantly improves the current carrying capacity and power density of the device, but also effectively extends the service life of the device; at the same time, in high-frequency application scenarios, the excellent heat dissipation performance supports higher switching frequencies and speeds, providing technical support for the realization of miniaturized and lightweight power supply systems.

[0043] Furthermore, the semiconductor structure further includes: a first metal electrode 13, embedded in the source layer 9, and extending from the top surface to the bottom surface of the source layer 9 along the axial direction of the columnar transistor unit; a second metal electrode 14, embedded in the drain layer 10, and extending from the top surface to the bottom surface of the drain layer 10 along the axial direction of the columnar transistor unit; and m third metal electrodes 15, each embedded in m polysilicon layers 8, and extending from the top surface to the bottom surface of the corresponding polysilicon layer 8 along the axial direction of the columnar transistor unit.

[0044] Specifically, in this embodiment of the invention, a first metal electrode 13 is embedded in the source layer 9. The first metal electrode 13 extends from the top surface to the bottom surface of the source layer 9 along the axial direction of the columnar transistor unit, providing a current path so that charge carriers can smoothly flow into the conductive channel of the MOSFET. A second metal electrode 14 is embedded in the drain layer 10. The second metal electrode 14 extends from the top surface to the bottom surface of the drain layer 10 along the axial direction of the columnar transistor unit, collecting charge carriers and forming a current output. A third metal electrode 15 is embedded in each polysilicon layer 8. The third metal electrode 15 extends from the top surface to the bottom surface of the polysilicon layer 8 along the axial direction of the columnar transistor unit, controlling the current flow through voltage.

[0045] Please refer to Figure 8 The second aspect of the present invention provides a method for fabricating a semiconductor structure, the method comprising: S101: providing a substrate; wherein the substrate comprises, from bottom to top, a base substrate 1 and an oxide isolation layer 2; S102: forming a columnar transistor unit, m gate holes 6, m oxide layers 7 and m polysilicon layers 8 on the substrate; wherein m is a positive integer; the columnar transistor unit has a layered encapsulation structure, comprising, from the inside to the outside, a source layer 9, a body layer 11, a drift region layer 12 and a drain layer 10; the m gate holes 6 are uniformly spaced in a ring. The source layer 9 and the drain layer 10 are connected and extend from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and also extend through the body layer 11 and the drift layer 12; m oxide layers 7 are formed on the walls of m gate holes 6 respectively; m polysilicon layers 8 are filled in the m gate holes 6 respectively; the polysilicon layers 8, together with the oxide layer 7, source layer 9, body layer 11, drift layer 12 and drain layer 10 on one side of the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors in the columnar transistor unit.

[0046] Specifically, step S101 is performed first: a substrate is provided; wherein the substrate comprises a base substrate 1 and an oxide isolation layer 2 from bottom to top.

[0047] Specifically, in the embodiments of the present invention, the provided semiconductor structure can be either an N-type semiconductor structure or a P-type semiconductor structure. The following textual embodiments will only use an N-type lateral double-diffused field-effect transistor as an example for explanation. First, provide... Figure 1 The substrate shown can be an SOI substrate with P-type silicon. The substrate includes, from bottom to top, a P-type base substrate 1, an oxide isolation layer 2, and a P-type top substrate 3.

[0048] Next, step S102 is performed: a columnar transistor unit, m gate holes 6, m oxide layers 7, and m polysilicon layers 8 are formed on the substrate; where m is a positive integer; the columnar transistor unit has a layered encapsulation structure, which includes, from the inside out: a source layer 9, a body layer 11, a drift region layer 12, and a drain layer 10; the m gate holes 6 are evenly distributed in a ring between the source layer 9 and the drain layer 10, and are all arranged along the axial direction of the columnar transistor unit from top to bottom. The surface extends to the bottom surface and penetrates the body layer 11 and the drift layer 12; m oxide layers 7 are formed on the walls of m gate holes 6 respectively; m polysilicon layers 8 are filled in the m gate holes 6 respectively; the polysilicon layers 8, together with the oxide layer 7, source layer 9, body layer 11, drift layer 12 and drain layer 10 on one side of the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors in the columnar transistor unit.

[0049] Further, the formation of columnar transistor units, m gate vias 6, m oxide layers 7, and m polysilicon layers 8 on the substrate includes: forming an initial body layer 4 and an initial drift region layer 5 on the substrate, the initial body layer 4 and the initial drift region layer 5 having a layered encapsulation structure, the initial drift region layer 5 encapsulating the outer surface of the initial body layer 4; forming m gate vias 6, the m gate vias 6 being uniformly spaced in a ring between the source layer 9 to be formed and the drain layer 10 to be formed, and all... The columnar transistor unit extends from the top surface to the bottom surface along its axial direction, and also extends through the initial body layer 4 and the initial drift layer 5; m oxide layers 7 are formed on the walls of m gate holes 6 respectively; m polysilicon layers 8 are filled in the m gate holes 6 respectively; a source layer 9 is formed at the center of the initial body layer 4, and a drain layer 10 is formed on the outside of the initial drift layer 5; the remaining area of ​​the initial body layer 4 is used as the body layer 11, and the remaining area of ​​the initial drift layer 5 is used as the drift layer 12.

[0050] Furthermore, the layers of the columnar transistor unit are in a concentric layered structure.

[0051] Furthermore, each gate hole 6 has an annular sector configuration in a cross section perpendicular to the axial direction.

[0052] Furthermore, the thickness of the oxide layer 7 located in the drift region layer 12 is greater than the thickness of the oxide layer 7 located in the body region layer 11.

[0053] Furthermore, the method also includes forming a heat dissipation layer 16 on the outer surface of the drain layer 10.

[0054] Furthermore, the method further includes: forming a first metal electrode 13 in the source layer 9, the first metal electrode 13 extending from the top surface to the bottom surface of the source layer 9 along the axial direction of the columnar transistor unit; forming a second metal electrode 14 in the drain layer 10, the second metal electrode 14 extending from the top surface to the bottom surface of the drain layer 10 along the axial direction of the columnar transistor unit; and forming m third metal electrodes 15 in m polysilicon layers 8, the third metal electrodes 15 extending from the top surface to the bottom surface of the corresponding polysilicon layer 8 along the axial direction of the columnar transistor unit.

[0055] Specifically, in this embodiment of the invention, a thin layer of silicon dioxide is thermally oxidized on the surface of the top substrate 3. Photoresist is then formed on the upper surface of the silicon dioxide. An implantation window is formed in the photoresist using an exposure and development process. P-type ion implantation is performed on the top substrate 3 through the implantation window, removing the photoresist. Then, photoresist is formed again on the upper surface of the silicon dioxide. An implantation window is formed in the photoresist using an exposure and development process. N-type ion implantation is performed on the top substrate 3 through the implantation window, removing the photoresist. Thermal propulsion is then performed to form… Figure 2 The initial body layer 4 and the initial drift layer 5 shown are layered and wrapped together, with the initial drift layer 5 wrapped around the outer surface of the initial body layer 4.

[0056] Then, dry etching is used to create an opening in the region where the initial volume region layer 4 and the initial drift region layer 5 meet. Figure 3 The m gate holes 6 shown are evenly spaced in a ring between the source layer 9 and the drain layer 10 to be formed, and each gate hole extends from the top surface to the bottom surface along the axial direction of the columnar transistor unit. Each gate hole 6 has a ring sector configuration in a cross section perpendicular to the axial direction, which can optimize the electric field distribution within the semiconductor structure, thereby improving the breakdown voltage and current handling capability of the device.

[0057] Silicon dioxide is filled into m gate holes 6 using chemical vapor deposition, followed by chemical mechanical polishing to remove excess silicon dioxide from the surface. Then, the silicon dioxide in the m gate holes 6 is etched, simultaneously removing excess substrate, forming a layer on the hole walls of the m gate holes 6. Figure 4 The oxide layer 7 shown is layer m. The thickness of oxide layer 7 located in drift region layer 12 is greater than the thickness of oxide layer 7 located in body region layer 11. Oxide layer 7 located in drift region layer 12 can serve as field plate oxide layer, and oxide layer 7 located in body region layer 11 can serve as gate oxide layer.

[0058] Polysilicon is deposited in m gate holes 6 using low-pressure chemical vapor deposition, followed by chemical mechanical polishing to remove excess polysilicon from the surface, forming... Figure 5 The diagram shows m polysilicon layers 8. The oxide layer 7 and polysilicon layer 8 located in the initial drift region layer 5 can serve as field plates, and the oxide layer 7 and polysilicon layer 8 located in the initial bulk region layer 4 can serve as gate plates.

[0059] Photoresist is formed on the top surface of the columnar transistor unit. An implantation window is formed in the photoresist using exposure and development processes. N-type heavily doped ions are implanted into the initial bulk layer 4 and the initial drift layer 5 through the implantation window. Figure 6 As shown, a source layer 9 is formed at the center of the initial body layer 4, and a drain layer 10 is formed outside the initial drift layer 5. The remaining area of ​​the initial body layer 4 serves as the body layer 11, and the remaining area of ​​the initial drift layer 5 serves as the drift layer 12. The source layer 9, body layer 11, drift layer 12, and drain layer 10 form a concentric layered structure, achieving an optimized distribution of the electric field in the radial direction, which can improve the breakdown voltage. The current flows vertically along the axial direction, and heat can be directly dissipated from the drain located on the outer side, reducing thermal resistance and improving the self-heating effect.

[0060] A thick layer of silicon dioxide is chemically vapor-deposited on the top surface of the columnar transistor unit. Photoresist is then formed on the silicon dioxide surface. An etching window is created in the photoresist using an exposure and development process. Through this etching window, the source layer 9, drain layer 10, and m polysilicon layers 8 are etched until the oxide isolation layer 2 is exposed, forming contact holes. Figure 7 As shown, metal is physically vapor-deposited within the contact holes to form a first metal electrode 13 within the source layer 9. The first metal electrode 13 extends from the top surface to the bottom surface of the source layer 9 along the axial direction of the columnar transistor unit. A second metal electrode 14 is formed within the drain layer 10, extending from the top surface to the bottom surface of the drain layer 10 along the axial direction of the columnar transistor unit. A third metal electrode 15 is formed within each polysilicon layer 8, extending from the top surface to the bottom surface of that polysilicon layer 8 along the axial direction of the columnar transistor unit.

[0061] The method in this embodiment further includes forming a heat dissipation layer 16 on the outer surface of the drain layer 10. The heat dissipation layer 16 can provide an efficient and low thermal resistance heat dissipation channel, improve the current carrying capacity and power density of the device, and effectively extend the service life of the device; at the same time, in high-frequency application scenarios, the excellent heat dissipation performance supports higher switching frequencies and speeds, providing technical support for the realization of miniaturized and lightweight power supply systems.

[0062] A third aspect of the present invention provides a chip comprising the semiconductor structure described above.

[0063] A fourth aspect of the present invention provides a circuit comprising the semiconductor structure described above.

[0064] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0065] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0066] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; wherein, from bottom to top, the substrate comprises a base substrate and an oxide isolation layer; The columnar transistor unit formed on the substrate has a layered encapsulation structure, which includes, from the inside out: a source layer, a bulk layer, a drift region layer and a drain layer. m gate holes are evenly spaced in a ring between the source layer and the drain layer, and each hole extends from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and also penetrates the body layer and the drift layer; where m is a positive integer. m oxide layers are formed on the walls of m gate holes respectively; m polycrystalline silicon layers are respectively filled into m gate vias; Among them, the polysilicon layer, together with the oxide layer, source layer, bulk layer, drift layer and drain layer on one side of the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors in the columnar transistor unit.

2. The semiconductor structure according to claim 1, characterized in that, The columns of the transistor unit are arranged in a concentric layered structure.

3. The semiconductor structure according to claim 1, characterized in that, Each gate hole has a ring sector configuration in a cross section perpendicular to the axial direction.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the oxide layer located in the drift region layer is greater than the thickness of the oxide layer located in the bulk region layer.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a heat dissipation layer formed on the outer surface of the drain layer.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The first metal electrode is embedded in the source layer and extends from the top surface to the bottom surface of the source layer along the axial direction of the columnar transistor unit. The second metal electrode is embedded in the drain layer and extends from the top surface to the bottom surface of the drain layer along the axial direction of the columnar transistor unit. m third metal electrodes are embedded in m polysilicon layers and extend from the top surface to the bottom surface of the corresponding polysilicon layer along the axial direction of the columnar transistor unit.

7. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure fabrication method includes: A substrate is provided; wherein, from bottom to top, the substrate comprises a base substrate and an oxide isolation layer; A columnar transistor unit, m gate holes, m oxide layers, and m polysilicon layers are formed on the substrate; where m is a positive integer. The columnar transistor unit has a layered encapsulation structure, which includes, from the inside out, a source layer, a body layer, a drift region layer, and a drain layer. The m gate holes are evenly spaced in a ring between the source layer and the drain layer, and all penetrate from the top surface to the bottom surface along the axial direction of the columnar transistor unit, and penetrate the body layer and the drift region layer. The m oxide layers are formed on the walls of the m gate holes. The m polysilicon layers fill the m gate holes. The polysilicon layers, together with the oxide layer, source layer, body layer, drift region layer, and drain layer on one side in the circumferential direction, constitute a lateral double-diffused field-effect transistor, thereby forming 2m lateral double-diffused field-effect transistors within the columnar transistor unit.

8. The semiconductor structure fabrication method according to claim 7, characterized in that, The formation of columnar transistor units, m gate holes, m oxide layers, and m polysilicon layers on the substrate includes: An initial body region layer and an initial drift region layer are formed on the substrate. The initial body region layer and the initial drift region layer have a layered encapsulation structure, with the initial drift region layer encapsulating the outer surface of the initial body region layer. m gate holes are formed, and the m gate holes are evenly distributed in a ring between the source layer to be formed and the drain layer to be formed. They all penetrate from the top surface to the bottom surface along the axial direction of the columnar transistor unit and penetrate the initial body region layer and the initial drift region layer. m oxide layers are formed on the walls of m gate holes respectively; m polycrystalline silicon layers are filled into m gate holes respectively; A source layer is formed at the center of the initial bulk layer, and a drain layer is formed outside the initial drift layer. The remaining initial bulk layer region is used as the bulk layer, and the remaining initial drift layer region is used as the drift layer.

9. The semiconductor structure fabrication method according to claim 7, characterized in that, The columns of the transistor unit are arranged in a concentric layered structure.

10. The semiconductor structure fabrication method according to claim 7, characterized in that, Each gate hole has a ring sector configuration in a cross section perpendicular to the axial direction.

11. The semiconductor structure fabrication method according to claim 7, characterized in that, The thickness of the oxide layer located in the drift region layer is greater than the thickness of the oxide layer located in the bulk region layer.

12. The semiconductor structure fabrication method according to claim 7, characterized in that, The method further includes forming a heat dissipation layer on the outer surface of the drain layer.

13. The semiconductor structure fabrication method according to claim 7, characterized in that, The method further includes: A first metal electrode is formed within the source layer, and the first metal electrode extends from the top surface to the bottom surface of the source layer along the axial direction of the columnar transistor unit. A second metal electrode is formed within the drain layer, and the second metal electrode extends from the top surface to the bottom surface of the drain layer along the axial direction of the columnar transistor unit. Each of the m polysilicon layers has a third metal electrode formed therein, and the third metal electrode extends from the top surface to the bottom surface of the corresponding polysilicon layer along the axial direction of the columnar transistor unit.

14. A chip, characterized in that, The chip comprises the semiconductor structure according to any one of claims 1-6.

15. A circuit, characterized in that, The circuit comprises the semiconductor structure described in any one of claims 1-6.

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