Display device

Abstract

A display device is provided, comprising: a first transistor including a gate electrode; a second transistor including a lower gate electrode, an upper gate electrode, and a first end electrically connected to an end of the first transistor; a lower gate signal line extending in a first direction; an upper gate signal line disposed on the lower gate signal line and extending in the first direction; and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. In an overlapping region where the lower gate signal line or the upper gate signal line overlaps with the first connection pattern, the entire upper gate signal line overlaps with a portion of the lower gate signal line.

Description

[0001] This application is a divisional application of the invention patent application filed on January 5, 2021, with application number "202110007113.4" and invention title "Display Device". Technical Field

[0002] The embodiment relates to a display device. Background Technology

[0003] A display device is a means of displaying images for providing visual information to a user. A display device may include pixels, and each pixel may include a light-emitting element that generates light and pixel circuitry that provides a driving current to the light-emitting element. The pixel circuitry may include stacked conductive layers.

[0004] In the process of forming conductive layers to create pixel circuits, the conductive layers may become misaligned due to mask misalignment. In this case, the capacitance between the conductive layers in a pixel row may be inconsistent, resulting in inconsistent retrace voltages for the pixel rows. Consequently, blemishes may be detected in the display device, potentially degrading its display quality.

[0005] It will be understood that the background art in the technical section is partly intended to provide useful background information for understanding the technology. However, the background art in the technical section may also include ideas, concepts, or understandings of subjects not disclosed herein that were known or understood by a person skilled in the art prior to the corresponding valid date of submission. Summary of the Invention

[0006] The embodiment provides a display device with improved display quality.

[0007] The display device according to an embodiment may include: a first transistor including a gate electrode disposed on a substrate; a second transistor including a lower gate electrode disposed on the substrate, an upper gate electrode disposed on the lower gate electrode, and a first end electrically connected to an end of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. In an overlapping region where the lower gate signal line or the upper gate signal line can overlap with the first connection pattern, the entire upper gate signal line can overlap with a portion of the lower gate signal line.

[0008] In an embodiment, in the stacked region, the width of the upper gate signal line in the second direction may be smaller than the width of the lower gate signal line in the second direction.

[0009] In an embodiment, the difference between the width of the lower gate signal line in the second direction and the width of the upper gate signal line in the second direction can be greater than about 1 μm.

[0010] In an embodiment, the first connection pattern may extend along a second direction in the overlapping area.

[0011] In an embodiment, the width of the first lower gate signal line along the second direction can be substantially equal both inside and outside the stacked region, and the width of the first upper gate signal line along the second direction both inside and outside the stacked region can be substantially equal.

[0012] In an embodiment, in a plan view, the lower gate signal line may protrude along a second direction in the stacked region.

[0013] In an embodiment, in a plan view, the upper gate signal line may be recessed along a second direction in the stacked region.

[0014] In one embodiment, the first transistor may include a first active layer disposed between a substrate and a gate electrode, and the second transistor may include a second active layer disposed between a lower gate electrode and an upper gate electrode. A first end of the second active layer may be electrically connected to an end of the first active layer.

[0015] In an embodiment, the first active layer of the first transistor may include polysilicon, and the second active layer of the second transistor may include oxide semiconductor.

[0016] In an embodiment, the first connection pattern can electrically connect the gate electrode of the first transistor and the second end of the second active layer of the second transistor.

[0017] In an embodiment, the display device may further include: a second connection pattern that electrically connects the end of the first active layer and the first end of the second active layer, wherein the first connection pattern and the second connection pattern may be disposed on the same layer.

[0018] The display device according to an embodiment may include: a first transistor including a gate electrode disposed on a substrate; a second transistor including a lower gate electrode disposed on the substrate, an upper gate electrode disposed on the lower gate electrode, and a first end electrically connected to an end of the first transistor; a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode; an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode of the first transistor and a second end of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. In an overlapping region where the lower gate signal line or the upper gate signal line can overlap with the first connection pattern, the entire lower gate signal line may overlap with a portion of the upper gate signal line.

[0019] In an embodiment, in the stacked region, the width of the upper gate signal line in the second direction may be larger than the width of the lower gate signal line in the second direction.

[0020] In an embodiment, the difference between the width of the upper gate signal line in the second direction and the width of the lower gate signal line in the second direction can be greater than about 1 μm.

[0021] In an embodiment, the first connection pattern may extend along a second direction in the overlapping area.

[0022] In an embodiment, the width of the first lower gate signal line along the second direction can be substantially equal both inside and outside the stacked region, and the width of the first upper gate signal line along the second direction both inside and outside the stacked region can be substantially equal.

[0023] In an embodiment, in a plan view, the lower gate signal line may be recessed along a second direction in the stacked region.

[0024] In an embodiment, in a plan view, the upper gate signal line may protrude along a second direction in the stacked region.

[0025] In an embodiment, the first transistor may include a first active layer disposed between a substrate and a gate electrode, and the second transistor may include a second active layer disposed between a lower gate electrode and an upper gate electrode, wherein a first end of the second active layer is electrically connected to an end of the first active layer.

[0026] In an embodiment, the first active layer of the first transistor may include polysilicon, and the second active layer of the second transistor may include oxide semiconductor.

[0027] In an embodiment, the first connection pattern can electrically connect the gate electrode of the first transistor and the second end of the second active layer of the second transistor.

[0028] In an embodiment, the display device may further include: a second connection pattern that electrically connects the end of the first active layer and the first end of the second active layer, wherein the first connection pattern and the second connection pattern may be disposed on the same layer.

[0029] In the display device according to the embodiment, in the stacking region where the lower gate signal line or the upper gate signal line can overlap with the first connection pattern, the entire upper gate signal line can overlap with a portion of the lower gate signal line, or the entire lower gate signal line can overlap with a portion of the upper gate signal line, thereby constantly maintaining the capacitance between the lower gate signal line and the first connection pattern, as well as the capacitance between the upper gate signal line and the first connection pattern. Therefore, the flyback voltage of the first connection pattern caused by the gate signals applied to the lower and upper gate signal lines can be constant. Furthermore, no blemishes appear in the display device, thus improving the display quality. Attached Figure Description

[0030] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view showing a display device according to an embodiment; Figure 2 This is an equivalent circuit diagram showing the pixels according to an embodiment; Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown Figure 2 A layout diagram of example pixels in the image; Figure 16 It is along Figure 13 A schematic cross-sectional view taken by line I-I' in the middle; Figure 17 It is shown Figure 13 A layout diagram of an example of region A in the diagram; Figure 18 It is along Figure 17 A schematic cross-sectional view taken from line II-II' in the middle; Figure 19 It is shown Figure 13 A layout diagram of an example of region A in the diagram; Figure 20 It is shown Figure 13A layout diagram of an example of region A in the diagram; Figure 21 This is a diagram showing the flyback voltage of the third node based on the second gate signal; Figure 22 It is shown Figure 13 A layout diagram of an example of region A in the diagram; Figure 23 It is along Figure 22 A schematic cross-sectional view taken from line III-III' in the diagram; Figure 24 It is shown Figure 13 A layout diagram of an example of region A in the diagram; Figure 25 It is shown Figure 13 The layout diagram of an example of region A in the diagram; and Figure 26 It is shown Figure 2 A layout diagram of example pixels in the image. Detailed Implementation

[0031] The display device according to the embodiments will be explained in detail below with reference to the accompanying drawings.

[0032] Some parts not related to the description may be omitted in order to describe the disclosed embodiments, and the same reference numerals refer to the same elements throughout the specification.

[0033] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0034] The terms “and” and “or” can be used in a connecting or separating sense and can be understood as equivalent to “and / or”. In the specification and claims, the phrase “at least one of…” is intended, for the purposes of its meaning and interpretation, to include the meaning of “at least one selected from the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”. It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, these components should not be limited by these terms. These components are used only to distinguish one component from another. For example, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0035] As used here, unless the context clearly indicates otherwise, the singular form “one” or “a (kind / being)” is intended to include the plural form as well.

[0036] It will also be understood that the terms “comprising” and / or “including,” “having” and / or “possessing” are used in this specification, and they or they may indicate the presence of the stated features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components and / or any combination thereof.

[0037] When a layer, film, region, substrate, area, or element is referred to as being "on" another layer, film, region, substrate, area, or element, the layer, film, region, substrate, area, or element may be directly on the other layer, film, region, substrate, area, or element, or an intermediate layer, film, region, substrate, area, or element may exist between them. Conversely, when a layer, film, region, substrate, area, or element is referred to as being "directly on" another layer, film, region, substrate, area, or element, an intermediate layer, film, region, substrate, area, or element may not exist between them. Furthermore, when a layer, film, region, substrate, area, or element is referred to as being "below" another layer, film, region, substrate, area, or element, the layer, film, region, substrate, area, or element may be directly below the other layer, film, region, substrate, area, or element, or an intermediate layer, film, region, substrate, area, or element may exist between them. Conversely, when a layer, membrane, region, substrate, area, or element is referred to as being "directly below" another layer, membrane, region, substrate, area, or element, the intermediate layer, membrane, region, substrate, area, or element may not exist between them. Furthermore, "above" or "on" can include being positioned on or below an object and does not necessarily imply a direction based on gravity.

[0038] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” “above,” etc., as shown in the accompanying drawings, are used to describe the relationship between one element or component and another element or component. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, in the case of flipping the device shown in the drawings, a device positioned “below” or “under” another device may also be placed “above” said other device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0039] For ease of illustration, the dimensions of the components in the accompanying drawings are exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0040] Additionally, the terms "overlapping" or "overlapping" indicate that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented towards" indicate that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, although the first and second elements still face each other, they may be understood as being indirectly opposite each other. When an element is described as "not overlapping" another element or "not overlapping" another element, this may include elements spaced apart from each other, offset from each other, or arranged separately from each other, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art.

[0041] In the specification, expressions such as "A and / or B" mean A, B, or A and B. Furthermore, expressions such as "at least one of A and B" mean A, B, or A and B.

[0042] In the following embodiments, when a component is referred to as “on a plane”, it should be understood as the component being viewed from above, and when a component is referred to as “on a schematic cross-section”, it should be understood as the component being cut vertically and viewed from the side.

[0043] It will be understood that when a layer, region, or component is referred to as "connected" or "bonded" to another layer, region, or component, that layer, region, or component may be "directly connected" or "directly bonded" to said other layer, region, or component, or may be "indirectly connected" or "indirectly bonded" to said other layer, region, or component with other layers, regions, or components situated between them. For example, it will be understood that when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, that layer, region, or component may be "directly electrically connected" or "directly electrically bonded" to said other layer, region, or component, or may be "indirectly electrically connected" or "indirectly electrically bonded" to said other layer, region, or component with other layers, regions, or components situated between them. Furthermore, when an element is referred to as "contacting" another element or "in contact" with another element, the element may be in "electrical contact" or "physical contact" with the other element, or in "indirect contact" or "direct contact" with the other element.

[0044] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated values ​​and indicate an acceptable range of deviation from the particular values ​​as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated values.

[0045] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it is understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] Figure 1 This is a plan view showing a display device according to an embodiment.

[0048] Reference Figure 1 The display device according to an embodiment may include pixels PX. Each pixel PX may refer to a single region defined by dividing a display area for displaying color in a plan view, and one pixel PX may display a predetermined basic color. In other words, one pixel PX may be the smallest unit that can display a color independent of another pixel PX. Pixels PX may be arranged or positioned along a first direction DR1 and a second direction DR2 that intersects or crosses the first direction DR1.

[0049] Figure 2 This is an equivalent circuit diagram showing the pixels according to an embodiment.

[0050] Reference Figure 2 According to an embodiment, a pixel PX may include a pixel circuit PC and a light-emitting element EL. The pixel circuit PC may provide a drive current to the light-emitting element EL. The light-emitting element EL may emit light based on the drive current provided from the pixel circuit PC. The pixel circuit PC may include at least one transistor and at least one capacitor to generate the drive current.

[0051] In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor CAP. However, the disclosure is not limited thereto, and in an embodiment, the pixel circuit PC may include two to six transistors, or eight or more transistors, and / or two or more capacitors.

[0052] The first transistor T1 can be electrically connected between the first node N1 and the second node N2. The gate electrode of the first transistor T1 can be electrically connected to the third node N3. The first transistor T1 can generate a drive current based on the voltage between the first node N1 and the third node N3.

[0053] The second transistor T2 can be electrically connected between the data line 171 and the first node N1. The gate electrode of the second transistor T2 can receive the first gate signal GS1. The second transistor T2 can transmit the data voltage DV to the first node N1 based on the first gate signal GS1.

[0054] The third transistor T3 can be electrically connected between the second node N2 and the third node N3. The gate electrode of the third transistor T3 can receive the second gate signal GS2. The third transistor T3 can be electrically connected to the second node N2 and the third node N3 based on the second gate signal GS2 to compensate for the threshold voltage of the first transistor T1.

[0055] A fourth transistor T4 can be electrically connected between the first initialization voltage line 133 and the third node N3. The gate electrode of the fourth transistor T4 can receive a third gate signal GS3. In an embodiment, when pixel PX is included in the Nth (N is a positive integer equal to or greater than 2) pixel row, the third gate signal GS3 can be a first gate signal applied to the (N-1)th pixel row. The fourth transistor T4 can receive a first initialization voltage IV1 from the first initialization voltage line 133 and can transmit the first initialization voltage IV1 to the third node N3 based on the third gate signal GS3 to initialize the gate electrode of the first transistor T1.

[0056] The fifth transistor T5 can be electrically connected between the power line 172 and the first node N1. The gate electrode of the fifth transistor T5 can receive the transmit control signal EM. The power line 172 can transmit the first power voltage VDD from the first power source.

[0057] The sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4. The gate electrode of the sixth transistor T6 can receive the transmit control signal EM. The fifth transistor T5 and the sixth transistor T6 can transmit the drive current generated from the first transistor T1 to the light-emitting element EL based on the transmit control signal EM.

[0058] The seventh transistor T7 can be electrically connected between the second initialization voltage line 161 and the fourth node N4. The gate electrode of the seventh transistor T7 can receive the fourth gate signal GS4. In an embodiment, if pixel PX is included in the Nth pixel row, the fourth gate signal GS4 can be the first gate signal applied to the (N+1)th pixel row. The seventh transistor T7 can receive the second initialization voltage IV2 from the second initialization voltage line 161 and can transmit the second initialization voltage IV2 to the fourth node N4 based on the fourth gate signal GS4 to initialize the light-emitting element EL.

[0059] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor with a single-gate structure, while each of the third transistor T3 and the fourth transistor T4 may be a transistor with a dual-gate structure. However, the disclosure is not limited thereto. In such an embodiment, the gate electrode of each of the third transistor T3 and the fourth transistor T4 may include a lower gate electrode and an upper gate electrode, and the lower gate electrode and the upper gate electrode may be electrically connected to each other.

[0060] In this embodiment, the active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed of polysilicon, while the active layer of each of the third transistor T3 and the fourth transistor T4 may be formed of oxide semiconductor. In this embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS, while each of the third transistor T3 and the fourth transistor T4 may be an NMOS. However, the disclosure is not limited thereto.

[0061] Capacitor CAP can be electrically connected between power line 172 and the third node N3. When the second transistor T2 is off, capacitor CAP can maintain the voltage between the first node N1 and the third node N3, allowing the light-emitting element EL to emit light.

[0062] The light-emitting element EL can be electrically connected between the fourth node N4 and the second power supply. The second power supply can provide a second power voltage VSS. In an embodiment, the second power voltage VSS can be less than the first power voltage VDD. The light-emitting element EL can emit light based on the driving current transmitted from the pixel circuit PC.

[0063] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 It is shown Figure 2 The layout diagram of an example pixel PX in the diagram. Figure 16 It is along Figure 13 A schematic cross-sectional view taken from line I-I' in the diagram.

[0064] Reference Figures 2 to 16 The pixel PX may include a first active layer 110, a first conductive layer 120, a second conductive layer 130, a second active layer 140, a third conductive layer 150, a fourth conductive layer 160, a fifth conductive layer 170, a first electrode 180, an emitter layer 190, and a second electrode 200, which may be disposed on the substrate 100.

[0065] Within the spirit and scope of the disclosure, substrate 100 may be an insulating substrate including glass, quartz, plastic, etc. In an embodiment, substrate 100 may include a first flexible layer, a first barrier layer disposed on the first flexible layer, a second flexible layer disposed on the first barrier layer, and a second barrier layer disposed on the second flexible layer. Within the spirit and scope of the disclosure, the first flexible layer and the second flexible layer may include organic insulating materials (such as polyimide (PI), etc.). Within the spirit and scope of the disclosure, the first barrier layer and the second barrier layer may include inorganic insulating materials (such as silicon oxide, silicon nitride, amorphous silicon, etc.).

[0066] The first active layer 110 may be disposed on the substrate 100. In an embodiment, the first active layer 110 may include polycrystalline silicon. However, the disclosure is not limited thereto, and in an embodiment, within the spirit and scope of the disclosure, the first active layer 110 may include amorphous silicon, oxide semiconductor, etc.

[0067] A buffer layer may be disposed between the substrate 100 and the first active layer 110. The buffer layer can prevent impurities from penetrating through the substrate 100 toward the surface above the substrate 100. The buffer layer can provide a planarized upper surface above the substrate 100. Within the spirit and scope of the disclosure, the buffer layer may include an inorganic insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.). The buffer layer may be omitted.

[0068] The first conductive layer 120 may be disposed on the first active layer 110. Within the spirit and scope of the disclosure, the first conductive layer 120 may include a conductive material (such as molybdenum (Mo), copper (Cu), etc.).

[0069] The first insulating layer 101 may be disposed between the first active layer 110 and the first conductive layer 120. Within the spirit and scope of the disclosure, the first insulating layer 101 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0070] The first conductive layer 120 may include a first gate signal line 121, an emitter control signal line 122, and a conductive pattern 123. The first gate signal line 121 may extend in a first direction DR1. The emitter control signal line 122 may be spaced apart from the first gate signal line 121 and may extend in the first direction DR1. The conductive pattern 123 may be positioned or disposed between the first gate signal line 121 and the emitter control signal line 122.

[0071] The first portion of the first gate signal line 121 superimposed on the first active layer 110 can form the gate electrode of the second transistor T2, and the second portion of the first gate signal line 121 superimposed on the first active layer 110 can form the gate electrode of the seventh transistor T7. The portion of the first active layer 110 superimposed on the gate electrode of the second transistor T2 can be the channel region of the second transistor T2, and the portion of the first active layer 110 superimposed on the gate electrode of the seventh transistor T7 can be the channel region of the seventh transistor T7. Therefore, the first portion of the first gate signal line 121 and the first active layer 110 can form the second transistor T2, and the second portion of the first gate signal line 121 and the first active layer 110 can form the seventh transistor T7.

[0072] The first portion of the transmit control signal line 122 superimposed on the first active layer 110 can form the gate electrode of the fifth transistor T5, and the second portion of the transmit control signal line 122 superimposed on the first active layer 110 can form the gate electrode of the sixth transistor T6. The portion of the first active layer 110 superimposed on the gate electrode of the fifth transistor T5 can be the channel region of the fifth transistor T5, and the portion of the first active layer 110 superimposed on the gate electrode of the sixth transistor T6 can be the channel region of the sixth transistor T6. Therefore, the first portion of the transmit control signal line 122 and the first active layer 110 can form the fifth transistor T5, and the second portion of the transmit control signal line 122 and the first active layer 110 can form the sixth transistor T6.

[0073] The portion of the conductive pattern 123 that overlaps with the first active layer 110 can form the gate electrode of the first transistor T1. The portion of the first active layer 110 that overlaps with the gate electrode of the first transistor T1 can form the channel region of the first transistor T1. Therefore, the portion of the conductive pattern 123 and the first active layer 110 can form the first transistor T1.

[0074] The second conductive layer 130 may be disposed on the first conductive layer 120. Within the spirit and scope of the disclosure, the second conductive layer 130 may include a conductive material (such as molybdenum (Mo), copper (Cu), etc.).

[0075] The second insulating layer 102 may be disposed between the first conductive layer 120 and the second conductive layer 130. Within the spirit and scope of the disclosure, the second insulating layer 102 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0076] The second conductive layer 130 may include a first lower gate signal line 131, a second lower gate signal line 132, a first initialization voltage line 133, and a conductive line 134. The first lower gate signal line 131 may extend in a first direction DR1. The second lower gate signal line 132 may be spaced apart from the first lower gate signal line 131 and may extend in the first direction DR1. The first initialization voltage line 133 may be spaced apart from the second lower gate signal line 132 and may extend in the first direction DR1. The conductive line 134 may be spaced apart from the first lower gate signal line 131 and may extend in the first direction DR1.

[0077] Conductive line 134 can be stacked with conductive pattern 123. Conductive pattern 123 and conductive line 134 can form capacitor CAP.

[0078] The second active layer 140 may be disposed on the second conductive layer 130. The second active layer 140 may not be stacked with the first active layer 110. In an embodiment, the second active layer 140 may include an oxide semiconductor. However, the disclosure is not limited thereto, and in an embodiment, within the spirit and scope of the disclosure, the second active layer 140 may include amorphous silicon, polycrystalline silicon, etc.

[0079] The third insulating layer 103 may be disposed between the second conductive layer 130 and the second active layer 140. Within the spirit and scope of the disclosure, the third insulating layer 103 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0080] The third conductive layer 150 may be disposed on the second active layer 140. Within the spirit and scope of the disclosure, the third conductive layer 150 may include a conductive material (such as molybdenum (Mo), copper (Cu), etc.).

[0081] The fourth insulating layer 104 may be disposed between the second active layer 140 and the third conductive layer 150. Within the spirit and scope of the disclosure, the fourth insulating layer 104 may include an inorganic insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0082] The third conductive layer 150 may include a first upper gate signal line 151 and a second upper gate signal line 152. The first upper gate signal line 151 may extend in a first direction DR1. The second upper gate signal line 152 may be spaced apart from the first upper gate signal line 151 and may extend in the first direction DR1.

[0083] The portion of the first lower gate signal line 131 stacked with the second active layer 140 can form the lower gate electrode of the third transistor T3, and the portion of the first upper gate signal line 151 stacked with the second active layer 140 can form the upper gate electrode of the third transistor T3. The portion of the second active layer 140 stacked with the lower and upper gate electrodes of the third transistor T3 can be the channel region of the third transistor T3. Therefore, the aforementioned portions of the first lower gate signal line 131, the second active layer 140, and the first upper gate signal line 151 can form the third transistor T3. The third transistor T3 can be a transistor with a dual-gate structure.

[0084] The portion of the second lower gate signal line 132 that overlaps with the second active layer 140 can form the lower gate electrode of the fourth transistor T4, and the portion of the second upper gate signal line 152 that overlaps with the second active layer 140 can form the upper gate electrode of the fourth transistor T4. The portion of the second active layer 140 that overlaps with the lower and upper gate electrodes of the fourth transistor T4 can be the channel region of the fourth transistor T4. Therefore, the aforementioned portion of the second lower gate signal line 132, the second active layer 140, and the second upper gate signal line 152 can form the fourth transistor T4. The fourth transistor T4 can be a transistor with a dual-gate structure.

[0085] A fourth conductive layer 160 may be disposed on the third conductive layer 150. Within the spirit and scope of the disclosure, the fourth conductive layer 160 may include a conductive material (such as aluminum (Al), titanium (Ti), copper (Cu), etc.). In embodiments, the fourth conductive layer 160 may have a multilayer structure including stackable Ti layers, Al layers, and Ti layers.

[0086] The fifth insulating layer 105 may be disposed between the third conductive layer 150 and the fourth conductive layer 160. Within the spirit and scope of the disclosure, the fifth insulating layer 105 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) and / or organic insulating materials (such as polyimide (PI), etc.).

[0087] The fourth conductive layer 160 may include a second initialization voltage line 161, a first connection pattern 162, a second connection pattern 163, a third connection pattern 164, a first contact pattern 165, a second contact pattern 166, and a third contact pattern 167. The second initialization voltage line 161 may extend in a first direction DR1. The second initialization voltage line 161 may be electrically connected to the first active layer 110 through a first contact hole CH1. Therefore, the second initialization voltage line 161 may be electrically connected to the seventh transistor T7.

[0088] The first connection pattern 162 may be spaced apart from the second initialization voltage line 161. The first connection pattern 162 may be electrically connected to the conductive pattern 123 through the second contact hole CH2, and may be electrically connected to the second active layer 140 through the third contact hole CH3. Therefore, the first connection pattern 162 may electrically connect the gate electrode of the first transistor T1 and the second end of the third transistor T3. For example, the first connection pattern 162 may electrically connect the gate electrode of the first transistor T1 and the second end 142 of the second active layer 140.

[0089] The second connection pattern 163 may be spaced apart from the first connection pattern 162. The second connection pattern 163 may be electrically connected to the first active layer 110 through the fourth contact hole CH4, and may be electrically connected to the second active layer 140 through the fifth contact hole CH5. Therefore, the second connection pattern 163 may electrically connect the end of the first transistor T1 and the first end of the third transistor T3. As an example, the second connection pattern 163 may electrically connect the end 111 of the first active layer 110 and the first end 141 of the second active layer 140.

[0090] The third connection pattern 164 may be spaced apart from the second connection pattern 163. The third connection pattern 164 can be electrically connected to the first initialization voltage line 133 through the sixth contact hole CH6, and can be electrically connected to the second active layer 140 through the seventh contact hole CH7. Therefore, the third connection pattern 164 can electrically connect the first initialization voltage line 133 and the second active layer 140. The first initialization voltage line 133 can be electrically connected to the fourth transistor T4 through the third connection pattern 164.

[0091] The first contact pattern 165 may be spaced apart from the third connection pattern 164. The first contact pattern 165 may be electrically connected to the first active layer 110 through the eighth contact hole CH8. Therefore, the first contact pattern 165 may be electrically connected to the second transistor T2.

[0092] The second contact pattern 166 may be spaced apart from the first contact pattern 165. The second contact pattern 166 may be electrically connected to the first active layer 110 through the ninth contact hole CH9, and may be electrically connected to the conductive line 134 through the tenth contact hole CH10. Therefore, the second contact pattern 166 may be electrically connected to the fifth transistor T5 and the capacitor CAP.

[0093] The third contact pattern 167 may be spaced apart from the second contact pattern 166. The third contact pattern 167 may be electrically connected to the first active layer 110 through the eleventh contact hole CH11. Therefore, the third contact pattern 167 may be electrically connected to the sixth transistor T6.

[0094] A fifth conductive layer 170 may be disposed on the fourth conductive layer 160. Within the spirit and scope of the disclosure, the fifth conductive layer 170 may include a conductive material (such as aluminum (Al), titanium (Ti), copper (Cu), etc.). In embodiments, the fifth conductive layer 170 may have a multilayer structure including stackable Ti layers, Al layers, and Ti layers.

[0095] The sixth insulating layer 106 may be disposed between the fourth conductive layer 160 and the fifth conductive layer 170. Within the spirit and scope of the disclosure, the sixth insulating layer 106 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) and / or organic insulating materials (such as polyimide (PI), etc.).

[0096] The fifth conductive layer 170 may include a data line 171, a power voltage line 172, and a fourth contact pattern 173. The data line 171 may extend in the second direction DR2. The data line 171 may be electrically connected to the first contact pattern 165 through the twelfth contact hole CH12. Therefore, the data line 171 may be electrically connected to the second transistor T2 through the first contact pattern 165.

[0097] The power voltage line 172 may be spaced apart from the data line 171 and may extend in the second direction DR2. The power voltage line 172 may be electrically connected to the second contact pattern 166 through the thirteenth contact hole CH13. Therefore, the power voltage line 172 may be electrically connected to the fifth transistor T5 and the capacitor CAP through the second contact pattern 166.

[0098] The fourth contact pattern 173 may be spaced apart from the power voltage line 172. The fourth contact pattern 173 may be electrically connected to the third contact pattern 167 through the fourteenth contact hole CH14.

[0099] The first electrode 180 may be disposed on the fifth conductive layer 170. Within the spirit and scope of the disclosure, the first electrode 180 may include a conductive material (such as a metal, alloy, transparent conductive oxide, etc.). For example, within the spirit and scope of the disclosure, the first electrode 180 may include silver (Ag), indium tin oxide (ITO), etc. In embodiments, the first electrode 180 may have a multilayer structure including stackable ITO layers, Ag layers, and ITO layers.

[0100] The seventh insulating layer 107 may be disposed between the fifth conductive layer 170 and the first electrode 180. Within the spirit and scope of the disclosure, the seventh insulating layer 107 may include inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) and / or organic insulating materials (such as polyimide (PI), etc.).

[0101] The first electrode 180 can be electrically connected to the fourth contact pattern 173 through a contact hole. Therefore, the first electrode 180 can be electrically connected to the sixth transistor T6 through the third contact pattern 167 and the fourth contact pattern 173.

[0102] An eighth insulating layer 108 may be disposed on the first electrode 180. The eighth insulating layer 108 may cover or overlap the first electrode 180, and may be disposed on the seventh insulating layer 107. The eighth insulating layer 108 may have a pixel opening exposing at least a portion of the first electrode 180. In an embodiment, the pixel opening may expose a central portion of the first electrode 180, and the eighth insulating layer 108 may cover or overlap a peripheral portion of the first electrode 180. Within the spirit and scope of the disclosure, the eighth insulating layer 108 may comprise an organic insulating material (such as polyimide (PI)).

[0103] The emitting layer 190 may be disposed on the first electrode 180. The emitting layer 190 may be disposed on the first electrode 180 exposed by the pixel opening. The emitting layer 190 may include at least one of organic light-emitting materials and quantum dots.

[0104] In the embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. For example, within the spirit and scope of the disclosure, low-molecular-weight organic compounds may include copper phthalocyanine, diphenylbenzidine (N,N'-diphenylbenzidine), trihydroxyquinoline aluminum (tri-(8-hydroxyquinoline)aluminum), etc. Within the spirit and scope of the disclosure, high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, etc.

[0105] In embodiments, the quantum dot may include a core comprising group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. In embodiments, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell can prevent chemical denaturation of the core, thereby serving as a protective layer for maintaining semiconductor properties and a charging layer for imparting electrophoretic properties to the quantum dot.

[0106] The second electrode 200 can be disposed on the emitting layer 190. In an embodiment, the second electrode 200 can also be disposed on the eighth insulating layer 108. Within the spirit and scope of the disclosure, the second electrode 200 may include conductive materials (such as metals, alloys, transparent conductive oxides, etc.). For example, within the spirit and scope of the disclosure, the second electrode 200 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode 180, the emitting layer 190, and the second electrode 200 can form a light-emitting element EL.

[0107] Figure 17 It is shown Figure 13 The layout diagram of region A in the example. Figure 18 It is along Figure 17 A schematic cross-sectional view taken from line II-II' in the diagram.

[0108] Reference Figure 17 and Figure 18 A first upper gate signal line 151 may be disposed on a first lower gate signal line 131, and a first connection pattern 162 may be disposed on the first upper gate signal line 151. The first connection pattern 162 may intersect or cross with the first lower gate signal line 131 and the first upper gate signal line 151, which may extend in the first direction DR1. The area where the first lower gate signal line 131 or the first upper gate signal line 151 may overlap with the first connection pattern 162 may be defined as an overlap region OA. The first connection pattern 162 may extend in the overlap region OA along the second direction DR2.

[0109] In the stacked region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be smaller than the width 131W of the first lower gate signal line 131 in the second direction DR2. The entire first upper gate signal line 151 can overlap with a portion of the first lower gate signal line 131 in the stacked region OA. In other words, a portion of the first lower gate signal line 131 can overlap with the first upper gate signal line 151 in the stacked region OA, and another portion of the first lower gate signal line 131 can not overlap with the first upper gate signal line 151 in the stacked region OA. For example, the central portion of the first lower gate signal line 131 in the second direction DR2 can overlap with the first upper gate signal line 151 in the stacked region OA, and the side portion of the first lower gate signal line 131 in the second direction DR2 can not overlap with the first upper gate signal line 151 in the stacked region OA.

[0110] In the comparative example, when the first lower gate signal line and the first upper gate signal line partially overlap each other in the stacked region, the capacitance between the first lower gate signal line and the first upper gate signal line changes due to tolerances in the process of forming the first upper gate signal line on the first lower gate signal line. However, in the embodiment, in the stacked region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be smaller than the width 131W of the first lower gate signal line 131 in the second direction DR2, and the entire first upper gate signal line 151 can overlap with a portion of the first lower gate signal line 131 in the stacked region OA. Therefore, although tolerances in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131 are taken into account, the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be maintained constant.

[0111] In an embodiment, in the stacked region OA, the difference between the width 131W of the first lower gate signal line 131 in the second direction DR2 and the width 151W of the first upper gate signal line 151 in the second direction DR2 can be greater than approximately 1 μm. In other words, in the stacked region OA, the difference between the width 131W of the first lower gate signal line 131 in the second direction DR2 and the width 151W of the first upper gate signal line 151 in the second direction DR2 can be greater than approximately 1 μm. In the process of forming the first upper gate signal line 151 on the first lower gate signal line 131, a tolerance smaller than approximately 0.5 μm may occur in the second direction DR2. Because the difference between the width 131W of the first lower gate signal line 131 and the width 151W of the first upper gate signal line 151 in the second direction DR2 can be greater than about 1 μm in the stacked region OA, although the process of forming the first upper gate signal line 151 on the first lower gate signal line 131 may have a tolerance smaller than about 0.5 μm in the second direction DR2, the entire first upper gate signal line 151 can overlap with a portion of the first lower gate signal line 131 in the stacked region OA.

[0112] In an embodiment, the width of the first lower gate signal line 131 along the second direction DR2 and the width of the first upper gate signal line 151 along the second direction DR2 can each be constant. For example, the width of the first lower gate signal line 131 outside the stacked region OA along the second direction DR2 can be substantially equal to the width 131W of the first lower gate signal line 131 inside the stacked region OA along the second direction DR2, and the width of the first upper gate signal line 151 outside the stacked region OA along the second direction DR2 can be substantially equal to the width 151W of the first upper gate signal line 151 inside the stacked region OA along the second direction DR2.

[0113] Figure 19 It is shown Figure 13 The layout diagram of region A in the example. Figure 20 It is shown Figure 13 The layout diagram of region A in the example.

[0114] Reference Figure 19In one embodiment, the first lower gate signal line 131 may protrude along the second direction DR2 in a plan view within the stacked region OA. In such an embodiment, a portion of the first upper gate signal line 151 outside the stacked region OA may not be stacked with the first lower gate signal line 131, and the first lower gate signal line 131 may have a protruding portion 131P protruding along the second direction DR2 within the stacked region OA. For example, the width of the first lower gate signal line 131 outside the stacked region OA along the second direction DR2 may be smaller than the width 131W of the first lower gate signal line 131 inside the stacked region OA along the second direction DR2, and the width of the first upper gate signal line 151 outside the stacked region OA along the second direction DR2 may be substantially equal to the width 151W of the first upper gate signal line 151 inside the stacked region OA along the second direction DR2.

[0115] Reference Figure 20 In one embodiment, the first upper gate signal line 151 may be recessed along the second direction DR2 in a plan view within the stacked region OA. In such an embodiment, a portion of the first upper gate signal line 151 outside the stacked region OA may not be stacked with the first lower gate signal line 131, and the first upper gate signal line 151 may have a recessed portion 151R recessed along the second direction DR2 within the stacked region OA. For example, the width of the first lower gate signal line 131 outside the stacked region OA along the second direction DR2 may be substantially equal to the width 131W of the first lower gate signal line 131 inside the stacked region OA along the second direction DR2, and the width of the first upper gate signal line 151 outside the stacked region OA along the second direction DR2 may be larger than the width 151W of the first upper gate signal line 151 inside the stacked region OA along the second direction DR2.

[0116] Figure 21 This is a diagram showing the flyback voltage of the third node N3 based on the second gate signal GS2.

[0117] Reference Figure 2 , Figure 18 and Figure 21 When the second gate signal GS2 applied to the gate electrode of the third transistor T3 changes from low to high, the second node N2 and the third node N3 can be electrically connected to each other, allowing the first transistor T1 to be diode-connected. Then, when the second transistor T2 is turned on based on the first gate signal GS1, the data voltage DV can be applied to the first node N1. Therefore, the voltage V_N3, which can compensate for the threshold voltage of the first transistor T1 from the data voltage DV, can be applied to the third node N3. Then, when the second gate signal GS2 changes from high to low, the voltage V_N3 of the third node N3 can increase or decrease by the same amount as the flyback voltage V_KB.

[0118] Because capacitors can be formed in the stacked region OA between the first lower gate signal line 131 and the first connection pattern 162, and between the first upper gate signal line 151 and the first connection pattern 162, the first lower gate signal line 131 and the first upper gate signal line 151 will electrically affect the first connection pattern 162. When the second gate signal GS2 transmitted by the first lower gate signal line 131 and the first upper gate signal line 151 changes from a high level to a low level, the voltage V_N3 of the first connection pattern 162 at the third node N3 can increase or decrease the flyback voltage V_KB by that amount.

[0119] In the comparative example, where the retrace voltages V_KB appearing in the pixel rows may differ from one another, blemishes may appear in the display device. However, in the embodiment, because the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be maintained constant, the retrace voltages V_KB appearing in the pixel rows can be substantially equal to one another. Therefore, blemishes will not appear in the display device, and the display quality of the display device can be improved.

[0120] In the following text, references will not be repeated. Figures 22 to 25 The described display device can be compared with the reference. Figures 17 to 20 The description of the display device consists of components that are substantially the same as or similar to those in the device.

[0121] Figure 22 It is shown Figure 13 The layout diagram of region A in the example. Figure 23 It is along Figure 22 A schematic cross-sectional view taken from line III-III' in the diagram.

[0122] Reference Figure 22 and Figure 23In the stacked region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be larger than the width 131W of the first lower gate signal line 131 in the second direction DR2. The entire first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the stacked region OA. In other words, a portion of the first upper gate signal line 151 can overlap with the first lower gate signal line 131 in the stacked region OA, and another portion of the first upper gate signal line 151 can not overlap with the first lower gate signal line 131 in the stacked region OA. For example, the central portion of the first upper gate signal line 151 in the second direction DR2 can overlap with the first lower gate signal line 131 in the stacked region OA, and the side portion of the first upper gate signal line 151 in the second direction DR2 can not overlap with the first lower gate signal line 131 in the stacked region OA.

[0123] In an embodiment, in the stacked region OA, the width 151W of the first upper gate signal line 151 in the second direction DR2 can be larger than the width 131W of the first lower gate signal line 131 in the second direction DR2, and the entire first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the stacked region OA. Therefore, although tolerances in the process of forming the first upper gate signal line 151 on the first lower gate signal line 131 are taken into account, the first upper gate signal line 151 can shield the first lower gate signal line 131 from the first connection pattern 162. Therefore, the capacitance between the first lower gate signal line 131 and the first connection pattern 162 and the capacitance between the first upper gate signal line 151 and the first connection pattern 162 can be maintained constant.

[0124] In an embodiment, in the stacked region OA, the difference between the width 151W of the first upper gate signal line 151 in the second direction DR2 and the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than approximately 1 μm. In other words, in the stacked region OA, the difference between the width 151W of the first upper gate signal line 151 in the second direction DR2 and the width 131W of the first lower gate signal line 131 in the second direction DR2 can be greater than approximately 1 μm. In the process of forming the first upper gate signal line 151 on the first lower gate signal line 131, a tolerance smaller than approximately 0.5 μm may occur in the second direction DR2. In the stacked region OA, since the difference between the width 151W of the first upper gate signal line 151 in the second direction DR2 and the width 131W of the first lower gate signal line 131 in the second direction DR2 is greater than about 1 μm, although the process of forming the first upper gate signal line 151 on the first lower gate signal line 131 may have a tolerance smaller than about 0.5 μm in the second direction DR2, the entire first lower gate signal line 131 can overlap with a portion of the first upper gate signal line 151 in the stacked region OA.

[0125] In this embodiment, the width of the first lower gate signal line 131 along the second direction DR2 and the width of the first upper gate signal line 151 along the second direction DR2 can each be constant. For example, the width of the first lower gate signal line 131 along the second direction DR2 outside the stacked region OA can be substantially equal to the width 131W of the first lower gate signal line 131 along the second direction DR2 inside the stacked region OA, and the width of the first upper gate signal line 151 along the second direction DR2 outside the stacked region OA can be substantially equal to the width 151W of the first upper gate signal line 151 along the second direction DR2 inside the stacked region OA. In other words, the width of the first lower gate signal line 131 along the second direction DR2 both inside and outside the stacked region OA can be substantially equal. Similarly, the width of the first upper gate signal line 151 along the second direction DR2 both inside and outside the stacked region OA can be substantially equal.

[0126] Figure 24 It is shown Figure 13 The layout diagram of region A in the example. Figure 25 It is shown Figure 13 The layout diagram of region A in the example.

[0127] Reference Figure 24In one embodiment, the first lower gate signal line 131 may be recessed along the second direction DR2 in the plan view within the stacked region OA. In such an embodiment, a portion of the first lower gate signal line 131 outside the stacked region OA may not be stacked with the first upper gate signal line 151, and the first lower gate signal line 131 may have a recessed portion 131R in the stacked region OA that is recessed along the second direction DR2. For example, the width of the first lower gate signal line 131 outside the stacked region OA along the second direction DR2 may be larger than the width 131W of the first lower gate signal line 131 inside the stacked region OA along the second direction DR2, and the width of the first upper gate signal line 151 outside the stacked region OA along the second direction DR2 may be substantially equal to the width 151W of the first upper gate signal line 151 inside the stacked region OA along the second direction DR2.

[0128] Reference Figure 25 In one embodiment, in the stacked region OA, the first upper gate signal line 151 may protrude along the second direction DR2 in the plan view. In such an embodiment, a portion of the first lower gate signal line 131 outside the stacked region OA may not be stacked with the first upper gate signal line 151, and the first upper gate signal line 151 may have a protruding portion 151P protruding along the second direction DR2 in the stacked region OA. For example, the width of the first lower gate signal line 131 outside the stacked region OA along the second direction DR2 may be substantially equal to the width 131W of the first lower gate signal line 131 inside the stacked region OA along the second direction DR2, and the width of the first upper gate signal line 151 outside the stacked region OA along the second direction DR2 may be smaller than the width 151W of the first upper gate signal line 151 inside the stacked region OA along the second direction DR2.

[0129] Figure 26 It is shown Figure 2 A layout diagram of an example pixel PX. Except for the structure of the first connecting pattern 1162 and the location of the third contact hole CH3, refer to... Figure 26 The described pixel PX can be compared with the reference Figures 3 to 16 The described pixels PX are essentially the same or similar. Therefore, the description of repeating elements will be omitted.

[0130] Reference Figure 26In this embodiment, the third contact hole CH3, which electrically connects the second active layer 140 and the first connection pattern 1162, may not be superimposed on the first gate signal line 121. In other words, the third contact hole CH3 and the first gate signal line 121 may be spaced apart from each other in a planar view. Therefore, the path used to compensate the threshold voltage of the first transistor T1 through the second active layer 140, the third contact hole CH3, and the first connection pattern 1162 may not be superimposed on the first gate signal line 121 that transmits the first gate signal.

[0131] When the third contact hole CH3 overlaps with the first gate signal line 121 (in other words, when the path used to compensate the threshold voltage of the first transistor T1 overlaps with the first gate signal line 121), the resistance of the second active layer 140 increases due to the first gate signal transmitted through the first gate signal line 121, thus reducing the on-state current of the third transistor T3. However, in an embodiment, the third contact hole CH3, which electrically connects the second active layer 140 and the first connection pattern 1162, may not overlap with the first gate signal line 121, so that the first gate signal transmitted through the first gate signal line 121 can substantially not affect the path used to compensate the threshold voltage of the first transistor T1. Therefore, the reduction in the on-state current of the third transistor T3 due to the increase in the resistance of the second active layer 140 can be prevented.

[0132] Within the spirit and scope of the disclosure, the display device according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0133] Although the display device according to the embodiments has been described with reference to the accompanying drawings, the embodiments shown are examples and modifications and changes may be made without departing from the technical spirit described in the claims.

Claims

1. A display device, the display device comprising: A first transistor includes: a first active layer disposed on a substrate, the first active layer including a first channel; and a gate electrode disposed on the first active layer, the gate electrode being stacked with the first channel; An insulating layer is disposed on the gate electrode; A conductive layer is disposed on the insulating layer, and the conductive layer and the gate electrode form a capacitor; The second transistor includes: a lower gate electrode disposed on the insulating layer; a second active layer disposed on the lower gate electrode, the second active layer including a second channel stacked with the lower gate electrode, and a first end of the second active layer electrically connected to an end of the first active layer; and an upper gate electrode disposed on the second active layer, the upper gate electrode being stacked with the second channel. A lower gate signal line extends in a first direction, and a portion of the lower gate signal line forms the lower gate electrode; An upper gate signal line is disposed on the lower gate signal line and extends in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and A first connection pattern is disposed on the upper gate signal line, and connects the second end of the second active layer to the gate electrode, wherein... The width of the upper gate signal line overlapping with the first connection pattern is greater than the width of the lower gate signal line overlapping with the first connection pattern. The first active layer of the first transistor comprises polysilicon. The second active layer of the second transistor comprises an oxide semiconductor, and The conductive layer and the lower gate electrode are disposed on the same layer.

2. The display device according to claim 1, wherein, The width of the upper gate signal line overlapping with the first connection pattern is greater than the width of the upper gate signal line overlapping with the second active layer of the second transistor.

3. The display device according to claim 2, wherein, The width of the lower gate signal line overlapping with the first connection pattern is equal to the width of the lower gate signal line overlapping with the second active layer of the second transistor.

4. The display device according to claim 1, wherein, The width of the lower gate signal line overlapping with the first connection pattern is smaller than the width of the lower gate signal line overlapping with the second active layer of the second transistor.

5. The display device according to claim 4, wherein, The width of the upper gate signal line overlapping with the first connection pattern is equal to the width of the upper gate signal line overlapping with the second active layer of the second transistor.

6. The display device according to claim 1, wherein, The first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction that intersects the first direction.

7. The display device according to claim 6, wherein, The difference between the width of the upper gate signal line and the width of the lower gate signal line is greater than 1 μm.

8. The display device according to claim 6, wherein, The first connection pattern extends in the second direction.

9. The display device according to claim 6, wherein, In the plan view, the first region where the lower gate signal line overlaps with the first connection pattern is located within the second region where the upper gate signal line overlaps with the first connection pattern. The width of the lower gate signal line in the second direction is equal both inside and outside the first region, and The width of the upper gate signal line is equal both inside and outside the second region in the second direction.

10. The display device according to claim 1, further comprising: The second connection pattern electrically connects the end of the first active layer and the first end of the second active layer. The first connection pattern and the second connection pattern are disposed on the same layer.

11. A display device, the display device comprising: A first transistor includes: a first active layer disposed on a substrate, the first active layer including a first channel; and a gate electrode disposed on the first active layer, the gate electrode being stacked with the first channel; An insulating layer is disposed on the gate electrode; A conductive layer is disposed on the insulating layer, and the conductive layer and the gate electrode form a capacitor; The second transistor includes: a lower gate electrode disposed on the insulating layer; a second active layer disposed on the lower gate electrode, the second active layer including a second channel stacked with the lower gate electrode, and a first end of the second active layer electrically connected to an end of the first active layer; and an upper gate electrode disposed on the second active layer, the upper gate electrode being stacked with the second channel. A lower gate signal line extends in a first direction, and a portion of the lower gate signal line forms the lower gate electrode; An upper gate signal line is disposed on the lower gate signal line and extends in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and A first connection pattern is disposed on the upper gate signal line, and connects the second end of the second active layer to the gate electrode, wherein... The width of the upper gate signal line overlapping with the first connection pattern is smaller than the width of the lower gate signal line overlapping with the first connection pattern. The first active layer of the first transistor comprises polysilicon. The second active layer of the second transistor comprises an oxide semiconductor, and The conductive layer and the lower gate electrode are disposed on the same layer.

12. The display device according to claim 11, wherein, The width of the upper gate signal line overlapping with the first connection pattern is smaller than the width of the upper gate signal line overlapping with the second active layer of the second transistor.

13. The display device according to claim 12, wherein, The width of the lower gate signal line overlapping with the first connection pattern is equal to the width of the lower gate signal line overlapping with the second active layer of the second transistor.

14. The display device according to claim 11, wherein, The width of the lower gate signal line overlapping with the first connection pattern is greater than the width of the lower gate signal line overlapping with the second active layer of the second transistor.

15. The display device according to claim 14, wherein, The width of the upper gate signal line overlapping with the first connection pattern is equal to the width of the upper gate signal line overlapping with the second active layer of the second transistor.

16. The display device according to claim 11, wherein, The first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction that intersects the first direction.

17. The display device according to claim 16, wherein, The difference between the width of the lower gate signal line and the width of the upper gate signal line is greater than 1 μm.

18. The display device according to claim 16, wherein, The first connection pattern extends in the second direction.

19. The display device according to claim 16, wherein, In the plan view, the second region where the upper gate signal line overlaps with the first connection pattern is located within the first region where the lower gate signal line overlaps with the first connection pattern. The width of the lower gate signal line in the second direction is equal both inside and outside the first region, and The width of the upper gate signal line is equal both inside and outside the second region in the second direction.

20. The display device according to claim 11, further comprising: The second connection pattern electrically connects the end of the first active layer and the first end of the second active layer. The first connection pattern and the second connection pattern are disposed on the same layer.

21. A display device, the display device comprising: A first transistor includes: a first active layer disposed on a substrate, the first active layer including a first channel; and a gate electrode disposed on the first active layer, the gate electrode being stacked with the first channel; An insulating layer is disposed on the gate electrode; The second transistor includes: a lower gate electrode disposed on the insulating layer; a second active layer disposed on the lower gate electrode, the second active layer including a second channel stacked with the lower gate electrode, and a first end of the second active layer electrically connected to an end of the first active layer; and an upper gate electrode disposed on the second active layer, the upper gate electrode being stacked with the second channel. A lower gate signal line extends in a first direction, and a portion of the lower gate signal line forms the lower gate electrode; An upper gate signal line is disposed on the lower gate signal line and extends in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and A first connection pattern is disposed on the upper gate signal line, and connects the second end of the second active layer to the gate electrode, wherein... The first connection pattern intersects with the lower gate signal line and the upper gate signal line in the plan view. The lower gate signal line and the upper gate signal line extend and partially overlap each other, and In the intersection region where the first connection pattern intersects with the lower gate signal line or the upper gate signal line, and in the intermediate region adjacent to the intersection region in the first direction, the upper gate signal line is superimposed on the lower gate signal line.

22. The display device according to claim 21, wherein, The width of the lower gate signal line in the intersection region is greater than the width of the lower gate signal line in the non-intersection region where the first connection pattern does not intersect with the lower gate signal line and the upper gate signal line, and the non-intersection region and the intersection region are separated by the intermediate region between the intersection region and the non-intersection region.

23. The display device according to claim 22, wherein, The width of the upper gate signal line in the cross region is equal to the width of the upper gate signal line in the non-cross region.

24. The display device according to claim 22, wherein, The second active layer of the second transistor is located in the non-cross region.

25. The display device according to claim 21, wherein, The width of the upper gate signal line in the intersection region is less than the width of the upper gate signal line in the non-intersection region where the first connection pattern does not intersect with the lower gate signal line and the upper gate signal line, and the non-intersection region and the intersection region are separated by the intermediate region between the intersection region and the non-intersection region.

26. The display device according to claim 25, wherein, The width of the lower gate signal line in the cross region is equal to the width of the lower gate signal line in the non-cross region.

27. The display device according to claim 21, wherein, The first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction that intersects the first direction.

28. The display device according to claim 27, wherein, The difference between the width of the upper gate signal line in the intersection region and the width of the lower gate signal line in the intersection region is greater than 1 μm.

29. The display device according to claim 27, wherein, The first connection pattern extends in the second direction.

30. A display device, the display device comprising: A first transistor includes: a first active layer disposed on a substrate, the first active layer including a first channel; and a gate electrode disposed on the first active layer, the gate electrode being stacked with the first channel; An insulating layer is disposed on the gate electrode; The second transistor includes: a lower gate electrode disposed on the insulating layer; a second active layer disposed on the lower gate electrode, the second active layer including a second channel stacked with the lower gate electrode, and a first end of the second active layer electrically connected to an end of the first active layer; and an upper gate electrode disposed on the second active layer, the upper gate electrode being stacked with the second channel. A lower gate signal line extends in a first direction, and a portion of the lower gate signal line forms the lower gate electrode; An upper gate signal line is disposed on the lower gate signal line and extends in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and A first connection pattern is disposed on the upper gate signal line, and connects the second end of the second active layer to the gate electrode, wherein... The first connection pattern intersects with the lower gate signal line and the upper gate signal line in the plan view. The upper gate signal line and the lower gate signal line extend and partially overlap each other, and In the intersection region where the first connection pattern intersects with the lower gate signal line or the upper gate signal line, and in the intermediate region adjacent to the intersection region in the first direction, the lower gate signal line is superimposed on the upper gate signal line.

31. The display device according to claim 30, wherein, The width of the lower gate signal line in the intersection region is less than the width of the lower gate signal line in the non-intersection region where the first connection pattern does not intersect with the lower gate signal line and the upper gate signal line. The non-intersection region and the intersection region are separated by the intermediate region between the intersection region and the non-intersection region.

32. The display device according to claim 31, wherein, The width of the upper gate signal line in the cross region is equal to the width of the upper gate signal line in the non-cross region.

33. The display device according to claim 31, wherein, The second active layer of the second transistor is located in the non-cross region.

34. The display device according to claim 30, wherein, The width of the upper gate signal line in the intersection region is greater than the width of the upper gate signal line in the non-intersection region where the first connection pattern does not intersect with the lower gate signal line and the upper gate signal line, and the non-intersection region and the intersection region are separated by the intermediate region between the intersection region and the non-intersection region.

35. The display device according to claim 34, wherein, The width of the lower gate signal line in the cross region is equal to the width of the lower gate signal line in the non-cross region.

36. The display device according to claim 30, wherein, The first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction that intersects the first direction.

37. The display device according to claim 36, wherein, The difference between the width of the lower gate signal line in the intersection region and the width of the upper gate signal line in the intersection region is greater than 1 μm.

38. The display device according to claim 36, wherein, The first connection pattern extends in the second direction.

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