Solar cells and photovoltaic modules

Abstract

This application provides a solar cell and a photovoltaic module. The solar cell includes a semiconductor substrate, a passivation contact layer, and multiple first grid lines. The passivation contact layer is disposed on at least one side surface of the semiconductor substrate. The passivation contact layer includes multiple first passivation contact portions, which are spaced apart along a first direction. Multiple first grid lines are arranged along the first direction. The first grid lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate. In this way, at least a portion of the first passivation contact portions on the side away from the semiconductor substrate are provided with multiple first grid lines, thereby achieving both high photoelectric conversion efficiency and production efficiency, and meeting the capacity requirements for mass production.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that directly convert sunlight into electrical energy. Because they are green and environmentally friendly products that do not cause pollution, and because solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In solar cells, controlling the recombination current density and optimizing the light absorption efficiency in the metallized region are key aspects of improving the photoelectric conversion efficiency. To address the high recombination current density in the metallized region of solar cells and avoid the severe parasitic absorption problem caused by the deposition of polycrystalline silicon (Poly or Poly-Si) across the entire surface, polycrystalline silicon (Poly or Poly-Si) is typically fabricated only in the metal contact region, i.e., a poly-finger structure.

[0004] With the continuous iteration of photovoltaic technology, dense grid schemes have been widely researched and applied. By increasing the number of fine grid lines, grid line resistance loss can be effectively reduced, and carrier collection efficiency can be improved, thereby increasing cell efficiency. However, as the number of fine grid lines continues to increase, the poly patterning area of ​​the corresponding metal contact region also increases. Poly patterning usually relies on laser equipment for processing, and the increase in patterning area directly leads to a significant increase in the time consumed by the laser processing process, greatly reducing the production capacity of laser equipment and making it difficult to meet the production capacity requirements of large-scale mass production. Summary of the Invention

[0005] Therefore, it is necessary to provide a solar cell and photovoltaic module that can balance high photoelectric conversion efficiency and production efficiency to meet the capacity requirements of mass production.

[0006] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0007] Semiconductor substrate;

[0008] A passivation contact layer is disposed on at least one surface of the semiconductor substrate; the passivation contact layer includes a plurality of first passivation contact portions, the plurality of first passivation contact portions being arranged at intervals along a first direction;

[0009] Multiple first gate lines are arranged along the first direction; the first gate lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate;

[0010] In particular, at least a portion of the first passivated contacts have multiple first gate lines on the side facing away from the semiconductor substrate.

[0011] The solar cell provided in this application embodiment has multiple first grid lines on the side of each first passivation contact portion away from the semiconductor substrate in at least a portion of the first passivation contact portions. In this way, the number of first passivation contact portions is less than the number of first grid lines without changing the number of first grid lines. That is, when the entire passivation contact layer is patterned, the total area of ​​the passivation contact layer that is removed is reduced. This improves the efficiency of passivation contact layer patterning, ensures the production capacity of laser equipment, improves the production efficiency of solar cells, and meets the production capacity requirements of mass production. At the same time, it avoids the impact of the entire passivation contact layer on the photoelectric conversion efficiency of the solar cell, so that the solar cell maintains a high photoelectric conversion efficiency. In particular, it is compatible with high-number dense grid schemes, so that the solar cell can balance high photoelectric conversion efficiency and production efficiency to meet the production capacity requirements of mass production.

[0012] In one embodiment, the plurality of first passivated contacts include at least one first passivated contact sub-part and at least one second passivated contact sub-part;

[0013] The first passivated contact portion has a first gate line on the side opposite to the semiconductor substrate, where a ≥ 1;

[0014] The second passivated contact portion has b first gate lines on the side opposite to the semiconductor substrate; wherein b > a, and both a and b are positive integers.

[0015] In one embodiment, the first passivated contact portion has a dimension of W1 along the first direction, the second passivated contact portion has a dimension of W2 along the first direction, and the first gate line has a dimension of S along the first direction, wherein W2 > W1, W2:S > 2, and W1:S > 1.

[0016] In one embodiment, 1 < W2: W1 ≤ 10.

[0017] In one embodiment, 1 < b: a ≤ 10.

[0018] In one embodiment, the area of ​​the first passivated contact portion is smaller than the area of ​​the second passivated contact portion in the thickness direction of the semiconductor substrate.

[0019] In one embodiment, the area of ​​all the second passivated contact portions on one side surface of the semiconductor substrate is between 10% and 35%.

[0020] In one embodiment, the plurality of first passivated contacts include a plurality of first passivated contact sub-parts and a plurality of second passivated contact sub-parts; the plurality of first passivated contact sub-parts and the plurality of second passivated contact sub-parts are alternately distributed along the first direction.

[0021] In one embodiment, at least one of the first passivated contact portions is located between two adjacent second passivated contact portions.

[0022] In one embodiment, the plurality of first passivated contact portions include a plurality of first passivated contact sub-portions; all first passivated contact sub-portions are provided with at least one second passivated contact sub-portion on at least one side along the first direction.

[0023] In one embodiment, all the first passivated contact portions are provided with a plurality of second passivated contact portions on at least one side along the first direction;

[0024] Along the direction from the first passivated contact portion to the second passivated contact portion, the size W2 of the plurality of second passivated contact portions gradually increases along the first direction.

[0025] In one embodiment, along the direction from the first passivated contact portion to the second passivated contact portion, the number of the first gate lines corresponding to the plurality of second passivated contact portions gradually increases.

[0026] In one embodiment, all the first passivated contact portions are provided with a plurality of sets of second passivated contact portions on at least one side along the first direction;

[0027] Each group includes multiple second passivated contact portions, and the dimensions W2 of the second passivated contact portions in each group are equal along the first direction;

[0028] In two adjacent groups of second passivated contact portions, the size of the second passivated contact portion along the first direction in the group closer to the first passivated contact portion is smaller than the size of the second passivated contact portion along the first direction in the group farther from the first passivated contact portion.

[0029] In one embodiment, the number of the first gate lines corresponding to the second passivated contact portion in each group is equal;

[0030] In two adjacent groups of second passivated contact portions, the number of first gate lines corresponding to the second passivated contact portions in the group closer to the first passivated contact portion is less than the number of first gate lines corresponding to the second passivated contact portions in the group farther from the first passivated contact portion.

[0031] In one embodiment, the dimension L1 of the first gate line along the second direction is smaller than the dimension L2 of the first passivated contact portion along the second direction; the difference between L2 and L1 is between 0 and 10 mm; the second direction intersects the first direction.

[0032] In one embodiment, the passivation contact layer further includes a second passivation contact portion;

[0033] The second passivated contact portion is located on at least one side of the plurality of first passivated contacts along the second direction, and is connected to all of the plurality of first passivated contacts;

[0034] The first gate line is disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and on the side of the corresponding second passivation contact portion away from the semiconductor substrate.

[0035] In one embodiment, the dimension L1 of the first gate line along the second direction is greater than the dimension L2 of the first passivated contact portion along the second direction; the difference between L1 and L2 is between 20 and 150 mm.

[0036] In one embodiment, the dimension L3 of the second passivated contact portion along the second direction is between 10 and 150 mm;

[0037] And / or, the second passivated contact portion is configured as a strip-shaped structure extending along the first direction.

[0038] In one embodiment, the solar cell further includes a second grid line disposed on the side of the second passivated contact away from the semiconductor substrate; the second grid line is connected to the first grid line.

[0039] In one embodiment, the passivation contact layer further includes a plurality of third passivation contacts.

[0040] The plurality of third passivated contacts are arranged in a row along the first direction and in a column along the second direction; the first direction and the second direction are parallel to the surface of the semiconductor substrate and intersect each other;

[0041] All the third passivated contacts located in the same column are located between two adjacent first passivated contacts; each of the third passivated contacts is connected to the corresponding first passivated contacts at both ends along the first direction.

[0042] In one embodiment, the solar cell further includes a second grid line;

[0043] The second gate line is disposed on the side of the plurality of first passivated contacts facing away from the semiconductor substrate and on the side of the plurality of third passivated contacts located in the same row facing away from the semiconductor substrate.

[0044] In one embodiment, the spacing between any two adjacent first gate lines is equal.

[0045] In one embodiment, the spacing between any two adjacent first passivated contacts is equal.

[0046] In one embodiment, the dimensional difference between any two first passivated contacts along the second direction is n, and the value of n is in the range of -5mm≤n≤5mm;

[0047] And / or, the first passivated contact portion is configured as a strip structure extending along the second direction;

[0048] The second direction intersects with the first direction.

[0049] In one embodiment, the first passivated contact portion includes a first doped portion.

[0050] In one embodiment, the first passivation contact further includes a first dielectric portion and a first substrate doped portion, wherein the first dielectric portion is located on the side of the first doped portion closer to the semiconductor substrate;

[0051] The first substrate doped portion is disposed within the semiconductor substrate and is located on the side of the first dielectric portion away from the first doped portion. The doping type of the first substrate doped portion is the same as that of the first doped portion.

[0052] In one embodiment, the region between adjacent first passivated contacts includes a polished surface or a textured surface;

[0053] And / or, the maximum distance between the region between adjacent first passivation contacts and the side of the passivation contact layer distributed on the same side away from the semiconductor substrate is H1; the maximum distance between the surface of the first substrate doped portion away from the first dielectric portion and the side of the passivation contact layer distributed on the same side away from the semiconductor substrate is H2; H1≥H2.

[0054] In one embodiment, the first passivated contact portion includes at least two first sidewalls disposed opposite each other along a first direction, and the distance between the two first sidewalls along the first direction gradually decreases from the semiconductor substrate toward the first passivated contact portion.

[0055] In one embodiment, the solar cell further includes a first passivation layer that covers the area between the first passivation contact and the adjacent first passivation contact.

[0056] In one embodiment, the solar cell further includes a first antireflection layer that covers the first passivation layer.

[0057] Secondly, embodiments of this application provide a solar cell, comprising:

[0058] Semiconductor substrate;

[0059] A passivation contact layer is disposed on at least one surface of the semiconductor substrate; the passivation contact layer includes a plurality of first passivation contacts and at least one second passivation contact.

[0060] The plurality of first passivated contact portions are arranged at intervals along a first direction; the plurality of first passivated contact portions are provided with a second passivated contact portion on at least one side along a second direction; the plurality of first passivated contact portions are all connected to the same second passivated contact portion;

[0061] The first direction and the second direction are parallel to the surface of the semiconductor substrate and intersect each other.

[0062] The solar cell provided in this application embodiment includes a passivation contact layer comprising a plurality of first passivation contacts and at least one second passivation contact. The plurality of first passivation contacts have a second passivation contact on at least one side along a second direction. All the plurality of first passivation contacts are connected to the same second passivation contact. This effectively shortens the dimension of the first passivation contacts along the second direction, correspondingly shortening the length of the groove along the second direction. This effectively shortens the length of laser grooving, thereby significantly reducing the area, time, and difficulty of patterning the passivation contact layer, ensuring the efficiency of laser grooving, guaranteeing the production capacity of laser equipment, and improving the production efficiency of the solar cell. Simultaneously, since the plurality of first passivation contacts are arranged at intervals along the first direction, meaning the passivation contact layer is located in a localized area on at least one side of the semiconductor substrate, the parasitic absorption of the entire passivation contact layer can be avoided from affecting the photoelectric conversion efficiency of the solar cell, thus maintaining a high photoelectric conversion efficiency.

[0063] In one embodiment, the solar cell includes a plurality of first grid lines arranged along the first direction;

[0064] The dimension of the first gate line along the second direction is larger than the dimension of the first passivated contact portion along the second direction;

[0065] The first gate line is disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and the side of the corresponding second passivation contact portion away from the semiconductor substrate.

[0066] In one embodiment, at least one of the first gate lines is provided on the side of the first passivated contact that is away from the semiconductor substrate;

[0067] And / or, the dimension of each of the first passivated contact portions along the first direction is W, and the dimension of the first gate line along the first direction is S, where W: S > 1;

[0068] And / or, the number of the first gate lines is greater than or equal to the number of the first passivated contacts.

[0069] Thirdly, embodiments of this application provide a solar cell, comprising:

[0070] Semiconductor substrate;

[0071] A passivation contact layer is disposed on at least one surface of the semiconductor substrate; the passivation contact layer includes a plurality of first passivation contact portions arranged along a first direction; the first direction is parallel to the surface of the semiconductor substrate;

[0072] Multiple grooves are defined between each pair of adjacent first passivation contacts; in the thickness direction of the semiconductor substrate, the ratio of the area of ​​the passivation contact layer to the sum of the areas of all the grooves is between 0.2 and 2.4.

[0073] The solar cell provided in this application limits the area ratio of the passivation contact layer to all grooves to 0.2–2.4. This allows for flexible design of the ratio based on the number of fine grid lines and the production capacity of the laser equipment. This enables the passivation contact layer to adapt to dense grid schemes with an increased number of fine grid lines, accommodating a high number of fine grids without expanding the patterned area. This reduces the difficulty and time required for laser grooving, improving both laser patterning efficiency and photoelectric conversion efficiency, thus resolving the contradiction between patterning and performance in related technologies. Furthermore, a reasonable groove area ratio effectively suppresses parasitic absorption caused by full-surface polying, ensuring light utilization. The appropriately sized passivation contact layer area ensures the continuity of carrier collection channels, preventing collection efficiency degradation due to insufficient passivation contact layer. This improves both the photoelectric conversion efficiency and the production efficiency of the solar cell.

[0074] In one embodiment, the passivation contact layer accounts for 20% to 70% of the area of ​​one side surface of the semiconductor substrate.

[0075] In one embodiment, the solar cell further includes a plurality of first grid lines arranged along the first direction; the first grid lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate;

[0076] In particular, at least a portion of the first passivated contacts have multiple first gate lines on the side facing away from the semiconductor substrate.

[0077] In one embodiment, the plurality of first passivated contacts include at least one first passivated contact sub-part and at least one second passivated contact sub-part;

[0078] The first passivated contact portion has a first gate line on the side opposite to the semiconductor substrate, where a ≥ 1;

[0079] The second passivated contact portion has b first gate lines on the side opposite to the semiconductor substrate; b; where b > a, and a and b are both positive integers.

[0080] In one embodiment, in the thickness direction of the semiconductor substrate, the area of ​​the first passivation contact portion is smaller than the area of ​​the second passivation contact portion;

[0081] And / or, the area of ​​all the second passivated contact portions on one side surface of the semiconductor substrate is between 10% and 35%.

[0082] In one embodiment, the passivation contact layer further includes a second passivation contact portion; the second passivation contact portion is located on at least one side of the plurality of first passivation contacts along a second direction and is connected to all of the plurality of first passivation contacts; the second direction intersects the first direction.

[0083] In one embodiment, the solar cell further includes a plurality of first grid lines arranged along the first direction; the first grid lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and the side of the corresponding second passivation contact portion away from the semiconductor substrate.

[0084] In one embodiment, at least one of the first gate lines is provided on the side of the first passivated contact that is away from the semiconductor substrate;

[0085] And / or, the dimension of each of the first passivated contact portions along the first direction is W, and the dimension of the first gate line along the first direction is S, where W: S > 1;

[0086] And / or, the number of the first gate lines is greater than or equal to the number of the first passivated contacts.

[0087] Fourthly, embodiments of this application provide a photovoltaic module, including the solar cell described in any of the above embodiments. This improves the photoelectric conversion efficiency and production efficiency of the photovoltaic module. Attached Figure Description

[0088] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0089] Figure 1 This is a first top view of a solar cell in some embodiments of this application.

[0090] Figure 2 This is a second top view of a solar cell in some embodiments of this application.

[0091] Figure 3 This is a third top view of a solar cell in some embodiments of this application.

[0092] Figure 4 This is a fourth top view of a solar cell in some embodiments of this application.

[0093] Figure 5 This is a first top view of a solar cell in some other embodiments of this application.

[0094] Figure 6 This is a second top view of a solar cell in some other embodiments of this application.

[0095] Figure 7 This is a third top view of a solar cell in some other embodiments of this application.

[0096] Figure 8 This is a fourth top view of the solar cell in some other embodiments of this application.

[0097] Figure 9 This is a first top view of a solar cell in some embodiments of this application.

[0098] Figure 10 This is a second top view of a solar cell in some embodiments of this application.

[0099] Figure 11 This is a third top view of a solar cell in some embodiments of this application.

[0100] Figure 12 This is a first partial cross-sectional view of a solar cell in some embodiments of this application.

[0101] Figure 13 This is a second partial cross-sectional view of a solar cell in some embodiments of this application.

[0102] Figure 14 This is a third partial cross-sectional view of a solar cell in some embodiments of this application.

[0103] Figure 15 This is a first top view of a solar cell in some embodiments of this application.

[0104] Figure 16 This is a second top view of a solar cell in some embodiments of this application.

[0105] Figure 17 This is a partial cross-sectional view of a solar cell in some embodiments of this application.

[0106] Figure 18 This is a third top view of a solar cell in some embodiments of this application.

[0107] Figure 19 This is a fourth top view of the solar cell in some embodiments of this application.

[0108] Figure 20 This is a first top view of a solar cell in some other embodiments of this application.

[0109] Figure 21 This is a second top view of a solar cell in some other embodiments of this application.

[0110] Figure 22 This is a third top view of the solar cell in some other embodiments of this application.

[0111] Figure 23 This is a fourth top view of the solar cell in some other embodiments of this application.

[0112] Figure 24 This is a partial cross-sectional view of a solar cell in some other embodiments of this application.

[0113] Figure 25 This is a first top view of a solar cell in other embodiments of this application.

[0114] Figure 26 This is a second top view of a solar cell in other embodiments of this application.

[0115] Figure 27 for Figure 26 A partial cross-sectional view of the solar cell shown along direction AA.

[0116] Figure 28This is yet another partial cross-sectional view of a solar cell in some embodiments of this application.

[0117] Figure 29 This is another partial cross-sectional view of a solar cell in some embodiments of this application.

[0118] Figure 30 This is another partial cross-sectional view of a solar cell in some embodiments of this application.

[0119] Figure 31 The images shown are scanning electron microscope images of the grooves in solar cells in some embodiments of this application.

[0120] Figure 32 This is a graph showing the relationship between the passivation contact layer area ratio and short-circuit current in some embodiments of this application.

[0121] Figure 33 This is a graph showing the relationship between the passivation contact layer area ratio and the open-circuit voltage in some embodiments of this application.

[0122] Figure 34 This is a graph showing the relationship between the passivation contact layer area ratio and the fill factor in some embodiments of this application.

[0123] Figure 35 This is a graph showing the relationship between the passivation contact layer area ratio and photoelectric conversion efficiency in some embodiments of this application.

[0124] Explanation of icon numbers:

[0125] 10. Solar cell; 11. Semiconductor substrate; 11a. First surface; 11b. Second surface; 12. Passivation contact layer; 12a. First passivation contact portion; 12a1. First passivation contact sub-portion; 12a2. Second passivation contact sub-portion; 12b. Second passivation contact portion; 12c. Third passivation contact portion; 12a11. First sidewall; 121. First dielectric layer; 121a. First dielectric portion; 122. First doped layer; 122a. First doped portion; 123. First substrate doped layer; 123a. First substrate doped portion; 13. Groove; 14. First gate line; 15. Second gate line; 17. First passivation layer; 18. First antireflection layer; 19. Second doped layer; 20. Second passivation layer; 21. Second antireflection layer; X. First direction; Y. Second direction. Detailed Implementation

[0126] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0127] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0128] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0129] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0130] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0131] Embodiments of the application are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shape of the area shown herein, but should include shape deviations due to, for example, manufacturing techniques.

[0132] In solar cells, controlling the recombination current density and optimizing the light absorption efficiency in the metallized region are key aspects of improving the photoelectric conversion efficiency. To address the high recombination current density in the metallized region of solar cells and avoid the severe parasitic absorption problem caused by the deposition of polycrystalline silicon (Poly or Poly-Si) across the entire surface, polycrystalline silicon (Poly or Poly-Si) is typically fabricated only in the metal contact region, i.e., a poly-finger structure.

[0133] With the continuous iteration of photovoltaic technology, dense grid schemes have been widely researched and applied. By increasing the number of fine grid lines, grid line resistance loss can be effectively reduced, and carrier collection efficiency can be improved, thereby increasing cell efficiency. However, as the number of fine grid lines continues to increase, the poly patterning area of ​​the corresponding metal contact region also increases. Poly patterning usually relies on laser equipment for processing, and the increase in patterning area directly leads to a significant increase in the time consumed by the laser processing process, greatly reducing the production capacity of laser equipment and making it difficult to meet the production capacity requirements of large-scale mass production.

[0134] To address the aforementioned technical issues, this application provides a solar cell and a photovoltaic module. Through a balanced design of the poly-finger structure and grid lines, the solar cell can achieve both high photoelectric conversion efficiency and production efficiency, meeting the capacity requirements for mass production.

[0135] The following will combine Figures 1-35 The solar cells and photovoltaic modules provided in the embodiments of this application will be described.

[0136] In a first aspect, embodiments of this application provide a solar cell 10, which may be a tunnel oxide passivated contact (TOPCon) cell.

[0137] See Figure 12 As shown, the solar cell 10 includes a semiconductor substrate 11, which provides support for the subsequently formed film layer. The semiconductor substrate 11 can be used to receive incident light and generate photogenerated carriers. The semiconductor substrate 11 includes a first surface 11a and a second surface 11b disposed opposite to each other along the thickness direction of the semiconductor substrate 11; one of the first surface 11a and the second surface 11b can be used to receive sunlight, that is, one of the first surface 11a and the second surface 11b is the light-receiving surface, and the other is the backlighting surface.

[0138] See Figure 1 As shown, the solar cell 10 includes a passivation contact layer 12, which is disposed on at least one side surface of the semiconductor substrate 11. The passivation contact layer 12 includes a plurality of first passivation contact portions 12a, which are spaced apart along a first direction X. The first direction X is parallel to the surface of the semiconductor substrate 11. That is, by patterning the entire passivation contact layer 12, for example by combining laser etching and wet etching processes, a plurality of first passivation contact portions 12a spaced apart along the first direction X are obtained. This allows grooves 13 to be defined between adjacent first passivation contact portions 12, so that a passivation contact layer 12 is disposed in a local area of ​​at least one side surface of the semiconductor substrate 11, thereby forming a polyfin structure. This reduces the recombination current density in the area where the first gate line 14 is located, improves the parasitic absorption problem of the entire passivation contact layer 12, and helps to improve the photoelectric conversion efficiency of the solar cell 10.

[0139] For example, the passivation contact layer 12 may be disposed on at least one of the first surface 11a and the second surface 11b. See also Figure 12 As shown, in this embodiment of the application, the first surface 11a can be the light-receiving surface, the second surface 11b can be the backlight surface, and the passivation contact layer 12 is disposed on the second surface 11b as an example.

[0140] See Figures 1 to 11As shown, the solar cell 10 includes multiple first grid lines 14, which are arranged along a first direction X. The first grid lines 14 are disposed on the side of the corresponding first passivation contact portion 12a facing away from the semiconductor substrate 11. At least a portion of the first passivation contacts 12a have multiple first grid lines 14 on the side facing away from the semiconductor substrate 11. That is, multiple first grid lines 14 can be correspondingly disposed on all first passivation contacts 12a, or multiple first grid lines 14 can be correspondingly disposed on a portion of the first passivation contacts 12a, and at least one first grid line 14 can be correspondingly disposed on a portion of the first passivation contacts 12a. This allows the number of first passivation contacts 12a to be less than the number of first grid lines 14 while keeping the number of first grid lines 14 constant. This reduces the number of grooves 13 defined by all the first passivation contacts 12a. In other words, when the entire passivation contact layer 12 is patterned, the total area of ​​the removed passivation contact layer 12 is reduced. For example, the area of ​​the first grid... When the number of lines 14 is 336 (corresponding to the dense grid scheme), with the number of first grid lines 14 remaining unchanged at 336, the number of first passivation contact portions 12a can be 228 or even less, and the number of corresponding grooves 13 can be 227 or even less. That is to say, the area of ​​the removed passivation contact layer 12 is greatly reduced. In this way, the efficiency of patterning the passivation contact layer 12 can be greatly improved, ensuring the production capacity of the laser equipment, improving the production efficiency of the solar cell 10, and meeting the production capacity requirements of mass production. At the same time, since the passivation contact layer 12 is disposed in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivation contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency. Especially in the dense grid scheme, the limitation of the photoelectric conversion efficiency gain brought by the entire passivation contact layer 12 to the dense grid scheme can be avoided, which is conducive to the effective improvement of the photoelectric conversion efficiency of the solar cell under the dense grid scheme.

[0141] For example, the first gate line 14 may be a fine gate line, and the first gate line 14 may extend along the second direction Y. The first gate line 14 extends in the same direction as the first passivation contact portion 12a, so that the first gate line 14 can be easily formed on the first passivation contact portion 12a.

[0142] In summary, the solar cell 10 provided in this application includes a semiconductor substrate 11, a passivation contact layer 12, and multiple first gate lines 14. By having the passivation contact layer 12 include multiple first passivation contact portions 12a spaced apart along a first direction X; and by having the first gate lines 14 disposed on the side of the corresponding first passivation contact portion 12a facing away from the semiconductor substrate 11; and by having multiple first gate lines 14 disposed on the side of at least a portion of the first passivation contact portions 12a facing away from the semiconductor substrate 11, the number of first passivation contact portions 12a can be less than the number of first gate lines 14 without changing the number of first gate lines 14, thus ensuring that all first passivation contact portions 12a... The number of defined grooves 13 is reduced, meaning that when the passivation contact layer 12 is patterned over the entire surface, the total area of ​​the passivation contact layer 12 that is removed is reduced. This improves the efficiency of patterning the passivation contact layer 12, ensures the production capacity of the laser equipment, increases the production efficiency of the solar cell 10, and meets the production capacity requirements of mass production. At the same time, it avoids the impact of the passivation contact layer 12 over the entire surface on the photoelectric conversion efficiency of the solar cell 10, allowing the solar cell to maintain a high photoelectric conversion efficiency. In particular, it is compatible with high-number grid schemes, thus enabling the solar cell 10 to balance high photoelectric conversion efficiency and production efficiency, meeting the production capacity requirements of mass production.

[0143] In one embodiment, see Figures 1 to 3 As shown, all first passivation contact portions 12a have multiple first gate lines 14 on the side opposite to the semiconductor substrate 11; and at least a portion of the first passivation contact portions 12a have the same number of corresponding first gate lines 14.

[0144] In this way, a high degree of regularity and consistency in the patterned layout of the passivation contact layer 12 can be achieved. On the one hand, the regular layout can improve the problem of uneven local carrier collection caused by the difference in the number of first gate lines 14 on some of the first passivation contact portions 12a, ensuring that carriers on the surface of the semiconductor substrate 11 can be efficiently transported to the first gate lines 14 in each region, effectively reducing the local recombination current density and further improving the photoelectric conversion efficiency of the solar cell 10. On the other hand, it is beneficial to the patterned processing of the passivation contact layer 12, improving the stability and efficiency of the patterned processing of the passivation contact layer 12, and making it easier to be compatible with high-number dense gate schemes. While ensuring the number of gate lines to enhance the carrier collection capability, production efficiency is further optimized.

[0145] In one embodiment, see Figures 1 to 3 As shown, the first passivated contact portion 12a has a dimension of W along the first direction X, and the first gate line 14 has a dimension of S along the first direction X, where W: S > 2.

[0146] In other words, the dimension of the first passivated contact portion 12a along the first direction X is greater than twice the linewidth of the first gate line 14, so that at least two first gate lines 14 can be provided on the first passivated contact portion 12a. Thus, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is less than the number of first gate lines 14, thereby reducing the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is reduced, which greatly reduces the difficulty of patterning the passivated contact layer 12, thereby improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0147] In one embodiment, see Figures 4 to 7 As shown, the plurality of first passivation contact portions 12a include at least one first passivation contact sub-port 12a1 and at least one second passivation contact sub-port 12a2; the first passivation contact sub-port 12a1 has a first gate line 14 on the side away from the semiconductor substrate 11, where a ≥ 1; the second passivation contact sub-port 12a2 has b first gate lines 14 on the side away from the semiconductor substrate 11; wherein, b > a, and a and b are both positive integers.

[0148] In this way, at least one first gate line 14 can be provided on the side of the first passivated contact portion 12a1 facing away from the semiconductor substrate 11, and at least two first gate lines 14 can be provided on the side of the second passivated contact portion 12a2 facing away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is less than the number of first gate lines 14, thereby reducing the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is reduced, which can greatly reduce the difficulty of patterning the passivated contact layer 12, thereby improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0149] In one embodiment, see Figure 4 , Figures 8 to 10As shown, the first passivated contact portion 12a1 has a dimension of W1 along the first direction X, and the second passivated contact portion 12a2 has a dimension of W2 along the first direction X; the first gate line 14 has a dimension of S along the first direction X, where W2 > W1, W2:S > 2, and W1:S > 1.

[0150] In other words, the dimension of the first passivated contact portion 12a1 along the first direction X is larger than the linewidth of the first gate line 14, and the dimension of the second passivated contact portion 12a2 along the first direction X is larger than twice the linewidth of the first gate line 14. This allows the first passivated contact portion 12a1 to have at least one first gate line 14 on the side facing away from the semiconductor substrate 11, and the second passivated contact portion 12a2 to have at least two first gate lines 14 on the side facing away from the semiconductor substrate 11. Thus, while maintaining the same number of first gate lines 14, the number of first passivated contact portions 12a is less than the number of first gate lines 14, making... The number of grooves 13 defined by all the first passivated contact portions 12a is reduced, that is, the total area of ​​the passivated contact layer 12 that is removed is reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10; at the same time, since the passivated contact layer 12 is disposed in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0151] In one embodiment, see Figure 4 , Figures 8 to 10 As shown, 1 < W2: W1 ≤ 10. Preferably, 1 < W2: W1 ≤ 5. Specifically, W2: W1 can be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, or any value greater than 1 and less than or equal to 5.

[0152] In this way, the first passivated contact portion 12a1 can be provided with at least one first gate line 14 on the side away from the semiconductor substrate 11, and the second passivated contact portion 12a2 can be provided with at least five first gate lines 14 on the side away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is much smaller than the number of first gate lines 14, which further reduces the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is further reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, further improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0153] In one embodiment, see Figure 4 , Figure 8 As shown, 1 < b: a ≤ 10. Preferably, 1 < b: a ≤ 5. Specifically, b: a can be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, or any value greater than 1 and less than or equal to 5.

[0154] In this way, the first passivated contact portion 12a1 can be provided with at least one first gate line 14 on the side away from the semiconductor substrate 11, and the second passivated contact portion 12a2 can be provided with at least five first gate lines 14 on the side away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is much smaller than the number of first gate lines 14, which further reduces the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is further reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, further improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0155] In one embodiment, see Figure 4 As shown, in the thickness direction of the semiconductor substrate 11, the area of ​​the first passivation contact portion 12a1 is smaller than the area of ​​the second passivation contact portion 12a2.

[0156] In one example, when the size of the second passivated contact portion 12a2 along the first direction X is W2, which is greater than the size of the first passivated contact portion 12a1 along the first direction X is W1, the size of the first passivated contact portion 12a1 along the second direction Y and the size of the second passivated contact portion 12a2 along the second direction Y can be equal.

[0157] It should be noted that A=B in this application can be understood as A and B being approximately equal or absolutely equal. The difference between the two is between -5% and 5%, which is considered to be equal.

[0158] In one embodiment, the area of ​​all the second passivated contact portions 12a2 on one side surface of the semiconductor substrate 11 is between 10% and 35%.

[0159] In some examples, the passivation contact layer 12 accounts for 20% to 70% of the area of ​​one side surface of the semiconductor substrate 11.

[0160] In this way, the area of ​​the second passivation contact portion 12a2 in the passivation contact layer can be larger, and multiple first gate lines 14 are provided on the side of the second passivation contact portion 12a2 away from the semiconductor substrate 11. Thus, with the number of first gate lines 14 remaining unchanged, the number of first passivation contact portions 12a in the passivation contact layer can be significantly smaller than the number of first gate lines 14. This further reduces the number of grooves 13 defined by all the first passivation contact portions 12a, that is, further reduces the total area of ​​the removed passivation contact layer 12. This greatly reduces the difficulty of patterning the passivation contact layer 12, further improves the patterning efficiency of the passivation contact layer 12, ensures the production capacity of the laser equipment, and improves the production efficiency of the solar cell 10. At the same time, since the passivation contact layer 12 is provided in a local area on at least one side of the semiconductor substrate 11, the influence of the entire passivation contact layer 12 on the photoelectric conversion efficiency of the solar cell 10 can be avoided, so that the solar cell maintains a high photoelectric conversion efficiency.

[0161] In one embodiment, see Figures 4 to 7 As shown, the plurality of first passivated contact portions 12a include a plurality of first passivated contact sub-portions 12a1 and a plurality of second passivated contact sub-portions 12a2; the plurality of first passivated contact sub-portions 12a1 and the plurality of second passivated contact sub-portions 12a2 are alternately distributed along the first direction X.

[0162] Since the number of first gate lines 14 corresponding to the second passivated contact portion 12a2 is greater than the number of first gate lines 14 corresponding to the first passivated contact portion 12a1, the second passivated contact portion 12a2 corresponds to a high gate line density region, and the first passivated contact portion 12a1 can be a basic gate line density region. By distributing multiple first passivated contact portions 12a1 and multiple second passivated contact portions 12a2 alternately along the first direction X, on the one hand, the high gate line density region and the basic gate line density region can form a uniformly spaced current collection network on the surface of the semiconductor substrate 11. That is, the multi-gate line design of the second passivated contact portion 12a2 enhances the fast extraction capability of charge carriers and reduces the recombination loss of charge carriers during the transmission process. Especially for regions in the semiconductor substrate 11 with high charge carrier concentration or long transmission path, the multi-gate line layout can shorten the migration distance of charge carriers to the gate line and reduce the probability of bulk recombination and surface recombination. On the other hand, it can balance the stress distribution on the surface of the semiconductor substrate 11, improve the bonding stability between the passivation contact layer 12 and the semiconductor substrate 11 and the gate line, reduce defects such as cracks and peeling caused by uneven stress during the battery manufacturing process (such as high-temperature annealing, coating and other processes), and ensure the long-term reliability and photoelectric conversion efficiency stability of the battery.

[0163] In one embodiment, see Figures 5 to 7 As shown, at least one first passivated contact portion 12a1 is located between two adjacent second passivated contact portions 12a2.

[0164] When patterning the passivation contact layer 12, a mask layer is usually first formed on the side of the passivation contact layer 12 away from the semiconductor substrate 11. Then, a groove is made on the mask layer using a laser, and then wet etching is used to form a plurality of first passivation contact portions 12a arranged at intervals along the first direction X. However, when the laser makes grooves in the edge region of the semiconductor substrate 11, the optical system of the laser equipment is prone to aberrations such as field curvature, astigmatism, and coma, which makes the laser spot of the laser equipment prone to distortion, such as the laser spot size becoming larger, the shape being distorted, and the energy being dispersed. In addition, the mask quality in the edge region of the semiconductor substrate 11 is relatively poor, which means that the closer to the edge region of the semiconductor substrate 11, the worse the laser processing quality becomes. This makes it easy for the edge region of the semiconductor substrate 11 to have incomplete film opening, resulting in film residue after subsequent wet etching and causing a decrease in yield. Based on this, in this embodiment, by placing at least one first passivated contact portion 12a1 between two adjacent second passivated contact portions 12a2, and the dimension W2 of the second passivated contact portion 12a2 along the first direction X is greater than the dimension W1 of the first passivated contact portion 12a1 along the first direction X, the number of grooves 13 in the edge region of the semiconductor substrate 11 along both sides of the first direction X can be reduced. In other words, the laser processing area in the edge region of the semiconductor substrate 11 along both sides of the first direction X can be reduced, thereby improving the problem of incomplete laser film opening in the edge region of the semiconductor substrate 11 along both sides of the first direction X and improving the yield of the solar cell 10.

[0165] In one embodiment, see Figures 8 to 11 As shown, the plurality of first passivated contact portions 12a include a plurality of first passivated contact sub-portions 12a1; all first passivated contact sub-portions 12a1 are provided with at least one second passivated contact sub-portion 12a2 on at least one side along the first direction X.

[0166] In this way, the number of grooves 13 in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be reduced, that is, the laser processing area in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be reduced, thereby improving the problem of incomplete laser film opening in the edge region of at least one side of the semiconductor substrate 11 along the first direction X and improving the yield of the solar cell 10.

[0167] In one embodiment, see Figure 15 , Figure 16 As shown, all first passivated contact portions 12a1 are provided with a plurality of second passivated contact portions 12a2 on at least one side along the first direction X; along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the size W2 of the plurality of second passivated contact portions 12a2 gradually increases along the first direction X.

[0168] In this way, the number of grooves 13 in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be further reduced, that is, the laser processing area in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be further reduced, thereby further improving the problem of incomplete laser film opening in the edge region of at least one side of the semiconductor substrate 11 along the first direction X; moreover, when performing electroluminescence testing on the solar cell 10, the probability of defects such as uneven brightness in the solar cell 10 can be greatly reduced, thereby improving the yield of the solar cell 10.

[0169] In one embodiment, see Figures 15 to 19 As shown, along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the number of corresponding first gate lines 14 on the plurality of second passivated contact portions 12a2 gradually increases.

[0170] Thus, by gradually increasing the number of first gate lines 14 on multiple second passivated contact portions 12a2 along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the gradient increase in the number of first gate lines 14 can be adapted to the gradient design of the size W2 of the second passivated contact portion 12a2 along the first direction X (i.e., the size W2 of multiple second passivated contact portions 12a2 gradually increases along the first direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2). This reduces the laser processing area and improves the problem of unclean edge film opening, while ensuring the synchronous improvement of the carrier collection capacity of the passivated contact area, and improving the recombination loss caused by the extension of the carrier transport path due to the increase in size. In addition, the gradient in the number of gate lines makes the carrier collection efficiency on the surface of the semiconductor substrate 11 uniformly distributed, effectively alleviating the undesirable phenomenon of uneven brightness in electroluminescence testing. This not only ensures the high photoelectric conversion efficiency brought by the dense gate design, but also further improves the yield and performance stability of the solar cell 10.

[0171] In one embodiment, see Figures 20 to 24 As shown, all first passivated contact portions 12a1 have multiple sets of second passivated contact portions 12a2 on at least one side along the first direction X; each set includes multiple second passivated contact portions 12a2, and the dimensions W2 of the second passivated contact portions 12a2 in each set along the first direction X are all equal; in two adjacent sets of second passivated contact portions 12a2, the dimension of the second passivated contact portion 12a2 in the set closer to the first passivated contact portion 12a1 along the first direction X is smaller than the dimension of the second passivated contact portion 12a2 in the set farther away from the first passivated contact portion 12a1 along the first direction X.

[0172] Thus, by using a smaller W2 for the second passivation contact portion 12a2 within the group closer to the first passivation contact portion 12a1, and a larger W2 for the second passivation contact portion 12a2 in the group farther away, the number and area of ​​edge slots are further reduced by using larger-sized second passivation contact portions 12a2 in the edge region, thereby reducing the laser processing area and effectively improving the problem of unclean edge film opening, while also achieving a smooth transition in carrier collection capability. In addition, the grouping gradient design simplifies the control difficulty of mask fabrication and patterning processes, ensuring the production efficiency of the solar cell 10 while being compatible with dense grid designs, thereby improving the production yield and photoelectric conversion efficiency of the solar cell 10.

[0173] In one embodiment, see Figures 20 to 24 As shown, the number of first gate lines 14 on the second passivated contact portion 12a2 in each group is equal; in two adjacent groups of second passivated contact portions 12a2, the number of first gate lines 14 on the second passivated contact portion 12a2 in the group closer to the first passivated contact portion 12a1 is less than the number of first gate lines 14 on the second passivated contact portion 12a2 in the group farther away from the first passivated contact portion 12a1.

[0174] Thus, by maintaining a consistent number of first gate lines 14 in the second passivated contact portion 12a2 within each group, the uniformity of the carrier collection path within the group is ensured, avoiding uneven current distribution and carrier recombination losses caused by local gate line density differences, and guaranteeing the stability of the photoelectric conversion efficiency per unit area. Simultaneously, the number of gate lines between adjacent groups increases in a gradient away from the first passivated contact portion 12a1, precisely synergizing with the inter-group increase in the size of the second passivated contact portion 12a2. This allows the larger passivated contact area to enhance carrier extraction capability through more gate lines, avoiding the problem of extended carrier transport paths due to size expansion. Furthermore, it effectively reduces the number of grooves 13 in the edge region of the semiconductor substrate 11 along the first direction X, further improving the problem of incomplete laser delamination and increasing the yield of the solar cell 10.

[0175] In one embodiment, see Figures 19 to 21 , Figure 23 As shown, the dimension L1 of the first gate line 14 along the second direction Y is smaller than the dimension L2 of the first passivated contact portion 12a along the second direction Y; the difference between L2 and L1 is between 0 and 10 mm; for example, the difference between L2 and L1 can be 0.1 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, or between any two of the above values. The second direction Y is parallel to the surface of the semiconductor substrate 11 and intersects with the first direction X.

[0176] Thus, by limiting the dimension L2 of the first passivated contact portion 12a along the second direction Y to be slightly larger than the corresponding dimension L1 of the first gate line 14, and controlling the difference between the two within a reasonable range of 0 to 10 mm, sufficient tolerance space is reserved for process steps such as photolithography alignment and gate line fabrication. This effectively avoids misalignment between the gate line and the passivated contact portion due to process deviations, ensuring that the two always maintain reliable and effective contact, reducing the risk of performance degradation caused by poor contact, and improving production consistency and yield. At the same time, it avoids the additional increase in the patterning area and difficulty of the passivated contact layer 12 due to the moderate increase of L2, thereby simplifying the process and improving production efficiency. In addition, the reasonable size difference can ensure the effective contact area for carrier transport, avoid the increase in contact resistance, and further ensure the photoelectric conversion efficiency and performance stability of the solar cell 10 while being compatible with the dense gate design and optimizing the processing effect of the edge region.

[0177] In one embodiment, see Figure 22 As shown, the passivation contact layer 12 further includes a second passivation contact portion 12b; the second passivation contact portion 12b is located on at least one side of the plurality of first passivation contacts 12a along the second direction Y, and the second passivation contact portion 12b is connected to the plurality of first passivation contacts 12a; the first gate line 14 is disposed on the side of the first passivation contact portion 12a away from the semiconductor substrate 11 and the side of the second passivation contact portion 12b away from the semiconductor substrate 11.

[0178] This effectively shortens the dimension of the first passivated contact portion 12a along the second direction Y, and correspondingly shortens the length of the groove 13 along the second direction Y. This effectively shortens the length of laser grooving, thereby greatly reducing the area of ​​the passivated contact layer 12 to be removed, reducing the difficulty and time required for patterning the passivated contact layer 12, ensuring the efficiency of laser grooving, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since multiple first passivated contact portions 12a are arranged at intervals along the first direction, that is, the passivated contact layer 12 is provided in a local area on at least one side of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0179] In one embodiment, see Figure 22 As shown, the dimension L1 of the first gate line 14 along the second direction Y is greater than the dimension L2 of the first passivated contact portion 12a along the second direction Y; the difference between L1 and L2 is between 20 and 150 mm; both the first direction X and the second direction Y are parallel to the surface of the semiconductor substrate 11 and intersect each other. Specifically, the difference between L1 and L2 can be 20 mm, 40 mm, 50 mm, 70 mm, 90 mm, 110 mm, 130 mm, 150 mm, or any value between 20 mm and 150 mm.

[0180] Thus, by limiting the dimension L1 of the first gate line 14 along the second direction Y to be greater than the dimension L2 of the first passivation contact portion 12a, and controlling the difference to be within 20-150 mm, the length of the groove 13 and the workload of laser grooving are further reduced by L2, thereby improving the patterning efficiency of the passivation contact layer 12. Simultaneously, the first gate line 14 extends to the second passivation contact portion 12b, ensuring the effective contact area between the first gate line 14 and the passivation contact layer 12, and avoiding carrier transport losses. Furthermore, a reasonable difference range can accommodate dense gate design and process requirements, ensuring photoelectric conversion efficiency while further optimizing production efficiency, achieving a synergistic improvement in performance and process.

[0181] In one embodiment, see Figure 22 As shown, the dimension L3 of the second passivated contact portion 12b along the second direction Y is between 10 and 150 mm; both the first direction X and the second direction Y are parallel to the surface of the semiconductor substrate 11 and intersect each other. Specifically, the dimension L3 of the second passivated contact portion 12b along the second direction Y can be 10 mm, 30 mm, 50 mm, 70 mm, 100 mm, 120 mm, 150 mm, or any value between 10 mm and 150 mm.

[0182] Thus, by limiting the dimension L3 of the second passivated contact portion 12b along the second direction Y to 10-150 mm, both the effective contact area with the first grid line 14 is ensured, guaranteeing smooth and lossless carrier transport, and the patterning difficulty of the passivated contact layer 12 is avoided due to excessive size. Furthermore, this reasonable range synergizes with the size design of the first grid line 14 and the first passivated contact portion 12a, continuing to shorten the laser grooving length and improve patterning efficiency, while also maintaining stable compatibility with dense grid schemes. This further optimizes production consistency and efficiency while ensuring the photoelectric conversion efficiency of the solar cell 10.

[0183] In one embodiment, see Figure 22 As shown, the second passivated contact portion 12b is constructed as a strip-shaped structure extending along the first direction X.

[0184] In one embodiment, see Figure 22 As shown, the solar cell 10 also includes a second grid line 15, which is disposed on the side of the second passivated contact portion 12b away from the semiconductor substrate 11; the second grid line 15 is connected to the first grid line 14.

[0185] Thus, by setting a second grid line 15 connected to the first grid line 14 on the second passivated contact portion 12b, a crisscrossing current collection and discharge network is constructed. This not only allows the second grid line 15 to quickly conduct the charge carriers collected by the first grid line 14, shortening the current transmission path, reducing series resistance and energy loss, and improving the fill factor, but also fully utilizes the charge carrier transport characteristics of the second passivated contact portion 12b to increase the current collection channels and further accommodate dense grid designs. In addition, it does not increase the patterning difficulty of the passivation contact layer 12, and significantly improves the photoelectric conversion efficiency and performance stability of the solar cell 10 while ensuring production efficiency.

[0186] It should be noted that the second gate line 15 can be the main gate line, and the second gate line 15 can extend along the first direction X.

[0187] In one embodiment, see Figure 23 As shown, the passivation contact layer 12 also includes a plurality of third passivation contact portions 12c, which are arranged in a row along the first direction X and in a column along the second direction Y. The first direction X and the second direction Y are parallel to the surface of the semiconductor substrate 11 and intersect each other. All third passivation contact portions 12c located in the same column are located between two adjacent first passivation contact portions 12a. Each third passivation contact portion 12c is connected to the corresponding first passivation contact portion 12a at both ends along the first direction X.

[0188] Thus, multiple first passivation contacts 12a can be connected to form a mesh structure through multiple third passivation contacts 12c. A groove 13, which is the mesh of the mesh structure, is defined between two adjacent first passivation contacts 12a and two third passivation contacts 12c. This increases the area of ​​the passivation contact layer 12 in the thickness direction of the semiconductor substrate 11 and reduces the area of ​​all grooves 13 in the plane perpendicular to the thickness direction of the semiconductor substrate 11, i.e., the area of ​​the removed passivation contact layer 12, thereby improving the efficiency of the passivation contact layer 12 patterning. At the same time, it can ensure the number of first grid lines 14 of the solar cell 10, thereby improving the photoelectric conversion efficiency of the solar cell 10 and the production efficiency of the solar cell 10. On the other hand, it expands the carrier collection coverage area, effectively collects carriers in the region between adjacent first passivation contacts 12a, shortens the carrier transport path, and reduces recombination losses. In addition, the connection structure between the third passivation contact 12c and the first passivation contact 12a enhances the overall structural stability of the passivation contact layer 12 and provides more uniform contact support for the grid lines, further compatibility with dense grid design, and significantly improves the photoelectric conversion efficiency and performance reliability of the solar cell 10 while ensuring production efficiency.

[0189] In one embodiment, see Figure 23As shown, the solar cell 10 also includes a second grid line 15; the second grid line 15 is disposed on the side of a plurality of first passivation contacts 12a away from the semiconductor substrate 11 and on the side of a plurality of third passivation contacts 12c located in the same row away from the semiconductor substrate 11.

[0190] It should be noted that the second gate line 15 can be the main gate line, and the second gate line 15 can extend along the first direction X.

[0191] In one embodiment, see Figure 23 As shown, the spacing between any two adjacent first grid lines 14 is equal.

[0192] Thus, by ensuring that the spacing between any two adjacent first gate lines 14 is equal, a uniformly distributed carrier collection channel can be formed on the surface of the semiconductor substrate 11, ensuring that the carrier transport path length is consistent in each region. This avoids problems such as increased local carrier recombination loss or excessive parasitic absorption caused by uneven spacing, significantly improving the stability of photoelectric conversion efficiency. Furthermore, the spacing between adjacent first gate lines 14 does not change with the dimension of the first passivation contact portion 12a along the first direction X. Therefore, the fabrication process of the first gate lines 14 is not affected by the pattern of the passivation contact layer 12, allowing for the fabrication of the first gate lines 14 using existing processes or screen printing, thereby reducing the fabrication cost of the solar cell 10 and improving its production efficiency. In addition, the equal spacing design simplifies the process control of photolithography mask fabrication and gate line processing, which is beneficial for ensuring process accuracy and production consistency under a dense-gate scheme, reducing processing defects caused by spacing deviations, and enhancing the performance reliability and mass production adaptability of the solar cell 10.

[0193] In one embodiment, see Figure 23 As shown, the spacing between any two adjacent first passivated contact portions 12a is equal.

[0194] Thus, by ensuring that the spacing between any two adjacent first passivation contact portions 12a is equal, the passivation contact layer 12 can form a uniformly distributed structure on the surface of the semiconductor substrate 11. This ensures a consistent carrier collection environment in each region, avoids excessive differences in local carrier transport paths and increased recombination losses due to uneven spacing, and guarantees the stability and uniformity of photoelectric conversion efficiency. Furthermore, the equal spacing design simplifies the process control of photolithography mask fabrication and laser grooving, facilitates precise control of processing parameters, reduces processing defects caused by spacing deviations, and improves production consistency and yield.

[0195] In one embodiment, see Figure 23 As shown, the size difference between any two first passivated contact portions 12a along the second direction Y is n, and the value of n ranges from -5mm to n to 5mm; the second direction Y is parallel to the surface of the semiconductor substrate 11 and intersects with the first direction X.

[0196] This ensures that the structural dimensions of each first passivation contact 12a are highly consistent in the second direction Y, thereby guaranteeing the uniformity of the carrier collection environment on the surface of the semiconductor substrate 11. Specifically, the carrier transport path length and effective contact area with the gate line corresponding to each passivation contact tend to be consistent, avoiding imbalances in carrier collection efficiency in local areas due to size differences, reducing recombination losses, and ensuring the stability of the photoelectric conversion efficiency of the solar cell 10. Furthermore, the small size difference accommodates reasonable process errors, reducing the difficulty of precision control in mask preparation and patterning, avoiding alignment errors or processing defects caused by excessive size deviations, while not affecting the simplified advantages of the overall patterning of the passivation contact layer 12. This synergizes with designs such as dense gate adaptation and edge region yield optimization, further consolidating the synergistic improvement in photoelectric conversion efficiency and production efficiency while enhancing production consistency and yield.

[0197] In one embodiment, see Figure 23 As shown, the first passivated contact portion 12a is configured as a strip structure extending along the second direction Y; the second direction Y is parallel to the surface of the semiconductor substrate 11 and intersects with the first direction X.

[0198] Thus, by constructing the first passivation contact 12a as a strip extending along the second direction Y, the first passivation contact 12a can be adapted to the first gate line 14, maximizing the contact area between the two, shortening the carrier transport path, and reducing recombination losses. In addition, the strip-shaped patterning process is simple, which can further reduce the processing difficulty and cost of the passivation contact layer 12, and the structure has strong uniformity, ensuring the consistency of carrier collection on the substrate surface. While being compatible with dense gate design and optimizing edge processing yield, it simultaneously improves the photoelectric conversion efficiency and production efficiency of the solar cell 10.

[0199] In one embodiment, see Figures 12 to 14 , Figure 17 , Figure 24 As shown, the first passivated contact portion 12a includes a first doped portion 122a.

[0200] In other words, the passivation contact layer 12 includes a first doped layer 122. By patterning the entire first doped layer 122, a plurality of first doped portions 122a are obtained, which are spaced apart along the first direction X, so that the first passivation contact portion 12a includes the first doped portion 122a. In other words, the groove 13 penetrates the first doped layer 122 along the thickness direction of the semiconductor substrate 11.

[0201] In this way, parasitic absorption caused by the first doped layer 122 on the entire surface can be avoided, so that the solar cell 10 can maintain a high photoelectric conversion efficiency.

[0202] In some examples, the passivation contact layer 12 further includes a first dielectric layer 121, which is disposed between the first doped portion 122a and the semiconductor substrate 11, and covers the surface of the semiconductor substrate 11. The first dielectric layer 121 and the first doped portion 122a form a highly efficient passivation-conductivity synergistic structure. The first dielectric layer 121 can effectively suppress recombination on the surface of the semiconductor substrate 11, and the first doped portion 122a can achieve selective carrier transport. The two work together to ensure carrier collection efficiency. The first doped portions 122a are arranged at intervals, which avoids parasitic absorption caused by the entire surface of the first doped layer 122a, and eliminates the need for full-through processing of the first dielectric layer 121, which is the core of the passivation function, thus reducing the difficulty of patterning and the risk of damage.

[0203] It should be noted that the first dielectric layer 121 can be a tunneling layer, through which majority carriers (e.g., electrons) can pass through the tunneling layer via the tunneling effect. The tunneling layer can also block minority carriers (e.g., holes), thereby enabling selective collection of carriers, preventing electron-hole recombination, reducing the surface recombination rate, and increasing the open-circuit voltage. The first doped portion 122a has low resistance, which can effectively reduce current loss and increase conductivity.

[0204] For example, the tunneling layer material may include tunneling oxide.

[0205] For example, the material of the tunneling layer may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0206] For example, the material of the first doped portion 122a may include doped polycrystalline silicon, doped amorphous silicon, or doped microcrystalline silicon. This embodiment of the application uses doped polycrystalline silicon as an example for illustration.

[0207] In one embodiment, see Figures 12 to 14 , Figure 17 , Figure 24 As shown, the passivation contact layer 12 also includes a first substrate doped layer 123. The first substrate doped layer 123 is disposed in the semiconductor substrate 11 and is located on the side of the first dielectric layer 121 away from the first doped portion 122a. The first substrate doped layer 123 and the first doped portion 122a have the same doping type.

[0208] In this way, the carrier concentration on the surface of the semiconductor substrate 11 can be enhanced, the carrier transport channel can be optimized, the recombination loss of carriers inside the substrate can be reduced, and the carrier collection efficiency can be improved. At the same time, it can form a potential gradient synergy with the first doped part 122a, reduce the carrier transport resistance, and buffer the interface stress between the semiconductor substrate 11 and the first dielectric layer 121, reduce the interface defect state density, and enhance the passivation effect of the first dielectric layer 121. This balances electrical performance and structural stability, which is beneficial to improving the photoelectric conversion efficiency of the solar cell 10.

[0209] It should be noted that the first substrate doped layer 123 can be formed simultaneously with the first doped layer 122. That is, when the first doped layer 122 is formed, the dopant element undergoes internal diffusion, thereby forming the first substrate doped layer 123 disposed within the semiconductor substrate 11 and having the same doping type as the first doped layer 122. In addition, the doping concentration of the first substrate doped layer 123 is lower than that of the first doped layer 122.

[0210] In one embodiment, see Figure 14 , Figure 17 , Figure 24 As shown, the first passivated contact portion 12a includes a first dielectric portion 121a and a first substrate doped portion 123a. The first dielectric portion 121a is located on the side of the first doped portion 122a close to the semiconductor substrate 11. The first substrate doped portion 123a is disposed in the semiconductor substrate 11 and is located on the side of the first dielectric portion 121a away from the first doped portion 122a. The doping type of the first substrate doped portion 123a is the same as that of the first doped portion 122a.

[0211] In other words, by patterning the first dielectric layer 121 and the first substrate doped layer 123, the first dielectric portion 121a and the first substrate doped portion 123a are obtained. In other words, the groove 13 penetrates the first dielectric layer 121 and the first substrate doped layer 16 along the thickness direction of the semiconductor substrate 11. This completely eliminates the film structure in the non-metallic contact region, maximizing the reduction of parasitic absorption losses in that region and improving photon utilization. Furthermore, the fully penetrating structure avoids interfacial recombination caused by residual film layers, optimizes the carrier transport environment, and reduces recombination losses, thereby improving the photoelectric conversion efficiency of the solar cell 10.

[0212] In one embodiment, see Figure 28 As shown, the area between adjacent first passivated contact portions 12a includes a polished surface. That is, the bottom wall of the groove 13 is a polished surface.

[0213] This effectively reduces the surface roughness and surface state density of the region between adjacent first passivation contacts 12a, reduces interfacial recombination losses of charge carriers in the region between adjacent first passivation contacts 12a, optimizes the charge carrier transport environment, and ensures photoelectric conversion efficiency. At the same time, the polished surface can avoid residual etching impurities on the rough surface, improve the cleanliness and precision of patterning, reduce process defects, and ensure the structural consistency of the passivation contact layer 12.

[0214] In another embodiment, see Figure 29 As shown, the area between adjacent first passivated contact portions 12a includes a textured surface. That is, the bottom wall of the groove 13 has a textured surface.

[0215] This effectively increases the light absorption area between adjacent first passivated contact portions 12a, reduces incident light reflection loss, and improves photon utilization and carrier generation, laying the foundation for improved photoelectric conversion efficiency. Simultaneously, the textured structure can be achieved through existing etching processes without increasing process complexity. This does not affect the patterning efficiency and grid compatibility of the passivation contact layer 12, and further enhances the light absorption performance and photoelectric conversion efficiency of the solar cell 10 while maintaining production efficiency advantages.

[0216] In one embodiment, see Figure 30 and Figure 31 As shown, the first passivation contact portion 12a includes at least two first sidewalls 12a11 disposed opposite to each other along the first direction X. The distance between the two sidewalls 12a1 gradually decreases along the first direction X in the direction from the semiconductor substrate 11 to the first passivation contact portion 12a. That is, in the second direction Y, the first passivation contact portion 12a has a trapezoidal structure.

[0217] In other words, from the direction of the semiconductor substrate 11 toward the first passivated contact portion 12a, the distance between the two groove sidewalls of the groove 13 that are disposed opposite each other along the first direction X gradually increases.

[0218] Thus, on the one hand, during laser grooving and wet etching processes, the risk of film residue on the sidewall 12a1 of the first passivation contact 12a can be reduced, improving the patterning accuracy and yield. On the other hand, it can avoid interface recombination concentration caused by sharp sidewalls 12a1, optimize the carrier transport environment, and reduce recombination losses. In addition, it is beneficial to the continuity and thickness uniformity of subsequent film deposition between two adjacent first passivation contacts 12a. For example, it can improve the continuity and thickness uniformity of the first passivation layer 17 and the first antireflection layer 18 between two adjacent first passivation contacts 12a, thereby improving the passivation effect and increasing the photoelectric conversion efficiency of the solar cell 10.

[0219] It should be noted that the first passivation contact 12a may also include two second sidewalls (not shown) disposed opposite each other along the second direction Y. The distance between the two second sidewalls gradually decreases along the first direction X in the direction from the semiconductor substrate 11 towards the first passivation contact 12a. Both second sidewalls are connected to the two first sidewalls 12a11. In the thickness direction of the semiconductor substrate 11, the first passivation contact 12a may be quadrilateral, such as rectangular. Of course, in the thickness direction of the semiconductor substrate 11, the first passivation contact 12a may also be of other shapes, and the first passivation contact 12a is not limited to a quadrilateral; it can be designed according to actual needs.

[0220] In one embodiment, see Figure 14 , Figure 28 As shown, the maximum distance between the region between adjacent first passivation contact portions 12a and the side of the passivation contact layer 12 distributed on the same side away from the semiconductor substrate 11 is H1; the maximum distance between the surface of the first substrate doped portion 123a away from the first dielectric portion 121a and the side of the passivation contact layer 12 distributed on the same side away from the semiconductor substrate is H2; H1≥H2.

[0221] In other words, the maximum distance between the bottom wall of the groove 13 and the passivation contact layer 12 distributed on the same side away from the semiconductor substrate 11 is H1; the maximum distance between the side of the first substrate doped portion 123a near the bottom wall of the groove 13 and the side of the passivation contact layer 12 distributed on the same side away from the semiconductor substrate 11 is H2; H1≥H2.

[0222] This ensures that no first substrate doped portion 123a remains in the area between adjacent first passivation contacts 12a, avoiding interfacial recombination and carrier transport obstruction caused by residual film layers, and optimizing carrier selective transport efficiency. Simultaneously, this dimensional relationship ensures precise control of the etching process, reducing process defects caused by over-etching or under-etching, and improving the yield of patterning processes.

[0223] In one embodiment, see Figures 27 to 30 As shown, the solar cell 10 also includes a first passivation layer 17, which covers the area between the first passivation contact 12a and adjacent first passivation contacts 12a. This improves the passivation effect of the solar cell 10, reduces recombination, and benefits the photoelectric conversion efficiency of the solar cell 10.

[0224] It should be noted that the first passivation layer 17 can be a single-layer structure or a multilayer structure. The material of the first passivation layer 17 can include oxides, nitrides, etc. Oxides can include at least one of aluminum oxide, titanium oxide, tin oxide, zirconium oxide, and hafnium oxide, and nitrides can include at least one of silicon nitride and silicon oxynitride.

[0225] In one embodiment, see Figures 27 to 30 As shown, the solar cell 10 also includes a first antireflection layer 18, which covers the first passivation layer 17. This improves the light utilization rate of the solar cell 10, thus enhancing its photoelectric conversion efficiency. Furthermore, the first antireflection layer 18 forms a physical protective barrier, preventing the first passivation layer 17 from being contaminated or damaged in subsequent processes, ensuring the stability of its surface defect saturation and carrier recombination suppression functions, and strengthening the long-term reliability of the solar cell 10.

[0226] For example, see Figures 28 to 30 As shown, the passivation contact layer 12 is disposed on the second surface 11b of the semiconductor substrate 11. The solar cell also includes a second doped layer 19, a second passivation layer 20, and a second antireflection layer 21. The second doped layer 19 is disposed in the first surface 11a of the semiconductor substrate 11, the second passivation layer 20 is disposed on the side of the second doped layer 19 facing away from the semiconductor substrate 11, and the second antireflection layer 21 is disposed on the side of the second passivation layer 20 facing away from the semiconductor substrate 11. The second doped layer 19 can be configured as an emitter, for example, a boron emitter or other emitters. The first surface 11a can have a textured structure.

[0227] Secondly, see Figure 25 and Figure 26 As shown, this application embodiment provides a solar cell 10, including a semiconductor substrate 11 and a passivation contact layer 12; the passivation contact layer 12 is disposed on at least one side surface of the semiconductor substrate 11; the passivation contact layer 12 includes a plurality of first passivation contact portions 12a and at least one second passivation contact portion 12b; the plurality of first passivation contact portions 12a are arranged at intervals along a first direction X; the plurality of first passivation contact portions 12a are provided with a second passivation contact portion 12b on at least one side along a second direction Y; the plurality of first passivation contact portions 12a are all connected to the same second passivation contact portion 12b; the first direction X and the second direction Y are both parallel to the surface of the semiconductor substrate 11 and intersect each other.

[0228] In some examples, a groove 13 is defined between adjacent first passivated contacts 12a;

[0229] The solar cell 10 provided in this embodiment includes a passivation contact layer 12 comprising a plurality of first passivation contact portions 12a and at least one second passivation contact portion 12b. The plurality of first passivation contact portions 12a are arranged along a first direction X, and the plurality of first passivation contact portions 12a are provided with a second passivation contact portion 12b on at least one side along a second direction Y. All the plurality of first passivation contact portions 12a are connected to the same second passivation contact portion 12b. This effectively shortens the dimension of the first passivation contact portion 12a along the second direction Y, and correspondingly shortens the length of the groove 13 along the second direction Y. This effectively... Shortening the length of laser grooving can greatly reduce the area, time, and difficulty of patterning the passivation contact layer 12, ensuring the efficiency of laser grooving, ensuring the production capacity of laser equipment, and improving the production efficiency of solar cell 10. At the same time, since multiple first passivation contact portions 12a are arranged at intervals along the first direction X, that is, the passivation contact layer 12 is disposed in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivation contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of solar cell 10, so that solar cell 10 maintains a high photoelectric conversion efficiency.

[0230] In one embodiment, the passivation contact layer 12 accounts for 20% to 70% of the area of ​​one side surface of the semiconductor substrate 11.

[0231] Accordingly, in the thickness direction of the semiconductor substrate 11, the ratio of the sum of the areas of all the grooves 13 to the area of ​​one side surface of the semiconductor substrate 11 is between 30% and 80%. That is, the area of ​​the laser-grooved grooves accounts for 30% to 80% of the area of ​​one side surface of the semiconductor substrate 11.

[0232] In one embodiment, see Figure 25 and Figure 26 As shown, the solar cell 10 includes a plurality of first grid lines 14 arranged along the first direction X; the size of the first grid lines 14 along the second direction Y is larger than the size of the first passivation contact portion 12a along the second direction Y; the first grid lines 14 are disposed on the side of the corresponding first passivation contact portion 12a away from the semiconductor substrate 11 and the side of the corresponding passivation contact portion 12b away from the semiconductor substrate 11.

[0233] Thus, by limiting the dimension of the first gate line 14 along the second direction Y to be larger than the dimension of the first passivation contact portion 12a along the second direction Y, and by placing the first gate line 14 at both the first passivation contact portion 12a and the second passivation contact portion 12b, the patterning area, time, and difficulty of the passivation contact layer 12 are reduced, improving the patterning efficiency of the passivation contact layer 12. Furthermore, the extension of the first gate line 14 to the second passivation contact portion 12b ensures the effective contact area between the first gate line 14 and the passivation contact layer 12, preventing the carrier transport path from breaking or the contact resistance from increasing due to the shortening of the first passivation contact portion 12a. In addition, it is compatible with high-number dense-gate schemes, enhancing carrier collection efficiency and improving photoelectric conversion efficiency without increasing process complexity, further achieving a synergistic improvement in battery performance and production efficiency, and ensuring performance stability and mass production adaptability under the dense-gate design.

[0234] In one embodiment, see Figure 25 and Figure 26 As shown, the difference between the dimension of the first gate line 14 along the second direction Y and the dimension of the first passivated contact portion 12a along the second direction Y is between 20 and 150 mm. Specifically, the difference between L1 and L2 can be 20 mm, 40 mm, 50 mm, 70 mm, 90 mm, 110 mm, 130 mm, 150 mm, or any value between 20 mm and 150 mm.

[0235] Thus, by limiting the dimension L1 of the first grid line 14 along the second direction Y to be greater than the dimension L2 of the first passivation contact portion 12a, and controlling the difference within 20-150 mm, the laser grooving length is reduced by shortening L2, thereby reducing the area, time, and difficulty of patterning the passivation contact layer 12, ensuring the efficiency of laser grooving, guaranteeing laser production capacity, and improving the production efficiency of the solar cell 10. Simultaneously, the first grid line 14 extends to the second passivation contact portion 12b, ensuring the effective contact area between the first grid line 14 and the passivation contact layer 12, and avoiding carrier transport losses. Furthermore, a reasonable difference range can accommodate dense grid design and process requirements, further optimizing production efficiency while ensuring photoelectric conversion efficiency, achieving a synergistic improvement in performance and process.

[0236] In one embodiment, see Figure 25 and Figure 26 As shown, at least one first gate line 14 is provided on the side of the first passivation contact portion 12a away from the semiconductor substrate 11. That is, the first passivation contact portion 12a and the first gate line 14 can be provided in a one-to-one correspondence; or one first passivation contact portion 12a can correspond to multiple first gate lines 14.

[0237] In other words, the dimension of each first passivated contact portion 12a along the first direction X is W, and the dimension of the first gate line 14 along the first direction X is S, where W: S > 1.

[0238] In one embodiment, see Figure 25 and Figure 26 As shown, the number of first gate lines 14 is greater than or equal to the number of first passivated contact portions 12a.

[0239] When the first passivated contact portion 12a and the first gate line 14 are arranged in a one-to-one correspondence, the number of first gate lines 14 is equal to the number of first passivated contact portions 12a; when one first passivated contact portion 12a can correspond to multiple first gate lines 14, the number of first gate lines 14 is greater than the number of first passivated contact portions 12a.

[0240] In one embodiment, see Figure 25 and Figure 26 As shown, the dimension of the second passivated contact portion 12b along the second direction Y is between 10 and 150 mm. Specifically, the dimension L3 of the second passivated contact portion 12b along the second direction Y can be 10 mm, 30 mm, 50 mm, 70 mm, 100 mm, 120 mm, 150 mm, or any value between 10 mm and 150 mm.

[0241] Thus, by limiting the dimension L3 of the second passivated contact portion 12b along the second direction Y to 10-150 mm, both the effective contact area with the first grid line 14 is ensured, guaranteeing smooth and lossless carrier transport, and the patterning difficulty of the passivated contact layer 12 is avoided due to excessive size. Furthermore, this reasonable range synergizes with the size design of the first grid line 14 and the first passivated contact portion 12a, shortening the laser grooving length, improving patterning efficiency, and ensuring stable compatibility with dense grid schemes. This further optimizes production consistency and efficiency while guaranteeing the photoelectric conversion efficiency of the solar cell 10.

[0242] In one embodiment, see Figure 25 and Figure 26 As shown, the second passivated contact portion 12b is constructed as a strip-shaped structure extending along the first direction X.

[0243] In one embodiment, see Figure 26 and Figure 27 As shown, the passivation contact layer 12 also includes a plurality of third passivation contact portions 12c, which are arranged in a row along the first direction X and in a column along the second direction Y; all third passivation contact portions 12c located in the same column are located between two adjacent first passivation contact portions 12a; each third passivation contact portion 12c is connected to the corresponding first passivation contact portion 12a at both ends along the first direction X.

[0244] Thus, multiple third passivated contact portions 12c can connect multiple first passivated contact portions 12a to form a mesh structure. A groove 13, which is the mesh hole of the mesh structure, is defined between two adjacent first passivated contact portions 12a and two third passivated contact portions 12c. In this way, on the one hand, the area of ​​the passivated contact layer 12 in the thickness direction of the semiconductor substrate 11 is further increased, and the area of ​​the removed passivated contact layer 12 is reduced. This can greatly reduce the area and difficulty of patterning the passivated contact layer 12, improve the patterning efficiency of the passivated contact layer 12, ensure laser production capacity, and improve the production efficiency of the solar cell 10. On the other hand, it expands the carrier collection coverage area, effectively collects carriers in the region between adjacent first passivated contact portions 12a, shortens the carrier transport path, and reduces recombination loss. In addition, the connection structure between the third passivation contact 12c and the first passivation contact 12a enhances the overall structural stability of the passivation contact layer 12 and provides more uniform contact support for the grid lines, further compatibility with dense grid design, and significantly improves the photoelectric conversion efficiency and performance reliability of the solar cell 10 while ensuring production efficiency.

[0245] In one embodiment, see Figure 26 As shown, the solar cell 10 includes a second grid line 15, which is disposed on the side of a plurality of first passivation contacts 12a away from the semiconductor substrate 11 and on the side of a plurality of third passivation contacts 12c located in the same column away from the semiconductor substrate 11; the second grid line 15 is connected to the first grid line 14.

[0246] In one embodiment, see Figure 26 As shown, the solar cell 10 includes a second grid line 15, which is disposed on the side of the second passivated contact portion 12b away from the semiconductor substrate 11; the second grid line 15 is connected to the first grid line 14.

[0247] Thirdly, see Figure 1 As shown, this application provides a solar cell 10, including a semiconductor substrate 11, a passivation contact layer 12, and a plurality of grooves 13; the passivation contact layer 12 is disposed on at least one side surface of the semiconductor substrate 11; the passivation contact layer 12 includes a plurality of first passivation contact portions 12a arranged at intervals along a first direction X; the first direction X is parallel to the surface of the semiconductor substrate 11; a groove 13 is defined between each two adjacent first passivation contact portions 12a; in the thickness direction of the semiconductor substrate 11, the ratio of the area of ​​the passivation contact layer 12 to the sum of the areas of all grooves 13 is between 0.2 and 2.4.

[0248] In related technologies, in order to improve the carrier collection capability and the photoelectric conversion efficiency of solar cells, the number of fine grid lines in solar cells is gradually increasing. That is, solar cells are gradually adopting a dense grid scheme. The more fine grid lines there are, the larger the area of ​​the passivation contact layer patterning, the larger the area of ​​laser grooving, and the longer the time required, which reduces the production capacity of the laser equipment. In other words, there is a conflict between the dense grid scheme and the production capacity of the laser equipment. Thus, under the dense grid scheme, there is a conflict between the production efficiency and photoelectric conversion efficiency of solar cells. Based on this, in this embodiment, by setting the ratio of the area of ​​the passivation contact layer 12 to the sum of the areas of all grooves 13 in the thickness direction of the semiconductor substrate 11 to be between 0.2 and 2.4, the ratio between the area of ​​the passivation contact layer 12 and the area of ​​all grooves 13 can be flexibly designed according to the number of fine grid lines and the production capacity of the laser equipment. This allows the passivation contact layer 12 to adapt to dense grid schemes with an increased number of fine grid lines, accommodating a high number of fine grid lines without increasing the patterned area, reducing the difficulty and time of laser grooving, and improving both laser patterning efficiency and photoelectric conversion efficiency, thus resolving the contradiction between patterning and performance in related technologies. In addition, by using a reasonable ratio of groove area 13, parasitic absorption caused by full-surface poly can be effectively suppressed, ensuring light utilization; by using an appropriate passivation contact layer 12 area, the continuity of carrier collection channels is ensured, avoiding collection efficiency degradation due to insufficient passivation contact layer 12. This can improve both the photoelectric conversion efficiency and production efficiency of the solar cell 10.

[0249] In summary, the solar cell 10 provided in this application, by limiting the area ratio of the passivation contact layer 12 to all grooves 13 to 0.2 to 2.4, allows for flexible design of the ratio between the area of ​​the passivation contact layer 12 and the area of ​​all grooves 13 based on the number of fine grid lines and the production capacity of the laser equipment. This enables the passivation contact layer 12 to adapt to dense grid schemes with an increased number of fine grid lines, accommodating a high number of fine grid lines without expanding the patterned area, reducing the difficulty and time of laser grooving, and improving both laser patterning efficiency and photoelectric conversion efficiency, thus resolving the contradiction between patterning and performance in related technologies. Furthermore, the reasonable area ratio of the grooves 13 effectively suppresses parasitic absorption caused by the whole-surface poly, ensuring light utilization. The adapted area of ​​the passivation contact layer 12 ensures the continuity of the carrier collection channel, avoiding collection efficiency degradation due to insufficient passivation contact layer 12. This improves both the photoelectric conversion efficiency and the production efficiency of the solar cell 10.

[0250] In one embodiment, the passivation contact layer 12 accounts for 20% to 70% of the area of ​​one side surface of the semiconductor substrate 11.

[0251] Accordingly, in the thickness direction of the semiconductor substrate 11, the ratio of the sum of the areas of all the grooves 13 to the area of ​​one side surface of the semiconductor substrate 11 is between 30% and 80%. That is, the area of ​​the laser-grooved grooves accounts for 30% to 80% of the area of ​​one side surface of the semiconductor substrate 11.

[0252] In one embodiment, see Figure 1 , Figure 4 As shown, the solar cell 10 also includes a plurality of first grid lines 14, which are arranged along a first direction X. The first grid lines 14 are disposed on the side of the corresponding first passivation contact portion 12a away from the semiconductor substrate 11. At least a portion of the first passivation contact portions 12a are provided with a plurality of first grid lines 14 on the side away from the semiconductor substrate 11.

[0253] In other words, multiple first grid lines 14 can be correspondingly provided on all first passivated contact portions 12a, or multiple first grid lines 14 can be correspondingly provided on a portion of the first passivated contact portions 12a, and at least one first grid line 14 can be correspondingly provided on a portion of the first passivated contact portions 12a. In this way, while keeping the number of first grid lines 14 unchanged, the number of first passivated contact portions 12a can be made smaller than the number of first grid lines 14, thereby reducing the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, when the passivated contact layer 12 is patterned, the total area of ​​the passivated contact layer 12 that is removed is reduced. This greatly reduces the area and difficulty of patterning the passivated contact layer 12, improves the efficiency of patterning the passivated contact layer 12, ensures the production capacity of the laser equipment, improves the production efficiency of the solar cell 10, and meets the production capacity requirements of mass production.

[0254] In one embodiment, see Figures 1 to 3 As shown, all first passivation contact portions 12a have multiple first gate lines 14 on the side opposite to the semiconductor substrate 11; and at least a portion of the first passivation contact portions 12a have the same number of corresponding first gate lines 14.

[0255] In this way, a high degree of regularity and consistency in the patterned layout of the passivation contact layer 12 can be achieved. On the one hand, the regular layout can improve the problem of uneven local carrier collection caused by the difference in the number of first gate lines 14 on some of the first passivation contact portions 12a, ensuring that carriers on the surface of the semiconductor substrate 11 can be efficiently transported to the first gate lines 14 in each region, effectively reducing the local recombination current density and further improving the photoelectric conversion efficiency of the solar cell 10. On the other hand, it is beneficial to the patterned processing of the passivation contact layer 12, improving the stability and efficiency of the patterned processing of the passivation contact layer 12, and making it easier to be compatible with high-number dense gate schemes. While ensuring the number of gate lines to enhance the carrier collection capability, production efficiency is further optimized.

[0256] In one embodiment, see Figures 1 to 3 As shown, the first passivated contact portion 12a has a dimension of W along the first direction X, and the first gate line 14 has a dimension of S along the first direction X, where W: S > 2.

[0257] In other words, the dimension of the first passivation contact portion 12a along the first direction X is greater than twice the linewidth of the first gate line 14, so that at least two first gate lines 14 can be provided on the first passivation contact portion 12a. Thus, with the number of first gate lines 14 remaining unchanged, the number of first passivation contact portions 12a is much smaller than the number of first gate lines 14, thereby reducing the number of grooves 13 defined by all the first passivation contact portions 12a. That is to say, the total area of ​​the removed passivation contact layer 12 is reduced, greatly reducing the difficulty of patterning the passivation contact layer 12, thereby improving the patterning efficiency of the passivation contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivation contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivation contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0258] In one embodiment, see Figures 4 to 7 As shown, the plurality of first passivated contact portions 12a include at least one first passivated contact sub-port 12a1 and at least one second passivated contact sub-port 12a2; the first passivated contact sub-port 12a1 has a first gate line 14 on the side away from the semiconductor substrate 11, where a ≥ 1; the second passivated contact sub-port 12a2 has b first gate lines 14 on the side away from the semiconductor substrate 11; where b > a, and a and b are both positive integers.

[0259] In this way, at least one first gate line 14 can be provided on the side of the first passivated contact portion 12a1 facing away from the semiconductor substrate 11, and at least two first gate lines 14 can be provided on the side of the second passivated contact portion 12a2 facing away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is less than the number of first gate lines 14, thereby reducing the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is reduced, which can greatly reduce the difficulty of patterning the passivated contact layer 12, thereby improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10.

[0260] In one embodiment, see Figure 4 , Figures 8 to 10As shown, the first passivated contact portion 12a1 has a dimension of W1 along the first direction X, and the second passivated contact portion 12a2 has a dimension of W2 along the first direction X; the first gate line 14 has a dimension of S along the first direction X, where W2 > W1, W2:S > 2, and W1:S > 1.

[0261] In other words, the dimension of the first passivated contact portion 12a1 along the first direction X is larger than the linewidth of the first gate line 14, and the dimension of the second passivated contact portion 12a2 along the first direction X is larger than twice the linewidth of the first gate line 14. This allows the first passivated contact portion 12a1 to have at least one first gate line 14 on the side facing away from the semiconductor substrate 11, and the second passivated contact portion 12a2 to have at least two first gate lines 14 on the side facing away from the semiconductor substrate 11. Thus, while maintaining the same number of first gate lines 14, the number of first passivated contact portions 12a is less than the number of first gate lines 14, making... The number of grooves 13 defined by all the first passivated contact portions 12a is reduced, that is, the total area of ​​the passivated contact layer 12 that is removed is reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10; at the same time, since the passivated contact layer 12 is disposed in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0262] In one embodiment, see Figure 4 , Figures 8 to 10 As shown, 1 < W2: W1 ≤ 10. Preferably, 1 < W2: W1 ≤ 5. Specifically, W2: W1 can be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, or any value greater than 1 and less than or equal to 5.

[0263] In this way, the first passivated contact portion 12a1 can be provided with at least one first gate line 14 on the side away from the semiconductor substrate 11, and the second passivated contact portion 12a2 can be provided with at least five first gate lines 14 on the side away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is much smaller than the number of first gate lines 14, which further reduces the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is further reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, further improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0264] In one embodiment, see Figure 4 , Figure 8 As shown, 1 < b: a ≤ 10. Preferably, 1 < b: a ≤ 5. Specifically, b: a can be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, or any value greater than 1 and less than or equal to 5.

[0265] In this way, the first passivated contact portion 12a1 can be provided with at least one first gate line 14 on the side away from the semiconductor substrate 11, and the second passivated contact portion 12a2 can be provided with at least five first gate lines 14 on the side away from the semiconductor substrate 11. In this way, while keeping the number of first gate lines 14 unchanged, the number of first passivated contact portions 12a is much smaller than the number of first gate lines 14, which further reduces the number of grooves 13 defined by all the first passivated contact portions 12a. That is to say, the total area of ​​the removed passivated contact layer 12 is further reduced, thereby greatly reducing the difficulty of patterning the passivated contact layer 12, further improving the patterning efficiency of the passivated contact layer 12, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since the passivated contact layer 12 is provided in a local area of ​​at least one side surface of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0266] In one embodiment, see Figure 4 As shown, on a plane perpendicular to the thickness direction of the semiconductor substrate 11, the area of ​​the first passivation contact portion 12a1 is smaller than the area of ​​the second passivation contact portion 12a2.

[0267] In one embodiment, the area of ​​all the second passivated contact portions 12a2 on one side surface of the semiconductor substrate 11 is between 10% and 35%.

[0268] In one embodiment, see Figures 4 to 11 As shown, the plurality of first passivated contact portions 12a include a plurality of first passivated contact sub-portions 12a1 and a plurality of second passivated contact sub-portions 12a2; the plurality of first passivated contact sub-portions 12a1 and the plurality of second passivated contact sub-portions 12a2 are alternately distributed along the first direction X.

[0269] Since the number of first gate lines 14 corresponding to the second passivated contact portion 12a2 is greater than the number of first gate lines 14 corresponding to the first passivated contact portion 12a1, the second passivated contact portion 12a2 corresponds to a high gate line density region, and the first passivated contact portion 12a1 can be a basic gate line density region. By distributing multiple first passivated contact portions 12a1 and multiple second passivated contact portions 12a2 alternately along the first direction X, on the one hand, the high gate line density region and the basic gate line density region can form a uniformly spaced current collection network on the surface of the semiconductor substrate 11. That is, the multi-gate line design of the second passivated contact portion 12a2 enhances the fast extraction capability of charge carriers and reduces the recombination loss of charge carriers during the transmission process. Especially for regions in the semiconductor substrate 11 with high charge carrier concentration or long transmission path, the multi-gate line layout can shorten the migration distance of charge carriers to the gate line and reduce the probability of bulk recombination and surface recombination. On the other hand, it can balance the stress distribution on the surface of the semiconductor substrate 11, improve the bonding stability between the passivation contact layer 12 and the semiconductor substrate 11 and the gate line, reduce defects such as cracks and peeling caused by uneven stress during the battery manufacturing process (such as high-temperature annealing, coating and other processes), and ensure the long-term reliability and photoelectric conversion efficiency stability of the battery.

[0270] In one embodiment, see Figures 4 to 7 As shown, at least one first passivated contact portion 12a1 is located between two adjacent second passivated contact portions 12a2.

[0271] When patterning the passivation contact layer 12, a mask layer is usually first formed on the side of the passivation contact layer 12 away from the semiconductor substrate 11. Then, a groove is made on the mask layer using a laser, and then wet etching is used to form a plurality of first passivation contact portions 12a arranged at intervals along the first direction. However, when the laser makes grooves in the edge region of the semiconductor substrate 11, the optical system of the laser equipment is prone to aberrations such as field curvature, astigmatism, and coma, which makes the laser spot of the laser equipment prone to distortion, such as the laser spot size becoming larger, the shape being distorted, and the energy being dispersed. In addition, the mask quality in the edge region of the semiconductor substrate 11 is relatively poor, which means that the laser processing quality is worse the closer to the edge region of the semiconductor substrate 11. This makes it easy for the laser to have incomplete film opening in the edge region of the semiconductor substrate 11, resulting in film residue after subsequent wet etching and causing a decrease in yield. Based on this, in this embodiment, by placing at least one first passivated contact portion 12a1 between two adjacent second passivated contact portions 12a2, and the dimension W2 of the second passivated contact portion 12a2 along the first direction X is greater than the dimension W1 of the first passivated contact portion 12a1 along the first direction X, the number of grooves 13 in the edge region of the semiconductor substrate 11 along both sides of the first direction X can be reduced. In other words, the laser processing area in the edge region of the semiconductor substrate 11 along both sides of the first direction X can be reduced, thereby improving the problem of incomplete laser film opening in the edge region of the semiconductor substrate 11 along both sides of the first direction X and improving the yield of the solar cell 10.

[0272] In one embodiment, see Figures 8 to 11 As shown, the plurality of first passivated contact portions 12a include a plurality of first passivated contact sub-portions 12a1; all first passivated contact sub-portions 12a1 are provided with at least one second passivated contact sub-portion 12a2 on at least one side along the first direction X.

[0273] In this way, the number of grooves 13 in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be reduced, that is, the laser processing area in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be reduced, thereby improving the problem of incomplete laser film opening in the edge region of at least one side of the semiconductor substrate 11 along the first direction X and improving the yield of the solar cell 10.

[0274] In one embodiment, see Figure 15 , Figures 17 to 19 As shown, all first passivated contact portions 12a1 are provided with a plurality of second passivated contact portions 12a2 on at least one side along the first direction X; along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the size W2 of the plurality of second passivated contact portions 12a2 gradually increases along the first direction X.

[0275] In this way, the number of grooves 13 in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be further reduced, that is, the laser processing area in the edge region of at least one side of the semiconductor substrate 11 along the first direction X can be further reduced, thereby further improving the problem of incomplete laser film opening in the edge region of at least one side of the semiconductor substrate 11 along the first direction X; moreover, when performing electroluminescence testing on the solar cell 10, the probability of defects such as uneven brightness in the solar cell 10 can be greatly reduced, thereby improving the yield of the solar cell 10.

[0276] In one embodiment, see Figures 15 to 19 As shown, along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the number of corresponding first gate lines 14 on the plurality of second passivated contact portions 12a2 gradually increases.

[0277] Thus, by gradually increasing the number of first gate lines 14 on multiple second passivated contact portions 12a2 along the direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2, the gradient increase in the number of first gate lines 14 can be adapted to the gradient design of the size W2 of the second passivated contact portion 12a2 along the first direction X (i.e., the size W2 of multiple second passivated contact portions 12a2 gradually increases along the first direction from the first passivated contact portion 12a1 to the second passivated contact portion 12a2). This reduces the laser processing area and improves the problem of unclean edge film opening, while ensuring the synchronous improvement of the carrier collection capacity of the passivated contact area, and improving the recombination loss caused by the extension of the carrier transport path due to the increase in size. In addition, the gradient in the number of gate lines makes the carrier collection efficiency on the surface of the semiconductor substrate 11 uniformly distributed, effectively alleviating the undesirable phenomenon of uneven brightness in electroluminescence testing. This not only ensures the high photoelectric conversion efficiency brought by the dense gate design, but also further improves the yield and performance stability of the solar cell 10.

[0278] In one embodiment, see Figures 20 to 23 As shown, all first passivated contact portions 12a1 have multiple sets of second passivated contact portions 12a2 on at least one side along the first direction X; each set includes multiple second passivated contact portions 12a2, and the dimensions W2 of the second passivated contact portions 12a2 in each set along the first direction X are all equal; in two adjacent sets of second passivated contact portions 12a2, the dimension of the second passivated contact portion 12a2 in the set closer to the first passivated contact portion 12a1 along the first direction X is smaller than the dimension of the second passivated contact portion 12a2 in the set farther away from the first passivated contact portion 12a1 along the first direction X.

[0279] Thus, by using a smaller W2 for the second passivation contact portion 12a2 within the group closer to the first passivation contact portion 12a1, and a larger W2 for the second passivation contact portion 12a2 in the group farther away, the number of grooves 13 is further reduced by using larger second passivation contact portions 12a2 in the edge region, thereby reducing the laser processing area and effectively improving the problem of unclean edge film opening, while also achieving a smooth transition in carrier collection capability. In addition, the grouping gradient design simplifies the control difficulty of mask preparation and patterning processes, ensuring the production efficiency of the solar cell 10 while being compatible with dense grid design, thereby improving the production yield and photoelectric conversion efficiency of the solar cell 10.

[0280] In one embodiment, see Figures 20 to 24 As shown, the number of first gate lines 14 on the second passivated contact portion 12a2 in each group is equal; in two adjacent groups of second passivated contact portions 12a2, the number of first gate lines 14 on the second passivated contact portion 12a2 in the group closer to the first passivated contact portion 12a1 is less than the number of first gate lines 14 on the second passivated contact portion 12a2 in the group farther away from the first passivated contact portion 12a1.

[0281] Thus, by maintaining a consistent number of first gate lines 14 in the second passivated contact portion 12a2 within each group, the uniformity of the carrier collection path within the group is ensured, avoiding uneven current distribution and carrier recombination losses caused by local gate line density differences, and guaranteeing the stability of photoelectric conversion efficiency per unit area. Simultaneously, the number of gate lines between adjacent groups increases in a gradient away from the first passivated contact portion 12a1, precisely synergizing with the inter-group increase in the size of the second passivated contact portion 12a2. This allows the larger passivated contact area to enhance carrier extraction capability through more gate lines, avoiding the problem of extended carrier transport paths due to size expansion. Furthermore, it effectively reduces the number of grooves 13 in the edge region of the semiconductor substrate 11 along the first direction X, further improving the problem of incomplete laser delamination and increasing the yield of the solar cell 10. Moreover, the grouping gradient design simplifies the process control difficulty of mask patterning and gate line fabrication, significantly improving the production consistency and yield of the solar cell 10 while maintaining compatibility with dense gate designs and ensuring high photoelectric conversion efficiency.

[0282] In one embodiment, see Figures 19 to 21 , Figure 23As shown, the dimension L1 of the first gate line 14 along the second direction Y is smaller than the dimension L2 of the first passivated contact portion 12a along the second direction Y; the difference between L2 and L1 is between 0 and 10 mm; for example, the difference between L2 and L1 can be 0.1 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, or between any two of the above values. The second direction Y is parallel to the surface of the semiconductor substrate 11 and intersects with the first direction X.

[0283] Thus, by limiting the dimension L2 of the first passivated contact portion 12a along the second direction Y to be slightly larger than the corresponding dimension L1 of the first gate line 14, and controlling the difference between the two within a reasonable range of 0 to 10 mm, sufficient tolerance space is reserved for process steps such as photolithography alignment and gate line fabrication. This effectively avoids misalignment between the gate line and the passivated contact portion due to process deviations, ensuring that the two always maintain reliable and effective contact, reducing the risk of performance degradation caused by poor contact, and improving production consistency and yield. At the same time, it avoids the additional increase in the patterning area and difficulty of the passivated contact layer 12 due to the moderate increase of L2, thereby simplifying the process and improving production efficiency. In addition, the reasonable size difference can ensure the effective contact area for carrier transport, avoid the increase in contact resistance, and further ensure the photoelectric conversion efficiency and performance stability of the solar cell 10 while being compatible with the dense gate design and optimizing the processing effect of the edge region.

[0284] In one embodiment, see Figure 22 As shown, the passivation contact layer 12 further includes a second passivation contact portion 12b; the second passivation contact portion 12b is located on at least one side of the plurality of first passivation contacts 12a along the second direction Y, and is connected to the plurality of first passivation contacts 12a; the second direction Y is parallel to the surface of the semiconductor substrate 11 and intersects with the first direction X.

[0285] This effectively shortens the dimension of the first passivated contact portion 12a along the second direction Y, and correspondingly shortens the length of the groove 13 along the second direction Y. This effectively shortens the length of laser grooving, thereby greatly reducing the area of ​​the passivated contact layer 12 to be removed, reducing the difficulty and time required for patterning the passivated contact layer 12, ensuring the efficiency of laser grooving, ensuring the production capacity of the laser equipment, and improving the production efficiency of the solar cell 10. At the same time, since multiple first passivated contact portions 12a are arranged at intervals along the first direction, that is, the passivated contact layer 12 is provided in a local area on at least one side of the semiconductor substrate 11, the parasitic absorption of the entire passivated contact layer 12 can be avoided from affecting the photoelectric conversion efficiency of the solar cell 10, so that the solar cell 10 maintains a high photoelectric conversion efficiency.

[0286] In one embodiment, see Figure 22As shown, the solar cell 10 also includes a plurality of first grid lines 14, which are arranged along a first direction X; the first grid lines 14 are disposed on the side of the corresponding first passivation contact portion 12a away from the semiconductor substrate 11 and the side of the corresponding passivation contact portion 12b away from the semiconductor substrate 11.

[0287] In some examples, the dimension L1 of the first gate line 14 along the second direction Y is greater than the dimension L2 of the first passivated contact portion 12a along the second direction Y.

[0288] Thus, by placing the second passivated contact portion 12b on at least one side of the plurality of first passivated contacts 12a along the second direction Y, and connecting it to all of the plurality of first passivated contacts 12a, the portion of the first gate line 14 longer than the first passivated contact portion 12a extends onto the second passivated contact portion 12b. This ensures the effective contact area between the first gate line 14 and the passivated contact layer 12, preventing the carrier transport path from breaking or the contact resistance from increasing due to the shortening of the size of the first passivated contact portion 12a.

[0289] In one embodiment, see Figure 22 As shown, the dimension L of the second passivated contact portion 12b along the second direction Y is between 10 and 150 mm. Specifically, the dimension L3 of the second passivated contact portion 12b along the second direction Y can be 10 mm, 30 mm, 50 mm, 70 mm, 100 mm, 120 mm, 150 mm, or any value between 10 mm and 150 mm.

[0290] Thus, by limiting the dimension L3 of the second passivated contact portion 12b along the second direction Y to 10-150 mm, both the effective contact area with the first grid line 14 is ensured, guaranteeing smooth and lossless carrier transport, and the patterning difficulty of the passivated contact layer 12 is avoided due to excessive size. Furthermore, this reasonable range synergizes with the size design of the first grid line 14 and the first passivated contact portion 12a, shortening the laser grooving length, improving patterning efficiency, and ensuring stable compatibility with dense grid schemes. This further optimizes production consistency and efficiency while guaranteeing the photoelectric conversion efficiency of the solar cell 10.

[0291] In one embodiment, see Figure 22 As shown, the second passivated contact portion 12b is constructed as a strip-shaped structure extending along the first direction X.

[0292] In one embodiment, see Figure 22 As shown, the solar cell 10 also includes a second grid line 15, which is disposed on the side of the second passivated contact portion 12b away from the semiconductor substrate 11; the second grid line 15 is connected to the first grid line 14.

[0293] In one embodiment, see Figure 22As shown, the difference between L1 and L2 is between 20 and 150 mm. Specifically, the difference between L1 and L2 can be 20 mm, 40 mm, 50 mm, 70 mm, 90 mm, 110 mm, 130 mm, 150 mm, or any value between 20 mm and 150 mm.

[0294] Thus, by limiting the dimension L1 of the first gate line 14 along the second direction Y to be greater than the dimension L2 of the first passivation contact portion 12a, and controlling the difference to be within 20-150 mm, the length of the groove 13 and the workload of laser grooving are further reduced by shortening L2, thereby improving the patterning efficiency of the passivation contact layer 12. Simultaneously, the first gate line 14 extends to the second passivation contact portion 12b, ensuring the effective contact area between the first gate line 14 and the passivation contact layer 12, and avoiding carrier transport losses. Furthermore, a reasonable difference range can accommodate dense gate design and process requirements, ensuring photoelectric conversion efficiency while further optimizing production efficiency, achieving a synergistic improvement in performance and process.

[0295] In one embodiment, see Figures 25 to 26 As shown, at least one first gate line 14 is provided on the side of the first passivation contact portion 12a away from the semiconductor substrate 11. That is, the first passivation contact portion 12a and the first gate line 14 can be provided in a one-to-one correspondence; or one first passivation contact portion 12a can correspond to multiple first gate lines 14.

[0296] In one embodiment, see Figures 25 to 26 As shown, the dimension of each first passivated contact portion 12a along the first direction X is W, and the dimension of the first gate line 14 along the first direction X is S, where W:S>1. In this way, at least one first gate line 14 can be correspondingly provided on the first passivated contact portion 12a.

[0297] In one embodiment, see Figures 25 to 26 As shown, the number of first gate lines 14 is greater than or equal to the number of first passivated contact portions 12a.

[0298] When the first passivated contact portion 12a and the first gate line 14 are arranged in a one-to-one correspondence, the number of first gate lines 14 is equal to the number of first passivated contact portions 12a; when one first passivated contact portion 12a can correspond to multiple first gate lines 14, the number of first gate lines 14 is greater than the number of first passivated contact portions 12a.

[0299] In one embodiment, see Figures 22 to 23 , Figures 25 to 26As shown, the passivation contact layer 12 also includes a plurality of third passivation contact portions 12c, which are arranged in a row along the first direction X and in a column along the second direction Y. The first direction X and the second direction Y are parallel to the surface of the semiconductor substrate 11 and intersect each other. All third passivation contact portions 12c located in the same column are located between two adjacent first passivation contact portions 12a. Each third passivation contact portion 12c is connected to the corresponding first passivation contact portion 12a at both ends along the first direction X.

[0300] Thus, multiple first passivation contacts 12a can be connected to form a mesh structure through multiple third passivation contacts 12c. A groove 13, i.e., a mesh opening in the mesh structure, is defined between two adjacent first passivation contacts 12a and two third passivation contacts 12c. This increases the area of ​​the passivation contact layer 12 in the thickness direction of the semiconductor substrate 11 and reduces the area of ​​all grooves 13 in the thickness direction of the semiconductor substrate 11, i.e., the area of ​​the removed passivation contact layer 12, thereby improving the efficiency of the passivation contact layer 12 patterning. At the same time, it ensures the number of first grid lines 14 of the solar cell 10, thereby improving both the photoelectric conversion efficiency and the production efficiency of the solar cell 10. On the other hand, it expands the carrier collection coverage area, effectively collecting carriers in the region between adjacent first passivation contacts 12a, shortening the carrier transport path, and reducing recombination losses. In addition, the connection structure between the third passivation contact 12c and the first passivation contact 12a enhances the overall structural stability of the passivation contact layer 12 and provides more uniform contact support for the grid lines, further compatibility with dense grid design, and significantly improves the photoelectric conversion efficiency and performance reliability of the solar cell 10 while ensuring production efficiency.

[0301] In one embodiment, see Figures 22 to 23 , Figures 25 to 26 As shown, the solar cell 10 also includes a second grid line 15; the second grid line 15 is disposed on the side of a plurality of first passivation contacts 12a away from the semiconductor substrate 11 and on the side of a plurality of third passivation contacts 12c located in the same row away from the semiconductor substrate 11.

[0302] In one embodiment, see Figures 17 to 23 , Figures 25 to 26 As shown, the spacing between any two adjacent first grid lines 14 is equal.

[0303] Thus, by ensuring that the spacing between any two adjacent first gate lines 14 is equal, a uniformly distributed carrier collection channel can be formed on the surface of the semiconductor substrate 11, ensuring that the carrier transport path length is consistent in each region. This avoids problems such as increased local carrier recombination loss or excessive parasitic absorption caused by uneven spacing, significantly improving the stability of photoelectric conversion efficiency. Furthermore, the spacing between adjacent first gate lines 14 does not change with the dimension of the first passivation contact portion 12a along the first direction X. Therefore, the fabrication process of the first gate lines 14 is not affected by the pattern of the passivation contact layer 12, allowing for the fabrication of the first gate lines 14 using existing processes or screen printing, thereby reducing the fabrication cost of the solar cell 10 and improving its production efficiency. In addition, the equal spacing design simplifies the process control of photolithography mask fabrication and gate line processing, which is beneficial for ensuring process accuracy and production consistency under a dense-gate scheme, reducing processing defects caused by spacing deviations, and enhancing the performance reliability and mass production adaptability of the solar cell 10.

[0304] In one embodiment, see Figures 17 to 23 , Figures 25 to 26 As shown, the spacing between any two adjacent first passivated contact portions 12a is equal.

[0305] Thus, by ensuring that the spacing between any two adjacent first passivation contact portions 12a is equal, the passivation contact layer 12 can form a uniformly distributed structure on the surface of the semiconductor substrate 11. This ensures a consistent carrier collection environment in each region, avoids excessive differences in local carrier transport paths and increased recombination losses due to uneven spacing, and guarantees the stability and uniformity of photoelectric conversion efficiency. Furthermore, the equal spacing design simplifies the process control of photolithography mask fabrication and laser grooving, facilitates precise control of processing parameters, reduces processing defects caused by spacing deviations, and improves production consistency and yield.

[0306] In one embodiment, see Figures 17 to 23 , Figures 25 to 26 As shown, the size difference between any two first passivated contact portions 12a along the second direction Y is n, and the value of n ranges from -5mm to n to 5mm.

[0307] This ensures that the structural dimensions of each first passivation contact 12a are highly consistent in the second direction Y, thereby guaranteeing the uniformity of the carrier collection environment on the surface of the semiconductor substrate 11. Specifically, the carrier transport path length and effective contact area with the gate line corresponding to each passivation contact tend to be consistent, avoiding imbalances in carrier collection efficiency in local areas due to size differences, reducing recombination losses, and ensuring the stability of the photoelectric conversion efficiency of the solar cell 10. Furthermore, the small size difference accommodates reasonable process errors, reducing the difficulty of precision control in mask preparation and patterning, avoiding alignment errors or processing defects caused by excessive size deviations, while not affecting the simplified advantages of the overall patterning of the passivation contact layer 12. This synergizes with designs such as dense gate adaptation and edge region yield optimization, further consolidating the synergistic improvement in photoelectric conversion efficiency and production efficiency while enhancing production consistency and yield.

[0308] In one embodiment, see Figures 17 to 23 , Figures 25 to 26 As shown, the first passivated contact portion 12a is constructed as a strip-shaped structure extending along the second direction Y.

[0309] Thus, by constructing the first passivation contact 12a as a strip extending along the second direction Y, the first passivation contact 12a can be adapted to the first gate line 14, maximizing the contact area between the two, shortening the carrier transport path, and reducing recombination losses. In addition, the strip-shaped patterning process is simple, which can further reduce the processing difficulty and cost of the passivation contact layer 12, and the structure has strong uniformity, ensuring the consistency of carrier collection on the substrate surface. While being compatible with dense gate design and optimizing edge processing yield, it simultaneously improves the photoelectric conversion efficiency and production efficiency of the solar cell 10.

[0310] The following are some specific examples illustrating the parameters of the solar cells in this application, such as short-circuit current, open-circuit voltage, fill factor, and conversion efficiency.

[0311] Table 1: Differences in various parameters of different solar cells

[0312]

[0313] It should be noted that the solar cells in Comparative Example 1 and Comparative Example 2 both include a passivation contact layer covering the entire surface. In Comparative Example 1, the number of first grid lines is 228, and in Comparative Example 2, the number of first grid lines is 336 (corresponding to a dense grid scheme). In this embodiment, the solar cell includes a passivation contact layer and 336 first grid lines. The passivation contact layer includes multiple first passivation contact portions spaced apart along a first direction; the 336 first grid lines are arranged along the first direction; the first grid lines are disposed on corresponding first passivation contact portions, and at least a portion of the first passivation contact portions have multiple first grid lines; the first grid lines can be fine grid lines. Comparative Example 1 is the basic comparative example, and all parameters in Comparative Example 1 are zero.

[0314] In Table 1, compared to the 228 first grid lines in Comparative Example 1, Comparative Example 2 uses 336 first grid lines. The short-circuit current and open-circuit voltage of the solar cell are slightly reduced, the fill factor increases by 0.95, and the photoelectric conversion efficiency increases by 0.18%. This means that increasing the number of first grid lines can improve the photoelectric conversion efficiency of the solar cell. Compared to Comparative Example 1, the passivation contact layer in this embodiment is patterned to form a poly-finger structure, with 336 first grid lines. The open-circuit voltage of the solar cell remains essentially unchanged, while the short-circuit current, fill factor, and photoelectric conversion efficiency are all increased. Compared to Comparative Example 2, this embodiment, while maintaining the same number of first grid lines, improves the parasitic absorption problem of the entire passivation contact layer 12 by patterning the passivation contact layer, resulting in a significant improvement in the photoelectric conversion efficiency of the solar cell. In summary, by making the passivation contact layer of the solar cell include a plurality of first passivation contact portions spaced apart along the first direction, and at least a portion of the first passivation contact portions are provided with a plurality of first grid lines, that is, by patterning the passivation contact layer, the patterned passivation contacts can be adapted to the arrangement and number of the first grid lines of the solar cell, especially the number and arrangement of grid lines in the dense grid scheme, thereby improving the photoelectric conversion efficiency of the solar cell.

[0315] Figure 32 The graphs showing the relationship between the passivation contact layer area ratio and short-circuit current in some embodiments of this application are illustrated. Figure 33 The graphs showing the relationship between the passivation contact layer area ratio and open-circuit voltage in some embodiments of this application are shown. Figure 34 The graphs showing the ratio of passivation contact layer area to fill factor in some embodiments of this application are shown. Figure 35 This application shows graphs illustrating the relationship between the passivation contact layer area ratio and photoelectric conversion efficiency in some embodiments; combined with Figures 32 to 35As can be seen, in the embodiments of this application, the area ratio of the passivation contact layer on one side surface of the semiconductor substrate is between 20% and 70%, and the photoelectric conversion efficiency, short-circuit current, open-circuit voltage and fill factor of the solar cell are all high. With the number of first grid lines unchanged, especially in the dense grid scheme, the area ratio of the passivation contact layer is between 20% and 70%, which is beneficial to improve the performance of the solar cell.

[0316] Fourthly, the photovoltaic module provided in this application includes the solar cell 10 in any of the above embodiments. This improves the photoelectric conversion efficiency and production efficiency of the photovoltaic module.

[0317] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0318] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: Semiconductor substrate; A passivation contact layer is disposed on at least one surface of the semiconductor substrate; The passivation contact layer includes a plurality of first passivation contact portions, which are spaced apart along a first direction; Multiple first gate lines are arranged along the first direction; the first gate lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate; In particular, at least a portion of the first passivated contacts have multiple first gate lines on the side facing away from the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, The plurality of first passivated contact portions include at least one first passivated contact sub-port and at least one second passivated contact portion; The first passivated contact portion has a first gate line on the side opposite to the semiconductor substrate, where a ≥ 1; The second passivated contact portion has b first gate lines on the side opposite to the semiconductor substrate; wherein b > a, and both a and b are positive integers.

3. The solar cell according to claim 2, characterized in that, The first passivated contact portion has a dimension of W1 along the first direction, and the second passivated contact portion has a dimension of W2 along the first direction; the first gate line has a dimension of S along the first direction, wherein W2 > W1, W2:S > 2, and W1:S > 1.

4. The solar cell according to claim 3, characterized in that, 1 < W2: W1 ≤ 10.

5. The solar cell according to claim 2, characterized in that, 1 < b: a ≤ 10.

6. The solar cell according to claim 2, characterized in that, In the thickness direction of the semiconductor substrate, the area of ​​the first passivated contact portion is smaller than the area of ​​the second passivated contact portion.

7. The solar cell according to claim 2, characterized in that, The area of ​​all the second passivated contacts on one side surface of the semiconductor substrate is between 10% and 35%.

8. The solar cell according to claim 2, characterized in that, The plurality of first passivated contact portions include a plurality of first passivated contact sub-ports and a plurality of second passivated contact sub-ports; the plurality of first passivated contact sub-ports and the plurality of second passivated contact sub-ports are alternately distributed along the first direction.

9. The solar cell according to claim 8, characterized in that, At least one of the first passivated contact portions is located between two adjacent second passivated contact portions.

10. The solar cell according to claim 2, characterized in that, The plurality of first passivated contact portions include a plurality of first passivated contact sub-portions; all first passivated contact sub-portions are provided with at least one second passivated contact sub-portion on at least one side along the first direction.

11. The solar cell according to claim 10, characterized in that, All the first passivated contact portions are provided with a plurality of second passivated contact portions on at least one side along the first direction; Along the direction from the first passivated contact portion to the second passivated contact portion, the size W2 of the plurality of second passivated contact portions gradually increases along the first direction.

12. The solar cell according to claim 11, characterized in that, Along the direction from the first passivated contact portion to the second passivated contact portion, the number of the first gate lines corresponding to the plurality of second passivated contact portions gradually increases.

13. The solar cell according to claim 10, characterized in that, All the first passivated contact portions are provided with multiple sets of second passivated contact portions on at least one side along the first direction; Each group includes multiple second passivated contact portions, and the dimensions W2 of the second passivated contact portions in each group are equal along the first direction; In two adjacent groups of second passivated contact portions, the size of the second passivated contact portion along the first direction in the group closer to the first passivated contact portion is smaller than the size of the second passivated contact portion along the first direction in the group farther from the first passivated contact portion.

14. The solar cell according to claim 13, characterized in that, The number of the first gate lines corresponding to the second passivated contact portion in each group is equal; In two adjacent groups of second passivated contact portions, the number of first gate lines corresponding to the second passivated contact portions in the group closer to the first passivated contact portion is less than the number of first gate lines corresponding to the second passivated contact portions in the group farther from the first passivated contact portion.

15. The solar cell according to claim 1, characterized in that, The dimension L1 of the first gate line along the second direction is smaller than the dimension L2 of the first passivated contact portion along the second direction; the difference between L2 and L1 is between 0 and 10 mm; the second direction intersects the first direction.

16. The solar cell according to claim 1, characterized in that, The passivation contact layer also includes a second passivation contact portion; The second passivated contact portion is located on at least one side of the plurality of first passivated contact portions along the second direction, and is connected to all of the plurality of first passivated contact portions; The first gate line is disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and on the side of the corresponding second passivation contact portion away from the semiconductor substrate; the second direction intersects with the first direction.

17. The solar cell according to claim 16, characterized in that, The dimension L1 of the first gate line along the second direction is greater than the dimension L2 of the first passivated contact portion along the second direction; the difference between L1 and L2 is between 20 and 150 mm.

18. The solar cell according to claim 16, characterized in that, The dimension L3 of the second passivated contact portion along the second direction is between 10 and 150 mm; And / or, the second passivated contact portion is configured as a strip-shaped structure extending along the first direction.

19. The solar cell according to claim 16, characterized in that, The solar cell further includes a second grid line, which is disposed on the side of the second passivated contact portion away from the semiconductor substrate; the second grid line is connected to the first grid line.

20. The solar cell according to claim 1, characterized in that, The passivation contact layer also includes multiple third passivation contacts. The plurality of third passivated contacts are arranged in a row along the first direction and in a column along the second direction; the first direction and the second direction are parallel to the surface of the semiconductor substrate and intersect each other; All the third passivated contacts located in the same column are located between two adjacent first passivated contacts; each of the third passivated contacts is connected to the corresponding first passivated contacts at both ends along the first direction.

21. The solar cell according to claim 20, characterized in that, The solar cell also includes a second grid line; The second gate line is disposed on the side of the plurality of first passivated contacts facing away from the semiconductor substrate and on the side of the plurality of third passivated contacts located in the same row facing away from the semiconductor substrate.

22. The solar cell according to claim 1, characterized in that, The spacing between any two adjacent first gate lines is equal.

23. The solar cell according to claim 1, characterized in that, The spacing between any two adjacent first passivated contact portions is equal.

24. The solar cell according to any one of claims 1 to 23, characterized in that, The dimensional difference between any two first passivated contact portions along the second direction is n, and the value of n is in the range of -5mm≤n≤5mm; And / or, the first passivated contact portion is configured as a strip structure extending along the second direction; The second direction intersects with the first direction.

25. The solar cell according to any one of claims 1 to 23, characterized in that, The first passivated contact portion includes a first doped portion.

26. The solar cell according to claim 25, characterized in that, The first passivated contact portion further includes a first dielectric portion and a first substrate doped portion, wherein the first dielectric portion is located on the side of the first doped portion closer to the semiconductor substrate; The first substrate doped portion is disposed within the semiconductor substrate and is located on the side of the first dielectric portion away from the first doped portion. The doping type of the first substrate doped portion is the same as that of the first doped portion.

27. The solar cell according to claim 26, characterized in that, The region between adjacent first passivated contacts includes a polished surface or a textured surface. And / or, the maximum distance between the region between adjacent first passivation contacts and the side of the passivation contact layer distributed on the same side away from the semiconductor substrate is H1; the maximum distance between the surface of the first substrate doped portion away from the first dielectric portion and the side of the passivation contact layer distributed on the same side away from the semiconductor substrate is H2. H1≥H2.

28. The solar cell according to any one of claims 1 to 23, characterized in that, The first passivated contact portion includes at least two first sidewalls disposed opposite each other along a first direction, and the distance between the two first sidewalls along the first direction gradually decreases from the semiconductor substrate toward the first passivated contact portion.

29. The solar cell according to any one of claims 1 to 23, characterized in that, The solar cell further includes a first passivation layer that covers the first passivation contact portion and the area between adjacent first passivation contacts.

30. The solar cell according to claim 29, characterized in that, The solar cell further includes a first antireflection layer, which covers the first passivation layer.

31. A solar cell, characterized in that, include: Semiconductor substrate; A passivation contact layer is disposed on at least one surface of the semiconductor substrate; The passivation contact layer includes a plurality of first passivation contacts and at least one second passivation contact; The plurality of first passivated contact portions are arranged at intervals along a first direction; the plurality of first passivated contact portions are provided with a second passivated contact portion on at least one side along a second direction; the plurality of first passivated contact portions are all connected to the same second passivated contact portion; The first direction and the second direction are parallel to the surface of the semiconductor substrate and intersect each other.

32. The solar cell according to claim 31, characterized in that, The solar cell includes a plurality of first grid lines arranged along the first direction; The dimension of the first gate line along the second direction is larger than the dimension of the first passivated contact portion along the second direction; The first gate line is disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and the side of the corresponding second passivation contact portion away from the semiconductor substrate.

33. The solar cell according to claim 32, characterized in that, The first passivated contact portion has at least one first gate line on the side opposite to the semiconductor substrate; And / or, the dimension of the first passivated contact portion along the first direction is W, and the dimension of the first gate line along the first direction is S, where W: S > 1; And / or, the number of the first gate lines is greater than or equal to the number of the first passivated contacts.

34. A solar cell, characterized in that, include: Semiconductor substrate; A passivation contact layer is disposed on at least one surface of the semiconductor substrate; The passivation contact layer includes a plurality of first passivation contact portions arranged along a first direction; Multiple grooves are defined between each pair of adjacent first passivation contacts; in the thickness direction of the semiconductor substrate, the ratio of the area of ​​the passivation contact layer to the sum of the areas of all the grooves is between 0.2 and 2.

4.

35. The solar cell according to claim 34, characterized in that, The passivation contact layer accounts for 20% to 70% of the area of ​​one side surface of the semiconductor substrate.

36. The solar cell according to claim 34 or 35, characterized in that, The solar cell further includes a plurality of first grid lines, which are arranged along the first direction; the first grid lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate; In particular, at least a portion of the first passivated contacts have multiple first gate lines on the side facing away from the semiconductor substrate.

37. The solar cell according to claim 36, characterized in that, The plurality of first passivated contact portions include at least one first passivated contact sub-port and at least one second passivated contact portion; The first passivated contact portion has a first gate line on the side opposite to the semiconductor substrate, where a ≥ 1; The second passivated contact portion has b first gate lines on the side opposite to the semiconductor substrate; b; where b > a, and a and b are both positive integers.

38. The solar cell according to claim 37, characterized in that, In the thickness direction of the semiconductor substrate, the area of ​​the first passivation contact portion is smaller than the area of ​​the second passivation contact portion; And / or, the area of ​​all the second passivated contact portions on one side surface of the semiconductor substrate is between 10% and 35%.

39. The solar cell according to claim 34 or 35, characterized in that, The passivation contact layer further includes a second passivation contact portion; the second passivation contact portion is located on at least one side of the plurality of first passivation contact portions along a second direction, and is connected to all of the plurality of first passivation contact portions; the second direction intersects with the first direction.

40. The solar cell according to claim 39, characterized in that, The solar cell further includes a plurality of first grid lines, which are arranged along the first direction; the first grid lines are disposed on the side of the corresponding first passivation contact portion away from the semiconductor substrate and the side of the corresponding second passivation contact portion away from the semiconductor substrate.

41. The solar cell according to claim 40, characterized in that, The first passivated contact portion has at least one first gate line on the side opposite to the semiconductor substrate; And / or, the dimension of each of the first passivated contact portions along the first direction is W, and the dimension of the first gate line along the first direction is S, where W: S > 1; And / or, the number of the first gate lines is greater than or equal to the number of the first passivated contacts.

42. A photovoltaic module, characterized in that, Including the solar cell according to any one of claims 1 to 41.

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