Wafer-level semiconductor color display integrated chip, its fabrication method and application

Abstract

This application discloses a wafer-level semiconductor color display integrated chip, its fabrication method, and its application. The integrated chip includes a wafer-level driving carrier, full-color light-emitting units, an insulating dielectric layer, and an electrical connection structure with thermal conductivity. The driving carrier includes multiple independent driving units, and each full-color light-emitting unit includes multiple sub-pixels. Each sub-pixel includes at least three light-emitting units of different colors stacked sequentially. Each driving unit drives a corresponding light-emitting unit. The insulating dielectric layer is distributed between the driving carrier and the full-color light-emitting units, as well as between different semiconductor light-emitting layers within the full-color light-emitting units. The electrical connection structure connects each light-emitting unit to its corresponding driving unit and forms a thermally conductive path to accelerate heat exchange between the integrated chip and the external environment. This application can achieve pixel colorization of micro-LED arrays with direct emission of different colors from inorganic semiconductors, and improve their light extraction efficiency, resolution, and operational stability.

Description

Technical Field

[0001] This application relates to a semiconductor display device, specifically to a wafer-level semiconductor color display integrated chip, its fabrication method, and its application, belonging to the field of optoelectronic technology. Background Technology

[0002] With the rapid development of display technology, various display devices such as televisions, tablets, smartphones, augmented reality (AR) and virtual reality (VR) have led to a geometric increase in the amount of information humans can obtain through vision. This has further spurred and promoted the development of new display technologies such as organic light-emitting diode (OLED) display technology and Micro-LED display technology.

[0003] OLED display technology requires no backlight, is self-emissive, and boasts higher color saturation and a wider color gamut, while also offering the advantage of flexible display. However, if Micro-OLED is used to integrate and fabricate a display, the inherent disadvantages of OLED materials lead to defects such as screen burn-in, insufficient brightness, and eye fatigue.

[0004] Micro-LED display technology uses micron-sized LEDs as pixels, featuring high brightness, high contrast, and long lifespan. Micro-LED display pixels, based on inorganic semiconductor gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP) multi-component compound materials, offer advantages such as high brightness, high contrast, fast response time, long lifespan, and low power consumption. They do not suffer from the inherent drawbacks of OLED materials and may replace OLED as the new mainstream technology in the future.

[0005] Micro-LED displays typically consist of two parts: Micro-LED light-emitting pixels and a driver. The underlying driver is an LED display driver circuit manufactured using silicon (Si) CMOS integrated circuit technology. Then, the chips of the Micro-LED array are connected to the Si CMOS circuit through different integration processes, thereby realizing a Micro-LED display screen that can independently control the brightness of each pixel.

[0006] For applications such as AR / VR, colorization is essential for display chips. However, on the one hand, it is currently impossible to obtain inorganic semiconductor materials of different systems and structures simultaneously on the same substrate, which fundamentally limits the development of color display chips. On the other hand, full-colorization is a key challenge in Micro-LED display chip technology, but the three existing solutions for achieving full-colorization in Micro-LED—mass transfer technology, three-color combining technology, and monolithic full-color technology—all have some shortcomings.

[0007] Specifically, mass transfer technology involves manufacturing multiple colors of Micro-LED devices separately and then physically transferring them onto a single panel to create a full-color display. This method is limited by critical dimensions, making it difficult to produce microdisplays with high pixel density and high resolution. Furthermore, the transfer process is complex, requires high-precision equipment, has high manufacturing costs, and low yield.

[0008] Three-color combining technology uses semiconductor processes to manufacture red, green, and blue monochrome Micro-LED arrays separately, and then splices them together using optical prisms to form a full-color micro-display. This method requires extremely high alignment precision, resulting in low production efficiency and high cost. Furthermore, light loss from optical prisms and other optical components is significant, leading to a decrease in display brightness and efficiency.

[0009] Single-chip full-color technology utilizes blue or ultraviolet Micro-LEDs combined with quantum dot color conversion materials to convert blue or ultraviolet light into red, green, and blue light, thus achieving Micro-LED colorization. Displays based on quantum dot technology are expensive. This is because quantum dots are much smaller than liquid crystal molecules, requiring specialized production equipment and processing techniques for manufacturing. The complex processes and materials lead to higher costs. Furthermore, quantum dot materials are prone to degradation or thermalization when exposed to light and heat for extended periods, resulting in decreased display quality and reduced display lifespan. In addition, although quantum dot display technology offers excellent color reproduction, the differences in color reproduction mechanisms between quantum dot materials and liquid crystal displays result in high calibration costs. Particularly in the control of extremely small Micro-LEDs, further improvements are needed to precisely control color reproduction, but current technology cannot yet achieve this. Summary of the Invention

[0010] The purpose of this application is to provide a wafer-level semiconductor color display integrated chip, its fabrication method, and its application, in order to overcome the shortcomings of the prior art.

[0011] To achieve the aforementioned objectives, the technical solution adopted in this application includes:

[0012] The first aspect of this application provides a wafer-level semiconductor color display integrated chip, comprising:

[0013] A wafer-level driving carrier includes multiple independent driving units arranged in an array along a first direction. Each driving unit has a first driving electrode and a second driving electrode and is used to drive a corresponding light-emitting unit.

[0014] A full-color light-emitting unit is disposed on the wafer-level driving carrier and includes a plurality of sub-pixels arranged in an array along a first direction. Each sub-pixel includes at least three light-emitting units with different emission wavelengths stacked along a second direction. A plurality of light-emitting units with the same emission wavelength are arranged in an array along the first direction within the same semiconductor light-emitting layer. Each light-emitting unit has a first working electrode and a second working electrode. The second direction is perpendicular to the first direction.

[0015] An insulating dielectric layer is at least distributed between the wafer-level driving carrier and the full-color light-emitting unit, and between different semiconductor light-emitting layers in the full-color light-emitting unit;

[0016] An electrical connection structure with thermal conductivity includes a first conductive structure and a second conductive structure. The first conductive structure is used to electrically connect the first driving electrodes of the plurality of driving units and the first working electrodes of the plurality of light-emitting units. The second conductive structure is used to electrically connect the second driving electrode of each driving unit to the second working electrode of a corresponding light-emitting unit. Both the first conductive structure and the second conductive structure include a through-hole structure disposed in the insulating dielectric layer and a thermally and electrically conductive material filled in the through-hole structure. At least the first conductive structure is partially exposed on the surface of the chip to exchange heat with the outside.

[0017] In one embodiment, the semiconductor light-emitting layer includes a wafer-level semiconductor structure layer, in which a plurality of light-emitting functional units are formed in an array arranged along a first direction and electrically isolated from each other. Each light-emitting functional unit is electrically coupled to a first working electrode and a second working electrode to form a light-emitting unit. The wafer-level semiconductor structure layer includes a first semiconductor conductive layer, an active layer and a second semiconductor conductive layer arranged sequentially along a second direction. The first semiconductor conductive layer and the second semiconductor conductive layer have different conductivity types, namely n-type or p-type.

[0018] In this process, multiple light-emitting functional units within the wafer-level semiconductor structure layer can be electrically isolated through methods such as ion implantation and mesa etching.

[0019] Preferably, electrical isolation between adjacent light-emitting functional units can be achieved by etching annular grooves between them. An optical isolation structure is formed by filling the annular grooves with light-blocking materials such as black or white resin or reflective materials, thereby eliminating optical crosstalk between multiple light-emitting units within the same semiconductor light-emitting layer. Furthermore, diamond nanoparticles can be incorporated into the aforementioned light-blocking or reflective materials to better meet the requirements for preventing optical crosstalk and improving thermal conductivity.

[0020] In one embodiment, the first conductive structure includes:

[0021] The first conductive via structure includes a first through hole extending along a second direction and a thermally and electrically conductive material filled in the first through hole. The first through hole continuously penetrates the insulating dielectric layer and the plurality of semiconductor light-emitting layers, and its top end is exposed on the chip surface.

[0022] The first conductive wiring is used at least to electrically connect the first driving electrodes of the plurality of driving units together and then to electrically connect them to the first conductive via structure.

[0023] The second conductive wiring is used at least to electrically connect the first working electrodes of the plurality of light-emitting units in each of the semiconductor light-emitting layers together and then electrically connect them to the first conductive via structure.

[0024] Preferably, the first conductive via structure is a cylindrical structure with openings at both ends, and is arranged around multiple sub-pixels within the full-color light-emitting unit. The inner wall of the cylindrical structure is formed as a light-reflecting surface to reduce side light emission from the full-color light-emitting unit and improve its quantum efficiency.

[0025] In some cases, the wall thickness of the cylindrical structure can gradually decrease along the direction away from the wafer-level driving carrier, so that the heat inside the integrated chip can be quickly transferred to the outside, and the temperature at different depths inside the integrated chip can be made uniform. This not only ensures its working performance, especially the stability of long-term operation, but also makes the light-emitting units at different positions inside the integrated chip exhibit basically consistent working performance, thereby achieving a better display effect.

[0026] In one embodiment, the first conductive wiring includes a thermally and electrically conductive line that extends continuously along a first direction and is disposed between the wafer-level driving carrier and the full-color light-emitting unit.

[0027] Furthermore, the cross-sectional area of ​​the first conductive wiring in the first direction is preferably 30% or more of the area of ​​the first cross-section, more preferably 40% or more, and particularly preferably 50% to 60%. Also, the cross-sectional area of ​​the first conductive wiring in the second direction is preferably 5% or more of the area of ​​the second cross-section, more preferably 15% or more, and particularly preferably 20% to 50%. Wherein, the first cross-section is the radial cross-section of the integrated chip, and the second cross-section is the cross-section of the portion of the integrated chip located between the wafer-level driving carrier and the full-color light-emitting unit along the axial direction of the integrated chip. This design not only achieves faster current transmission efficiency and improves the control speed of the integrated chip, but also facilitates faster collection and transfer of heat inside the integrated chip. In addition, a reflective structure can be formed on the back side of the full-color light-emitting unit, further improving the front light emission of the full-color light-emitting unit and increasing its display brightness.

[0028] Furthermore, the periphery of the first conductive wiring is connected to the first conductive via structure to further improve the heat transfer efficiency between the two and form a barrel-shaped protective structure to provide better protection for the full-color light-emitting unit.

[0029] Furthermore, the first conductive wiring may have a mesh structure, a grid structure, or other similar structures, and is not limited to these.

[0030] In one embodiment, the second conductive wiring includes a non-transparent conductive line and a transparent conductive material. The non-transparent conductive line is continuously arranged on the light-emitting surface of the semiconductor light-emitting layer and divides the light-emitting surface of the semiconductor light-emitting layer into a plurality of patterned transparent regions. The patterned transparent regions are covered with the transparent conductive material. The transparent conductive material is electrically contacted with the first working electrode of a plurality of light-emitting units in the semiconductor light-emitting layer and the non-transparent conductive line, and is electrically connected to the first conductive via structure through the non-transparent conductive line. Each patterned transparent region corresponds to a pixel unit, and each pixel unit includes at least three sub-pixels.

[0031] The light-emitting surface of the semiconductor light-emitting layer is the side of the semiconductor light-emitting layer that is away from the wafer-level driving carrier.

[0032] Furthermore, by adjusting the wire diameter and thickness of the non-transparent conductive lines, a light-blocking structure can be formed to reduce light crosstalk between adjacent pixel units. Combined with the aforementioned light isolation structure, this further enhances the display resolution of the integrated chip.

[0033] Furthermore, the non-transparent conductive circuit is preferably formed of metals with high thermal and electrical conductivity such as Ag and Cu, and is more preferably a grid structure formed by connecting metal wires and metal strips. The transparent conductive material can be formed of transparent conductive materials such as ITO, AZO, carbon nanotube film, and graphene film, and is particularly preferred to be formed of materials with high light transmittance, high thermal conductivity, and high electrical conductivity such as carbon nanotube film and graphene film.

[0034] Furthermore, the shape of the patterned light-transmitting area can be a regular or irregular geometric shape such as a rhombus, rectangle, hexagon, circle, or ellipse.

[0035] In one embodiment, there are multiple second conductive structures, each of which includes a second through-hole extending along a second direction and a thermally and electrically conductive material filled in the second through-hole. A portion of the second through-hole is distributed between the full-color light-emitting unit and the wafer-level driving carrier, while another portion of the second through-hole continuously penetrates one or more of the semiconductor light-emitting layers.

[0036] In one embodiment, the driving unit includes a CMOS driving unit, such as a Si-based CMOS driving unit.

[0037] In one embodiment, the driving unit has a size of 100nm-10μm, a driving current of 0.01μA-10A, and a carrier mobility of 1cm. 2 / V·s-1000cm 2 / V·s.

[0038] In one embodiment, the pixel unit includes a red light emitting unit, a green light emitting unit, and a blue light emitting unit arranged sequentially along a direction away from the wafer-level driving carrier. This arrangement is because red light has a long wavelength, easily passing through green and blue light emitting materials, reducing light loss; green light also has high transmittance in blue light emitting materials, resulting in low light loss; while blue light has a short wavelength, making it difficult to pass through green and blue light emitting materials, leading to high light loss.

[0039] In one embodiment, the light-emitting unit is an inorganic light-emitting unit, wherein the inorganic semiconductor material includes III-V compounds, such as group III nitrides like GaN, InGaN, and AlInGaN, or group III phosphides or group III arsenides like AlGaInP. Compared to organic light-emitting units such as OLEDs, light-emitting units based on all-inorganic materials have advantages such as high luminous brightness, low power consumption, long lifespan, and radiation resistance.

[0040] In one embodiment, the light-emitting unit is a vertical light-emitting unit, with a first working electrode and a second working electrode distributed along a second direction on both sides of the light-emitting unit. Specifically, the first working electrode is distributed on the surface of the light-emitting unit away from the wafer-level driving carrier, i.e., its light-emitting surface. Using this vertical light-emitting unit effectively utilizes the area of ​​the light-emitting chip and improves the utilization rate of the light-emitting material.

[0041] In one embodiment, the light-emitting unit includes a micro-LED light-emitting unit such as a Micro-LED or a vertical cavity semiconductor laser light-emitting unit.

[0042] Furthermore, the size of the light-emitting unit can be 1-10 μm. The spacing between adjacent light-emitting units in the same light-emitting semiconductor layer can be 1-10 μm.

[0043] In one embodiment, the thermally and electrically conductive material includes a metallic material or a combination of a metallic material and a non-metallic material, wherein the metallic material includes Cu or Ag, and the non-metallic material includes carbon nanotubes or diamond nanoparticles, etc.

[0044] For example, the thermally and electrically conductive material can be selected from copper (Cu), silver (Ag) nanowires, or Ag paste. More preferably, the thermally and electrically conductive material can be Ag paste doped with carbon nanotubes or diamond nanoparticles, which not only has high electrical conductivity but also low thermal resistance.

[0045] In one embodiment, an integrated microlens is further disposed on the light emitting surface of at least one light-emitting unit within the pixel unit.

[0046] Preferably, each of the light-emitting units has an integrated microlens disposed on its light-emitting surface. This facilitates better vertical emission of the light emitted by the light-emitting unit, thereby increasing its emitted light intensity. The microlens can be formed by directly processing the light-emitting surface of the semiconductor light-emitting layer, or by depositing a transparent resin on the light-emitting surface of the semiconductor light-emitting layer and then processing it.

[0047] In one embodiment, the insulating dielectric layer may be selected from, but is not limited to, high-k insulating dielectric layers that are transparent to visible light, such as silicon oxide, silicon nitride, or hafnium oxide.

[0048] A second aspect of this application provides a method for fabricating the wafer-level semiconductor color display integrated chip, comprising:

[0049] A first insulating dielectric layer is formed on a wafer-level driving carrier, and a first conductive wiring is arranged within the first insulating dielectric layer so that the first driving electrodes of multiple independent driving units are electrically connected through the first conductive wiring. Multiple second through-holes penetrating the first insulating dielectric layer along a second direction are also fabricated within the first insulating dielectric layer, and thermally and electrically conductive materials are filled into the second through-holes to form multiple second conductive structures. The bottom end of each second conductive structure is electrically connected to the second driving electrode of a corresponding driving unit.

[0050] Multiple semiconductor light-emitting layers and multiple second insulating dielectric layers are alternately stacked on the first insulating dielectric layer to form a stacked structure of semiconductor light-emitting layers and insulating dielectric layers. A second conductive wiring is provided on the light-emitting surface of each semiconductor light-emitting layer so that the first working electrodes of multiple light-emitting units in each semiconductor light-emitting layer are electrically connected through the second conductive wiring. Multiple deep holes extending in a second direction are processed in the stacked structure. Each deep hole continuously penetrates at least one semiconductor light-emitting layer or at least one semiconductor light-emitting layer and at least one second insulating dielectric layer and then seamlessly connects to a corresponding second through hole, thereby forming multiple extended second through holes. Each deep hole is filled with a thermally and electrically conductive material so that part of the second conductive structure is extended and the top end of each second conductive structure is electrically connected to the second working electrode of the corresponding light-emitting unit.

[0051] In addition, a first through hole is fabricated to continuously penetrate the stacked structure along the second direction, and a thermally and electrically conductive material is filled in the first through hole to form a first conductive via structure, and the first conductive via structure is electrically connected to the first conductive wiring and the second conductive wiring, with the top end of the first conductive via structure exposed on the chip surface.

[0052] In one embodiment, the preparation method specifically includes:

[0053] A first sub-insulating dielectric layer is formed on a wafer-level driving carrier, and a groove is formed on the surface of the first sub-insulating dielectric layer. The groove is filled with a thermally and electrically conductive material to form the first conductive wiring.

[0054] A second sub-insulating dielectric layer is formed on the first sub-insulating dielectric layer, thereby forming the first insulating dielectric layer. A plurality of second through holes arranged in an array are processed from the surface of the second sub-insulating dielectric layer, and thermally and electrically conductive materials are filled in the second through holes to form a plurality of second conductive structures.

[0055] In one embodiment, the preparation method specifically includes:

[0056] A first semiconductor light-emitting layer, a second semiconductor light-emitting layer, and a third semiconductor light-emitting layer are provided respectively. The first semiconductor light-emitting layer includes a plurality of first light-emitting units arranged in an array along a first direction. The second semiconductor light-emitting layer includes a plurality of second light-emitting units arranged in an array along the first direction. The third semiconductor light-emitting layer includes a plurality of third light-emitting units arranged in an array along the first direction.

[0057] The first semiconductor light-emitting layer is disposed on the first insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each first light-emitting unit to the second driving electrode of the corresponding driving unit through a corresponding second conductive structure. Then, a second conductive wiring is disposed on the first semiconductor light-emitting layer to electrically connect the first working electrodes of multiple first light-emitting units in the first semiconductor light-emitting layer. After that, a second insulating dielectric layer is formed on the first semiconductor light-emitting layer.

[0058] Multiple first deep holes are fabricated in an array on the surface of the second insulating dielectric layer. Each first deep hole continuously penetrates the second insulating dielectric layer and the first semiconductor light-emitting layer and is seamlessly connected to a corresponding second through hole. Then, thermally and electrically conductive material is filled into the first deep holes to form multiple first-elongated second conductive structures. The second semiconductor light-emitting layer is then placed on the second insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each second light-emitting unit to the second driving electrode of the corresponding driving unit through the corresponding first-elongated second conductive structure. Then, another second conductive wiring is formed on the second semiconductor light-emitting layer to electrically connect the first working electrodes of the multiple second light-emitting units in the second semiconductor light-emitting layer. Finally, another second insulating dielectric layer is formed on the second semiconductor light-emitting layer.

[0059] Multiple second deep holes are fabricated on the surface of the other second insulating dielectric layer. Each second deep hole continuously penetrates the other second insulating dielectric layer and the second semiconductor light-emitting layer and is seamlessly connected to a corresponding first deep hole. Then, thermally and electrically conductive material is filled into the second deep holes to form multiple secondary extended second conductive structures. The third semiconductor light-emitting layer is then disposed on the other second insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each third light-emitting unit to the second driving electrode of the corresponding driving unit through the corresponding secondary extended second conductive structure, thereby forming the stacked structure. Then, another second conductive wiring is disposed on the third semiconductor light-emitting layer to electrically connect the first working electrodes of the multiple third light-emitting units in the third semiconductor light-emitting layer.

[0060] The first conductive via structure is then fabricated within the stacked structure, and the first conductive via structure is electrically connected to the first conductive wiring and the plurality of second conductive wirings.

[0061] In some cases, a set of second vias, the same number as the number of second working electrodes of all the first light-emitting units in the first semiconductor light-emitting layer, can be fabricated on the first insulating dielectric layer. These second vias are then filled with thermally and electrically conductive material to form a set of second conductive structures. These second conductive structures are used to electrically connect the second working electrodes of each first light-emitting unit in the first semiconductor light-emitting layer to the second driving electrodes of the corresponding driving units. Subsequently, a set of first-lengthened second vias, the same number as the number of second working electrodes of all the second light-emitting units in the second semiconductor light-emitting layer, are fabricated on the second insulating dielectric layer, continuously penetrating the second insulating dielectric layer, the first light-emitting semiconductor layer, and the first insulating dielectric layer. These first-lengthened second vias are then filled with thermally and electrically conductive material to form a set of first-lengthened second conductive structures. These first-lengthened second conductive structures are used to electrically connect the second working electrodes of each second light-emitting unit in the second semiconductor light-emitting layer to the second driving electrodes of the corresponding driving units. Subsequently, a set of secondary elongated second vias, the same number as the number of second working electrodes of all the third light-emitting units in the third semiconductor light-emitting layer, are continuously formed on the other second insulating dielectric layer, penetrating the two second insulating dielectric layers, the first light-emitting semiconductor layer, and the first insulating dielectric layer. These secondary elongated second vias are filled with thermally and electrically conductive material to form a set of secondary extended second conductive structures. These secondary extended second conductive structures are then used to electrically connect the second working electrodes of each third light-emitting unit in the third semiconductor light-emitting layer to the second driving electrodes of the corresponding driving units. However, this approach is relatively difficult to implement.

[0062] In one embodiment, the preparation method specifically includes:

[0063] A plurality of first working electrodes and a plurality of second working electrodes are respectively disposed on a first surface and a second surface of the semiconductor light-emitting layer, wherein the first surface is opposite to the second surface, and the first surface is the light-emitting surface and is away from the wafer-level driving carrier.

[0064] Non-transparent conductive lines are continuously arranged on the first surface of the semiconductor light-emitting layer to divide the first surface into multiple patterned transparent areas, and each patterned transparent area corresponds to a pixel unit, each pixel unit including at least three sub-pixels. A transparent conductive material is coated on the patterned transparent area, and the transparent conductive material is electrically contacted with the first working electrode of the multiple light-emitting units in the semiconductor light-emitting layer and the non-transparent conductive lines, thereby forming the second conductive wiring.

[0065] In one embodiment, the fabrication method specifically includes: setting an integrated microlens on the light-emitting surface of the semiconductor light-emitting layer, wherein each microlens corresponds to at least one sub-pixel.

[0066] In one embodiment, the preparation method specifically includes: using the first insulating dielectric layer as a bonding layer to bond the wafer-level driving carrier to an adjacent semiconductor light-emitting layer.

[0067] In one embodiment, the preparation method specifically includes: using the second insulating dielectric layer as a bonding layer to bond two adjacent semiconductor light-emitting layers together.

[0068] The bonding can be achieved using equipment such as a wafer bonding machine.

[0069] The third aspect of this application provides the application of the wafer-level semiconductor color display integrated chip in the fabrication of display devices, particularly in full-color display devices.

[0070] Furthermore, the application of the wafer-level semiconductor color display integrated chip is not limited to the field of micro-displays, but also has significant application value in fields such as projection indicators, cursor prompts, outdoor projection, and intelligent automotive headlights.

[0071] Compared with the prior art, the advantages of this application include:

[0072] (1) A solution for full-color display of small-pitch micro-pixels is provided, which effectively breaks through the technical bottlenecks of mass transfer and quantum dot color conversion. It can realize pixel colorization of Micro-LED arrays with direct light emission of all inorganic semiconductors of different colors, and obtain a full-color integrated display chip. The full-color integrated display chip has the advantages of large size, high resolution, high luminous brightness, high working stability, low power consumption, long life and radiation resistance.

[0073] (2) The method for preparing a full-color integrated display chip is compatible with standard semiconductor processes, has the capability for large-size, wafer-level mass production, and can achieve low-cost manufacturing. Attached Figure Description

[0074] Figure 1 This is a schematic diagram of the axial cross-sectional structure of a wafer-level semiconductor color display integrated chip according to an embodiment of this application;

[0075] Figure 2 This is a top view of a wafer-level semiconductor color display integrated chip according to an embodiment of this application;

[0076] Figure 3 This is a cross-sectional structural schematic diagram of a first insulating dielectric layer with a built-in second conductive structure in one embodiment of this application;

[0077] Figure 4This is a schematic diagram of an inorganic semiconductor light-emitting layer integrated with a wafer-level Si-based CMOS driving substrate in one embodiment of this application. Detailed Implementation

[0078] The technical solution, implementation process, and principles of this application will be further explained below with reference to the accompanying drawings and embodiments.

[0079] Please see Figures 1-3 The wafer-level semiconductor color display integrated chip provided in this embodiment includes:

[0080] The wafer-level Si-based CMOS driving substrate, which serves as the wafer-level driving carrier 1, is fabricated on a high-quality Si wafer and includes multiple CMOS driving units arranged in an array along a direction parallel to the surface of the driving substrate (i.e., the first direction). The CMOS driving units are characterized by having extremely small size, high driving current and carrier mobility. Each driving unit has a first driving electrode and a second driving electrode (not shown in the figure, which can be an n-type electrode and a p-type electrode, respectively) and is used to drive a corresponding Micro-LED unit.

[0081] A full-color light-emitting unit 2 is disposed on the wafer-level driving carrier 1 and includes multiple sub-pixels arranged in an array along a first direction. Each sub-pixel includes red, green, and blue Micro-LED units stacked sequentially along a direction perpendicular to the surface of the driving substrate (i.e., the second direction). Multiple red LED units are arranged in an array along the first direction within a red light-emitting semiconductor layer 21, multiple green LED units are arranged in an array along the first direction within a green light-emitting semiconductor layer 22, and multiple blue LED units are arranged in an array along the first direction within a blue light-emitting semiconductor layer 23. Each Micro-LED unit is a vertical light-emitting unit, and it has a first working electrode and a second working electrode on its two sides in the second direction, respectively. The first working electrode is disposed on the side (i.e., the light emitting surface) of each Micro-LED unit away from the wafer-level driving carrier 1. For example, the first working electrode and the second working electrode are n-electrode and p-electrode, respectively. The red light-emitting LED unit can be InGaN / GaN-based or AlGaInP-based, and the green and blue light-emitting LED units can be GaN-based.

[0082] The insulating dielectric layer includes a first insulating dielectric layer 31 disposed between the wafer-level driving carrier 1 and the full-color light-emitting unit 2 and a plurality of second insulating dielectric layers 32 disposed between different semiconductor light-emitting layers. These insulating dielectric layers have low surface roughness and can be directly used as bonding layers between the wafer-level driving carrier 1 and the red light semiconductor light-emitting layer 21, as well as bonding layers between two adjacent semiconductor light-emitting layers.

[0083] An electrical connection structure with thermal conductivity includes a first conductive structure 41 and a second conductive structure 42.

[0084] The first conductive structure includes:

[0085] The first conductive via structure 411 includes a first through hole extending along the second direction and a thermally and electrically conductive material such as Ag paste or silver paste doped with carbon nanotubes or diamond particles filled in the first through hole. The first through hole continuously penetrates the above-mentioned insulating dielectric layer and multiple semiconductor light-emitting layers, and its top end is exposed on the surface of the integrated chip.

[0086] The first conductive wiring (not shown in the figure) is used to electrically connect the first driving electrodes of the multiple driving units together and then electrically connect them to the first conductive via structure 411.

[0087] The second conductive wiring includes a non-transparent conductive line 4121 and a transparent conductive material 4122. The non-transparent conductive line has a grid structure and is continuously arranged on the light-emitting surface of each semiconductor light-emitting layer, dividing the light-emitting surface of the semiconductor light-emitting layer into multiple patterned transparent areas (e.g., ...). Figure 2 The patterned light-transmitting area (shown as a rhombus shape) is covered with a light-transmitting conductive material. This material is electrically contacted with the first working electrodes of multiple light-emitting units within the semiconductor light-emitting layer and with the non-light-transmitting conductive lines. It is also electrically connected to the first conductive via structure 411 via the non-light-transmitting conductive lines 4122. Each patterned light-transmitting area corresponds to a pixel unit, and each pixel unit includes at least three sub-pixels. For example, the non-light-transmitting conductive lines 4121 are preferably formed of metals such as Ag or Cu, and the light-transmitting conductive material is preferably a carbon nanotube film or a graphene film. Furthermore, the non-light-transmitting conductive lines also serve as light-blocking structures between adjacent pixel units to reduce optical crosstalk between them.

[0088] Furthermore, the aforementioned first conductive via structure 411 is a cylindrical structure with openings at both ends, which surrounds multiple sub-pixels within the full-color light-emitting unit 2, and its inner wall is formed as a light-reflecting surface. Simultaneously, the wall thickness of this cylindrical structure can gradually decrease along the direction away from the wafer-level driving carrier.

[0089] Furthermore, the aforementioned first conductive wiring includes a thermally and electrically conductive line extending continuously along a first direction, having a mesh-like or grid-like structure, and disposed between the wafer-level driving carrier 1 and the full-color light-emitting unit 2. For example, the cross-sectional area of ​​the first conductive wiring in the first direction is approximately 50% of the first cross-sectional area, and the cross-sectional area in the second direction is approximately 30% of the second cross-sectional area. The first cross-section is the radial cross-section of the integrated chip, and the second cross-section is the cross-section of the portion of the integrated chip located between the wafer-level driving carrier 1 and the full-color light-emitting unit 2 along the axial direction of the integrated chip. More preferably, the wire diameter of the aforementioned first conductive wiring is 1 μm or more, which not only has low resistance but also high thermal conductivity. Simultaneously, the periphery of the first conductive wiring is integrally connected to the first conductive via structure.

[0090] Each second conductive structure 42 is used to electrically connect the second driving electrode of each driving unit to the second working electrode of a corresponding light-emitting unit.

[0091] Furthermore, there are multiple second conductive structures 42, each including a second through-hole extending along a second direction and a thermally and electrically conductive material filling the through-hole. A portion of the second through-holes is distributed between the full-color light-emitting unit 2 and the wafer-level driving carrier 1, while another portion of the second through-holes continuously penetrates one or more semiconductor light-emitting layers. For example, please refer to [reference needed]. Figure 3 A portion of the second conductive structure 42 is distributed between the full-color light-emitting unit 2 and the wafer-level driving carrier 1, and includes multiple second through holes 421 opened in the first insulating dielectric layer 31 and thermally and electrically conductive materials such as Ag paste or silver paste doped with carbon nanotubes or diamond particles filled in the second through holes 421. It can not only reduce the internal series resistance of the chip when it is working, but also facilitate the rapid transfer of heat inside the chip and avoid local high temperature.

[0092] Furthermore, an integrated microlens (not shown in the figure) can be disposed on the light emitting surface of the aforementioned light-emitting unit. This facilitates better vertical emission of the light emitted by the light-emitting unit, thereby increasing its emitted light intensity.

[0093] Furthermore, the aforementioned semiconductor light-emitting layer can all include a wafer-level semiconductor structure layer. Each wafer-level semiconductor structure layer includes a first semiconductor conductive layer, an active layer, and a second semiconductor conductive layer sequentially disposed along the second direction. The first semiconductor conductive layer and the second semiconductor conductive layer have different conductivity types, namely n-type or p-type. For an example, please refer again. Figure 1The red semiconductor layer 21 includes a p-type semiconductor conductive layer 211, a quantum well active layer 212, and an n-type semiconductor conductive layer 213 sequentially disposed along the direction away from the wafer-level driving carrier 1. The green semiconductor layer 22 includes a p-type semiconductor conductive layer 221, a quantum well active layer 222, and an n-type semiconductor conductive layer 223 sequentially disposed along the direction away from the wafer-level driving carrier 1. The blue semiconductor layer 23 includes a p-type semiconductor conductive layer 231, a quantum well active layer 232, and an n-type semiconductor conductive layer 233 sequentially disposed along the direction away from the wafer-level driving carrier 1.

[0094] Each wafer-level semiconductor structure layer contains multiple light-emitting functional units arranged in an array along a first direction and electrically isolated from each other. Each light-emitting functional unit is electrically bonded to an n-electrode and a p-electrode, thereby forming a light-emitting unit. For example, for the red light semiconductor layer 21, the quantum well active layer 212 and the n-type semiconductor conductive layer 213 can be etched until the p-type semiconductor conductive layer 231 is exposed, forming a groove structure between adjacent red light LED units, so that adjacent red light LED units are electrically isolated from each other. Then, black matrix material or white wall adhesive can be filled in these groove structures to form an optical isolation structure, avoiding optical crosstalk between adjacent red light LED units.

[0095] This embodiment provides a method for fabricating the above-mentioned wafer-level semiconductor color display integrated chip, which includes the following steps:

[0096] S1, in wafer-level driving carrier 1 (i.e. Figure 4 An insulating dielectric is deposited on the surface of a Si CMOS chip to form a first sub-insulating dielectric layer. A first conductive wiring is then formed on the surface of this first sub-insulating dielectric layer to connect the first driving electrodes (preferably n-type electrodes) of each driving unit. Furthermore, during wiring, slots need to be cut on the surface of the first sub-insulating dielectric layer, and the cross-sectional area of ​​the first conductive wiring in both the first and second directions should meet the requirements described above. This not only reduces the series resistance during chip operation but also allows for more rapid heat dissipation from the chip's interior through the first conductive wiring.

[0097] S2. After the first conductive wiring is fabricated, the surface of the first sub-insulating dielectric layer is polished to a smooth surface using grinding and polishing processes, while retaining the thermally and electrically conductive material in the groove.

[0098] S3. A second sub-insulating dielectric layer is deposited on the first sub-insulating dielectric layer to form the first insulating dielectric layer. Then, multiple arrayed second through holes are formed on the surface of the first insulating dielectric layer using photolithography, etching and other processes. Each second through hole is filled with Ag paste, Ag paste doped with carbon nanotubes or diamond nanoparticles, or Cu, etc., to ensure vertical conductivity and form a second conductive structure. Each second conductive structure is electrically connected to the second driving electrode (preferably p-type electrode) of a corresponding driving unit. These second conductive structures can be divided into two groups, a and b. Each second conductive structure in group a is also connected to the second working electrode (preferably p-electrode) of a corresponding red LED unit. Each second conductive structure in group b is used to connect to the p-electrode of the green LED unit and the blue LED unit, respectively.

[0099] S4. A Si-substrate red-light Micro-LED wafer is provided, comprising a Si substrate and multiple red-light LED units arrayed on the Si substrate. These red-light LED units are formed by multiple light-emitting functional units capable of independently emitting red light within a red-light semiconductor light-emitting layer. The active layer therein contains a GaN / InGaN quantum well structure, and this red-light semiconductor light-emitting layer can be grown on the Si substrate. The p-electrode of each red-light LED unit is independent. A hybrid alignment bonding process is then used, employing a first insulating dielectric layer as a bonding layer to bond and integrate the wafer-level driving carrier 1 and the Si-substrate red-light Micro-LED wafer, such that the p-electrode of each red-light LED unit is electrically connected to the p-type electrode of a corresponding driving unit through a second conductive structure in group a above.

[0100] S5. The Si substrate of the red-light Micro-LED wafer is removed using a wet etching process, and then the Aln / AlGaN buffer layer between the Si substrate and the n-type GaN is etched away using a dry etching process to expose the n(++)-GaN layer. (See [reference needed]) Figure 4 Then, microlenses are integrally formed on the surface of the n(++)-GaN layer through etching and other processes. Each microlens can correspond to a red LED unit to ensure that the red light can be emitted vertically and improve the emitted light intensity. Afterwards, ohmic contact electrodes are fabricated on the surface of the n(++)-GaN layer and rewiring is performed, i.e., a second conductive wiring is laid out to ensure that the red light emitted by the red LED unit can be emitted from the surface of the n-type n(++)-GaN layer.

[0101] S6. An insulating dielectric is deposited on the red light-emitting semiconductor layer to form a second insulating dielectric layer. Then, photolithography and etching are performed to form an array of multiple first deep holes on the surface of the second insulating dielectric layer. Each first deep hole is seamlessly connected to the corresponding second conductive structure in group b above. Then, Ag paste, Ag paste doped with carbon nanotubes or diamond nanoparticles, or Cu are filled into the first deep holes to ensure vertical conductivity, thereby forming multiple primary extended second conductive structures. These primary extended second conductive structures can be further divided into two groups, I and II. Each primary extended second conductive structure in group I will be used to connect to the p electrode of a corresponding green LED unit. The primary extended second conductive structures in group II will be used to connect to the p electrode of a blue LED unit.

[0102] S7. Provide a Si substrate green micro-LED wafer, which has a similar structure to a Si substrate red micro-LED wafer but uses a different material and includes multiple green LED units. Then, referring to the operations in steps S4-S5 above, use a second insulating dielectric layer to bond the Si substrate green micro-LED wafer to the red semiconductor light-emitting layer, and electrically connect the p electrode of each green LED unit to the p-type electrode of the corresponding driving unit through a corresponding first-extended second conductive structure in group I. Then, remove the Si substrate and buffer layer of the Si substrate green micro-LED wafer to expose the n(++)-GaN layer in the green semiconductor light-emitting layer. Subsequently, fabricate a microlens corresponding to each green LED unit on the green semiconductor light-emitting layer so that the green light can be emitted more vertically. Subsequently, an ohmic contact electrode was fabricated on the surface of the n(++)-GaN layer of the green light-emitting semiconductor layer, and the wiring was rewired, that is, a second conductive wiring was laid out again, to ensure that the red light emitted by the red LED unit and the green light emitted by the green LED unit can be emitted from the surface of the n-type n(++)-GaN layer of the green light-emitting semiconductor layer.

[0103] S8. Referring to the operation in step S6, an insulating medium is deposited on the green semiconductor light-emitting layer to form another second insulating medium layer. Then, photolithography and etching are performed to form an array of multiple second deep holes on the surface of the other second insulating medium layer. Each second deep hole is seamlessly connected to the corresponding first-extended second conductive structure in group II. Then, Ag paste, Ag paste doped with carbon nanotubes or diamond nanoparticles, or Cu are filled into the second deep holes to ensure vertical conductivity, thereby forming multiple second-extended second conductive structures. Each second-extended second conductive structure will be used to connect to the p electrode of a corresponding blue LED unit.

[0104] S9. Provide a Si substrate blue micro-LED wafer, which has a similar structure to a Si substrate red micro-LED wafer but uses a different material and includes multiple blue LED units. Then, referring to the operations in steps S4-S5 above, use another second insulating dielectric layer to bond the Si substrate blue micro-LED wafer to the green semiconductor light-emitting layer, and electrically connect the p electrode of each blue LED unit to the p-type electrode of a corresponding driving unit through a corresponding secondary extended second conductive structure. Then, remove the Si substrate and buffer layer of the Si substrate blue micro-LED wafer to expose the n(++)-GaN layer in the blue semiconductor light-emitting layer. Subsequently, fabricate a microlens corresponding to each blue LED unit on the blue semiconductor light-emitting layer to enable better vertical emission of blue light. Then, an ohmic contact electrode is fabricated on the surface of the n(++)-GaN layer of the blue light-emitting semiconductor layer, and the wiring is rewired, that is, a second conductive wiring is laid out again, to ensure that the red light emitted by the red LED unit, the green light emitted by the green LED unit, and the blue light emitted by the blue LED can all be emitted from the surface of the n-type n(++)-GaN layer of the blue light-emitting semiconductor layer.

[0105] S10. After the above steps, a full-color light-emitting unit can be obtained. Then, photolithography and etching are performed on the edge area of ​​the surface of the full-color light-emitting unit to form a first through hole that penetrates from the surface of the full-color light-emitting unit into the first insulating dielectric layer. The first through hole is filled with Ag paste, Ag paste doped with carbon nanotubes or diamond nanoparticles, or Cu, etc., to ensure vertical conductivity and form the first conductive via structure. This allows the first conductive wiring and the second conductive wiring to be electrically connected to the first conductive via structure.

[0106] It should be understood that the above embodiments are merely illustrative of the technical concept and features of this application, and are intended to enable those skilled in the art to understand the content of this application and implement it accordingly. They should not be construed as limiting the scope of protection of this application. All equivalent changes or modifications made in accordance with the spirit and essence of this application should be included within the scope of protection of this application.

Claims

1. A wafer-level semiconductor color display integrated chip, characterized in that, include: A wafer-level driving carrier includes multiple independent driving units arranged in an array along a first direction. Each driving unit has a first driving electrode and a second driving electrode and is used to drive a corresponding light-emitting unit. A full-color light-emitting unit is disposed on the wafer-level driving carrier and includes a plurality of sub-pixels arranged in an array along a first direction. Each sub-pixel includes at least three light-emitting units with different emission wavelengths stacked along a second direction. A plurality of light-emitting units with the same emission wavelength are arranged in an array along the first direction within the same semiconductor light-emitting layer. Each light-emitting unit has a first working electrode and a second working electrode. The second direction is perpendicular to the first direction. An insulating dielectric layer is at least distributed between the wafer-level driving carrier and the full-color light-emitting unit, and between different semiconductor light-emitting layers in the full-color light-emitting unit; An electrical connection structure with thermal conductivity includes a first conductive structure and a second conductive structure. The first conductive structure is used to electrically connect the first driving electrodes of the plurality of driving units and the first working electrodes of the plurality of light-emitting units. The second conductive structure is used to electrically connect the second driving electrode of each driving unit to the second working electrode of a corresponding light-emitting unit. Both the first conductive structure and the second conductive structure include a through-hole structure disposed in the insulating dielectric layer and a thermally and electrically conductive material filled in the through-hole structure. At least the first conductive structure is partially exposed on the surface of the chip to exchange heat with the outside.

2. The wafer-level semiconductor color display integrated chip according to claim 1, characterized in that: The semiconductor light-emitting layer includes a wafer-level semiconductor structure layer, in which a plurality of light-emitting functional units are formed in an array arranged along a first direction and electrically isolated from each other. Each light-emitting functional unit is electrically coupled to a first working electrode and a second working electrode to form a light-emitting unit. The wafer-level semiconductor structure layer includes a first semiconductor conductive layer, an active layer and a second semiconductor conductive layer arranged sequentially along a second direction. The first semiconductor conductive layer and the second semiconductor conductive layer have different conductivity types.

3. The wafer-level semiconductor color display integrated chip according to claim 1, characterized in that, The first conductive structure includes: The first conductive via structure includes a first through hole extending along a second direction and a thermally and electrically conductive material filled in the first through hole. The first through hole continuously penetrates the insulating dielectric layer and the plurality of semiconductor light-emitting layers, and its top end is exposed on the chip surface. The first conductive wiring is used at least to electrically connect the first driving electrodes of the plurality of driving units together and then to electrically connect them to the first conductive via structure. The second conductive wiring is used at least to electrically connect the first working electrodes of the plurality of light-emitting units in each semiconductor light-emitting layer together and then electrically connect them to the first conductive via structure. And / or, there are multiple second conductive structures, each of which includes a second through-hole extending along a second direction and a thermally and electrically conductive material filled in the second through-hole, and a portion of the second through-hole is distributed between the full-color light-emitting unit and the wafer-level driving carrier, while another portion of the second through-hole continuously penetrates one or more of the semiconductor light-emitting layers.

4. The wafer-level semiconductor color display integrated chip according to claim 3, characterized in that: The first conductive via structure is a cylindrical structure with openings at both ends, and is arranged around multiple sub-pixels within the full-color light-emitting unit, and the inner wall of the cylindrical structure is formed as a light-reflecting surface; And / or, the first conductive wiring includes a thermally and electrically conductive line that extends continuously along a first direction and is disposed between the wafer-level driving carrier and the full-color light-emitting unit; And / or, the second conductive wiring includes a non-transparent conductive line and a transparent conductive material. The non-transparent conductive line is continuously arranged on the light-emitting surface of the semiconductor light-emitting layer and divides the light-emitting surface of the semiconductor light-emitting layer into a plurality of patterned transparent areas. The patterned transparent areas are covered with the transparent conductive material. The transparent conductive material is electrically contacted with the first working electrode of a plurality of light-emitting units in the semiconductor light-emitting layer and the non-transparent conductive line, and is electrically connected to the first conductive via structure through the non-transparent conductive line. Each patterned transparent area corresponds to a pixel unit, and each pixel unit includes at least three sub-pixels.

5. The wafer-level semiconductor color display integrated chip according to claim 1, characterized in that: The driving unit includes a CMOS driving unit; and / or, the driving unit has a size of 100nm-10μm, a driving current of 0.01μA-10A, and a carrier mobility of 1cm⁻¹. 2 / V·s-1000cm 2 / V·s; And / or, the pixel unit includes a red light emitting unit, a green light emitting unit and a blue light emitting unit arranged sequentially along a direction away from the wafer-level driving carrier; And / or, the light-emitting unit is an inorganic light-emitting unit, wherein the inorganic semiconductor material includes III-V compounds; And / or, the light-emitting unit is a vertical light-emitting unit, wherein its first working electrode and second working electrode are distributed on both sides of the light-emitting unit along a second direction; And / or, the light-emitting unit includes a micro-LED light-emitting unit or a vertical-cavity semiconductor laser light-emitting unit; And / or, the size of the light-emitting unit is 1-10 μm; and / or, the spacing between adjacent light-emitting units in the light-emitting semiconductor layer is 1-10 μm; And / or, the thermally and electrically conductive material includes a metallic material or a combination of a metallic material and a non-metallic material, wherein the metallic material includes Cu or Ag, and the non-metallic material includes carbon nanotubes or diamond nanoparticles; And / or, at least one light-emitting unit within the pixel unit is further provided with an integrated microlens on its light-emitting surface.

6. The method for fabricating a wafer-level semiconductor color display integrated chip according to any one of claims 1-5, characterized in that, include: A first insulating dielectric layer is formed on a wafer-level driving carrier, and a first conductive wiring is arranged in the first insulating dielectric layer so that the first driving electrodes of multiple independent driving units are electrically connected through the first conductive wiring. A plurality of second through holes penetrating the first insulating dielectric layer along a second direction are processed in the first insulating dielectric layer, and thermally and electrically conductive materials are filled in the second through holes to form a plurality of second conductive structures. The bottom end of each second conductive structure is electrically connected to the second driving electrode of a corresponding driving unit. Multiple semiconductor light-emitting layers and multiple second insulating dielectric layers are alternately stacked on the first insulating dielectric layer to form a stacked structure of semiconductor light-emitting layers and insulating dielectric layers. A second conductive wiring is provided on the light-emitting surface of each semiconductor light-emitting layer so that the first working electrodes of multiple light-emitting units in each semiconductor light-emitting layer are electrically connected through the second conductive wiring. Multiple deep holes extending in a second direction are processed in the stacked structure. Each deep hole continuously penetrates at least one semiconductor light-emitting layer or at least one semiconductor light-emitting layer and at least one second insulating dielectric layer and then seamlessly connects to a corresponding second through hole, thereby forming multiple extended second through holes. Each deep hole is filled with a thermally and electrically conductive material so that part of the second conductive structure is extended and the top end of each second conductive structure is electrically connected to the second working electrode of the corresponding light-emitting unit. In addition, a first through hole is fabricated to continuously penetrate the stacked structure along the second direction, and a thermally and electrically conductive material is filled in the first through hole to form a first conductive via structure, and the first conductive via structure is electrically connected to the first conductive wiring and the second conductive wiring, with the top end of the first conductive via structure exposed on the chip surface.

7. The preparation method according to claim 6, characterized in that, Specifically, it includes: A first sub-insulating dielectric layer is formed on a wafer-level driving carrier, and a groove is formed on the surface of the first sub-insulating dielectric layer. The groove is filled with a thermally and electrically conductive material to form the first conductive wiring. A second sub-insulating dielectric layer is formed on the first sub-insulating dielectric layer, thereby forming the first insulating dielectric layer. A plurality of second through holes arranged in an array are processed from the surface of the second sub-insulating dielectric layer, and thermally and electrically conductive materials are filled in the second through holes to form a plurality of second conductive structures.

8. The preparation method according to any one of claims 6-7, characterized in that, Specifically, it includes: A first semiconductor light-emitting layer, a second semiconductor light-emitting layer, and a third semiconductor light-emitting layer are provided respectively. The first semiconductor light-emitting layer includes a plurality of first light-emitting units arranged in an array along a first direction. The second semiconductor light-emitting layer includes a plurality of second light-emitting units arranged in an array along the first direction. The third semiconductor light-emitting layer includes a plurality of third light-emitting units arranged in an array along the first direction. The first semiconductor light-emitting layer is disposed on the first insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each first light-emitting unit to the second driving electrode of the corresponding driving unit through a corresponding second conductive structure. Then, a second conductive wiring is disposed on the first semiconductor light-emitting layer to electrically connect the first working electrodes of multiple first light-emitting units in the first semiconductor light-emitting layer. After that, a second insulating dielectric layer is formed on the first semiconductor light-emitting layer. Multiple first deep holes are fabricated in an array on the surface of the second insulating dielectric layer. Each first deep hole continuously penetrates the second insulating dielectric layer and the first semiconductor light-emitting layer and is seamlessly connected to a corresponding second through hole. Then, thermally and electrically conductive material is filled into the first deep holes to form multiple first-extended second conductive structures. The second semiconductor light-emitting layer is then placed on the second insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each second light-emitting unit to the second driving electrode of the corresponding driving unit through the corresponding first-extended second conductive structure. Then, another second conductive wiring is formed on the second semiconductor light-emitting layer to electrically connect the first working electrodes of the multiple second light-emitting units in the second semiconductor light-emitting layer. Finally, another second insulating dielectric layer is formed on the second semiconductor light-emitting layer. Multiple second deep holes are fabricated on the surface of the other second insulating dielectric layer. Each second deep hole continuously penetrates the other second insulating dielectric layer and the second semiconductor light-emitting layer and is seamlessly connected to a corresponding first deep hole. Then, thermally and electrically conductive material is filled into the second deep holes to form multiple secondary extended second conductive structures. The third semiconductor light-emitting layer is then disposed on the other second insulating dielectric layer, and a hybrid alignment bonding process is used to electrically connect the second working electrode of each third light-emitting unit to the second driving electrode of the corresponding driving unit through the corresponding secondary extended second conductive structure, thereby forming the stacked structure. Then, another second conductive wiring is disposed on the third semiconductor light-emitting layer to electrically connect the first working electrodes of the multiple third light-emitting units in the third semiconductor light-emitting layer. The first conductive via structure is then fabricated within the stacked structure, and the first conductive via structure is electrically connected to the first conductive wiring and the plurality of second conductive wirings.

9. The preparation method according to claim 6, characterized in that, Specifically, it includes: A plurality of first working electrodes and a plurality of second working electrodes are respectively disposed on a first surface and a second surface of the semiconductor light-emitting layer, wherein the first surface is opposite to the second surface, the first surface is the light-emitting surface and is away from the wafer-level driving carrier. Non-transparent conductive lines are continuously arranged on the first surface of the semiconductor light-emitting layer to divide the first surface into multiple patterned light-transmitting areas, and each patterned light-transmitting area corresponds to a pixel unit, each pixel unit including at least three sub-pixels. A light-transmitting conductive material is coated on the patterned light-transmitting area, and the light-transmitting conductive material is electrically contacted with the first working electrode of the multiple light-emitting units in the semiconductor light-emitting layer and the non-transparent conductive lines, thereby forming the second conductive wiring. And / or, an integrated microlens is disposed on the light-emitting surface of the semiconductor light-emitting layer, each microlens corresponding to at least one sub-pixel; And / or, using the first insulating dielectric layer as a bonding layer, the wafer-level driving carrier is bonded to an adjacent semiconductor light-emitting layer, and / or, using the second insulating dielectric layer as a bonding layer, two adjacent semiconductor light-emitting layers are bonded to each other.

10. A display device, characterized in that, Includes the wafer-level semiconductor color display integrated chip as described in any one of claims 1-5.

Images