Display panel

Abstract

This application discloses a display panel including a substrate, a first conductive layer, a first planarization layer, a second conductive layer, an anode layer, and a pixel definition layer. The first planarization layer has a first groove exposing the first conductive layer. The anode layer is located on the side of the second conductive layer facing away from the substrate, and the anode layer is electrically connected to the second conductive layer. A via is formed in the first groove of the second conductive layer. The top edge of the via and the bottom edge of the pixel opening have a first distance in a first direction parallel to the surface of the substrate, and the first distance is greater than or equal to 0 micrometers. Therefore, the embodiments of this application can design-wise ensure that there are no ramp portions of the second conductive layer or the anode layer directly below the pixel opening area, thereby improving the flatness of the anode layer exposed by the pixel opening, thus improving the problems of poor viewing angle symmetry and uneven brightness of the display panel, and improving optical performance.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] With the development of display technology, organic light-emitting diodes (OLEDs) have captured a large share of the market due to their advantages such as thinness, high brightness, and low power consumption. In OLED manufacturing, the stepped structure of the metal wires in the thin film transistor (TFT) driving circuit creates uneven terrain, such as deep holes at the junctions of the metal wires. Therefore, a planarization layer is needed to fill these uneven terrains and form a flat surface. Then, the anode (ANO) is fabricated on the planarization layer.

[0003] However, due to the complex terrain beneath the anode, the anode flatness is ≥150nm, which directly causes optical performance defects such as poor viewing angle symmetry and insufficient brightness uniformity of the display panel, making it difficult to meet the performance requirements of high-end display products. Summary of the Invention

[0004] This application provides a display panel to improve the flatness of the anode layer exposed by the pixel opening, thereby improving the problems of poor viewing angle symmetry and uneven brightness of the display panel, and thus improving optical performance.

[0005] This application provides a display panel, comprising: a substrate; a first conductive layer located on one side of the substrate; a first planarization layer located on the side of the first conductive layer opposite to the substrate, the first planarization layer having a first groove exposing the first conductive layer; a second conductive layer located on the side of the first planarization layer opposite to the substrate, the second conductive layer extending to the inner wall of the first groove and connected to the first conductive layer; an anode layer located on the side of the second conductive layer opposite to the substrate, the anode layer being electrically connected to the second conductive layer; and a pixel definition layer located on the side of the anode layer opposite to the substrate, the pixel definition layer having a pixel opening exposing the anode layer; wherein, the second conductive layer forms a via in the first groove, the top edge of the via and the bottom edge of the pixel opening having a first distance in a first direction, the first direction being parallel to the surface of the substrate, the first distance being greater than or equal to 0 micrometers.

[0006] In some embodiments, the first distance is greater than 1 micrometer.

[0007] In some embodiments, the bottom edge of the via and the bottom edge of the pixel opening have a second distance in the first direction, the second distance being greater than 3 micrometers.

[0008] In some embodiments, the bottom edge of the via and the top edge of the via have a third distance in the first direction, the third distance being less than or equal to 2 micrometers.

[0009] In some embodiments, the first conductive layer includes a surface located around the periphery of the first groove, the sidewall of the first groove having a first inclination angle with the surface, and the first inclination angle being greater than or equal to 50°.

[0010] In some embodiments, the method further includes: a second planarization layer located between the second conductive layer and the anode layer, the second planarization layer having a third groove and a fourth groove spaced apart, the third groove being aligned with the first groove; wherein the anode layer extends to the inner wall of the fourth groove and connects to the second conductive layer.

[0011] In some embodiments, the first groove and the fourth groove are located on opposite sides of the pixel opening along the first direction.

[0012] In some embodiments, the system further includes: a third conductive layer located between the substrate and the first planarization layer; a third planarization layer located between the third conductive layer and the first planarization layer, the third planarization layer having a fifth groove exposing the third conductive layer, the fifth groove being spaced apart from the first groove; wherein the first conductive layer extends to the inner wall of the fifth groove and is connected to the third conductive layer.

[0013] In some embodiments, the thickness of the first planarization layer is 1.8 micrometers to 2.5 micrometers, and the thickness of the second conductive layer is 0.6 micrometers to 0.7 micrometers.

[0014] In some embodiments, the anode layer has a second groove aligned with the first groove, and the pixel definition layer fills the second groove.

[0015] In some embodiments, the method further includes: a fourth planarization layer located between the second planarization layer and the anode layer, the fourth planarization layer having a sixth groove and a seventh groove spaced apart, the sixth groove being aligned with the third groove, and the seventh groove being aligned with the fourth groove and communicating with it; wherein the inner diameter of the seventh groove is larger than the outer diameter of the fourth groove, the anode layer is located on the inner wall of the seventh groove and the inner wall of the fourth groove, and the anode layer forms a step between the fourth groove and the seventh groove.

[0016] In some embodiments, the first conductive layer includes a surface located around the periphery of the first groove, the sidewall of the first groove having a first tilt angle with the surface; the sidewall of the third groove having a second tilt angle relative to the surface of the first conductive layer, the sixth groove having a third tilt angle relative to the surface, and both the second tilt angle and the third tilt angle being equal to the first tilt angle.

[0017] In the display panel of this application embodiment, the second conductive layer overlaps with the first conductive layer through a first groove of the first flattening layer, and a via is formed in the first groove of the second conductive layer, thereby causing the anode layer to be uneven or have a ramp at the position corresponding to the via. Since the top edge of the via and the bottom edge of the pixel opening have a first distance in a first direction, and the first distance is greater than or equal to 0 micrometers, this design ensures that the ramp portion of the second conductive layer is not exposed directly below the pixel opening area. As the film layers are stacked, the uneven area of ​​the anode layer will shrink inward relative to the via below, that is, the ramp of the anode layer will be further away from the pixel opening. Therefore, this application embodiment can design to ensure that there is no ramp portion of the second conductive layer or the ramp portion of the anode layer directly below the pixel opening area, thereby improving the flatness of the anode layer exposed by the pixel opening, thereby improving the problems of poor viewing angle symmetry and uneven brightness of the display panel, and thus improving the optical performance.

[0018] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0021] Figure 1 This is a FIB diagram of a display panel provided in one embodiment of this application;

[0022] Figure 2 yes Figure 1 A graph showing the flatness of the anode layer in the display panel; Figure 3 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application; Figure 4 This is another cross-sectional structural schematic diagram of the display panel provided in some embodiments of this application; Figure 5 This is another FIB diagram of the display panel provided in some embodiments of this application; Figure 6 It is a curve comparing the flatness of the anode layer before and after optimization.

[0023] Explanation of reference numerals in the attached figures: 100. Display panel; X. First direction; 1. Substrate; 2. First conductive layer; 201. Surface; 3. First leveling layer; 31. First groove; A1. First inclination angle; 4. Second conductive layer; 41. Via; 5. Anode layer; 51. Second groove; 52. Second through hole 6. Pixel definition layer; 61. Pixel aperture; 7. Second flattening layer; 71. Third groove; A2. Second inclination angle; 72. Fourth groove; 72R. Outer diameter; 8. Third conductive layer; 9. Third flat layer; 91. Fifth groove; 10. Fourth flat layer; 11. Sixth groove; A3. Third inclination angle; 12. Seventh groove; 12R. Inner diameter. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] Please see Figure 1 and Figure 2 , Figure 1 This is a FIB diagram of a display panel provided in one embodiment of this application. Figure 2 yes Figure 1 A graph showing the flatness of the anode layer in the display panel.

[0026] See Figure 1 A FIB image, or Focused Ion Beam (FIB) cross-sectional image, is a microscopic cross-sectional image obtained by precisely cutting and grinding semiconductor devices such as display panels at the nanometer level using focused ion beam technology, combined with scanning electron microscopy (SEM) imaging. In this image, the first groove 31 exposes the first conductive layer 2, and the second conductive layer 4 extends into the first groove 31 and connects with the first conductive layer 2.

[0027] However, since the flatness of the anode layer 5 cannot be seen with the naked eye in the FIBT scale, the flatness of the anode layer 5 is characterized by measuring the distance between each position of the flat layer and the reference plane.

[0028] See Figure 2 , Figure 2 The test measures the flatness of the exposed portion of the anode layer 5 through the pixel opening. The horizontal axis represents the detection position, and the vertical axis represents the film thickness difference. The point at the horizontal axis of 4 can be used as a standard (distance from the reference plane is 0). The positive or negative value of the vertical axis represents the height difference between other points around point 4 and the reference plane. The absolute value of the vertical axis shows that the left end of the anode layer 5 is the lowest, and the right end is the highest. This means that in the area corresponding to the pixel opening, there is a significant slope on the left side of the anode layer 5. This severely affects the flatness of the light-emitting layer on the anode layer 5, leading to optical performance defects such as poor viewing angle symmetry and insufficient brightness uniformity in the display panel.

[0029] Based on this, this application provides a display panel, comprising: a substrate; a first conductive layer located on one side of the substrate; a first planarization layer located on the side of the first conductive layer opposite to the substrate, the first planarization layer having a first groove exposing the first conductive layer; a second conductive layer located on the side of the first planarization layer opposite to the substrate, the second conductive layer extending to the inner wall of the first groove and connected to the first conductive layer; an anode layer located on the side of the second conductive layer opposite to the substrate, the anode layer being electrically connected to the second conductive layer; and a pixel defining layer located on the side of the anode layer opposite to the substrate, the pixel defining layer having a pixel opening exposing the first surface; wherein, the second conductive layer forms a through hole in the first groove, the top edge of the through hole and the bottom edge of the pixel opening having a first distance in a first direction, the first direction being parallel to the surface of the substrate, the first distance being greater than or equal to 0 micrometers.

[0030] In the display panel provided in this application embodiment, the second conductive layer overlaps with the first conductive layer through a first groove of the first flattening layer, and a via is formed in the first groove of the second conductive layer, thereby causing the anode layer to be uneven or have a ramp at the position corresponding to the via. Since the top edge of the via and the bottom edge of the pixel opening have a first distance in a first direction, and the first distance is greater than or equal to 0 micrometers, this design ensures that the ramp portion of the second conductive layer is not exposed directly below the pixel opening area. As the film layers are stacked, the uneven area of ​​the anode layer will shrink inward relative to the via below, that is, the ramp of the anode layer will be further away from the pixel opening. Therefore, this application embodiment can ensure by design that there is no ramp portion of the second conductive layer or the ramp portion of the anode layer directly below the pixel opening area, thereby improving the flatness of the anode layer exposed by the pixel opening, thereby improving the problems of poor viewing angle symmetry and uneven brightness of the display panel, and thus improving the optical performance.

[0031] The structure of the display panel provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0032] Please see Figure 3 , Figure 3 This is a cross-sectional structural diagram of a display panel provided in some embodiments of this application.

[0033] This display panel 100 is widely used in various display terminal products such as wearable devices (smart bracelets, smartwatches, VR devices), mobile phones, e-books, e-newspapers, televisions, and personal portable computers.

[0034] The display panel 100 includes a substrate 1, a first conductive layer 2, a first planarization layer 3, a second conductive layer 4, an anode layer 5, and a pixel definition layer 6. The first conductive layer 2 is located on one side of the substrate 1, and the first planarization layer 3 is located on the side of the first conductive layer 2 opposite to the substrate 1. The first planarization layer 3 has a first groove 31 exposing the first conductive layer 2. The second conductive layer 4 is located on the side of the first planarization layer 3 opposite to the substrate 1, extending to the inner wall of the first groove 31 and connecting to the first conductive layer 2. The anode layer 5 is located on the side of the second conductive layer 4 opposite to the substrate 1, and is electrically connected to the second conductive layer 4. The pixel definition layer 6 is located on the side of the anode layer 5 opposite to the substrate 1, and has a pixel opening 61 exposing the anode layer 5. The second conductive layer 4 forms a through-hole 41 within the first groove 31. The top edge of the through-hole 41 and the bottom edge of the pixel opening 61 have a first distance in a first direction X, which is parallel to the surface of the substrate 1. The first distance is greater than or equal to 0 micrometers.

[0035] It should be noted that the Z-direction in the figure represents the direction perpendicular to the surface of substrate 1, and also represents the thickness direction of the display panel and the stacking direction of the film layers. Substrate 1 can be a driving substrate, which includes a substrate and a thin film transistor (TFT) layer located on the substrate. As the basic support structure of the display panel 100, the substrate includes one or a combination of a glass substrate and a flexible substrate. This substrate is adaptable to various product forms such as folded and non-folded, and provides a stable deposition substrate for subsequent film layers.

[0036] In some embodiments, the thin-film transistor layer may, from bottom to top, include a substrate, a buffer layer, an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, a second gate, an interlayer dielectric layer, a source, and a drain. The buffer layer is located on the substrate, the active layer is located on the buffer layer, and the first gate insulating layer is located on the buffer layer and covers the active layer. The first gate is located on the first gate insulating layer, and the second gate insulating layer is located on the first gate insulating layer and covers the first gate. The second gate is located on the second gate insulating layer, and the interlayer dielectric layer is located on the second gate insulating layer and covers the second gate. The source and drain are located on the interlayer dielectric layer and are respectively connected to both sides of the active layer through vias.

[0037] The first conductive layer 2 is located on one side surface of the substrate 1 and can be deposited by processes such as sputtering and evaporation. The material can be metals such as copper, aluminum, and molybdenum or their alloys. It is used to realize signal transmission of the TFT driving circuit and constitutes the basic layer for circuit connection. For example, the first conductive layer 2 is electrically connected to the drain of the thin film transistor layer in the substrate 1.

[0038] The first planarization layer 3 is located on the side of the first conductive layer 2 facing away from the substrate 1, and is prepared by coating and curing an insulating material such as polyimide. The first planarization layer 3 is formed by photolithography etching to expose the first groove 31 of the first conductive layer 2, which is used for the subsequent electrical connection between the second conductive layer 4 and the first conductive layer 2.

[0039] The second conductive layer 4 is located on the side of the first planarization layer 3 facing away from the substrate 1. It can be made of the same or compatible metal material as the first conductive layer 2 and is formed through photolithography and etching processes. The second conductive layer 4 extends to the inner wall of the first groove 31 and connects with the first conductive layer 2, achieving electrical conductivity between the two conductive layers.

[0040] In some embodiments, based on their respective performance requirements, the thickness of the second conductive layer 4 is much smaller than the thickness of the first planarization layer 3, so that the second conductive layer 4 cannot fill the first groove 31, resulting in the formation of a via 41 in the first groove 31. The structural parameters of the first via 41 directly affect the flatness of the anode layer 5.

[0041] In some embodiments, since the second conductive layer 4 has a via 41, the anode layer 5 has a second groove 51 (i.e., an uneven area) that is aligned with the first groove 31, and the pixel definition layer fills the second groove 51.

[0042] Specifically, due to the morphology of the via 41, a second groove 51 will inevitably be formed during the conformal deposition of the anode layer 5, which aligns with the first groove 31. This second groove 51 is a morphological structure that cannot be avoided at the process level and does not serve an electrical connection function. One of the core design objectives of this application is to optimize the position, size, and tilt angle parameters of the first via 41 to prevent the pixel opening 61 from exposing the ramp area corresponding to the second conductive layer 4, thereby ensuring the surface flatness of the anode layer 5 used to support the light-emitting layer.

[0043] In some embodiments, the first distance is greater than 1 micrometer. This ensures, within the range of process tolerances, that the ramp portion of the second conductive layer 4 is not exposed directly below the pixel opening 61 region, thereby ensuring that the uneven area or ramp portion of the anode layer 5 is not exposed directly below the pixel opening 61 region.

[0044] The advantages of leaving the first groove 31 unfilled and retaining the via 41 are mainly reflected in two aspects: First, it avoids the risk of signal interference or short circuit caused by the large-area coverage of the second conductive layer 4; second, it optimizes the control of film flatness. If the first groove 31 is forcibly filled with conductive material, the surface of the conductive material is prone to undulation due to the step effect, which will damage the flatness of the subsequent film layer. Retaining the via 41 and optimizing parameters such as tilt angle and distance can minimize the negative impact on the flatness of the anode layer 5, while meeting the thickness performance requirements of the second conductive layer 4, reducing the amount of conductive material used, and reducing the manufacturing cost.

[0045] In some embodiments, the thickness of the first planarization layer 3 is 1.8 micrometers to 2.5 micrometers, and the thickness of the second conductive layer 4 is 0.6 micrometers to 0.7 micrometers.

[0046] The thickness of the first planarization layer 3 is controlled between 1.8 micrometers and 2.5 micrometers. This thickness setting is based on the filling requirements of the TFT driving circuit's concave-convex structure and the performance consideration of ensuring the flatness of the subsequent film layer. It can fully cover the surface of the first conductive layer 2 and level the basic morphology.

[0047] The thickness of the second conductive layer 4 is set to 0.6 micrometers to 0.7 micrometers. This parameter is determined based on the performance requirements of comprehensive conductivity, signal transmission efficiency, and film deposition compatibility.

[0048] The anode layer 5 is located on the side of the second conductive layer 4 facing away from the substrate 1, serving as the anode electrode of the OLED device. It can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). Since the second conductive layer 4 has a via 41, the anode layer 5 has a second groove 51 (i.e., an uneven area) aligned with the via 41 and the first groove 31. This alignment of the second groove 51 with the first groove 31 is not achieved through active alignment via photolithography, but rather through the natural adaptation of the anode layer 5 to the morphology of the first groove 31 and the first via 41 during conformal deposition. The anode layer 5 is formed along the contour of the first via 41, causing the projection range and morphology of the second groove 51 to naturally overlap with the first via 41 and the first groove 31, forming a regular recessed structure. Furthermore, the second groove 51 does not perform electrical connection functions.

[0049] The pixel definition layer 6 is located on the side of the anode layer 5 facing away from the substrate 1. It is made of an insulating material and is used to define the pixel area. The pixel definition layer 6 fills the second groove 51 to prevent the second groove 51 from affecting the deposition uniformity of the light-emitting layer. At the same time, the pixel definition layer 6 has a pixel opening 61 that exposes the anode layer 5. The area of ​​the pixel opening 61 is the deposition area of ​​the light-emitting layer and directly determines the light-emitting range of the pixel.

[0050] It should be noted that since the second conductive layer 4 covers the inner wall of the first groove 31 and the upper surface of the first flat layer 3, and the upper surface of the second conductive layer 4 (i.e. the surface facing away from the substrate 1) is flat, the second conductive layer 4 moves the climbing area of ​​the lower structure (i.e. the first groove 31) a certain distance away from the pixel opening 61. Therefore, the actual climbing area is the climbing area of ​​the second conductive layer 4.

[0051] Based on this, in order to optimize the flatness of the anode layer 5, this application defines the relative position of the first via 41 and the pixel opening 61: the first direction X is a direction parallel to the surface of the substrate 1 (i.e., a horizontal direction, corresponding to the X direction in the figure), and the top edge of the first via 41 and the bottom edge of the pixel opening 61 have a first distance L1 in the first direction X. The first distance is greater than 1 micrometer, which can prevent the ramp structure of the edge of the via 41 from extending to the anode layer 5 area corresponding to the pixel opening 61 and reduce the surface undulation of the anode layer 5.

[0052] In some embodiments, to improve the flatness optimization effect, the bottom edge of the first via 41 and the bottom edge of the pixel opening 61 have a second distance L2 in the first direction X, the second distance being greater than 3 micrometers, to ensure that there is no main structure of the first via 41 and surrounding ramp area below the anode layer 5 corresponding to the pixel opening 61.

[0053] In some embodiments, the bottom edge of the first via 41 and the top edge of the first via 41 have a third distance L3 in the first direction X, the third distance L3 being less than or equal to 2 micrometers, which shortens the horizontal span of the via 41 ramp and reduces the impact of the ramp structure on the surface flatness of the anode layer 5 exposed by the pixel opening 61.

[0054] In some embodiments, the first conductive layer 2 includes a surface 201 located around the first groove 31 (i.e., a flat area of ​​the first conductive layer 2 not exposed by the first groove 31). The sidewall of the first groove 31 and the surface 201 have a first tilt angle A1 (i.e., Taper angle), and the first tilt angle A1 is greater than or equal to 50°. This tilt angle design can reduce the steepness of the sidewall of the first groove 31, which can not only reduce the projection range of the first groove 31 to reduce the area of ​​the depression, but also further reduce the third distance L3 while keeping the film thickness unchanged, further optimizing the surface flatness below the exposed anode layer 5.

[0055] It is understandable that if the depression range of the lower membrane layer is larger, the depression range of the upper membrane layer will also be larger.

[0056] It should be noted that since the via 41 and the second groove 51 formed on the upper film layer of the first groove 31 are formed based on the morphology of the first groove 31, theoretically the taper angles of the via 41 and the second groove 51 that are aligned are equal to the taper angle of the first groove 31 (both ≥50°).

[0057] Therefore, in the manufacturing process, it is only necessary to control the taper angle of the first groove 31 through process control.

[0058] Precise control of the tilt angle of each groove can be achieved by adjusting the IUV process during the preparation of the first planarization layer 3. The complete formation process of the first planarization layer 3 includes four core steps: coating, photolithography, IUV, and curing. The connection and function of each process are as follows: First, the coating process uniformly covers the surface of the first conductive layer 2 with insulating materials such as polyimide to form an initial film layer. Then, the photolithography process is carried out. Through photoresist coating, exposure, development, and etching, the first groove 31 exposing the first conductive layer 2 is formed on the initial film layer. After photolithography, the Taper angle (first tilt angle A1) of the sidewall of the first groove 31 is close to 90°, which is relatively steep. After photolithography, the IUV (i.e., ultraviolet light irradiation) process is entered. This process is a key step connecting photolithography and curing. Its core function is to pre-treat the PLN (planarization layer) material. IUV will reduce the first tilt angle A1 of the first groove, thereby forming a longer climbing area. Finally, the curing process is carried out to make the PLN material form a stable insulating structure, ensuring the mechanical and insulating properties of the planarization layer.

[0059] The IUV process controls the groove tilt angle as follows: If the IUV process is turned on, the ultraviolet light will decompose the small molecules in the PLN material (process negative products). After the small molecules are decomposed, they are cured, which can significantly improve the curing degree of the PLN material and enhance the viscosity and structural stability of the adhesive layer. However, the removal of small molecules will reduce the fluidity of the PLN material, making it difficult for the sidewall of the first groove 31 to adjust its shape during the curing process, and ultimately the Taper angle will become smaller. Conversely, if the IUV process is turned off, the small molecules in the PLN material are not decomposed, and the material retains good fluidity. During the subsequent curing process, the sidewall of the first groove 31 will naturally form a gentle tilt shape due to the material's own fluidity and surface tension, making it less prone to collapse. This can increase the Taper angle and achieve the tilt angle requirement of A1 ≥ 50°.

[0060] See Figure 3 The display panel 100 may further include a second planarization layer 7, located between the second conductive layer 4 and the anode layer 5. The second planarization layer 7 is made of the same or compatible insulating material as the first planarization layer 3 and is used to further fill the minor undulations on the surface of the second conductive layer 4. The second planarization layer 7 has a third groove 71 and a fourth groove 72 spaced apart. The third groove 71 is aligned with the first groove 31, and the anode layer 5 extends to the inner wall of the fourth groove 72 and connects to the second conductive layer 4.

[0061] The third groove 71 is not formed by precise alignment after being actively created through photolithography, but rather is a structure naturally formed during the conformal deposition of the second planarization layer 7, adapting to the morphology of the first via 41 and the first groove 31. The fourth groove 72 is a dedicated electrical connection channel, specifically used to achieve electrical connection between the anode layer 5 and the second conductive layer 4. The anode layer 5 extends to the inner wall of the fourth groove 72 and docks with the second conductive layer 4 to ensure stable current transmission.

[0062] In some embodiments, the first groove 31 (and the corresponding third groove 71) and the fourth groove 72 are located on opposite sides of the pixel opening 61 along the first direction X. The symmetrical distribution of the avoidance structure (on the side of the third groove 71) and the conductive connection structure (on the side of the fourth groove 72) below the anode layer 5 ensures that they do not overlap, effectively avoiding the aggravation of local depression caused by groove overlap, further optimizing the surface flatness of the anode layer 5, and reducing the negative impact of unilateral structural undulations or superimposed depressions on flatness.

[0063] This symmetrical distribution also has the following advantages: 1) Dispersing film stress: The symmetrical structure can effectively offset the residual stress generated during the deposition and curing of each film layer, avoiding film warping and cracking caused by stress accumulation on one side, especially suitable for the repeated bending requirements of flexible display panels; 2) Optimizing process compatibility: The symmetrical layout can reduce the alignment difficulty of processes such as photolithography and deposition, reduce process deviations caused by the complexity of the one-sided structure, and improve the preparation yield; 3) Improving optical consistency: The symmetrical bottom layer structure can ensure that the refraction and reflection paths of light in the pixel area are consistent, further improving the symmetry of the viewing angle and avoiding the problem of image quality degradation on one side of the viewing angle.

[0064] In some embodiments, the design of the fourth groove 72 can also refer to the design of the first groove 31 to ensure that the climbing area of ​​the fourth groove 72 is not within the range of the pixel opening 61.

[0065] For example, the taper angle B1 of the fourth groove 72 is greater than or equal to 50°. If the via 41 formed by the second conductive layer 4 is called the first via 41, then the via formed by the anode layer 5 in the fourth groove 72 can be called the second via 52. The distance between the top edge of the second via 52 and the bottom edge of the pixel opening 61 in the first direction X is L4, and the distance between the bottom edge of the second via 52 and the top edge of the second via 52 in the first direction X is L5, where L4 is greater than 1 micrometer and L5 is less than or equal to 2 micrometers.

[0066] Please see Figure 4 , Figure 4 This is another cross-sectional structural schematic diagram of a display panel provided in some embodiments of this application. This embodiment is similar to... Figure 3 The difference in the embodiment is that it also includes a third conductive layer 8, a third planarization layer 9, and a fourth planarization layer 10.

[0067] The display panel may further include a third conductive layer 8 and a third planarization layer 9, with the third conductive layer 8 located between the substrate 1 and the first planarization layer 3. The third planarization layer 9 is located between the third conductive layer 8 and the first planarization layer 3, and is used to fill the recessed structure on the surface of the third conductive layer 8. The third planarization layer 9 has a fifth groove 91 that exposes the third conductive layer 8, and the fifth groove 91 is spaced apart from the first groove 31. The first conductive layer 2 extends to the inner wall of the fifth groove 91 and connects with the third conductive layer 8, achieving orderly conduction of multiple conductive layers and adapting to the design requirements of complex driving circuits.

[0068] The fifth groove 91 and the first groove 31 are spaced apart, which means that the two maintain a reasonable distance in the first direction X, and their projections do not overlap. This can avoid the superposition of the depression effect of the two grooves, prevent the bottom surface undulation from being aggravated, and at the same time avoid signal crosstalk caused by the two conductive paths (the fifth groove 91 corresponds to the conduction of the first conductive layer 2 and the third conductive layer 8, and the first groove 31 corresponds to the conduction of the first conductive layer 2 and the second conductive layer 4) being too close.

[0069] In some embodiments, the fifth groove 91 is located to the left of the first groove 31 (e.g., Figure 4 As shown in the diagram, this layout design has multiple advantages: First, it can completely avoid the overlap of the projections of the fifth groove 91 and the first groove 31 in the direction perpendicular to the substrate 1, preventing the superposition of the depression effects of the two grooves, avoiding aggravation of the topographic undulations of the underlying layer, and reducing the difficulty of subsequent planarization layer leveling; Second, it can effectively avoid the area directly below the pixel opening 61, further optimizing the flatness and display performance of the anode layer 5. Specifically, avoiding the area directly below the pixel opening 61 can prevent the uneven structure of the fifth groove 91 from being transmitted to the corresponding light-emitting area of ​​the anode layer 5, eliminating problems such as uneven film thickness and climbing marks in this area, while avoiding stress concentration in the groove area from affecting the uniformity of light-emitting layer deposition.

[0070] The display panel may further include a fourth planarization layer 10, which is located between the second planarization layer 7 and the anode layer 5. The fourth planarization layer 10 has a sixth groove 11 and a seventh groove 12 spaced apart. The sixth groove 11 is aligned with the third groove 71, and the seventh groove 12 is aligned with the fourth groove 72 and communicates with each other.

[0071] The inner diameter 12R of the seventh groove 12 is larger than the outer diameter 72R of the fourth groove 72, forming a stepped groove structure. The anode layer 5 is located on the inner wall of the seventh groove 12 and the inner wall of the fourth groove 72, and the anode layer 5 forms a step between the fourth groove 72 and the seventh groove 12. This stepped structure can enhance the bonding force between the anode layer 5 and the second planarization layer 7 and the fourth planarization layer 10, while avoiding film peeling caused by stress concentration at the groove edges.

[0072] In some embodiments, the sidewall of the third groove 71 has a second tilt angle A2 relative to the surface 201 of the first conductive layer 2, and the second tilt angle A2 is equal to the first tilt angle A1. The sixth groove 11 has a third tilt angle A3 relative to the surface 201, and the third tilt angle A3 is also equal to the first tilt angle A1. The sidewall tilt angles of each groove are consistent, ensuring that the deposition thickness of subsequent conductive layers and anode layers 5 is uniform, avoiding surface undulations caused by tilt angle differences, and maximizing the flatness of the anode layer 5.

[0073] It should be noted that although the inclination angles of each groove are equal, as the film layers are stacked, the upper groove will be recessed relative to the lower groove or via. That is, the lateral distance between the upper groove and the bottom edge of the pixel opening 61 is greater than the first distance L1. In other words, by controlling that there is no ramp structure of the second conductive layer 4 directly below the pixel opening 61, the other ramp structures above will not be located directly below the pixel opening 61.

[0074] Please see Figure 5 , Figure 5 This is another FIB diagram of the display panel provided in some embodiments of this application. The overall structure of this FIB diagram is similar to... Figure 4 The structures are the same, the only difference being the relative positions of the fifth groove 91 and the first groove 31.

[0075] exist Figure 5 In the embodiment, the fifth groove 91 is located to the right of the first groove 31. Although the fifth groove 91 is located in the area below the pixel opening 61, the flatness of the anode layer 5 can also be improved by designing parameters such as the taper angle of the fifth groove 91.

[0076] See Figure 5 and Figure 1 The climbing area of ​​the first groove 31 is indicated by a dashed box. Figure 1 The slope of the first groove 31 in the middle is obvious, while after improvement Figure 5 The climbing distance of the first groove 31 in the structure is reduced, so the optimized structure can improve the flatness of the left edge of the anode layer 5.

[0077] Please see Figure 6 , Figure 6 This is a comparison curve of the flatness of the anode layer before and after optimization. The flatness curve after optimization is black, and the flatness curve before optimization is gray.

[0078] Comparing the two measurement curves shows that the left edge of the optimized anode layer 5 is positioned higher, resulting in a significant improvement in overall flatness. Test results indicate a flatness improvement of >200nm before optimization and <100nm after optimization.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel (100), characterized in that, include: substrate(1); The first conductive layer (2) is located on one side of the substrate (1); A first planarization layer (3) is located on the side of the first conductive layer (2) away from the substrate (1), and the first planarization layer (3) has a first groove (31) that exposes the first conductive layer (2). The second conductive layer (4) is located on the side of the first flat layer (3) away from the substrate (1). The second conductive layer (4) extends to the inner wall of the first groove (31) and is connected to the first conductive layer (2). An anode layer (5) is located on the side of the second conductive layer (4) away from the substrate (1), and the anode layer (5) is electrically connected to the second conductive layer (4); A pixel definition layer (6) is located on the side of the anode layer (5) away from the substrate (1), and the pixel definition layer (6) has a pixel opening (61) that exposes the anode layer (5). The second conductive layer (4) forms a via (41) in the first groove (31). The top edge of the via (41) and the bottom edge of the pixel opening (61) have a first distance in a first direction (X). The first direction (X) is parallel to the surface of the substrate (1). The first distance is greater than or equal to 0 micrometers.

2. The display panel (100) according to claim 1, characterized in that, The first distance is greater than 1 micrometer.

3. The display panel (100) according to claim 1, characterized in that, The bottom edge of the via (41) and the bottom edge of the pixel opening (61) have a second distance in the first direction (X), the second distance being greater than 3 micrometers.

4. The display panel (100) according to claim 3, characterized in that, The bottom edge of the via (41) and the top edge of the via (41) have a third distance in the first direction (X), the third distance being less than or equal to 2 micrometers.

5. The display panel (100) according to any one of claims 1 to 4, characterized in that, The first conductive layer (2) includes a surface (201) located around the first groove (31), and the sidewall of the first groove (31) has a first tilt angle (A1) between it and the surface (201), and the first tilt angle (A1) is greater than or equal to 50°.

6. The display panel (100) according to claim 1, characterized in that, Also includes: The second planarization layer (7) is located between the second conductive layer (4) and the anode layer (5). The second planarization layer (7) has a third groove (71) and a fourth groove (72) spaced apart. The third groove (71) is aligned with the first groove (31). The anode layer (5) extends to the inner wall of the fourth groove (72) and is connected to the second conductive layer (4).

7. The display panel (100) according to claim 6, characterized in that, The first groove (31) and the fourth groove (72) are located on opposite sides of the pixel opening (61) along the first direction (X).

8. The display panel (100) according to claim 1, characterized in that, Also includes: The third conductive layer (8) is located between the substrate (1) and the first planarization layer (3); The third planarization layer (9) is located between the third conductive layer (8) and the first planarization layer (3). The third planarization layer (9) has a fifth groove (91) that exposes the third conductive layer (8). The fifth groove (91) is spaced apart from the first groove (31). The first conductive layer (2) extends to the inner wall of the fifth groove (91) and connects with the third conductive layer (8).

9. The display panel (100) according to claim 1, characterized in that, The thickness of the first planarization layer (3) is 1.8 micrometers to 2.5 micrometers, and the thickness of the second conductive layer (4) is 0.6 micrometers to 0.7 micrometers.

10. The display panel (100) according to claim 1, characterized in that, The anode layer (5) has a second groove (51) that is aligned with the first groove (31), and the pixel definition layer (6) fills the second groove (51).

11. The display panel (100) according to claim 6, characterized in that, Also includes: The fourth flat layer (10) is located between the second flat layer (7) and the anode layer (5). The fourth flat layer (10) has a sixth groove (11) and a seventh groove (12) spaced apart. The sixth groove (11) is aligned with the third groove (71), and the seventh groove (12) is aligned with the fourth groove (72) and communicates with each other. The inner diameter (12R) of the seventh groove (12) is larger than the outer diameter (72R) of the fourth groove (72). The anode layer (5) is located on the inner wall of the seventh groove (12) and the inner wall of the fourth groove (72), and the anode layer (5) forms a step between the fourth groove (72) and the seventh groove (12).

12. The display panel (100) according to claim 11, characterized in that, The first conductive layer (2) includes a surface (201) located around the first groove (31), and the sidewall of the first groove (31) has a first angle (A1) between it and the surface (201). The sidewall of the third groove (71) has a second tilt angle (A2) relative to the surface (201) of the first conductive layer (2), and the sixth groove (11) has a third tilt angle (A3) relative to the surface (201), and the second tilt angle (A2) and the third tilt angle (A3) are both equal to the first tilt angle (A1).

Images