A Josephson junction superconducting quantum device and its fabrication method

Abstract

This invention provides a method for fabricating a Josephson junction superconducting quantum device, comprising the steps of: providing a substrate; sequentially forming a first superconducting film, a barrier film, and a second superconducting film on the substrate from bottom to top; etching the second superconducting film to form a second superconducting layer; etching the barrier film to form a barrier layer; etching the first superconducting film to form a lead groove and the first superconducting layer; forming an interlayer dielectric layer structure, the interlayer dielectric layer structure including a first dielectric layer and a second dielectric layer; forming a wiring layer, the wiring layer being located on the interlayer dielectric layer structure and the second superconducting layer and including lead-out portions and electrode portions; and etching the second superconducting layer again to remove the portion of the second superconducting layer exposed outside the electrode portions. The method for fabricating a Josephson junction superconducting quantum device of this invention can reduce the dielectric loss in the Josephson junction superconducting quantum device and improve the performance of the Josephson junction superconducting quantum device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a Josephson junction superconducting quantum device and its preparation method. Background Technology

[0002] Superconducting Josephson junctions, as core fundamental components, are widely used in various superconducting quantum devices such as superconducting quantum interference devices (QIUDs), superconducting qubits (qubits), and superconducting parametric amplifiers (PPAs). Superconducting quantum devices are the core support for the realization of cutting-edge technologies such as magnetic field detection, gate circuit quantum computers, quantum annealing simulators, and high-fidelity quantum information measurement and control. Their performance directly determines the application effect and development potential of these cutting-edge technologies.

[0003] Currently, the mainstream superconducting Josephson junctions in the industry are fabricated using a three-layer film structure and supporting processes, with Nb / Al-AlO being a typical example. x / Nb Josephson knot, and also developed NbN / AlN / NbN, Ta / Al-AlO x Josephson junctions with similar structures to those in novel material systems such as Ta. The structure of such superconducting Josephson junctions generally includes a core junction region (such as the Nb / Al-AlOx / Nb junction region), an interlayer insulating dielectric layer (such as the SiO2 layer), and a wiring layer (such as the Nb wiring layer). The fabrication process requires three layers of film etching, interlayer insulating dielectric layer forming, and wiring layer fabrication.

[0004] However, all existing superconducting Josephson junctions share a common technical defect: their interlayer insulating media (such as SiO2, AlN, etc.) generate significant dielectric losses. These dielectric losses directly lead to a series of serious performance degradation and operational stability problems in superconducting quantum devices. For example, in superconducting quantum interference devices (QFIDs), dielectric losses cause a significant decrease in their signal-to-noise ratio; in superconducting qubits (qubits), dielectric losses shorten their decoherence time and reduce their fidelity; in quantum annealing simulators, dielectric losses increase their computational error rate; and in superconducting parametric amplifiers (SPAs), dielectric losses cause gain attenuation. These problems caused by dielectric losses in the interlayer insulating media severely restrict the performance improvement of various three-layer superconducting Josephson junction structures, making it difficult for them to meet the high-performance requirements of cutting-edge superconducting quantum technologies for core components.

[0005] Therefore, how to provide a Josephson junction superconducting quantum device and its fabrication method to reduce the dielectric loss of the Josephson junction superconducting quantum device, improve the performance of the Josephson junction superconducting quantum device, and meet the needs of superconducting quantum technology has become an important problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a Josephson junction superconducting quantum device and its fabrication method, which solves the problem that the excessive dielectric loss of various superconducting Josephson junctions in the prior art leads to a series of serious performance degradation and insufficient operational stability of superconducting quantum devices.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a Josephson junction superconducting quantum device, characterized by comprising the following steps:

[0009] A substrate is provided, and a first superconducting film, a barrier film, and a second superconducting film are formed sequentially from bottom to top on the substrate;

[0010] The second superconducting film is etched to form a second superconducting layer, the second superconducting layer being strip-shaped;

[0011] The barrier film is etched to form a barrier layer, the barrier layer being partially exposed outside the second superconducting layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer is not less than 1 μm;

[0012] The first superconducting film is etched to form a lead groove and a first superconducting layer. The lead groove is located on one side of the first superconducting layer and exposes the substrate. The first superconducting layer is located below the barrier layer and is partially exposed outside the barrier layer.

[0013] An interlayer dielectric layer structure is formed, the interlayer dielectric layer structure including a first dielectric layer and a second dielectric layer, the first dielectric layer filling the lead groove, the second dielectric layer being located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer is not less than 2 μm;

[0014] A wiring layer is formed, which is located on the interlayer dielectric layer structure and the second superconducting layer and includes a lead-out portion and an electrode portion. The lead-out portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the lead-out portion and extends along the first direction to the side of the second superconducting layer away from the lead-out portion.

[0015] The second superconducting layer is etched again to remove the portion of the second superconducting layer exposed outside the electrode portion.

[0016] Optionally, the substrate includes any one of a silicon substrate, a thermally oxidized silicon substrate, a magnesium oxide substrate, or a sapphire substrate.

[0017] Optionally, after etching the first superconducting film, a pair of capacitor plates distributed on both sides of the first dielectric layer are also formed on the substrate, wherein one capacitor plate is electrically connected to the first superconducting layer, and the other capacitor plate is electrically connected to the lead-out portion of the wiring layer.

[0018] Optionally, the thickness of the first superconducting layer is in the range of 50 nm to 250 nm, the thickness of the barrier layer is in the range of 2 nm to 20 nm, and the thickness of the second superconducting layer is in the range of 50 nm to 250 nm.

[0019] Optionally, the material combination of the first superconducting film, the barrier film, and the second superconducting film includes Nb / Al-AlO. x / Nb, Nb / Al-AlN / Nb, NbN / AlN / NbN and Ta / Al-AlO x / Ta.

[0020] Optionally, forming the interlayer dielectric layer structure includes the following steps:

[0021] An interlayer dielectric film is formed, wherein the interlayer dielectric layer covers the second superconducting layer, the barrier layer, the first superconducting layer, and the substrate;

[0022] The interlayer dielectric film is thinned along the direction from the second superconducting layer to the barrier layer, so that the interlayer dielectric film exposes the upper surface of the second superconducting layer;

[0023] The interlayer dielectric film is etched, and a portion of the interlayer dielectric film filling the lead groove is retained to form the first dielectric layer. A portion of the interlayer dielectric film located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer is retained to form the second dielectric layer.

[0024] Optionally, the thickness of the first dielectric layer is in the range of 500 nm to 1000 nm, and the thickness of the second dielectric layer is in the range of 500 nm to 1000 nm.

[0025] Optionally, forming the wiring layer includes the following steps:

[0026] A metal layer is formed, which covers the second dielectric layer, the second superconducting layer, the barrier layer, the first superconducting layer, and the substrate;

[0027] The metal layer is etched to form the wiring layer.

[0028] The present invention also provides a Josephson junction superconducting quantum device, characterized in that it comprises:

[0029] Substrate;

[0030] A first superconducting film is covered on the substrate. The first superconducting film includes a lead groove and a first superconducting layer. The lead groove is located on one side of the first superconducting layer and exposes the substrate.

[0031] A barrier layer is located on the first superconducting layer;

[0032] The second superconducting layer is located on the barrier layer and exposes part of the barrier layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer is not less than 1 μm;

[0033] An interlayer dielectric layer structure is provided, comprising a first dielectric layer and a second dielectric layer. The first dielectric layer is filled within the lead groove, and the second dielectric layer is located on the first superconducting layer, surrounding the barrier layer and encircling the second superconducting layer. A predetermined distance exists between the inner edge of the second dielectric layer and the outer edge of the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer is not less than 2 μm.

[0034] A wiring layer is located on the interlayer dielectric layer structure and the second superconducting layer and includes a lead-out portion and an electrode portion. The lead-out portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the lead-out portion and extends along the first direction to the side of the second superconducting layer away from the lead-out portion. The first direction is from the lead-out groove to the first superconducting layer.

[0035] Optionally, the first superconducting film is further provided with a pair of capacitor plates distributed on both sides of the first dielectric layer, wherein one capacitor plate is electrically connected to the first superconducting layer, and the other capacitor plate is electrically connected to the lead-out portion of the wiring layer.

[0036] As described above, the fabrication method of the Josephson junction superconducting quantum device of the present invention includes the following steps: providing a substrate, and sequentially forming a first superconducting film, a barrier film, and a second superconducting film on the substrate from bottom to top; etching the second superconducting film to form a second superconducting layer, the second superconducting layer being strip-shaped; etching the barrier film to form a barrier layer, the barrier layer being partially exposed outside the second superconducting layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer being not less than 1 μm; etching the first superconducting film to form a lead groove and a first superconducting layer, the lead groove being located on one side of the first superconducting layer and exposing the substrate, the first superconducting layer being located below the barrier layer and partially exposed outside the barrier layer; forming an interlayer dielectric layer structure, the interlayer dielectric layer structure including a first dielectric layer and a second dielectric layer, the first dielectric layer filling the lead groove, the second dielectric layer being located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer being not less than 2 μm. μm; a wiring layer is formed, which is located on the interlayer dielectric layer structure and the second superconducting layer and includes an outlet portion and an electrode portion. The outlet portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the outlet portion and extends along a first direction to the side of the second superconducting layer away from the outlet portion; the second superconducting layer is etched again to remove the portion of the second superconducting layer exposed outside the electrode portion. The fabrication method of the Josephson junction superconducting quantum device of the present invention can reduce the dielectric loss in the Josephson junction superconducting quantum device, improve the performance of the Josephson junction superconducting quantum device, and broaden the application of the three-layer film structure Josephson junction in superconducting quantum devices, thus meeting the needs of superconducting quantum technology. Attached Figure Description

[0037] Figure 1 The diagram shows the process flow of the Josephson junction fabrication method in superconducting quantum devices according to Embodiment 1 of the present invention.

[0038] Figure 2 The image shown is a top view of the substrate provided in the fabrication method of the Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0039] Figure 3 Displayed as Figure 2 The structure shown is a cross-sectional view along the AA' direction.

[0040] Figure 4 The image shown is a top view of the structure obtained after forming a first superconducting film, a barrier film, and a second superconducting film in the fabrication method of a superconducting quantum device according to Embodiment 1 of the present invention.

[0041] Figure 5 Displayed as Figure 4 The structure shown is a cross-sectional view along the AA' direction.

[0042] Figure 6The image shown is a top view of the structure obtained after forming a second superconducting layer in the fabrication method of a Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0043] Figure 7 Displayed as Figure 6 The structure shown is a cross-sectional view along the AA' direction.

[0044] Figure 8 The image shown is a top view of the structure obtained after forming a barrier layer in the fabrication method of a Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0045] Figure 9 Displayed as Figure 8 The structure shown is a cross-sectional view along the AA' direction.

[0046] Figure 10 The image shown is a top view of the structure obtained after forming a lead groove and a second superconducting layer in the fabrication method of a Josephson junction for a superconducting quantum device according to Embodiment 1 of the present invention.

[0047] Figure 11 Displayed as Figure 10 The structure shown is a cross-sectional view along the AA' direction.

[0048] Figure 12 The image shown is a top view of the structure obtained after forming an interlayer dielectric film in the fabrication method of a Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0049] Figure 13 Displayed as Figure 12 The structure shown is a cross-sectional view along the AA' direction.

[0050] Figure 14 The image shown is a top view of the structure obtained after forming an interlayer dielectric layer structure in the fabrication method of a Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0051] Figure 15 Displayed as Figure 14 The structure shown is a cross-sectional view along the AA' direction.

[0052] Figure 16 The image shown is a top view of the structure obtained after forming a metal layer in the fabrication method of a Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention.

[0053] Figure 17 Displayed as Figure 16 The structure shown is a cross-sectional view along the AA' direction.

[0054] Figure 18 The image shown is a top view of the structure obtained after forming a wiring layer and removing a portion of the second superconducting layer exposed outside the electrode portion in the fabrication method of the Josephson junction in Embodiment 1 of the present invention.

[0055] Figure 19 Displayed as Figure 18 The structure shown is a cross-sectional view along the AA' direction.

[0056] Figure 20 The diagram shown is a three-dimensional structural diagram of the Josephson junction in a superconducting quantum device structure according to Embodiment 2 of the present invention.

[0057] Explanation of reference numerals in the attached figures

[0058] 101 substrate 102 First superconducting membrane 1021 Lead Wire Slot 1022 First superconducting layer 1023 capacitor plates 103 Barrier membrane 104 Second superconducting membrane 105 Second superconducting layer 106 Barrier layer 107 Interlayer dielectric membrane 108 Interlayer dielectric layer structure 1081 First dielectric layer 1082 Second dielectric layer 109 Metal layer 110 Wiring layer 1101 Introduction 1102 Electrode section D1 The shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer D2 The shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer S1~S7 step Detailed Implementation

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0061] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0062] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0063] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0064] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] Example 1

[0067] Please see Figure 1 The diagram shows a process flow chart of the fabrication method of the Josephson junction superconducting quantum device in this embodiment, which includes at least the following steps:

[0068] S1: A substrate is provided, and a first superconducting film, a barrier film and a second superconducting film are formed sequentially on the substrate from bottom to top;

[0069] S2: Etch the second superconducting film to form a second superconducting layer, the second superconducting layer being strip-shaped;

[0070] S3: Etch the barrier film to form a barrier layer, the barrier layer being partially exposed outside the second superconducting layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer is not less than 1 μm;

[0071] S4: Etch the first superconducting film to form a lead groove and a first superconducting layer. The lead groove is located on one side of the first superconducting layer and exposes the substrate. The first superconducting layer is located below the barrier layer and is partially exposed outside the barrier layer.

[0072] S5: Form an interlayer dielectric layer structure, the interlayer dielectric layer structure including a first dielectric layer and a second dielectric layer, the first dielectric layer filling the lead groove, the second dielectric layer being located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer is not less than 2 μm;

[0073] S6: Form a wiring layer, the wiring layer being located on the interlayer dielectric layer structure and the second superconducting layer and including a lead-out portion and an electrode portion, the lead-out portion being located on the interlayer dielectric layer structure, and the electrode portion protruding from the lead-out portion and extending along the first direction to the side of the second superconducting layer away from the lead-out portion;

[0074] S7: Etch the second superconducting layer again to remove the portion of the second superconducting layer exposed outside the electrode portion.

[0075] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0076] Please see Figures 2 to 5 Step S1: A substrate 101 is provided, and a first superconducting film 102, a barrier film 103, and a second superconducting film 104 are formed sequentially from bottom to top on the substrate 101. Figure 2 The image shown is a top view of the substrate 101 provided in the fabrication method of the Josephson junction in a superconducting quantum device according to Embodiment 1 of the present invention. Figure 3 Displayed as Figure 2 The structure shown is a cross-sectional view along the AA' direction. Figure 4 The image shown is a top view of the structure obtained after forming the first superconducting film 102, the barrier film 103, and the second superconducting film 104 in the fabrication method of the Josephson junction in Embodiment 1 of the present invention. Figure 5 Displayed as Figure 4 The structure shown is a cross-sectional view along the AA' direction.

[0077] As an example, the substrate 101 includes any one of a silicon substrate 101, a thermally oxidized silicon substrate 101, a magnesium oxide substrate 101, or a sapphire substrate 101.

[0078] As an example, the material of the first superconducting film 102 includes any one of niobium (Nb), tantalum (Ta), and niobium nitride (NbN), and the material of the second superconducting film 104 includes any one of niobium, tantalum, and niobium nitride.

[0079] As an example, the material of the barrier film 103 includes aluminum nitride (AlN), aluminum-aluminum nitride (Al-AlN), and aluminum-aluminum oxide (Al-AlO). x Any one of them.

[0080] As an example, before forming the first superconducting film 102, the barrier film 103 and the second superconducting film 104, a step of cleaning the substrate 101 is included to remove stains from the surface of the substrate 101.

[0081] As an example, the method for cleaning the substrate 101 includes either chemical cleaning or plasma cleaning.

[0082] Specifically, chemical cleaning includes methods such as concentrated sulfuric acid-hydrogen peroxide mixed solution cleaning and hydrofluoric acid cleaning, while plasma cleaning includes methods such as radio frequency glow discharge plasma cleaning and ion beam cleaning.

[0083] In this embodiment, the substrate 101 is a silicon substrate 101, and the substrate 101 is chemically cleaned, including the following steps:

[0084] (1) Preparation of cleaning solution: Mix 98% H2SO4 and 30% H2O2 in a ratio of 3:1 to prepare piranha solution.

[0085] (2) Piranha solution cleaning: After the above piranha solution is stabilized, heat it to 70 °C, and then put the silicon substrate 101 into the solution for cleaning for 20 min.

[0086] (3) First deionized water ultrasonic treatment: After cleaning, the silicon substrate 101 is placed in deionized water for ultrasonic treatment for 2 hours to remove the piranha solution remaining on the surface of the silicon substrate 101.

[0087] (4) First drying: After the ultrasonic treatment, the silicon substrate 101 is dried using a nitrogen gun.

[0088] (5) Buffered HF etching and cleaning: The silicon substrate 101 treated above is placed in a Buffered HF etching solution with an NH3-HF:HF ratio of 6:1 and cleaned for 10 min.

[0089] (6) Second deionized water ultrasonic treatment: After etching and cleaning, the silicon substrate 101 is placed in deionized water again for ultrasonic treatment for 2 hours to remove the residual etching solution on the surface of the substrate 101.

[0090] (7) Second drying: After ultrasonic treatment, the silicon substrate 101 is dried using a nitrogen gun.

[0091] (8) Equipment loading and vacuuming: The silicon substrate 101, after being cleaned and dried as described above, is quickly loaded into the sample tray of the multi-cavity magnetron sputtering equipment (including the Nb film sputtering chamber, the Al film sputtering chamber, and the oxide chamber). Then, the sample tray is placed into the sample inlet chamber of the equipment and the chamber door is closed. The sample inlet chamber is then evacuated to a vacuum level better than 2×10⁻⁶. -4 Pa.

[0092] As an example, the first superconducting film 102 is deposited on the substrate 101 using magnetron sputtering, specifically including the following steps:

[0093] (1) Load the substrate 101 into the sample injection chamber and evacuate it to 1×10⁻⁶. -4 Below Pa, the substrate 101 is then transferred to the superconducting metal coating chamber.

[0094] (2) Fix the substrate 101 in the superconducting metal film coating chamber, and evacuate the chamber to a vacuum level of 3×10⁻⁶. -5 Below Pa, adjust the process parameters such as the substrate 101 and the target spacing to preset values.

[0095] (3) Introduce working gas into the superconducting metal film coating chamber to maintain the pressure inside the chamber at a preset value.

[0096] (4) Use a baffle to block the area between the superconducting metal target and the substrate 101, and apply a set power to the target for pre-sputtering.

[0097] (5) Remove the baffle, maintain the set power to deposit the superconducting metal on the surface of the substrate 101, and after the preset deposition time is reached, turn off the input power and stop the process gas to complete the preparation of the first superconducting film.

[0098] As an example, the barrier film 103 is deposited on the substrate 101 using magnetron sputtering, specifically including the following steps:

[0099] (1) After the sample that has completed the preparation of the first superconducting film is cooled sufficiently, the sample is transferred to the coating chamber of the barrier film 103.

[0100] (2) Fix the sample in the barrier film 103 coating chamber and evacuate the chamber to 3×10⁻⁶. -5 Below Pa, adjust the process parameters such as the distance between the substrate 101 and the target or chemical vapor reaction source to preset values.

[0101] (3) Transfer the sample to the aluminum metal film coating chamber and evacuate the chamber to 3×10⁻⁶. -5 Below Pa, adjust the process parameters such as the spacing between the substrate 101 and the target to the preset values.

[0102] (4) Preparation of barrier film 103, specifically according to the selected barrier layer 106 material, is divided into the following three schemes:

[0103] ① Using aluminum nitride (AlN) film as barrier film material: Nitrogen-containing working gas is introduced into the aluminum metal film coating chamber to maintain the pressure in the chamber at a preset value; the relative area between the aluminum metal target and the substrate 101 is blocked by a baffle, and a set power is applied to the target for pre-sputtering; the baffle is removed, and the set power is maintained to deposit the aluminum nitride film on the surface of the lower film; after the preset deposition time is reached, the input power is turned off and the process gas is stopped to complete the preparation of the aluminum nitride barrier film.

[0104] ② Using an aluminum-aluminum nitride (Al-AlN) composite film as the barrier film material: A baffle is used to block the relative area between the aluminum metal target and the substrate 101, and a set power is applied to the target for pre-sputtering; the baffle is removed, and the set power is maintained to deposit the aluminum film onto the surface of the substrate 101; after the preset deposition time is reached, the input power is turned off and the process gas is stopped, completing the preparation of the aluminum metal film; after the sample is fully cooled in the chamber, a working gas containing nitrogen is introduced into the aluminum metal film deposition chamber to maintain the pressure inside the chamber at a preset value; the baffle is again used to block the relative area between the aluminum metal target and the substrate 101, and a set power is applied to the target for pre-sputtering; the baffle is removed again, and the set power is maintained to deposit the aluminum nitride film onto the surface of the lower aluminum film; after the preset deposition time is reached, the input power is turned off and the process gas is stopped, completing the preparation of the aluminum-aluminum nitride composite barrier film.

[0105] ③ Use aluminum-alumina (Al-AlO) x The composite film is used as a barrier film material: the relative area between the aluminum metal target and the substrate 101 is blocked by a baffle, and a set power is applied to the target for pre-sputtering; the baffle is removed, and the set power is maintained to deposit the aluminum film on the surface of the substrate 101; after the preset deposition time is reached, the input power is turned off and the process gas is stopped to complete the preparation of the aluminum metal film; after the sample is fully cooled in the chamber, the sample is transferred to the oxidation chamber; oxygen is introduced into the oxidation chamber to maintain the pressure in the chamber at a preset value; after the preset oxidation time is reached, the oxygen in the oxidation chamber is removed and the chamber vacuum environment is maintained again to complete the preparation of the aluminum-alumina composite barrier film.

[0106] Specifically, the above steps utilize a magnetron sputtering deposition equipment. This equipment should have at least two metal thin film deposition chambers and one oxidation chamber. One metal thin film deposition chamber should be equipped with a niobium (Nb) or tantalum (Ta) metal target, using an inert argon gas as the working gas, and powered by an energy source to prepare superconducting metal thin films such as niobium (Nb), tantalum (Ta), and niobium nitride (NbN). The other metal thin film deposition chamber should be equipped with an aluminum metal target, using an inert argon gas or an argon-nitrogen mixture as the working gas, and powered by an energy source to prepare aluminum metal thin films or directly prepare aluminum nitride barrier layer 106 thin films. The oxidation chamber is used to oxidize the aluminum metal thin film to form the barrier layer 106. The sample tray is transferred between the chambers under vacuum conditions via a sample transfer system. The background vacuum of the deposition chamber is below 4 × 10⁻⁶. -5 The current is 0.5 A to 10 A, the sputtering power is 100 W to 1000 W, the pressure is 0.3 Pa to 2 Pa, and the magnetron sputtering rate is 0.5 Å / s to 10 Å / s.

[0107] It should be noted that in the DC magnetron sputtering method, the magnetron sputtering equipment should also have a cooling function for the substrate 101, including but not limited to: water cooling of the substrate 101 backplane and helium blowing cooling of the sample surface. After each thin film is grown, the sample must be sufficiently cooled before the next thin film deposition step is performed.

[0108] As an example, the second superconducting film 104 is deposited on the substrate 101 using magnetron sputtering, specifically including the following steps:

[0109] (1) After the barrier film 103 is deposited, the sample is cooled sufficiently and then transferred to the superconducting metal film coating chamber.

[0110] (2) Evacuate the chamber to a vacuum level of 3×10⁻⁶. -5 Below Pa, adjust the process parameters such as the spacing between the substrate 101 and the target to preset values.

[0111] (3) Introduce working gas into the superconducting metal film coating chamber to maintain the pressure inside the chamber at a preset value.

[0112] (4) Use a baffle to block the area between the superconducting metal target and the substrate 101, and apply a set power to the target for pre-sputtering.

[0113] (5) Remove the baffle, maintain the set power to deposit the superconducting metal on the surface of the barrier film 103, and after the preset deposition time is reached, turn off the input power and stop the process gas to complete the preparation of the second superconducting film 104.

[0114] It should be noted that after the deposition of the first superconducting film 102, the barrier film 103, and the second superconducting film 104 are completed in sequence, the sample is cooled sufficiently and then needs to be transferred back to the sample injection chamber before nitrogen gas is introduced to break the vacuum in order to remove the sample.

[0115] As an example, the material combination of the first superconducting film 102, the barrier film 103, and the second superconducting film 104 includes Nb / Al-AlO. x / Nb, Nb / Al-AlN / Nb, NbN / AlN / NbN and Ta / Al-AlO x In this embodiment, the material combination of the first superconducting film 102, the barrier film 103, and the second superconducting film 104 is Nb / Al-AlO. x / Nb, its preparation includes the following steps:

[0116] (1) Preparation of the first Nb superconducting film: First, the substrate 101 sample is fixed in the Nb coating chamber, and the vacuum of the Nb coating chamber is evacuated to 3×10 -5Below Pa, adjust the distance between the substrate 101 and the target to a predetermined 50 mm. Next, introduce working gas into the Nb deposition chamber, maintaining the pressure in the Nb deposition chamber at 0.5 Pa. Then, use a baffle to shield the Nb target and the substrate 101, and apply a current of 1.5 A to the target to achieve a target power of 600 W for pre-sputtering for 1 min to clean the target surface. Finally, remove the baffle between the target and the substrate 101, so that the substrate 101 faces the target surface, and maintain a sputtering power of 600 W for sputtering deposition, allowing Nb metal to be sputtered from the target onto the substrate 101. After a predetermined sputtering time of 100 s, turn off the power input to the target and stop the process gas, completing the sputtering of the entire 150 nm thick Nb superconducting film.

[0117] (2) Preparation of Al-AlOx barrier layer film: First, after the sample is fully cooled for 20 min in the Nb sputtering chamber, it is transferred to the Al coating chamber. The substrate 101 sample is fixed in the Al coating chamber, and the vacuum of the Al coating chamber is evacuated to 4.5 × 10⁻⁶. -5 Below Pa, the distance between the substrate 101 and the target is adjusted to a predetermined 50 mm. Next, working gas is introduced into the Al deposition chamber, maintaining the pressure in the Al deposition chamber at 0.5 Pa. Then, a baffle is used to shield the Al target and the substrate 101, and a current of 0.3 A is applied to the target to achieve a target power of 115 W for pre-sputtering for 1 min to clean the target surface. Then, the baffle between the target and the substrate 101 is removed, so that the substrate 101 faces the target surface. Sputtering deposition is performed at a sputtering power of 115 W, allowing Al metal to be sputtered from the target onto the substrate 101. After a predetermined sputtering time of 40 s, the input power to the target is turned off, and the process gas is stopped, completing the sputtering of the entire 12 nm thick Nb superconducting thin film. Finally, the sample is thoroughly cooled in the Al sputtering chamber for 20 min and then transferred to the oxidation chamber. The oxidation chamber is allowed to cool to a vacuum level better than 1 × 10⁻⁶. -4 After passing through Pa, a mixed gas of 1% O2 and 99% Ar is introduced, and the pressure is adjusted to 2000 Pa. After timing for 210 seconds, the AlO2 process is complete. x The oxidation film formation was completed after cooling for 5 minutes. x Preparation of barrier layer film.

[0118] (3) Preparation of the second Nb superconducting film: First, the substrate 101 sample is fixed in the Nb coating chamber, and the vacuum of the Nb coating chamber is evacuated to 3×10 -5Below Pa, adjust the distance between the substrate 101 and the target to a predetermined 50 mm. Next, introduce working gas into the Nb deposition chamber, maintaining the pressure in the Nb deposition chamber at 0.5 Pa. Then, use a baffle to shield the Nb target and the substrate 101, and apply a current of 1.5 A to the target to achieve a target power of 600 W for pre-sputtering for 1 min to clean the target surface. Finally, remove the baffle between the target and the substrate 101, so that the substrate 101 faces the target surface, and maintain a sputtering power of 600 W for sputtering deposition, allowing Nb metal to be sputtered from the target onto the substrate 101. After a predetermined sputtering time of 100 s, turn off the input power to the target and stop the process gas, completing the sputtering of the entire 150 nm thick Nb superconducting film.

[0119] Please see again Figures 6 to 7 Step S2: Etch the second superconducting film 104 to form a second superconducting layer 105, wherein the second superconducting layer 105 is strip-shaped. Figure 6 The image shown is a top view of the structure obtained after forming the second superconducting layer 105 in the fabrication method of the Josephson junction in Embodiment 1 of the present invention. Figure 7 Displayed as Figure 6 The structure shown is a cross-sectional view along the AA' direction.

[0120] As an example, the second superconducting film 104 is patterned using exposure, development and etching techniques to prepare a long strip-shaped upper electrode pattern of the Josephson junction.

[0121] As an example, the thickness of the second superconducting layer 105 ranges from 50 nm to 250 nm.

[0122] Please see again Figures 8 to 9 Step S3: Etch the barrier film 103 to form a barrier layer 106, wherein the barrier layer 106 is partially exposed outside the second superconducting layer 105, and the shortest distance D1 between the outer edge of the barrier layer 106 and the outer edge of the second superconducting layer 105 is not less than 1 μm. Figure 8 The image shown is a top view of the structure obtained after forming barrier layer 106 in the fabrication method of superconducting quantum devices according to Embodiment 1 of the present invention. Figure 9 Displayed as Figure 8 The structure shown is a cross-sectional view along the AA' direction.

[0123] As an example, the barrier film 103 is patterned using an exposure, development and etching technique to prepare the barrier layer 106 pattern of the Josephson junction.

[0124] As an example, the thickness of the barrier layer 106 ranges from 2 nm to 20 nm.

[0125] Please see again Figures 10 to 11 Step S4: Etch the first superconducting film 102 to form a lead groove 1021 and a first superconducting layer 1022. The lead groove 1021 is located on one side of the first superconducting layer 1022 and exposes the substrate 101. The first superconducting layer 1022 is located below the barrier layer 106 and partially exposed outside the barrier layer 106. Figure 10 The image shown is a top view of the structure obtained after forming the lead groove 1021 and the second superconducting layer 105 in the fabrication method of the Josephson junction in the superconducting quantum device according to Embodiment 1 of the present invention. Figure 11 Displayed as Figure 10 The structure shown is a cross-sectional view along the AA' direction.

[0126] As an example, the first superconducting film 102 is patterned using exposure, development and etching techniques to prepare the first superconducting layer 1022 pattern of the Josephson junction.

[0127] As an example, the thickness of the first superconducting layer 1022 ranges from 50 nm to 250 nm.

[0128] Please see again Figures 14 to 15 Step S5: Form an interlayer dielectric layer structure 108, which includes a first dielectric layer 1081 and a second dielectric layer 1082. The first dielectric layer 1081 fills the lead groove 1021. The second dielectric layer 1082 is located on the first superconducting layer 1022 and surrounds the barrier layer 106 and the second superconducting layer 105. The shortest distance D2 between the outer edge of the second dielectric layer 1082 and the outer edge of the barrier layer 106 is not less than 2 μm. For example, the shortest distance D2 between the outer edge of the second dielectric layer 1082 and the outer edge of the barrier layer 106 is 4 μm, 6 μm, 8 μm, 10 μm, 15 μm, 18 μm, 20 μm, 30 μm, or 50 μm. Figure 14 The image shown is a top view of the structure obtained after forming the interlayer dielectric layer structure 108 in the fabrication method of the Josephson junction in the superconducting quantum device according to Embodiment 1 of the present invention. Figure 15 Displayed as Figure 14 The structure shown is a cross-sectional view along the AA' direction.

[0129] Specifically, the presence of the interlayer dielectric layer structure 108 reduces the coverage area of ​​the dielectric material, thereby reducing the dielectric loss of the superconducting quantum device based on the Josephson junction, improving the performance of the superconducting quantum device based on the Josephson junction, and meeting the needs of superconducting quantum technology.

[0130] As an example, the thickness of the first dielectric layer 1081 is in the range of 500 nm to 1000 nm, and the thickness of the second dielectric layer 1082 is in the range of 500 nm to 1000 nm.

[0131] As an example, forming the interlayer dielectric layer structure 108 includes the following steps:

[0132] (1) Please refer to Figures 12 to 13 An interlayer dielectric film 107 is formed, which covers the second superconducting layer 105, the barrier layer 106, the first superconducting layer 1022, and the substrate 101. Figure 12 The image shown is a top view of the structure obtained after forming the interlayer dielectric film 107 in the fabrication method of the Josephson junction in the superconducting quantum device according to Embodiment 1 of the present invention. Figure 13 Displayed as Figure 12 The structure shown is a cross-sectional view along the AA' direction.

[0133] Specifically, the interlayer dielectric film 107 is prepared using chemical vapor deposition equipment or magnetron sputtering equipment, and the material of the interlayer dielectric film 107 includes any one of silicon monoxide, silicon dioxide, aluminum oxide, aluminum nitride, silicon carbide, or silicon nitride.

[0134] As an example, the material of the interlayer dielectric film 107 includes any one of silicon monoxide (SiO), silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), and silicon nitride (SiN).

[0135] (2) Thin the interlayer dielectric film 107 in the direction from the second superconducting layer 105 to the barrier layer 106 so that the interlayer dielectric film 107 exposes the upper surface of the second superconducting layer 105.

[0136] Specifically, the interlayer dielectric film 107 is polished using chemical mechanical polishing technology to achieve planarization. The planarization process is precisely monitored using endpoint monitoring technologies such as optical interference and friction torque measurement until the interlayer dielectric film 107 on the upper surface of the first superconducting layer 1022 is completely removed, thus fully exposing the upper surface of the first superconducting layer 1022.

[0137] (3) Etch the interlayer dielectric film 107, retain a portion of the interlayer dielectric film 107 filling the lead groove 1021 to form the first dielectric layer 1081, and retain a portion of the interlayer dielectric film 107 located on the first superconducting layer 1022 and surrounding the barrier layer 106 and the second superconducting layer 105 to form the second dielectric layer 1082.

[0138] Specifically, the interlayer dielectric film 107 is processed using an exposure, development and etching technique to etch away the Josephson junction region and other interlayer dielectric films 107 outside of it, forming the interlayer dielectric layer structure 108.

[0139] Please see again Figures 18 to 19 Step S6: Forming a wiring layer 110, the wiring layer 110 being located on the interlayer dielectric layer structure 108 and the second superconducting layer 105 and including a lead-out portion 1101 and an electrode portion 1102. The lead-out portion 1101 is located on the interlayer dielectric layer structure 108, and the electrode portion 1102 protrudes from the lead-out portion 1101 and extends along the first direction to the side of the second superconducting layer 105 away from the lead-out portion 1101. Figure 18 The image shown is a top view of the structure obtained by forming the wiring layer 110 and removing the portion of the second superconducting layer 105 exposed outside the electrode portion 1102 in the fabrication method of the Josephson junction in Embodiment 1 of the present invention. Figure 19 Displayed as Figure 18 The structure shown is a cross-sectional view along the AA' direction.

[0140] Specifically, the overlapping region of the electrode portion 1102, the second superconducting layer 105, the barrier layer 106, and the first superconducting layer 1022 is the Josephson junction region.

[0141] As an example, forming the wiring layer 110 includes the following steps:

[0142] (1) Please refer to Figures 16 to 17 A metal layer 109 is formed, which covers the second dielectric layer 1082, the second superconducting layer 105, the barrier layer 106, the first superconducting layer 1022, and the substrate 101, wherein... Figure 16 The image shown is a top view of the structure obtained after forming metal layer 109 in the fabrication method of superconducting quantum devices according to Embodiment 1 of the present invention. Figure 17 Displayed as Figure 16 The structure shown is a cross-sectional view along the AA' direction.

[0143] Specifically, the metal layer 109 is prepared using a magnetron sputtering apparatus, and the material of the metal layer 109 includes any one of niobium (Nb), niobium nitride (NbN), or tantalum (Ta).

[0144] (2) Etch the metal layer 109 to form the wiring layer 110.

[0145] Specifically, the metal layer 109 is processed using a combination of exposure, development and etching techniques to etch out a long strip pattern of the wiring layer 110 perpendicular to the Josephson junction region.

[0146] Please see again Figure 2 Step S7: Etch the second superconducting layer 105 again to remove the portion of the second superconducting layer 105 exposed outside the electrode portion 1102, so as to expose the lower portion of the barrier layer 106.

[0147] Please refer to the following: Figures 18 to 19 A Josephson junction superconducting quantum device was fabricated, comprising: a substrate 101, a first superconducting film 102, a barrier layer 106, a second superconducting layer 105, an interlayer dielectric structure 108, and a wiring layer 110. The first superconducting film 102 covers the substrate 101 and has a lead groove 1021 and a first superconducting layer 1022 within it. The lead groove 1021 is located on one side of the first superconducting layer 1022 and exposes the substrate 101. The barrier layer 106 is located on the first superconducting layer 1022, and the second superconducting layer 105 is located on the barrier layer 106 and partially exposes the barrier layer 106. The shortest distance between the outer edge of the barrier layer 106 and the outer edge of the second superconducting layer 105 is not less than 1. The interlayer dielectric structure 108, with a diameter of μm, includes a first dielectric layer 1081 and a second dielectric layer 1082. The first dielectric layer 1081 fills the lead groove 1021. The second dielectric layer 1082 is located on the first superconducting layer 1022, and surrounds the barrier layer 106 and encircles the second superconducting layer 105. There is a predetermined distance between the inner edge of the second dielectric layer 1082 and the outer edge of the second superconducting layer 105. The shortest distance between the outer edge of the second dielectric layer 1082 and the outer edge of the barrier layer 106 is not less than 2 μm. μm, the wiring layer 110 is located on the interlayer dielectric layer structure 108 and the second superconducting layer 105 and includes a lead-out portion 1101 and an electrode portion 1102. The lead-out portion 1101 is located on the interlayer dielectric layer structure 108, and the electrode portion 1102 protrudes from the lead-out portion 1101 and extends along the first direction to the side of the second superconducting layer 105 away from the lead-out portion 1101. The first direction is from the lead-out groove to the first superconducting layer 1022.

[0148] The method for fabricating Josephson junction superconducting quantum devices in this embodiment reduces the area of ​​the interlayer dielectric layer through the design of the interlayer dielectric layer structure, thereby reducing the dielectric loss in the superconducting quantum devices fabricated in the Josephson junction and improving the performance of the superconducting quantum devices.

[0149] Example 2

[0150] This embodiment provides another method for fabricating a Josephson junction superconducting quantum device. The fabrication method in this embodiment is basically the same as that in Embodiment 1, except that:

[0151] After etching the first superconducting film 102, a pair of capacitor plates 1023 distributed on both sides of the first dielectric layer 1081 are formed on the substrate 101. One of the capacitor plates 1023 is electrically connected to the first superconducting layer 1022, and the other capacitor plate 1023 is electrically connected to the lead-out portion 1101 of the wiring layer 110.

[0152] By following the steps above, another type of Josephson junction superconducting quantum device can be fabricated. Please refer to [link to documentation]. Figure 20 The Josephson junction superconducting quantum device structure in this embodiment is basically the same as that in Embodiment 1, except that:

[0153] The first superconducting film 102 is further provided with a pair of capacitor plates 1023 distributed on both sides of the first dielectric layer 1081, wherein one capacitor plate 1023 is electrically connected to the first superconducting layer 1022, and the other capacitor plate 1023 is electrically connected to the lead-out portion 1101 of the wiring layer 110.

[0154] The fabrication method of the Josephson junction superconducting quantum device in this embodiment also reduces the area of ​​the interlayer dielectric layer. The fabricated Josephson junction superconducting quantum device has low dielectric loss and high performance, which can meet the requirements of superconducting quantum technology.

[0155] In summary, the fabrication method of the Josephson junction superconducting quantum device of the present invention includes the following steps: providing a substrate, and sequentially forming a first superconducting film, a barrier film, and a second superconducting film on the substrate from bottom to top; etching the second superconducting film to form a second superconducting layer, the second superconducting layer being strip-shaped; etching the barrier film to form a barrier layer, the barrier layer being partially exposed outside the second superconducting layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer being not less than 1 μm; etching the first superconducting film to form a lead groove and a first superconducting layer, the lead groove being located on one side of the first superconducting layer and exposing the substrate, the first superconducting layer being located below the barrier layer and partially exposed outside the barrier layer; forming an interlayer dielectric layer structure, the interlayer dielectric layer structure including a first dielectric layer and a second dielectric layer, the first dielectric layer filling the lead groove, the second dielectric layer being located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer being not less than 2 μm. μm; a wiring layer is formed, which is located on the interlayer dielectric layer structure and the second superconducting layer and includes an outlet portion and an electrode portion. The outlet portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the outlet portion and extends along a first direction to the side of the second superconducting layer away from the outlet portion; the second superconducting layer is etched again to remove the portion of the second superconducting layer exposed outside the electrode portion. The fabrication method of the Josephson junction superconducting quantum device of the present invention can reduce the dielectric loss in the Josephson junction superconducting quantum device, improve the performance of the Josephson junction superconducting quantum device, and broaden the application of the three-layer film structure Josephson junction in superconducting quantum devices, meeting the needs of superconducting quantum technology. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0156] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a Josephson junction superconducting quantum device, characterized in that, Includes the following steps: A substrate is provided, and a first superconducting film, a barrier film, and a second superconducting film are formed sequentially from bottom to top on the substrate; The second superconducting film is etched to form a second superconducting layer, the second superconducting layer being strip-shaped; The barrier film is etched to form a barrier layer, the barrier layer being partially exposed outside the second superconducting layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer is not less than 1 μm; The first superconducting film is etched to form a lead groove and a first superconducting layer. The lead groove is located on one side of the first superconducting layer and exposes the substrate. The first superconducting layer is located below the barrier layer and is partially exposed outside the barrier layer. An interlayer dielectric layer structure is formed, the interlayer dielectric layer structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer fills the lead groove, the second dielectric layer is located on the first superconducting layer and surrounds the barrier layer and the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer is not less than 2 μm; A wiring layer is formed, which is located on the interlayer dielectric layer structure and the second superconducting layer and includes a lead-out portion and an electrode portion. The lead-out portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the lead-out portion and extends along the first direction to the side of the second superconducting layer away from the lead-out portion. The second superconducting layer is etched again to remove the portion of the second superconducting layer exposed outside the electrode portion.

2. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that: The substrate includes any one of a silicon substrate, a thermally oxidized silicon substrate, a magnesium oxide substrate, or a sapphire substrate.

3. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that: After etching the first superconducting film, a pair of capacitor plates distributed on both sides of the first dielectric layer are formed on the substrate, wherein one capacitor plate is electrically connected to the first superconducting layer, and the other capacitor plate is electrically connected to the lead-out portion of the wiring layer.

4. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that: The thickness of the first superconducting layer ranges from 50 nm to 250 nm, the thickness of the barrier layer ranges from 2 nm to 20 nm, and the thickness of the second superconducting layer ranges from 50 nm to 250 nm.

5. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that: The material combination of the first superconducting film, the barrier film, and the second superconducting film includes Nb / Al-AlO. x / Nb, Nb / Al-AlN / Nb, NbN / AlN / NbN and Ta / Al-AlO x / Ta.

6. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that, Forming the interlayer dielectric layer structure includes the following steps: An interlayer dielectric film is formed, wherein the interlayer dielectric layer covers the second superconducting layer, the barrier layer, the first superconducting layer, and the substrate; The interlayer dielectric film is thinned along the direction from the second superconducting layer to the barrier layer, so that the interlayer dielectric film exposes the upper surface of the second superconducting layer; The interlayer dielectric film is etched, and a portion of the interlayer dielectric film filling the lead groove is retained to form the first dielectric layer. A portion of the interlayer dielectric film located on the first superconducting layer and surrounding the barrier layer and the second superconducting layer is retained to form the second dielectric layer.

7. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that: The thickness of the first dielectric layer ranges from 500 nm to 1000 nm, and the thickness of the second dielectric layer ranges from 500 nm to 1000 nm.

8. The method for fabricating the Josephson junction superconducting quantum device according to claim 1, characterized in that, Forming the wiring layer includes the following steps: A metal layer is formed, which covers the second dielectric layer, the second superconducting layer, the barrier layer, the first superconducting layer, and the substrate; The metal layer is etched to form the wiring layer.

9. A Josephson junction superconducting quantum device, characterized in that, include: Substrate; A first superconducting film is covered on the substrate. The first superconducting film includes a lead groove and a first superconducting layer. The lead groove is located on one side of the first superconducting layer and exposes the substrate. A barrier layer is located on the first superconducting layer; The second superconducting layer is located on the barrier layer and exposes part of the barrier layer, and the shortest distance between the outer edge of the barrier layer and the outer edge of the second superconducting layer is not less than 1 μm; An interlayer dielectric layer structure is provided, comprising a first dielectric layer and a second dielectric layer. The first dielectric layer is filled in the lead groove, and the second dielectric layer is located on the first superconducting layer, surrounding the barrier layer and encircling the second superconducting layer. There is a predetermined distance between the inner edge of the second dielectric layer and the outer edge of the second superconducting layer, and the shortest distance between the outer edge of the second dielectric layer and the outer edge of the barrier layer is not less than 2 μm. A wiring layer is located on the interlayer dielectric layer structure and the second superconducting layer and includes a lead-out portion and an electrode portion. The lead-out portion is located on the interlayer dielectric layer structure, and the electrode portion protrudes from the lead-out portion and extends along the first direction to the side of the second superconducting layer away from the lead-out portion. The first direction is from the lead-out groove to the first superconducting layer.

10. The Josephson junction superconducting quantum device according to claim 9, characterized in that: The first superconducting film also includes a pair of capacitor plates distributed on both sides of the first dielectric layer, wherein one capacitor plate is electrically connected to the first superconducting layer and the other capacitor plate is electrically connected to the lead-out portion of the wiring layer.

Images