Low-temperature atomic layer etching using rare gases
By using rare gases to form an inert layer and a fluorine-containing layer at low temperatures, and then using an energy source to activate and form a passivation layer, the problems of etching inhomogeneity and insufficient selectivity in low-temperature etching are solved, achieving vertical etching with high aspect ratio features and good control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2021-04-26
- Publication Date
- 2026-06-02
AI Technical Summary
Existing low-temperature etching techniques struggle to uniformly etch high aspect ratio features at low temperatures, leading to loss of critical feature size and etching inhomogeneity, particularly due to insufficient selectivity between silicon and silicon dioxide.
An inert layer is formed at low temperature using a rare gas, followed by a passivation layer formed using a fluorine-containing gas. This passivation layer is then activated by an energy source, and finally, anisotropic etching is achieved by ion etching of the substrate surface.
It effectively protects the sidewalls at low temperatures, prevents over-etching, improves etching selectivity and uniformity, and ensures vertical sidewalls and good control for high aspect ratio features.
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Figure CN122138633A_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application (PCT application number PCT / US2021 / 029214) filed on April 26, 2021, with application number 202180042877.5 and entitled "Low-Temperature Atomic Layer Etching Using Rare Gases". Technical Field
[0002] This disclosure generally relates to a method for etching using rare gases at low temperatures. Background Technology
[0003] Reliably manufacturing nanometer-sized and smaller features is one of the technological challenges of next-generation ultra-large-scale integration (VLSI) and very large-scale integration (ULSI) for semiconductor devices. However, as circuit technology pushes its limits, the shrinking size of VLSI and ULSI interconnect technologies places additional demands on processing power. Reliably forming gate structures on substrates is crucial for implementing VLSI and ULSI and for continued efforts to increase circuit density with the quality of individual substrates and chips.
[0004] To reduce manufacturing costs, integrated circuit (IC) manufacturers demand higher throughput and better device yields and performance per silicon substrate processed. Some manufacturing techniques currently under development for next-generation devices involve processing at cryogenic temperatures. Dry reactive ion etching of substrates uniformly maintained at cryogenic temperatures allows ions to bombard the upper surface of the material disposed on the substrate with reduced spontaneous etching, resulting in trenches with smooth, vertical sidewalls. Furthermore, cryogenic temperatures can improve the selectivity of etching one material relative to another. For example, the selectivity between silicon (Si) and silicon dioxide (SiO2) increases exponentially with decreasing temperature.
[0005] Conventional low-temperature fluorine-based etching processes tend to etch isotropically, which can lead to over-etching of the sidewalls of high aspect ratio features, resulting in loss of critical dimensions. One solution to protect the sidewalls from over-etching involves forming a passivation layer on the sidewalls, allowing the bottom portion of the feature to be bombarded by ions while the sidewalls remain protected by the passivation layer. However, it is often difficult to balance the ratio of etching gas to passivation layer forming gas to properly control the passivation rate and etch rate. Furthermore, the passivation rate and etch rate vary with aspect ratio, adding further challenges to achieving consistent and uniform etching of various structures of different sizes on a chip.
[0006] Therefore, an improved method for etching at low temperatures is needed. Summary of the Invention
[0007] This disclosure generally relates to a method for etching using rare gases at low temperatures.
[0008] In one aspect, a method for etching features in a substrate is provided. The method includes: cooling the substrate positioned in a chamber to a temperature below the triple point temperature of a first rare gas. The method further includes: allowing the first rare gas to flow into the chamber to form an inert layer on a plurality of exposed portions of the substrate. The method further includes: allowing a fluorinated precursor gas to flow into the chamber to form a fluorinated layer on the inert layer. The method further includes: exposing the fluorinated layer and the inert layer to an energy source to form a passivation layer on the plurality of exposed portions of the substrate, and exposing the substrate to ions to etch the substrate.
[0009] Multiple embodiments may include one or more of the following. The temperature may be from about -105 degrees Celsius to about -120 degrees Celsius. The first rare gas may be selected from xenon and krypton. The fluorine-containing precursor gas may be selected from SF6, NF3, and F2. Exposing the substrate to ions may further include: applying an RF bias voltage to the substrate, and forming ions by a second rare gas. The second rare gas may be selected from helium, neon, argon, and xenon. The substrate may include a silicon oxide layer disposed on a silicon layer.
[0010] In another aspect, a method for etching features in a substrate is provided. The method includes: receiving a silicon-component substrate on a substrate support in a chamber, the substrate support having a cooler operable to cool the substrate. The method further includes: cooling the substrate by cooling the cooler to a temperature of about -100 degrees Celsius or lower. The method further includes: infusing a xenon precursor gas into the chamber to coat a plurality of portions of the surface of the silicon with a xenon layer. The method further includes: infusing a fluorine-containing precursor gas into the chamber to coat the xenon layer with a fluorine-containing layer. The method further includes: exposing the xenon layer and the fluorine-containing layer to an energy source to form a xenon fluoride passivation layer, and exposing the substrate to ions to etch silicon from the surface of the silicon.
[0011] Multiple implementations may include one or more of the following: The temperature may be from about -105 degrees Celsius to about -120 degrees Celsius. The fluorine-containing precursor gas may be selected from SF6, NF3, and F2. Exposing the substrate to ions may further include: applying an RF bias voltage to electrodes in a substrate support, and allowing a rare gas to flow into the chamber. The rare gas may be helium. A xenon fluoride passivation layer may be formed on a plurality of sidewalls of the feature formed in the substrate, and the xenon fluoride passivation layer prevents or slows down lateral etching of the feature when the feature is etched in the substrate in a vertical direction. A silicon oxide layer may be formed on at least a portion of the silicon. The substrate may have at least one feature extending from a top surface of the substrate to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall, wherein the passivation layer is formed on the top surface of the substrate, the first sidewall, the second sidewall, and the bottom surface of the at least one feature.
[0012] In another aspect, a method for etching features in a substrate is provided. The method includes: receiving a silicon-component substrate on a substrate support in a chamber, the substrate having a substrate surface and at least one feature formed on the substrate, the at least one feature extending from the substrate surface and having a plurality of sidewalls and a bottom surface, the substrate support having a cooler operable to cool the substrate. The method further includes: cooling the substrate by cooling the cooler to a temperature of about -100 degrees Celsius or lower. The method further includes: forming a passivation layer over the substrate surface, the plurality of sidewalls of the at least one feature, and the bottom surface. Forming the passivation layer includes: infusing a xenon precursor gas into the chamber to coat a plurality of portions of the substrate surface with a xenon layer; infusing a fluorine-containing precursor gas into the chamber to coat the xenon layer with a fluorine-containing layer; and exposing the xenon layer and the fluorine-containing layer to plasma to form the passivation layer. The method further includes: exposing the substrate to ions to etch silicon from the bottom surface.
[0013] Multiple implementations may include one or more of the following: The temperature may be from about -105 degrees Celsius to about -120 degrees Celsius. The fluorine-containing precursor gas may be selected from SF6, NF3, and F2. Exposing the substrate to ions further includes: applying an RF bias voltage to electrodes in the substrate support, and allowing a rare gas to flow into the chamber. The rare gas may be helium.
[0014] In another aspect, a non-transitory computer-readable medium has instructions stored thereon that, when executed by a processor, cause the process to perform the operations described above. Attached Figure Description
[0015] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the embodiments briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as other equivalent embodiments are permissible.
[0016] Figure 1 A cross-sectional view of an example plasma processing chamber according to various aspects disclosed herein is shown.
[0017] Figure 2 A flowchart illustrating a method for etching features in a substrate according to aspects disclosed herein.
[0018] Figures 3A to 3E The various stages of the etching process according to the aspects disclosed herein are shown.
[0019] For ease of understanding, the same reference numerals are used where possible to designate common elements in the figures. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. Detailed Implementation
[0020] The following disclosure describes the low-temperature etching of the features. Certain details are described below and... Figures 1 to 3E The following descriptions are provided to provide a thorough understanding of the various embodiments of this disclosure. Further details describing known structures and systems commonly associated with cryogenic etching are not presented in the following disclosure to avoid unnecessarily obscuring the descriptions of the various embodiments. Furthermore, the device descriptions herein are illustrative and should not be construed as limiting the scope of the embodiments described herein.
[0021] The numerous details, operations, dimensions, angles, and other features shown in the accompanying drawings are merely illustrative of particular embodiments. Therefore, other embodiments can have different details, components, dimensions, angles, and features without departing from the spirit or scope of this disclosure. Furthermore, further embodiments of this disclosure can be practiced without the many details described below.
[0022] The feature is a recess in the surface of the substrate. The feature can have many different shapes, including but not limited to cylindrical, elliptical, rectangular, square, other polygonal recesses, and grooves.
[0023] Aspect ratio is a comparison of the depth of a feature to its critical dimension (e.g., width / diameter). Features formed by the disclosed methods can be high aspect ratio features. In some embodiments, a high aspect ratio feature is a feature having an aspect ratio of at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100. The critical dimension of a feature formed by the disclosed methods can be about 200 nm or less, for example, about 100 nm or less, about 50 nm or less, or about 20 nm or less.
[0024] In some etching processes, cryogenic etching (such as cryogenic etching) is used to remove material from devices with high aspect ratio (HAR) features at cold temperatures. Cryogenic etching cools the device during the etching process to prevent unwanted side reactions that can affect the etch profile of the feature. Conventional cryogenic fluorine-based etching processes tend to etch isotropically, which can over-etch the sidewalls of the feature, leading to loss of critical size. One solution to protect the sidewalls from over-etching is to use oxygen to passivate the silicon sidewalls of the feature. Oxygen reacts with the silicon sidewalls to form a silicon oxide passivation layer, allowing the bottom portion of the feature to be bombarded by ions while the sidewalls are protected by the silicon oxide passivation layer. However, it is difficult to balance the ratio of fluorine to oxygen to control the passivation rate and etch rate. Furthermore, the passivation rate and etch rate change with the aspect ratio, making it difficult to achieve consistent and uniform etching of multiple structures with different aspect ratios on the same chip. Further, the formation of the silicon oxide passivation layer consumes silicon from the sidewalls of the feature, which can affect the critical size of the feature.
[0025] In one aspect of this disclosure, a method for etching at low temperatures is provided. The method involves forming an inert layer with a rare gas on an exposed surface, such as the sidewalls of a feature, to passivate the sidewalls prior to the etching process. The inert layer inhibits spontaneous etching, thereby enabling the etching of HAR features using aggressive chemistry such as fluorine.
[0026] In one embodiment, the substrate containing the feature is cooled to a temperature near the triple point of the rare gas. While not bound by theory, it is believed that cooling the substrate to a temperature near the triple point of the rare gas allows the condensed rare gas to flow through surface dispersion forces and passivates the exposed surfaces of the feature. Unlike oxygen passivation, the inert layer does not consume silicon as in known oxygen-based processes. The substrate is then exposed to a fluorine-containing gas to form a fluorine-containing layer on the inert layer. The presence of the inert layer prevents the fluorine-containing gas from etching the feature. The inert layer and the fluorine-containing layer are then exposed to an energy source (such as plasma or ultraviolet photon activation) to form a passivation layer from the inert layer and the fluorine-containing layer. The substrate is then exposed to ions to anisotropically etch material from the upper surface of the substrate.
[0027] Figure 1 This is a schematic cross-sectional view of an example plasma processing chamber 100, shown configured as an etching chamber, having a substrate support assembly 101. The plasma processing chamber 100 is capable of performing the cryogenic etching process described herein. The substrate support assembly 101 is operable to uniformly maintain a surface or workpiece (such as substrate 300) at a cryogenic processing temperature. Dry reactive ion etching of substrate 300, maintained at a cryogenic processing temperature, allows ions to bombard the upper surface of the material disposed on substrate 300 with reduced spontaneous etching, resulting in the formation of trenches with smooth, vertical sidewalls. For example, as ions continue to bombard the upper surface of the low-k dielectric material, diffusion of ions in the pores of the low-k dielectric material disposed on substrate 300, uniformly maintained at a cryogenic processing temperature, is reduced to form trenches with smooth, vertical sidewalls. Furthermore, the selectivity of etching one material relative to another can be improved at cryogenic processing temperatures. For example, the selectivity between silicon (Si) and silicon dioxide (SiO2) increases exponentially with decreasing temperature.
[0028] The plasma processing chamber 100 includes a chamber body 102 having sidewalls 104, a bottom 106, and a cover 108 surrounding a processing region 110. An injection device 112 is coupled to the sidewalls 104 and / or the cover 108 of the chamber body 102. A gas panel 114 is coupled to the injection device 112 to allow processing gas to be supplied to the processing region 110. The injection device 112 may be one or more nozzles or inlet ports, or alternatively, a nozzle. The processing gas, along with any processing byproducts, is removed from the processing region 110 through an exhaust port 116 formed in the sidewalls 104 or the bottom 106 of the chamber body 102. The exhaust port 116 is coupled to a pumping system 127, which includes a throttle valve and a pump for controlling the vacuum level within the processing region 110.
[0029] The process gas can be excited to form plasma within the processing region 110. The process gas can be excited by capacitively or inductively coupling an RF power source to it. A plurality of coils 118 are disposed above the cover 108 of the plasma processing chamber 100 and coupled to an RF power supply 122 via a matching circuit 120. The RF power supply 122 can be low-frequency, high-frequency, or ultra-high-frequency.
[0030] A substrate support assembly 101 is disposed in the processing area 110 below the injection unit 112. The substrate support assembly 101 includes an ESC 103 and an ESC base assembly 105. The ESC base assembly 105 is coupled to the ESC 103 and a facility plate 107. The facility plate 107 is supported by a ground plane 111 and configured to facilitate electrical, cooling, heating, and gas connections with the substrate support assembly 101. The ground plane 111 is supported by a bottom 106 of the processing chamber. An insulating plate 109 insulates the facility plate 107 from the ground plane 111.
[0031] ESC base assembly 105 includes a base channel 115 coupled to a cryogenic cooler 117. The cryogenic cooler 117 provides a base fluid (such as a refrigerant) to the base channel 115, thereby maintaining the ESC base assembly 105 at a predetermined cryogenic temperature, and thus the substrate 300 at a predetermined cryogenic temperature. Similarly, facility plate 107 includes a facility channel 113 coupled to a cooler 119. The cooler 119 provides facility fluid to the facility channel 113, thereby maintaining the facility plate 107 at a predetermined temperature. In one example, the base fluid maintains the ESC base assembly 105 at a temperature higher than that of the facility plate 107. In one aspect, which may be combined with other aspects described herein, the cryogenic cooler 117 is coupled to an interface box to control the flow rate of the base fluid. The base fluid contains components that remain liquid at cryogenic temperatures below -50 degrees Celsius at operating pressures. The base fluid is generally insulating, such that no electrical path is formed through the base fluid when circulating through the substrate support assembly 101. Non-limiting examples of suitable facility fluids include fluorinated heat transfer fluids.
[0032] ESC 103 has a support surface 130 and a bottom surface 132 opposite to the support surface 130. ESC 103 can be made of ceramic materials, such as alumina (Al2O3), aluminum nitride (AlN), or other suitable materials or polymers, such as polyimide, polyether ether ketone (PEEK), polyarylether ether ketone (PAEK), etc.
[0033] ESC 103 includes an adsorption electrode 126 disposed within ESC 103. The adsorption electrode 126 may be configured as a monopolar or bipolar electrode, or other suitable arrangement. The adsorption electrode 126 is coupled to a facility plate 107 via an RF filter to an adsorption power supply 134, which provides DC power to electrostatically attach the substrate 300 to a support surface 130 of ESC 103. The RF filter prevents damage to electrical equipment or the presentation of electrical hazards outside the plasma processing chamber 100 from the RF power used for plasma generation (not shown).
[0034] ESC 103 includes one or more resistance heaters 128 embedded within it. The resistance heaters 128 control the temperature of ESC 103, which is cooled by ESC base assembly 105, to maintain a cryogenic processing temperature suitable for processing a substrate 300 disposed on the support surface 130 of substrate support assembly 101. The resistance heaters 128 are coupled to a heater power supply 136 via facility plate 107 and an RF filter. The RF filter prevents RF power used to form plasma (not shown) within the plasma processing chamber 100 from damaging electrical equipment or posing an electrical hazard outside the chamber. The heater power supply 136 can provide 500 watts or more of power to the resistance heaters 128. The heater power supply 136 includes a controller (not shown) for controlling the operation of the heater power supply 136, which is typically configured to heat the substrate 300 to a predetermined cryogenic temperature. In one aspect that can be combined with other aspects described herein, the resistance heater 128 includes a plurality of laterally separated heating blocks, wherein a controller enables at least one block of the resistance heater 128 to be preferentially heated relative to one or more of the remaining blocks. For example, the resistance heater 128 may be concentrically arranged in the plurality of separate heating blocks. The resistance heater 128 maintains the substrate 300 at a cryogenic processing temperature suitable for processing. In one aspect that can be combined with other aspects described herein, the cryogenic processing temperature is below about -10 degrees Celsius. For example, the cryogenic processing temperature is between about -10 degrees Celsius and about -150 degrees Celsius.
[0035] The plasma processing chamber 100 further includes a system controller 160 operable to control various aspects of the plasma processing chamber 100. The system controller 160 facilitates control and automation of the entire plasma processing chamber 100 and may include a central processing unit (CPU), memory, and support circuitry (or I / O). Software instructions and data may be encoded and stored in memory to instruct the CPU. The system controller 160 is capable of communicating with one or more components of the plasma processing chamber 100 via, for example, a system bus. A program (or computer instructions) readable by the system controller 160 determines which tasks can be performed on the substrate. In some aspects, the program is software readable by the system controller 160, which may include code for controlling one or more components of the plasma processing chamber 100. Although a single system controller 160 is shown in the figures, it should be understood that multiple system controllers may be used in conjunction with the aspects described herein.
[0036] Figure 2 A flowchart illustrating a method 200 for etching features in a substrate according to aspects disclosed herein. Figures 3A to 3EThe various stages of the etching process according to the aspects disclosed herein are shown. Although method 200 and Figures 3A to 3E This discussion is in the context of etching high aspect ratio features in a silicon substrate, but it should be understood that method 200 can be used to etch other features in other types of substrates.
[0037] Method 200 begins with operation 210, loading a substrate into a chamber, such as... Figure 1 The plasma processing chamber 100 is depicted in the image. In one example, a substrate 300 is positioned on a substrate support assembly (such as substrate support assembly 101) having a cooler (such as cooler 119) operable to cool the substrate. The substrate can be substrate 300. Substrate 300 includes a bulk silicon layer 310 on which a mask layer 312, such as a dielectric layer, such as a silicon oxide layer, is disposed. Substrate 300 without mask layer 312 (i.e., only silicon layer 310) can also be processed according to method 200. Substrate 300 has at least one feature 320 formed on substrate 300. At least one feature 320 extends a feature depth from top surface 322 of substrate 300 to bottom surface 324. At least one feature 320 has a width defined by a first sidewall 326a and a second sidewall 326b.
[0038] Method 200 continues at operation 220, wherein substrate 300 is cooled to a cryogenic temperature. As used herein, a cryogenic temperature refers to a temperature of about -100 degrees Celsius or lower. In some examples, the cryogenic temperature may be within a range, such as from about -160 degrees Celsius to -150 degrees Celsius, or from about -140 degrees Celsius to -120 degrees Celsius, or between about -120 degrees Celsius and about -100 degrees Celsius. In some examples, substrate 300 is cooled to a temperature of about -100 degrees Celsius or lower, or about -120 degrees Celsius or lower, or about -140 degrees Celsius or lower, or about -150 degrees Celsius or lower. In these or other examples, substrate 300 may be cooled to a temperature of about -150 degrees Celsius or higher, or about -140 degrees Celsius or higher, or about -120 degrees Celsius or higher, or about -100 degrees Celsius or higher. The ideal range will depend on a variety of factors, including but not limited to the chemical composition used (e.g., the triple point temperature of the rare gas used), the geometry of the etched features, and the type of material being etched. As mentioned elsewhere in this document, the temperature of the substrate can be controlled via a cooler. The temperature of the cooler can be lower than the temperature of the substrate itself.
[0039] As used herein, unless otherwise stated, the temperature of the substrate is intended to refer to the temperature of the substrate support assembly. This temperature may also be referred to as the cooler temperature. The substrate support assembly can control the temperature of the substrate using various heating and cooling mechanisms.
[0040] In one aspect, cooling the substrate to a cryogenic temperature can involve flowing a cooling fluid through a conduit in or near the substrate support. In another aspect, cooling the substrate to a cryogenic temperature can involve circulating a single or mixed refrigerant within the substrate support at the cryogenic temperature. In one example, a cryogenic cooler 117 is used to cool the substrate 300 to a cryogenic temperature.
[0041] Method 200 continues at operation 230, wherein a rare gas mixture is introduced into the chamber to coat multiple portions of the substrate with an inert layer 330, such as Figure 3B As shown. The rare gas mixture includes, consists of, or is substantially composed of a first rare gas. As used herein, the term "substantially composed of a first rare gas" means that the rare gas content of the rare gas mixture is greater than or equal to about 95%, 98%, or 99% of the rare gas mixture. The first rare gas is selected from argon (Ar), helium (He), neon (Ne), xenon (Xe), krypton (Kr), or combinations thereof. In one example, the first rare gas is xenon or a xenon precursor gas. In another example, the first rare gas is krypton. The rare gas mixture is generally etchant-free, meaning that the rare gas mixture does not contain any etchant gas. In one example, the processing region 110 consists of or is substantially composed of the first rare gas during operation 230. In one example, operation 230 is a plasma-free operation, meaning that there is no plasma in the processing region 110. Unlike oxygen passivation, the inert layer 330 does not consume silicon as known oxygen-based processes.
[0042] When the first rare gas condenses on the exposed surface of the substrate 300, an inert layer 330 is formed. Figure 3B In the depicted example, an inert layer 330 is formed on the top surface 322, the bottom surface 324, the first sidewall 326a, and the second sidewall 326b. The inert layer 330 can be a conformal layer or a non-conformal layer. During operation 230, a rare gas mixture flows into the processing region 110 while the substrate 300 is maintained at a low temperature. The low temperature is chosen so that the rare gas mixture can flow through surface dispersion forces and passivate the exposed surfaces of the substrate 300. In one example, the low temperature is chosen to cover the triple point temperature of the rare gas.
[0043] In an example where the rare gas is xenon, the triple point temperature of xenon is approximately -112 degrees Celsius, and the cryogenic temperature is maintained in the range of approximately -140 degrees Celsius to approximately -100 degrees Celsius, for example, in the range of approximately -120 degrees Celsius to approximately -105 degrees Celsius or from approximately -112 degrees Celsius to approximately -105 degrees Celsius. Maintaining the substrate at a cryogenic temperature covering the triple point temperature allows xenon to flow as a gas into the processing region 110 and condense on the cooled substrate 300 to form a xenon layer and passivate the exposed surfaces of the features.
[0044] In another example where the rare gas is krypton, the triple point of krypton is approximately -158 degrees Celsius, and the cryogenic temperature is maintained in the range of approximately -150 degrees Celsius to approximately -170 degrees Celsius, for example, from approximately -158 degrees Celsius to approximately -150 degrees Celsius. Cooling the substrate to a temperature slightly around or slightly above -158 degrees Celsius allows the condensed krypton to form a krypton layer and passivate the exposed surfaces of the features.
[0045] In one example, during operation 230, for a 300 mm substrate in a suitably sized chamber, the flow rate of the rare gas can be from about 50 sccm to about 500 sccm (e.g., from about 50 sccm to about 300 sccm). The rare gas can flow into the chamber to maintain a total chamber pressure of about 10 mTorr to about 100 mTorr (e.g., between about 25 mTorr and about 80 mTorr; between about 30 mTorr and about 70 mTorr; between about 25 mTorr and about 40 mTorr; or between about 60 mTorr and about 80 mTorr).
[0046] Method 200 continues in operation 240, wherein a fluorine-containing gas mixture flows into a chamber to coat an inert layer 330 with a fluorine-containing layer 340, as... Figure 3C As shown. Fluorine-containing gas mixtures include, consist of, or are substantially composed of fluorine-containing gases. As used herein, the term "substantially composed of fluorine-containing gases" means that the fluorine content of the fluorine-containing gas mixture is greater than or equal to about 95%, 98%, or 99% of the fluorine-containing gas mixture. The fluorine-containing gases are selected from SF6, NF3, F2, C4H8, CHF3, or combinations thereof. In one example, the fluorine-containing precursor gas is NF3. In another example, the fluorine-containing precursor gas is SF6. In one example, processing zone 110 consists of or is substantially composed of fluorine-containing gases. In one example, operation 240 is a plasma-free operation, meaning that plasma is not present in processing zone 110 during operation 240.
[0047] In one aspect, the fluorine-containing gas mixture further includes a rare gas. The rare gas can be selected from argon (Ar), helium (He), neon (Ne), xenon (Xe), krypton (Kr), or a combination of the above.
[0048] When fluorine-containing gas condenses on the exposed surface of the inert layer 330, a fluorine-containing layer 340 is formed. Figure 3C In the depicted example, a fluorinated layer 340 is formed on the top surface 332, the bottom surface 334, the first sidewall 336a, and the second sidewall 336b of the inert layer 330. The fluorinated layer 340 can be a conformal or non-conformal layer. During operation 240, a rare gas mixture flows into the chamber while the substrate is maintained at a cryogenic temperature. The cryogenic temperature is chosen such that the fluorinated gas can flow through surface dispersion forces and passivate the surface of the substrate. In one example, the fluorinated gas is SF6, and the cryogenic temperature is maintained between approximately -120°C and approximately -105°C. Maintaining the substrate at this cryogenic temperature allows the fluorinated gas to flow into the chamber as a gas and condense on the deposited inert layer 330.
[0049] In one example, during operation 240, the flow rate of the fluorinated gas can be from about 50 sccm to about 500 sccm (e.g., from about 50 sccm to about 300 sccm) for a 300 mm substrate in a suitably sized chamber. The fluorinated gas can be flowed into the chamber to maintain a total chamber pressure of about 30 mTorr to about 110 mTorr (e.g., between about 30 mTorr and about 100 mTorr; between about 40 mTorr and about 80 mTorr; between about 40 mTorr and about 50 mTorr; or between about 70 mTorr and about 80 mTorr). In one example, the total chamber pressure during operation 240 is slightly higher than the total chamber pressure during operation 230. For example, the total chamber pressure during operation 230 can be from about 25 mTorr to about 80 mTorr, while the total chamber pressure during operation 240 can be from about 40 mTorr to about 85 mTorr.
[0050] In one example, operations 230 and 240 do not overlap, meaning that the rare gas flow in operation 230 stops before the fluorinated gas flow in processing area 110 begins in operation 240. In another example, operations 230 and 240 partially overlap, meaning that the rare gas in operation 230 is still flowing into the processing area when the fluorinated gas flow in operation 240 begins.
[0051] In operation 250, the inert layer 330 and the fluorine-containing layer 340 are exposed to energy to form a passivation layer 350, such as Figure 3DAs shown. The energy activates the inert layer 330 and the fluorine-containing layer 340, forming a passivation layer 350 on the sidewalls 326a, 326b of feature 320. While not bound by theory, it is believed that the passivation layer 350 prevents or slows down lateral etching of feature 320 when it is etched in the vertical direction. In one example, where the inert layer 330 is formed of xenon and the fluorine-containing layer 340 is formed of SF6, the inert layer 330 and the fluorine-containing layer 340 react to form a xenon fluoride passivation layer. Xenon reacts with fluorine to form stable molecules. Xenon fluoride can include at least one of xenon difluoride (XeF2), xenon tetrafluoride (XeF4), and xenon hexafluoride (XeF6).
[0052] An energy source provides excitation energy (such as energy with ultraviolet or RF frequencies) to activate the deposited inert layer 330 and fluorine-containing layer 340 to form a passivation layer 350. In one aspect, energy is generated from an ultraviolet (UV) source and UV photons activate the deposited inert layer 330 and fluorine-containing layer 340 to form the passivation layer 350. In one example, the UV power can be from about 20% to about 100% (e.g., from about 20% to about 80%; from about 30% to about 50%). The UV power can be between about 200 watts and about 3,000 watts (e.g., between about 1,100 watts and about 2,500 watts; between about 1,500 watts and about 2,000 watts). In another example, the UV power can be from about 20% to about 100% (e.g., from about 20% to about 80%; from about 30% to about 50%). UV power can range from about 200 watts to about 1,000 watts (e.g., between about 200 watts and about 500 watts; between about 250 watts and about 350 watts).
[0053] In another aspect, the energy is plasma formed by a radio frequency (RF) power source in the presence of a plasma precursor gas mixture. Exposure to RF power ionizes at least a portion of the plasma precursor gas mixture, thereby forming plasma. RF power with a frequency between about 10 kHz and about 14 MHz is applied at a power level between about 1,000 W and about 5,000 W (e.g., between about 2,000 W and about 3,000 W, or about 2,500 W) to generate plasma. In one example, a frequency of 13.56 MHz is used. In another example, lower frequencies up to 400 kHz (e.g., 350 kHz) are used. Secondary power can be applied at power levels from about 10 watts to about 500 watts (e.g., from about 200 watts to about 400 watts; about 250 watts). The plasma precursor gas mixture includes an inert gas. In one example, the inert gas is helium, and plasma activation generates helium ions in processing region 110, which activate the deposited inert layer 330 and fluorine-containing layer 340 to form passivation layer 350. In another example, the inert gas includes a combination of argon and helium, and plasma activation generates ions in processing region 110, which activate the deposited inert layer 330 and fluorine-containing layer 340 to form passivation layer 350. In one example, operation 250 is a no-bias process, meaning that no bias is applied to the substrate.
[0054] In one aspect, during operation 250, the inert layer 330 and the fluorinated layer 340 are exposed to an ion flux to form a passivation layer 350. The ion flux can be one or more types of atomic or molecular matter with low ion energy. Therefore, in one aspect, the matter promotes a reaction between the inert layer 330 and the fluorinated layer 340, rather than a chemical reaction between the inert layer 330 and the fluorinated layer 340, and thus the ion flux originates from a source gas with relatively low chemical reactivity with the target component. Exemplary ionic substances include helium ions, neon ions, xenon ions, nitrogen ions, or argon ions accompanying helium ions.
[0055] In one example, during operation 250, the helium flow rate can be from about 100 sccm to about 500 sccm (e.g., from about 100 sccm to about 300 sccm) for a 300 mm substrate in a suitably sized chamber. Helium can flow into the chamber to maintain a total chamber pressure of about 10 millitorr to about 30 millitorr (e.g., between about 10 millitorr to about 20 millitorr; or between about 20 millitorr to about 30 millitorr). In one example, a cryogenic temperature is maintained during operation 250. In some embodiments, the substrate temperature can be scaled down to between about 500 degrees Celsius and about 1100 degrees Celsius, such as about 800 degrees Celsius.
[0056] At operation 260, the substrate / feature is bombarded with ion flux to etch the substrate. In one example, the ion flux is anisotropic, thus reducing the exposure of the passivated sidewalls of the feature. The ion flux bombards the portion of the passivation layer 350 covering a horizontal surface, such as... Figure 3E The substrate feature shown has a top surface 322 and a bottom surface 324. Removing the passivation layer 350 covering the top surface 322 exposes the mask layer 312, while removing the passivation layer covering the bottom surface 324 exposes the silicon material at the bottom of the feature 320. Portions 360a and 360b of the passivation layer 350 remain on the sidewalls 326a and 326b.
[0057] Ion flux can be generated using the same gas and low-frequency RF power from Operation 250. Ion flux can be generated from an inert gas using low-frequency RF source power. The ion flux can be one or more types of atomic or molecular matter with low ion energy. Exemplary ion matter includes helium ions, neon ions, xenon ions, nitrogen ions, argon ions, or combinations thereof, which have low ion potentials, enabling the provision of very low plasma DC bias to reduce the energy level of the ion flux. Advantageously, the process pressure is below 10 millitorrels for greater directionality, and more advantageously below 5 millitorrels. It has been found that low RF power on the order of 50 W to 100 W, depending on the ion potential of the feed gas, is beneficial for modifying low-k dielectric films by removing carbon matter from the silicon-oxide matrix.
[0058] In one example, the inert gas is helium, and plasma activation generates helium ions in processing region 110, which bombard and activate the passivation layer 350. In another example, the inert gas is a mixture of helium and argon, and plasma activation generates helium ions in processing region 110, which bombard and activate the passivation layer 350. Fluorine from the activated passivation layer 350 is etched from silicon at the bottom surface 324 of the substrate 300.
[0059] During operation 260, a bias voltage is also applied to substrate 300 to guide ions toward the horizontal surface of substrate 300. The bias voltage can be generated using power ranging from about 50 watts to about 1500 watts (e.g., from about 50 watts to about 250 watts; or from about 50 watts to about 100 watts). In one aspect, RF bias power is applied to electrodes in substrate support assembly 101, such as adsorption electrodes 126. In one example, the RF bias power can be applied at a power of less than 500 watts, such as between about 50 watts and about 250 watts, such as between about 50 watts and about 100 watts, the RF bias power having a frequency between about 2 MHz and about 13.56 MHz.
[0060] Unbound by theory, it is believed that bombarding the passivation layer 350 with ion flux separates the fluorine from the rare element, thereby allowing the fluorine to bind to the silicon in the silicon layer 310 and to be removed from or “etched” from the silicon in the silicon layer 310. The etching of operation 260 can be considered atomic-level etching or molecular-level etching (MLE) because the removed portion is on the order of the size of the molecular components in the silicon film.
[0061] Please note that operations 230 to 260 can be repeatedly performed or cycled in a passivation layer repair, followed by etching of the gate material, to achieve the target etching depth of the silicon material.
[0062] The implementation can include one or more of the following potential advantages. By utilizing the passivation and etching techniques described herein, features with high aspect ratios can be etched and shaped in a controlled manner, providing target profiles with substantially sharp right angles and upright (e.g., straight, vertical) sidewalls with steep slopes and accurate dimensions. Using an inert layer of rare gas as an etching precursor provides a scheme that allows atomic layer etching at low temperatures. Atomic layer etching at low temperatures can reduce or eliminate sidewall etching and provide more vertical features, which improves device performance and yield. Furthermore, because the first layer precursor is inert, corrosive chemicals such as fluorine can be used in the etching process while suppressing any spontaneous etching.
[0063] Therefore, an implementation is provided that etches silicon material to form features with targeted edge / corner profiles and aspect ratios. By utilizing passivation and etching modes, controlled ion trajectory / direction and sidewall / corner passivation protection can be obtained, thereby etching the silicon layer in a manner that produces multiple features with precise right-angled corners and vertical sidewall profiles and feature aspect ratios. Furthermore, the passivation and etching processes can be performed in a single chamber without breaking the vacuum, which reduces system complexity.
[0064] The embodiments and all functional operations described herein can be implemented in digital electronic circuit systems or in computer software, firmware, or hardware, including the structural devices and their structural equivalents disclosed herein, or combinations thereof. The embodiments described herein can be implemented as one or more non-transitory computer program products, i.e., one or more computer programs tangibly embodied in a machine-readable storage device, to perform or control the operation of a data processing device, such as a programmable processor, a computer, or multiple processors or computers.
[0065] The processes and logic flows described in this specification can be executed by one or more programmable processors, which execute one or more computer programs to perform functions by manipulating input data and generating outputs. The processes and logic flows can also be executed by dedicated logic circuit systems, and the device can also be implemented as a dedicated logic circuit system, such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit).
[0066] The term "data processing device" encompasses all devices, apparatuses, and machines used for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the device can include code that generates an execution environment for the computer program of interest, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof. For example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors, as well as any type of digital computer and any one or more processors.
[0067] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. Processors and memory can be supplemented by or incorporated into dedicated logic circuitry systems.
[0068] When describing elements of this disclosure or exemplary aspects thereof or implementations thereof, the articles “a / an” and “the / said” are intended to mean the presence of one or more elements among the elements.
[0069] The terms “including,” “contains,” and “have” are intended to be inclusive and mean that there may be other elements besides those listed.
[0070] While the foregoing is directed to various aspects of this disclosure, other and further aspects of this disclosure may be designed without departing from the essential scope of this disclosure, which is defined by the appended claims.
Claims
1. An etching method, comprising: The first rare gas flows into the processing area of the processing chamber; The exposed area of the substrate is brought into contact with the first rare gas, such that the first rare gas is absorbed on the surface of the exposed area, wherein the substrate is maintained at a low temperature that covers the triple point temperature of the first rare gas. A first layer of predetermined thickness is formed from the first rare gas on the surface of the exposed area; The fluorine-containing precursor gas is allowed to flow into the processing area; A second layer of predetermined thickness is formed on the first layer from the fluorine-containing precursor gas; A passivation layer is formed from the first layer and the second layer; as well as Etch material from the exposed areas of the substrate.
2. The etching method of claim 1, wherein the low temperature is from about -105 degrees Celsius to about -120 degrees Celsius.
3. The etching method of claim 1, wherein the low temperature is from about -150 degrees Celsius to about -160 degrees Celsius.
4. The etching method of claim 1, wherein the first rare gas is selected from xenon and krypton.
5. The etching method of claim 3, wherein the fluorine-containing precursor gas is selected from the group consisting of SF6, NF3 and F2.
6. The etching method of claim 1, wherein the etching method is repeated in multiple cycles to achieve the target etching depth of the substrate.
7. The etching method of claim 1, further comprising: The flow of the first rare gas into the processing area is stopped before the fluorine-containing precursor gas flows into the processing area.
8. The etching method of claim 1, wherein the flow of the first rare gas into the processing region and the flow of the fluorine-containing precursor gas into the processing region at least partially overlap.
9. The etching method of claim 1, wherein forming the passivation layer comprises exposing the first layer and the second layer to energy selected from plasma or ultraviolet photons.
10. The etching method of claim 1, wherein the substrate comprises a low-k dielectric material.
11. The etching method of claim 1, wherein the substrate comprises a silicon layer.
12. An etching method, comprising: A substrate is received on a substrate support located in the processing area of the processing chamber, the substrate support having a cooler; The first rare gas is allowed to flow into the processing area; The exposed area of the substrate is brought into contact with the first rare gas, such that the first rare gas is absorbed on the surface of the exposed area, wherein the substrate is cooled by the cooler to a low temperature of about -100 degrees Celsius or lower, and the low temperature covers the triple point temperature of the first rare gas. A first layer of predetermined thickness is formed from the first rare gas on the surface of the exposed area; The fluorine-containing precursor gas is allowed to flow into the processing area; A second layer of predetermined thickness is formed on the first layer from the fluorine-containing precursor gas; A passivation layer is formed from the first layer and the second layer; as well as Etch material from the exposed areas of the substrate.
13. The etching method of claim 12, wherein the low temperature is from about -105 degrees Celsius to about -120 degrees Celsius.
14. The etching method of claim 12, wherein the fluorine-containing precursor gas is selected from SF6, NF3 and F2.
15. The etching method of claim 14, wherein the first rare gas is xenon.
16. The etching method of claim 12, wherein etching the material from the exposed area of the substrate comprises: A bias voltage is applied to the electrodes in the substrate support; as well as Helium gas is then introduced into the processing area.
17. The etching method of claim 12, wherein the passivation layer is formed on a plurality of sidewalls of the feature, the feature is formed in the substrate, and the passivation layer prevents or slows down lateral etching of the feature when the feature is etched in the substrate in a vertical direction.
18. An etching method, comprising: A substrate is received on a substrate support located in a processing area of a processing chamber. The substrate has a substrate surface and at least one feature formed on the substrate. The at least one feature extends from the substrate surface and has a bottom surface and a plurality of sidewalls. The substrate support has a cooler operable to cool the substrate. The substrate is cooled to a low temperature, which covers the triple point temperature of the xenon precursor gas; A xenon fluoride passivation layer is formed on at least the plurality of sidewalls, wherein forming the xenon fluoride passivation layer includes: The substrate is brought into contact with the xenon precursor gas, such that the xenon precursor gas forms a xenon layer of predetermined thickness on the surfaces of the plurality of sidewalls. The xenon layer is brought into contact with a fluorine-containing precursor gas to form a fluorine-containing layer of predetermined thickness on the xenon layer; Expose the xenon layer and the fluorine-containing layer to ultraviolet photons to form the xenon fluoride passivation layer; and Etching material from the bottom surface of the feature.
19. The etching method of claim 18, wherein etching the material from the bottom surface of the feature comprises: A bias voltage is applied to the electrodes in the substrate support; Helium gas is introduced into the processing area to form helium ions; as well as The xenon fluoride passivation layer is bombarded with helium ions.
20. The etching method of claim 19, wherein etching the material from the bottom surface of the feature comprises exposing the bottom surface to fluorine from the xenon fluoride passivation layer.