Test protection system for power semiconductor wafers and test protection method based thereon

Abstract

This disclosure provides a test protection system and a test protection method based thereon for power semiconductor wafers, relating to the semiconductor field. The system includes: a test chamber, a tray, a probe card, and a vacuum device. The tray is used to hold the power semiconductor wafer and is provided with an adsorption device for adsorbing a first side of the power semiconductor wafer. The probe card includes a circuit board located in the test chamber and spaced apart from the tray, and multiple probes disposed on the side of the circuit board facing the tray and spaced apart. The multiple probes are used to make electrical contact with a second side of the power semiconductor wafer, wherein the first side and the second side are arranged opposite to each other. The vacuum device is slew-proofly connected to the test chamber and is used to evacuate the test chamber when a test voltage is applied to the power semiconductor wafer through the multiple probes, so that the gas pressure in the test chamber is in a negative pressure state, increasing the breakdown voltage of the gas in the test chamber, and realizing the reliability screening of large-size, high-voltage power semiconductor wafers.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a test and protection system for power semiconductor wafers and a test and protection method based thereon. Background Technology

[0002] In the manufacturing process of power semiconductor devices, the reliability and stability of the power semiconductor device chips on the power semiconductor wafer are crucial to the yield and reliability of subsequent production processes. Early screening of defects in the power semiconductor device chips on the power semiconductor wafer can significantly improve the yield of the power semiconductor devices after subsequent packaging.

[0003] Power devices, represented by novel power semiconductor materials such as silicon carbide and gallium nitride, are finding increasing applications in new energy vehicles and power generation systems. However, these materials and devices still face reliability challenges. The yield of power semiconductor device chips on power semiconductor wafers is still far lower than that of silicon devices, and the early failure rate of power semiconductor device chips is relatively high. To achieve reliable applications, it is currently necessary to conduct reliability screening of power semiconductor wafers under high temperature and high voltage conditions.

[0004] Reliability screening of power semiconductor wafers typically involves aging the power semiconductor device chips within the wafers under high temperature (up to 200°C) and high voltage conditions. To prevent oxidation and arcing issues under high voltage, the power semiconductor device wafers require appropriate protection.

[0005] A common industry practice for protection is to place the power semiconductor wafer in a sealed probe card, apply electrical stress to the wafer using probes, and fill the probe card with high-pressure gas. This utilizes the enhanced insulation properties of gas at high pressure to prevent problems such as increased leakage current and arcing caused by insufficient insulation during the aging test of the power semiconductor wafer.

[0006] This approach is effective for low-voltage or small-size wafers. However, as the voltage levels of power semiconductor devices in power semiconductor wafers increase, the voltage stress required during the aging process also increases. This necessitates increasingly higher pressure (several bars) for the probe card's filling gas. The high-pressure gas filling the probe card exerts significant pressure on its structure, easily causing deformation and leading to poor contact between the probe and the power semiconductor wafer in certain areas, rendering testing impossible. Furthermore, with the increasing size of power semiconductor wafers—currently from 6 inches to 8 inches and 12 inches—the pressure and deformation on the probe card are further increased, making probe contact problems increasingly prominent. The industry urgently needs to solve this problem to achieve reliable screening of large-size, high-voltage power semiconductor wafers. Summary of the Invention

[0007] The main objective of this disclosure is to provide a test and protection system for power semiconductor wafers and a test and protection method based thereon, so as to achieve reliability screening of large-size, high-voltage power semiconductor wafers.

[0008] To achieve the above objectives, a first aspect of this disclosure provides a test protection system for a power semiconductor wafer. The system includes: a sealable test chamber, a tray, a probe card, and a vacuum device. The tray holds the power semiconductor wafer located in the test chamber and is equipped with an adsorption device for adsorbing a first side of the power semiconductor wafer. The probe card includes a circuit board located in the test chamber and spaced apart from the tray, and a plurality of probes spaced apart and disposed on the side of the circuit board facing the tray. The probes are used to make electrical contact with a second side of the power semiconductor wafer, wherein the first and second sides are opposite to each other. The vacuum device is in continuous communication with the test chamber and is used to evacuate the test chamber when a test voltage is applied to the power semiconductor wafer through the probes, thereby creating a negative pressure in the test chamber and increasing the breakdown voltage of the gas in the test chamber.

[0009] In some embodiments of this disclosure, the system further includes: a protective gas injection device that is in on / off communication with the test chamber, the protective gas injection device being used to inject protective gas into the test chamber to replace the gas in the test chamber; and after the protective gas injection device injects protective gas into the test chamber, when a test voltage is applied to the power semiconductor wafer through multiple probes, the gas pressure in the test chamber remains in a negative pressure state.

[0010] In some embodiments of this disclosure, the power semiconductor wafer includes a plurality of power semiconductor device regions arranged in an array and spaced apart. Each power semiconductor device region includes a front electrode structure group disposed on a first surface, and each front electrode structure group includes at least one front electrode structure. A plurality of test unit regions are arranged in an array on the side of the circuit board facing the tray. The plurality of test unit regions correspond one-to-one with the plurality of power semiconductor device regions. Each test unit region includes a probe group for electrical contact with the electrode structure group of its corresponding power semiconductor device region. Each probe group includes at least one probe, thereby causing the plurality of probes to be arranged at intervals.

[0011] In some embodiments of this disclosure, each power semiconductor device region further includes a back electrode structure disposed on a second surface, and the tray is a conductive structure that electrically contacts the multiple back electrode structures.

[0012] In some embodiments of this disclosure, the system further includes a heating device that can heat the power semiconductor wafer via a tray.

[0013] In some embodiments of this disclosure, the test protection system further includes: a reinforcing insulating layer stacked on the circuit board facing the tray side, with the probe penetrating the reinforcing insulating layer from the circuit board and exposing the surface of the reinforcing insulating layer facing away from the circuit board.

[0014] In some embodiments of this disclosure, the edge of the tray is provided with a sealing structure; the system further includes: a cover plate that is fastened to the tray by the sealing structure to form a sealed test cavity, and a probe card is disposed on the side of the cover plate facing the tray, so that when the cover plate is fastened to the tray, the probe makes electrical contact on the second side of the power semiconductor wafer.

[0015] In some embodiments of this disclosure, the test protection system further includes: an air extraction port communicating between the vacuuming device and the test chamber, and an air inlet port communicating between the protective gas injection device and the test chamber.

[0016] The second aspect of this disclosure provides a test protection method for power semiconductor wafers, which is based on any of the test protection systems for power semiconductor wafers provided in the first aspect of this disclosure. The method includes: placing the power semiconductor wafer on a tray and adsorbing the first side of the power semiconductor wafer by an adsorption device; electrically contacting a plurality of probes on a probe card with the second side of the power semiconductor wafer and sealing the test chamber; evacuating the test chamber using a vacuum device to make the gas pressure in the test chamber negative, thereby increasing the breakdown voltage of the gas in the test chamber; and applying a test voltage to the power semiconductor wafer through the plurality of probes.

[0017] In some embodiments of this disclosure, the test protection system further includes: a protective gas injection device that is in on / off communication with the test chamber, the protective gas injection device being used to inject protective gas into the test chamber to replace the gas in the test chamber; the method further includes: injecting protective gas into the test chamber using the protective gas injection device, and the gas pressure in the test chamber remaining negative when a test voltage is applied to the power semiconductor wafer through multiple probes.

[0018] The power semiconductor wafer test protection system provided in this embodiment includes a vacuum device that is scalably connected to the test chamber. This vacuum device evacuates the test chamber when a test voltage is applied to the power semiconductor wafer through multiple probes, creating a negative pressure environment within the test chamber. Based on Pashin's law, the system utilizes the enhanced insulation capacity of gases under rarefied conditions to increase the breakdown voltage of the gas in the test chamber. This protects the power semiconductor wafer from high voltage application, preventing gas breakdown between adjacent probes and subsequent arcing when high voltage is applied. Simultaneously, the system leverages the reduced deformation of the probe card under negative pressure, ensuring that the overall pressure on the probe card does not exceed that of one atmosphere. This effectively reduces probe card deformation and structural strength requirements, mitigating the problem of poor electrical contact between the probe and the power semiconductor wafer caused by probe card deformation, and improving the reliability of the electrical contact between the probe card and the power semiconductor wafer. This enables reliable screening of large-size, high-voltage power semiconductor wafers. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic cross-sectional view of a test protection system for power semiconductor wafers provided in an embodiment of this disclosure; Figure 2 A schematic diagram of the breakdown voltage versus air pressure curve according to an embodiment of the present disclosure based on Parshen's law; Figure 3 A schematic cross-sectional view of a test protection system for a power semiconductor wafer provided in another embodiment of this disclosure; Figure 4 This is a schematic flowchart of a test protection method for power semiconductor wafers provided in an embodiment of the present disclosure. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In this disclosure, the terms “upper,” “lower,” “left,” “right,” “front,” “rear,” “top,” “bottom,” “inner,” “outer,” and “middle,” etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are primarily for the purpose of better describing this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0024] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain circumstances to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0025] Furthermore, the terms "set up," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection via an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Example 1 To address at least some of the aforementioned problems, embodiments of this disclosure provide a test protection system for a power semiconductor wafer 105, with reference to... Figure 1 The system includes: a sealable test chamber, a tray 106, a probe card, and a vacuum device; wherein, the tray 106 is used to hold a power semiconductor wafer 105 located in the test chamber, and the tray 106 is provided with an adsorption device for adsorbing the first side of the power semiconductor wafer 105; the probe card includes a circuit board 102 located in the test chamber and spaced apart from the tray 106, and a plurality of probes 104 disposed on the side of the circuit board 102 facing the tray 106 and spaced apart, the plurality of probes 104 being used for electrical contact with the second side of the power semiconductor wafer 105, wherein the first side and the second side are arranged opposite to each other; the vacuum device is in on / off communication with the test chamber, and the vacuum device is used to evacuate the test chamber when a test voltage is applied to the power semiconductor wafer 105 through the plurality of probes 104, so that the gas pressure in the test chamber is in a negative pressure state, thereby increasing the breakdown voltage of the gas in the test chamber.

[0028] In the above scheme, by setting up a vacuum pumping device that is in / out of communication with the test chamber, the vacuum pumping device is used to evacuate the test chamber when a test voltage is applied to the power semiconductor wafer 105 through multiple probes 104, so that the air pressure in the test chamber is in a negative pressure state (less than atmospheric pressure), thereby enhancing the insulation capability and voltage protection capability of the test protection system. (Reference) Figure 2 According to Pashin's law, this system utilizes the characteristic that insulation capacity is enhanced under rarefied gas conditions to increase the breakdown voltage of the gas in the test chamber. This protects the power semiconductor wafer 105 from high-voltage applications, preventing gas breakdown between adjacent probes 104 when high voltage is applied, thus avoiding arcing and insufficient insulation. Simultaneously, the system leverages the characteristic that negative gas pressure reduces probe card deformation, ensuring the overall pressure on the probe card does not exceed one atmosphere. This effectively reduces probe card deformation and structural strength requirements, mitigating the problem of poor electrical contact between probe 104 and the power semiconductor wafer 105 caused by probe card deformation, and improving the reliability of electrical contact between the probe card and the power semiconductor wafer 105. This enables reliability screening of large-size, high-voltage power semiconductor wafers 105. Furthermore, the vacuum system exhausts air from the test chamber, preventing oxidation of the power semiconductor wafer 105 under subsequent heating and other testing conditions.

[0029] It should be noted that while some related technologies involve testing wafers in vacuum environments, the primary reason for placing wafers in a vacuum is that unfinished wafers are easily oxidized in an oxygen-rich environment, leading to chemical reactions that could damage the functional structural layers on the wafer surface and thus affect its performance. In other words, the main purpose of placing wafers in a vacuum environment is to utilize the low oxygen content; there is no disclosed technological inspiration regarding the advantages of a vacuum environment, such as good insulation and low pressure applied to the structures within it.

[0030] Regarding scenarios where a large test voltage needs to be applied to the power semiconductor wafer 105, such as withstand voltage or aging tests, the related technologies do not include applications or technical inspirations that "set the test environment of the power semiconductor wafer 105 to a negative pressure state to increase the breakdown voltage of the gas in the test environment, thereby avoiding arcing caused by the large test voltage breaking down the gas between different probes 104 when a large test voltage is applied to the power semiconductor wafer 105 through multiple probes 104." This indicates that this is precisely the important technical point discovered by the inventors of this disclosure. Since a large test voltage is not required in the vacuum testing environment of the wafer in the related technologies, the technical problem of arcing between different probes 104 due to a large test voltage is avoided. Therefore, those skilled in the art, without creative effort, can obtain the solution shown in the embodiments of this application that "sets the test environment of the power semiconductor wafer 105 to a negative pressure state to increase the breakdown voltage of the gas in the test environment, thereby avoiding arcing caused by the breakdown of the gas between different probes 104 when a large test voltage is applied to the power semiconductor wafer 105 through multiple probes 104".

[0031] It should be noted that in this embodiment, the test voltage applied to the power semiconductor wafer 105 by the multiple probes 104 is greater than a set voltage value. This set voltage value is the critical value between the breakdown of the air between the two probes 104 and the insulation under normal pressure (atmospheric pressure). That is, in this embodiment, the test voltage would break down the air between the two probes 104 under normal pressure.

[0032] The following is in conjunction with the appendix Figures 1 to 3 The system disclosed herein is described in detail.

[0033] It should be noted that the reference Figure 1The aforementioned test protection system can be applied to power semiconductor wafers 105 for test types that require applying large test voltages, such as, but not limited to, withstand voltage tests and aging tests. The substrate for the aforementioned power semiconductor wafer 105 can be a semiconductor substrate such as, but not limited to, a silicon carbide wafer substrate.

[0034] For example, refer to Figure 1 The system may further include a protective gas injection device that is in / out of communication with the test chamber. The protective gas injection device injects protective gas into the test chamber to replace the gas in the test chamber. After the protective gas is injected into the test chamber, the gas pressure in the test chamber remains negative when a test voltage is applied to the power semiconductor wafer 105 through multiple probes 104. In this way, when a test voltage is applied to the power semiconductor wafer 105 through multiple probes 104, the gas in the test chamber is under negative pressure and consists of protective gas, thereby further venting water vapor and oxygen from the test chamber. Furthermore, the protective gas's ability to protect the power semiconductor wafer 105 and probes 104 from oxidation enhances the protection effect on the power semiconductor wafer 105.

[0035] For example, by coordinating the operation of the vacuum pump and the protective gas injection device, the gas in the test chamber can be configured to be under negative pressure and composed of protective gas, thereby further purging water vapor and oxygen from the test chamber. To achieve sufficient gas replacement, the vacuum pump and the protective gas injection device can be used in alternating operations to perform multiple cycles, thereby configuring the gas in the test chamber to be under negative pressure and composed of protective gas.

[0036] For example, refer to Figure 1The power semiconductor wafer 105 may include multiple arrays of power semiconductor device regions arranged at intervals. Each power semiconductor device region includes a front electrode structure group disposed on a first surface, and each front electrode structure group includes at least one front electrode structure. The circuit board 102 has multiple test unit regions arranged in an array facing the tray 106. Each test unit region corresponds one-to-one with a power semiconductor device region. Each test unit region includes a group of probes 104 for electrical contact with the electrode structure group of its corresponding power semiconductor device region. Each group of probes 104 includes at least one probe 104, thereby arranging the multiple probes 104 at intervals. In this configuration, because the test chamber is under negative pressure during testing, even when the power semiconductor wafer 105 is large, it is less prone to deformation. This improves the reliability of electrical contact between the probes 104 and the power semiconductor wafer 105 during voltage withstand or aging tests. Using a large-size power semiconductor wafer 105 allows for more power semiconductor device regions to be disposed, thereby increasing the number of power semiconductor device chips fabricated from a single power semiconductor wafer 105 and improving manufacturing efficiency.

[0037] For example, refer to Figure 1 Each power semiconductor device region also includes a back electrode structure disposed on the second surface, and the tray 106 is a conductive structure that electrically contacts multiple back electrode structures. By disposing of the back electrode structure on the second surface of the power semiconductor device region, the power semiconductor device can be a vertical power device, thereby improving the voltage withstand capability of the power semiconductor device. Furthermore, by reusing the tray 106 as a conductive structure that electrically contacts the back electrode structures, a single structure can have a dual function (wafer adsorption and serving as a test electrode for electrically contacting the back electrode structures), thus improving the system's integration.

[0038] For example, refer to Figure 1 The system may also include a heating device that heats the power semiconductor wafer 105 via the tray 106. By having the heating device heat the power semiconductor wafer 105 via the tray 106, the tray 106 can be used as part of the heating device (e.g., as part of the heating resistor of the heating device), thereby achieving a structure with dual functions (adsorbing the wafer and serving as part of the heating device), improving the system's integration.

[0039] For example, refer to Figure 1The system may further include a reinforcing insulating layer 103 stacked on the circuit board 102 facing the tray 106, with the probe 104 penetrating the reinforcing insulating layer 103 from the circuit board 102 and protruding from the surface of the reinforcing insulating layer 103 facing away from the circuit board 102. By providing a reinforcing insulating layer 103 on the back side of the circuit board 102, and by having the probe 104 make electrical contact with the first surface of the power semiconductor wafer 105 after penetrating the reinforcing insulating layer 103, the good insulation performance and high rigidity of the reinforcing insulating layer 103 can be utilized to not only improve the insulation performance between different probes 104, but also to improve the strength of the probe card and its resistance to deformation. Furthermore, the reinforcing insulating layer 103 can also be used to fix the probe 104, thereby improving the fixation firmness of the probe 104.

[0040] Regarding the arrangement of the reinforcing insulation layer 103, any structural layer capable of improving the rigidity and insulation of the probe card can be used. For example, a ceramic layer, but not limited to, can be used as the reinforcing insulation layer 103, taking advantage of the high rigidity and good insulation properties of ceramics to improve the rigidity and insulation of the reinforcing insulation layer 103.

[0041] For example, refer to Figure 1 The edge of the tray 106 is provided with a sealing structure 107. The test protection system may also include a cover plate 101 that is fastened to the tray via the sealing structure 107 to form a sealed test chamber. A probe card is disposed on the side of the cover plate 101 facing the tray 106, so that when the cover plate 101 and the tray 106 are fastened together, the probe 104 makes electrical contact with the second surface of the power semiconductor wafer 105. By adopting the above method, it is easy to form a sealed test chamber between the tray 106 and the cover plate 101. Furthermore, before applying a test voltage to the power semiconductor wafer 105, the air pressure in the test chamber is set to a negative pressure state. By utilizing the fact that the external atmospheric pressure is greater than the air pressure in the test chamber, the cover plate 101 and the tray 106 can be pressed together. In addition, the characteristic of the cover plate 101 deforming inward toward the test chamber during the pressing process can also be used to squeeze the probe card toward the power semiconductor wafer 105, so that the probe 104 is pressed against the second surface of the power semiconductor wafer 105. By utilizing the suction force of the test chamber under negative pressure, the tightness of the connection between the tray 106 and the cover plate 101 is increased, thereby improving the sealing effect of the test chamber. Furthermore, when it is necessary to separate the tray 106 and the cover plate 101, the air pressure in the test chamber only needs to be restored to normal atmospheric pressure. This simplifies the process of forming a sealed test chamber between the tray 106 and the cover plate 101. It also facilitates the handling of the power semiconductor wafer 105 by a robotic arm.

[0042] For example, refer to Figure 3The test protection system may further include: an air extraction port 109 connecting the vacuum pumping device and the test chamber, and an air inlet port 108 connecting the protective gas injection device and the test chamber. By providing the air extraction port 109 and the air inlet port 108, it is convenient to replace the air in the test chamber.

[0043] The number of evacuation ports 109 can be one or more, allowing the vacuuming device to vent air from the test chamber through the evacuation ports 109. Similarly, the number of inlet ports 108 can be one or more, allowing the protective gas injection device to inject protective gas into the test chamber through the inlet ports 108.

[0044] The type of protective gas can be varied. For example, in some embodiments, the protective gas can be, but is not limited to, nitrogen, inert gas, etc.

[0045] For example, refer to Figure 3 The test protection system may include, but is not limited to, a support structure such as a frame to support the entire structure, and the cover plate 101 and the tray 106 may both be mounted on the frame. The circuit board 102 may be, but is not limited to, a PCB board, thereby electrically connecting the probe 104 and the external wafer testing device through the traces on the PCB, thereby applying a test voltage to the probe 104.

[0046] The type of probe 104 can be varied. For example, probe 104 can be a probe structure such as, but not limited to, a metal spring probe or a metal sheet probe, that can abut against the surface of the power semiconductor wafer 105, thereby making electrical contact with the electrodes of the power semiconductor device chip in the power semiconductor wafer 105.

[0047] For example, a positioning and fixing structure can also be provided on the tray 106, so that after the power semiconductor wafer 105 is placed on the tray 106, the positioning and fixing structure positions and fixes the power semiconductor wafer 105. Then, the cover plate 101 on which the circuit board 102 is provided is fastened to the tray 106, thereby clamping the probe 104 on the circuit board 102 to the second side of the power semiconductor wafer 105, thereby improving the firmness of the electrical contact between the probe 104 and the power semiconductor wafer 105.

[0048] There are various ways to configure the sealable test chamber. For example, a housing with a test chamber can be used as the configuration structure for the sealable test chamber. Exemplarily, the housing includes an upper housing and a lower housing that can be snapped together to form a sealed test chamber; wherein the lower housing is provided with an adsorption device for adsorbing the first surface of a power semiconductor wafer 105, and both a first one-way valve and a second one-way valve are disposed in the lower housing. By disposing both the first and second one-way valves in the lower housing, neither valve occupies space in the upper housing, thus providing a larger mounting area for the probe card. By setting a first one-way valve and a second one-way valve, and based on the control of the first one-way valve and the second one-way valve, before the probe card applies a test voltage to the power semiconductor wafer 105 to test the power semiconductor wafer 105, the test chamber can be made into a negative pressure state composed of protective gas through the control of the first one-way valve and the second one-way valve, so as to attract the upper shell and the lower shell together. This eliminates the need to use the multiple bolts locking method in related technologies, making the locking simple and simplifying the locking difficulty between the upper shell and the lower shell, thereby improving the problem of difficult wafer fixture locking in related technologies.

[0049] Furthermore, since the upper and lower housings are attracted together using a negative pressure suction method, only a pressure-holding method (maintaining the air pressure in the test chamber at a negative pressure) is needed to ensure a stable and reliable attraction between the upper and lower housings, thus enabling rapid attraction between them. The negative pressure also reduces the deformation of the probe card, ensuring that the overall pressure on the probe card does not exceed the pressure of one atmosphere. This effectively reduces probe card deformation and structural strength requirements, improves the problem of poor electrical contact between the probe card and the power semiconductor wafer 105 due to probe card deformation, and enhances the reliability of the electrical contact between the probe card and the power semiconductor wafer 105.

[0050] Meanwhile, before testing, the air in the test chamber was evacuated and replaced with protective gas. The high insulation and high oxidation resistance of the airtight state under negative pressure of the protective gas prevented the breakdown of the gas and sparking caused by excessive test voltage during the testing of the power semiconductor wafer 105. It also slowed down the oxidation rate of the power semiconductor wafer 105 during testing and improved the reliability of the test.

[0051] For example, the negative pressure testing device may further include: a pressure detection device for measuring the air pressure in the test chamber and coupled to a vacuuming device; the pressure detection device is configured to: when the air pressure in the test chamber is detected to be greater than a first set negative pressure threshold, trigger the vacuuming device to evacuate the test chamber, so that the air pressure in the test chamber is maintained at a negative pressure state less than or equal to the first set negative pressure threshold. By setting a pressure detection device to check the air pressure in the test chamber, the air pressure in the test chamber can be understood in real time and accurately. When the air pressure in the test chamber is greater than the first set negative pressure threshold (indicating that the negative pressure in the test chamber is low, resulting in a small suction force between the upper and lower shells), the vacuuming device is automatically triggered to evacuate the test chamber, thereby enabling the air pressure in the test chamber to be stably and reliably maintained at a negative pressure state less than or equal to the first set negative pressure threshold with a relatively high negative pressure level.

[0052] The air pressure detection device can be set up using any air pressure sensor that can detect air pressure without affecting the testing of the power semiconductor wafer 105.

[0053] For example, the air pressure detection device can also be configured to: when the air pressure in the test chamber is detected to be less than a second set negative pressure threshold, trigger the vacuum pumping device to stop evacuating the test chamber, so that the air pressure in the test chamber is maintained at a negative pressure state greater than or equal to the second set negative pressure threshold; wherein, the second set negative pressure threshold is less than the first set negative pressure threshold. When the air pressure detection device detects that the air pressure in the test chamber is less than the second set negative pressure threshold, it indicates that the negative pressure in the test chamber is already relatively high. At this time, the suction force between the upper and lower shells is already large, which can meet the usage requirements. The vacuum pumping device can be automatically triggered to stop evacuating the test chamber, thereby enabling the air pressure in the test chamber to be stably and reliably maintained at a negative pressure state between the first and second set negative pressure thresholds. This prevents the vacuum pumping device from excessively evacuating the test chamber, which could lead to excessive pressure between the external atmospheric pressure and the air pressure in the test chamber, causing significant deformation of the upper shell and / or the lower shell, thereby affecting the reliability of the electrical contact between the probe card and the power semiconductor wafer 105.

[0054] For example, the pressure detection device is also coupled to a protective gas injection device; the pressure detection device is further configured to: when it detects that the pressure in the test chamber is greater than a third preset negative pressure threshold, it indicates that the difference between the pressure in the test chamber and the atmospheric pressure outside the test chamber is already small, and the suction force between the upper and lower housings is already low. If the protective gas injection device continues to inject protective gas into the test chamber, it will further reduce the difference between the external atmospheric pressure and the pressure in the test chamber, which may pose a risk of the upper and lower housings separating. At this time, the pressure detection device automatically triggers the protective gas injection device to stop injecting protective gas into the test chamber, so that the pressure in the test chamber is maintained at a negative pressure state less than or equal to the third preset negative pressure threshold, thereby avoiding the risk of the upper and lower housings separating due to the protective gas injection device continuing to inject protective gas into the test chamber. It should be noted that the third preset negative pressure threshold can be set in various ways. In some embodiments, the third preset negative pressure threshold can be equal to, less than, or greater than the first preset negative pressure threshold. In some embodiments, the difference between the third preset negative pressure threshold and the first preset negative pressure threshold can be less than a certain first preset difference.

[0055] For example, the pressure detection device can also be configured to: when the pressure in the test chamber is detected to be less than a fourth preset negative pressure threshold, indicating that the vacuuming device has sufficiently evacuated the test chamber, the pressure detection device can automatically trigger the protective gas injection device to inject protective gas into the test chamber, thereby replacing the air in the test chamber with protective gas. This maintains the pressure in the test chamber at a negative pressure greater than or equal to the fourth preset negative pressure threshold, preventing excessive pressure difference between the test chamber and the external atmospheric pressure, which could lead to significant deformation of the upper and / or lower housings and affect the reliability of electrical contact between the probe card and the power semiconductor wafer 105. It should be noted that the fourth preset negative pressure threshold can be set in various ways. In some embodiments, the fourth preset negative pressure threshold can be equal to, less than, or greater than a second preset negative pressure threshold. In some embodiments, the difference between the fourth preset negative pressure threshold and the second preset negative pressure threshold can be less than a certain second preset difference.

[0056] For example, the unidirectional flow direction of the first one-way valve is from the test chamber towards the vacuum pumping device; the first one-way valve is configured to open when the air pressure in the test chamber is greater than a first set negative pressure threshold, and to close when the air pressure in the test chamber is less than a second set negative pressure threshold. By coupling the switching between the open and closed states of the first one-way valve with the aforementioned first and second set negative pressure thresholds, the air pressure in the test chamber can be maintained between the first and second set negative pressure thresholds using only the first one-way valve, thereby simplifying the difficulty of maintaining the air pressure in the test chamber within a certain set negative pressure range.

[0057] For example, the unidirectional flow direction of the second one-way valve is from the protective gas injection device towards the test chamber. The second one-way valve is configured to close when the gas pressure in the test chamber is greater than a third preset negative pressure threshold, and to open when the gas pressure in the test chamber is less than a fourth preset negative pressure threshold. By coupling the switching between the open and closed states of the second one-way valve with the aforementioned third and fourth preset negative pressure thresholds, the gas pressure of the protective gas in the test chamber can be maintained between the third and fourth preset negative pressure thresholds using only the second one-way valve, thereby simplifying the difficulty of maintaining the gas pressure of the protective gas in the test chamber within a certain set negative pressure range.

[0058] For example, refer to Figure 1 A circuit board 102, such as but not limited to a PCB board, is fixed to the upper housing. The upper housing may have a frame, thereby fixing the circuit board 102 to the frame of the upper housing. The circuit board 102 and the upper housing are separated by an insulating layer of insulating material such as PEEK / PTFE to prevent creepage on the back of the pads (PAD points) in the middle area of ​​the circuit board 102. A reinforced insulating layer 103 composed of high-hardness / high-temperature resistant / insulating material is provided below the circuit board 102. The reinforced insulating layer 103 is used to fix the current-conducting medium (usually a spring-loaded probe) used for aging testing, while also improving the supporting rigidity of the circuit board 102 and the insulation between different probes. An upper sealing frame is used to maintain the airtightness of the test chamber after installation. Thus, the above structure constitutes the upper chamber for testing.

[0059] Exemplarily, the lower housing includes, but is not limited to, an adsorption device, a lower sealing frame, and a protective gas injection structure with adjustable pressure. The lower housing may be equipped with a heating device to heat the power semiconductor wafer 105. The heating device may be a heating plate with two one-way valves installed on it, acting as a first and a second one-way valve respectively. For each one-way valve, gas can only flow in one direction. The second one-way valve is additionally equipped with a pressure regulating spring, ensuring that the second pressure threshold for one-way flow of the second one-way valve is greater than atmospheric pressure. At this time, no gas will enter the test chamber after it is evacuated; however, when a protective gas such as high-pressure nitrogen or a high-pressure mixed gas is applied to the inlet 108 of the second one-way valve, protective gas can be effectively injected into the test chamber.

[0060] For example, there may be two air nozzles on the heating plate, one of which is a negative pressure suction nozzle connected to a first one-way valve; the other is a positive pressure air inlet nozzle connected to a second one-way valve.

[0061] For example, the lower housing can be electrically contacted with the second surface of the power semiconductor wafer 105, thereby forming a circuit for the test voltage through the lower housing. For example, the lower housing can be a conductive sheet that electrically contacts the second surface of the power semiconductor wafer 105, and can have adsorption devices such as adsorption holes on the conductive sheet for adsorbing the wafer.

[0062] There are several ways to configure the upper and lower sealing frames. For example, the upper and lower sealing frames can be configured as a sealing structure 107 consisting of a sealing frame and three O-rings. One O-ring is installed between the circuit board 102 and the upper housing to seal the upper area between the circuit board 102 and the housing. The upper sealing frame and one of the O-rings are fixedly mounted on the circuit board 102 to seal both the upper sealing frame and the circuit board 102. The last O-ring is installed on the heating plate to seal the upper and lower housings after they are snapped together to form the test chamber.

[0063] It should be noted that the first one-way valve's function is to allow one-way flow of negative pressure suction, preventing pressure release after the test chamber is evacuated, thus ensuring the test chamber maintains negative pressure. The second one-way valve is installed in reverse and includes an additional pressure regulating spring, ensuring that the second pressure threshold for one-way flow of the second one-way valve is greater than atmospheric pressure. Its function is to maintain a negative pressure state within the test chamber, allowing protective gas to be injected only when the positive pressure inlet is above a certain pressure (above atmospheric pressure). The protective gas injected through the positive pressure inlet can be various insulating protective gases such as nitrogen, improving the high-voltage withstand performance of the aging test within the test chamber. Furthermore, it should be noted that even after injecting a small amount of insulating protective gas, a certain amount of negative pressure is maintained within the test chamber, keeping the entire test chamber in a closed state.

[0064] For example, the first inlet of the first one-way valve is connected to the test chamber, and the first outlet of the first one-way valve is connected to the vacuum pumping device; the second inlet of the second one-way valve is connected to the protective gas injection device, and the second outlet of the second one-way valve is connected to the test chamber. In this manner, the inlets and outlets of the two one-way valves are arranged in opposite directions, thereby simplifying the setup of the first and second one-way valves.

[0065] For example, the first check valve includes a first pressure valve disposed within the first check valve, which is on / off connected between a first air inlet and a first air outlet. The first pressure valve is configured to open when the pressure difference between the first air inlet and the first air outlet is greater than a first set pressure threshold, and to close when the pressure difference between the first air inlet and the first air outlet is less than or equal to the first set pressure threshold. In this manner, the control of the opening and closing of the first check valve is coupled with the first set pressure threshold, thereby allowing the air pressure in the test chamber to be maintained at a certain set negative pressure state by setting an appropriate first set pressure threshold.

[0066] For example, the second check valve includes a second pressure valve disposed within the second check valve, the second pressure valve being able to switch on and off between a second air inlet and a second air outlet. The second pressure valve is configured to open when the air pressure at the second air inlet is greater than a second set pressure threshold, and to close when the air pressure at the second air inlet is less than or equal to the second set pressure threshold, wherein the second set pressure threshold is greater than one atmosphere. In this manner, the control of the opening and closing of the second check valve is coupled with the second set pressure threshold, thereby allowing the pressure of the protective gas in the test chamber to be maintained at a certain set negative pressure state by setting an appropriate second set pressure threshold.

[0067] For example, the second pressure valve includes: a second valve disposed within the second check valve, and a pressure regulating spring coupled to the second valve. The pressure regulating spring actuates the second valve to open when the air pressure at the second air inlet is greater than a second set pressure threshold, and actuates the second valve to close when the air pressure at the second air inlet is less than or equal to the second set pressure threshold. By employing a pressure regulating spring, the configuration for closing and opening the second check valve is achieved, thereby simplifying the coupling between the second check valve and the second set pressure threshold.

[0068] For example, a protective gas concentration detection device is provided in the test chamber for detecting the concentration of protective gas in the test chamber. The protective gas concentration detection device can detect the concentration of protective gas in the test chamber in real time and accurately, so as to facilitate timely judgment on whether the content of protective gas has reached a certain set concentration value range, thereby accurately controlling the amount of protective gas in the test chamber.

[0069] Example 2 This disclosure also provides a test protection method for power semiconductor wafers. This test protection method is based on any of the power semiconductor wafer test protection systems provided in Embodiment 1 of this disclosure, with reference to... Figure 1 , Figure 3 and Figure 4 The method mainly includes the following steps: In step S210, the power semiconductor wafer 105 is placed on the tray 106, and the first side of the power semiconductor wafer 105 is adsorbed by the adsorption device. In step S220, multiple probes 104 on the probe card are electrically contacted to the second side of the power semiconductor wafer 105, and the test cavity is sealed. In step S230, a vacuum pumping device is used to evacuate the test chamber so that the gas pressure in the test chamber is in a negative pressure state, thereby increasing the breakdown voltage of the gas in the test chamber. In step S240, a test voltage is applied to the power semiconductor wafer 105 through multiple probes 104.

[0070] For example, the test protection system may further include: a protective gas injection device that is in on / off communication with the test chamber, the protective gas injection device being used to inject protective gas into the test chamber to replace the gas in the test chamber.

[0071] For example, the method may further include: injecting protective gas into the test chamber using a protective gas injection device, and the gas pressure in the test chamber remains negative when a test voltage is applied to the power semiconductor wafer 105 through multiple probes 104.

[0072] For example, the method of using a vacuuming device and a protective gas injection device to evacuate the test chamber and inject protective gas to bring the gas pressure in the test chamber to a negative pressure state composed of protective gas may include: controlling the protective gas injection device to inject protective gas into the test chamber at a set inlet flow rate while controlling the vacuuming device to evacuate the test chamber at a set pumping flow rate; wherein the set pumping flow rate is greater than or equal to the set inlet flow rate; when the gas pressure in the test chamber is less than a second set negative pressure threshold, controlling the vacuuming device to stop evacuating the test chamber; when the gas pressure in the test chamber reaches a third set negative pressure threshold, controlling the protective gas injection device to stop injecting protective gas into the test chamber, so that the test chamber is in a negative pressure state composed of protective gas.

[0073] For example, the method of using a vacuum pumping device and a protective gas injection device to evacuate the test chamber and inject protective gas to bring the gas pressure in the test chamber to a negative pressure state composed of protective gas may include: Step 1: Control the vacuum pumping device to evacuate the test chamber until the gas pressure in the test chamber is less than a second set negative pressure threshold, then control the vacuum pumping device to stop evacuating the test chamber; Step 2: Control the protective gas injection device to inject protective gas into the test chamber until the gas pressure in the test chamber is greater than a third set negative pressure threshold, then control the protective gas injection device to stop injecting protective gas into the test chamber; Step 1 and Step 2 are executed alternately until the test chamber is in a negative pressure state composed of protective gas.

[0074] For example, the method of using a vacuuming device and a protective gas injection device to evacuate the test chamber and inject protective gas to bring the gas pressure in the test chamber to a negative pressure state composed of protective gas may include: controlling the protective gas injection device to inject protective gas into the test chamber, and when the gas pressure in the test chamber is greater than or equal to a set positive pressure threshold, controlling the protective gas injection device to stop injecting protective gas into the test chamber; after waiting for a set time, controlling the vacuuming device to evacuate the test chamber until the gas pressure in the test chamber is less than or equal to a second set negative pressure threshold; controlling the protective gas injection device to inject protective gas into the test chamber until the gas pressure in the test chamber reaches a third set negative pressure threshold, and controlling the protective gas injection device to stop injecting protective gas into the test chamber, so that the test chamber is in a negative pressure state composed of protective gas.

[0075] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A test and protection system for power semiconductor wafers, characterized in that, include: A sealable test chamber; A tray for holding a power semiconductor wafer located in the test cavity, the tray being provided with an adsorption device for adsorbing the first side of the power semiconductor wafer; The probe card includes a circuit board located in the test cavity and spaced apart from the tray, and a plurality of probes disposed on the side of the circuit board facing the tray and spaced apart. The plurality of probes are used to make electrical contact with a second surface of the power semiconductor wafer, wherein the first surface and the second surface are disposed opposite to each other. A vacuum pumping device is connected to the test chamber in a way that can be switched on and off. The vacuum pumping device is used to evacuate the test chamber when a test voltage is applied to the power semiconductor wafer through the plurality of probes, so that the gas pressure in the test chamber is in a negative pressure state, thereby increasing the breakdown voltage of the gas in the test chamber.

2. The system as described in claim 1, characterized in that, Also includes: A protective gas injection device that is in continuous or disconnectable communication with the test chamber, the protective gas injection device being used to inject protective gas into the test chamber to replace the gas in the test chamber; Furthermore, after the protective gas injection device injects protective gas into the test chamber, the gas pressure in the test chamber remains negative when the test voltage is applied to the power semiconductor wafer through the multiple probes.

3. The system as described in claim 1, characterized in that, The power semiconductor wafer includes multiple arrays of power semiconductor device regions arranged at intervals, each power semiconductor device region including a front electrode structure group disposed on the first surface, and each front electrode structure group including at least one front electrode structure. The circuit board has multiple test unit areas arranged in an array on the side facing the tray. Each of the multiple test unit areas corresponds one-to-one with a multiple power semiconductor device area. Each test unit area includes a probe group for electrical contact with the electrode structure group of its corresponding power semiconductor device area. Each probe group includes at least one probe, such that the multiple probes are arranged at intervals.

4. The system as described in claim 3, characterized in that, Each of the power semiconductor device regions further includes a back electrode structure disposed on the second surface, and the tray is a conductive structure that electrically contacts the plurality of back electrode structures.

5. The system as described in claim 3, characterized in that, It also includes a heating device that can heat the power semiconductor wafer via the tray.

6. The system as described in claim 1, characterized in that, Also includes: A reinforcing insulating layer is stacked on the circuit board facing the tray side, and the probe penetrates the reinforcing insulating layer from the circuit board and exposes the surface of the reinforcing insulating layer facing away from the circuit board.

7. The system as described in claim 2, characterized in that, The edges of the tray are provided with a sealing structure; The test protection system further includes: a cover plate that is fastened to the tray by the sealing structure to form a sealed test cavity, wherein the probe is disposed on the side of the cover plate facing the tray, so that when the cover plate is fastened to the tray, the probe makes electrical contact with the second side of the power semiconductor wafer.

8. The system as described in claim 7, characterized in that, Also includes: An air extraction port connecting the vacuum pumping device and the test chamber, and an air inlet port connecting the protective gas injection device and the test chamber.

9. A test protection method for power semiconductor wafers, characterized in that, The test protection method is based on the test protection system for power semiconductor wafers as described in any one of claims 1 to 8, and the method includes: A power semiconductor wafer is placed on a tray, and an adsorption device adsorbs the first side of the power semiconductor wafer. Multiple probes on the probe card are electrically contacted to the second side of the power semiconductor wafer, and the test cavity is sealed. The test chamber is evacuated using a vacuum pump to create a negative pressure environment, thereby increasing the breakdown voltage of the gas in the test chamber. Test voltages are applied to the power semiconductor wafer using the multiple probes.

10. The method as described in claim 9, characterized in that, The test protection system further includes: a protective gas injection device that is in continuous communication with the test chamber, the protective gas injection device being used to inject protective gas into the test chamber to replace the gas in the test chamber; The method further includes: injecting protective gas into the test chamber using the protective gas injection device, and maintaining a negative pressure in the test chamber when a test voltage is applied to the power semiconductor wafer through the plurality of probes.

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