Test structure and test method

CN122138669APending Publication Date: 2026-06-02SEMICON MFG SOUTH CHINA CORP +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SEMICON MFG SOUTH CHINA CORP
Filing Date
2024-11-28
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

In the existing technology, the performance of test structures for obtaining interconnect via resistance needs to be improved, especially in multilayer metal integrated circuits, where each metal layer needs to be electrically connected to the test signal loading terminal, resulting in an excessively large area occupied by the signal loading terminal in the test structure, which affects performance.

Method used

A test structure is provided, in which conductive stacked layers are longitudinally stacked on a substrate, any two conductive layers constitute a test conductive group, multiple test signal loading terminals are electrically connected to the conductive layers, and the conductive layers are melted by a fusible signal loading terminal, and the resistance of the two conductive layers is obtained through a set of test signal loading terminals, thereby reducing the number of test signal loading terminals used.

Benefits of technology

By reducing the number of test signal loading terminals, the occupied area is reduced, thereby improving the performance and accuracy of the test structure, making it suitable for interconnect via resistance testing in the semiconductor manufacturing industry.

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Abstract

A test structure and method are disclosed. The structure includes: a substrate comprising a region under test (UTP) and a signal loading region; a conductive stack structure, longitudinally stacked on top of the substrate above the UTP region, the conductive stack structure comprising multiple conductive layers, any two conductive layers constituting a test conductive group; multiple test signal loading terminals located above the substrate above the signal loading region, and electrically connected to the conductive layers in the test conductive group; and a fusible signal loading terminal located above the substrate on the side of the test signal loading terminal, and electrically connected to any conductive layer in the test conductive group. This reduces the area occupied by the test signal loading terminals, thereby improving the performance of the test structure.
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