Critical dimension bar structures for process monitoring and critical dimension monitoring method

Abstract

This invention provides a critical dimension strip structure and a critical dimension monitoring method for process monitoring. The critical dimension strip structure is a vertically symmetrical structure, capable of simultaneously performing ADI and AEI measurements at different positions within the critical dimension strip structure. The critical dimension strip structure includes a first measurement unit and a second measurement unit symmetrically arranged in the vertical direction. The first measurement unit is used for ADI measurement, and the second measurement unit is used for AEI measurement. Both the first and second measurement units include a long line and four short lines symmetrically placed on both sides of the long line. Both the long and short lines are strip-shaped. In the vertical direction, the long line of the first measurement unit is connected to the long line of the second measurement unit, and each short line of the first measurement unit is connected to a corresponding short line in the second measurement unit, enabling post-development inspection and post-etching inspection to be performed at symmetrical positions on the same structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a critical dimension strip structure for process monitoring and a critical dimension monitoring method. Background Technology

[0002] In advanced manufacturing processes for integrated circuits (ICs), process monitoring is a core element in ensuring chip performance, yield, and production stability. Among these processes, precise measurement of the microscopic feature dimensions formed after critical steps such as photolithography and etching—known as critical dimension (CD) monitoring—is one of the most direct means of assessing process windows and diagnosing process fluctuations.

[0003] To efficiently monitor process uniformity across the entire chip area, wafer fabs typically set up dedicated test patterns in non-product areas of the wafer (such as dicing slots), for example... Figure 1 The key dimension strip structures shown (i.e., the first CD Bar structure 1) serve as proxy monitoring points for process status. These structures are manufactured according to the general design rules of the process platform, and by measuring their dimensions, the processing quality of the product's circuit features can be indirectly reflected.

[0004] Currently, the industry commonly uses scanning electron microscopy (CD-SEM) to image and measure the dimensions of CD bars. This measurement process typically consists of two key stages: after-development inspection (ADI), performed immediately after photoresist development, and after-etch inspection (AEI), performed after the dielectric or metal layer etching is completed. ADI is used to monitor the photolithography patterning results, while AEI is used to confirm the final structural dimensions transferred to the substrate. Together, they form a critical data chain for evaluating the integrity of a single process layer.

[0005] However, existing monitoring methods face a fundamental challenge: Figure 2 As shown, when the electron beam used in CD-SEM scans the photoresist, it causes the photoresist material to shrink, leading to deviations in the subsequent etching process using the photoresist layer 12 as a mask. Specifically, the AEI measurement result a2 in substrate 11 is greater than the ADI measurement result a1, thus distorting the AEI measurement result. To mitigate this effect, the industry currently adopts a strategy of spatially offsetting the measurement positions of ADI and AEI. However, this approach weakens the direct correspondence between ADI and AEI data, hindering accurate process traceability and root cause analysis. This limitation in layout and data consistency is particularly pronounced when full-wafer-area scanning monitoring is required.

[0006] Therefore, ensuring a strict and reliable spatial correspondence between ADI and AEI data without sacrificing measurement accuracy, and adapting it to various monitoring scenarios from sampling points to the entire map, has become a key issue in improving the monitoring level of integrated circuit manufacturing processes. Summary of the Invention

[0007] The purpose of this invention is to provide a critical dimension strip structure and a critical dimension monitoring method for process monitoring, which can solve the problems of poor data matching and difficulty in process traceability caused by the measurement positions of ADI and AEI.

[0008] To solve the above technical problems, the present invention provides a critical dimension strip structure for process monitoring. The critical dimension strip structure is a vertically symmetrical structure, which can simultaneously perform ADI and AEI measurements at different positions of the critical dimension strip structure.

[0009] The critical dimension strip structure includes a first measurement unit and a second measurement unit symmetrically arranged in the vertical direction. The first measurement unit is used for ADI measurement, and the second measurement unit is used for AEI measurement.

[0010] Both the first measuring unit and the second measuring unit include a long line and four short lines symmetrically placed on both sides of the long line, and both the long line and the short lines are bar-shaped graphics;

[0011] In the vertical direction, the long line of the first measuring unit is connected to the long line of the second measuring unit, and each short line of the first measuring unit is connected to a corresponding short line in the second measuring unit.

[0012] In some embodiments, the center-to-center distance between the first measuring unit and the second measuring unit in the vertical direction is not less than a preset value.

[0013] In some embodiments, the preset value is 1 micrometer.

[0014] In some embodiments, the critical dimension strip structure is adapted to monitor the critical dimensions of at least one of the active region layer, the gate layer, and the metal interconnect layer.

[0015] In some embodiments, the critical dimension strip structure is disposed in the dicing groove or monitoring area of ​​the wafer.

[0016] On the other hand, the present invention provides a critical dimension monitoring method, comprising the following steps:

[0017] A wafer sample to be tested is provided, wherein a photoresist layer is disposed on the surface of the wafer sample, and the photoresist layer has the critical dimension strip structure;

[0018] ADI measurement was performed on the first measuring unit of the critical dimension strip structure;

[0019] An etching process is performed using the photoresist layer as a mask to transfer the critical dimension strip structure to the wafer;

[0020] AEI measurement is performed on the second measurement unit located in the critical dimension strip structure in the wafer.

[0021] In some embodiments, the center-to-center distance between the first measuring unit and the second measuring unit in the vertical direction is not less than a preset value.

[0022] In some embodiments, the preset value is 1 micrometer.

[0023] In some embodiments, the AEI measurement is followed by:

[0024] The ADI measurement data and AEI measurement data were matched and analyzed.

[0025] In some embodiments, both the ADI measurement and the AEI measurement are performed using a scanning electron microscope.

[0026] Compared with the prior art, the present invention has the following unexpected technical effects:

[0027] This invention provides a critical dimension strip structure and a critical dimension monitoring method for process monitoring. The critical dimension strip structure is symmetrical, enabling simultaneous ADI and AEI measurements at different positions. The critical dimension strip structure includes a first measurement unit and a second measurement unit symmetrically arranged in the vertical direction. The first measurement unit performs ADI measurements, and the second measurement unit performs AEI measurements. Both the first and second measurement units include a long line and four short lines symmetrically placed on either side of the long line, both of which are strip-shaped. In the vertical direction, the long line of the first measurement unit is connected to the long line of the second measurement unit, and each short line of the first measurement unit is connected to a corresponding short line in the second measurement unit. This allows post-development inspection and post-etching inspection to be performed symmetrically at the same structure. This design avoids the influence of electron beam measurement on subsequent etching dimensions, ensuring measurement accuracy, and also ensures a direct spatial correspondence between the two measurement data, significantly improving data traceability and process analysis accuracy. It also provides a feasible and efficient solution for full-wafer surface monitoring. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a key dimension strip structure in the prior art.

[0029] Figure 2 This is a schematic diagram illustrating the principle behind AEI dimension distortion caused by performing ADI and AEI measurements at the same location in existing technologies.

[0030] Figure 3 This is a schematic diagram of existing technology that uses staggered measurement units for ADI and AEI measurements.

[0031] Figure 4 This is a schematic diagram of a key dimension strip structure for process monitoring provided in an embodiment of the present invention.

[0032] Figure 5 Is adopted Figure 4 The diagram shows the location of ADI and AEI measurements within the same structure.

[0033] Figure 6 This is a schematic diagram of full-view measurement using the key dimension strip structure of this invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1-First CD Bar structure; 2-Second CD Bar structure; 11-Substrate; 12-Photoresist layer; 100-Critical dimension strip structure; 110-First measurement unit; 120-Second measurement unit; 111-First short line; 121-Second short line; 112-First long line; 122-Second long line. Detailed Implementation

[0036] As described in the background section, in existing critical dimension monitoring processes, to avoid systematic errors in subsequent AEI measurements caused by photoresist shrinkage (typically reaching 10%-15%) due to the CD-SEM electron beam, the industry-standard solution is to place the first CD Bar structure 1 for ADI measurement and the second CD Bar structure 2 for AEI measurement in different exposure units when designing the monitoring pattern (e.g., ...). Figure 3 (As shown) within. Among them, Figure 1 This is not only a diagram of the first CD Bar structure 1, but also a diagram of the second CD Bar structure 2.

[0037] The aforementioned misaligned measurement mode raises two significant problems in practical applications:

[0038] First, the data correspondence and traceability are poor: because ADI and AEI data come from two physically independent test structures, the process correlation between them is indirect. When process diagnostics are required, especially when correlation analysis is performed between online CD data and electrical test parameters or final chip yield, this inconsistency in data sources increases the uncertainty and complexity of the analysis.

[0039] Secondly, the application limitations of full-map monitoring: When implementing full-wafer-surface scanning monitoring, due to design rules and layout space constraints, it is difficult to achieve complete physical isolation between the ADI and AEI measurement structures at all monitoring points. This results in AEI measurements still inevitably being affected by the electron beam interference from adjacent ADI measurements in some areas, causing measurement data distortion and failing to accurately reflect the etching process results. Specifically, under traditional monitoring pattern design schemes, even with sampling methods such as 9-point monitoring, ADI and AEI measurements must be performed separately in two adjacent but non-overlapping measurement units (e.g., ...). Figure 3 (As shown). For full-map solutions that aim to monitor comprehensive data, measurement errors in overlapping areas become an unavoidable technical challenge. This constitutes the core technical contradiction that this invention aims to resolve: how to simultaneously meet the conflicting requirements of avoiding electron beam interference to ensure accurate AEI measurements, and ensuring strict spatial correspondence between ADI / AEI data to support high-precision process traceability.

[0040] To address the contradiction between data matching and measurement accuracy caused by limitations in the measurement structure design, this invention proposes a critical dimension bar (CD Bar) design scheme. Specifically, as follows... Figure 4 As shown, the critical dimension strip structure provided by this invention represents a fundamental improvement in physical design. Its core design lies in its vertically symmetrical layout, meaning the critical dimension strip structure is vertically symmetrical, enabling simultaneous ADI and AEI measurements at different locations within the critical dimension strip structure. This vertically symmetrical layout of the critical dimension strip structure, within the same CD Bar structure, includes a pair of measurement units mirror-symmetrically distributed in the vertical direction (Y direction), namely the first measurement unit and the second measurement unit. This innovative structural design allows ADI and AEI measurement functions, which previously had to be distributed across different physical structural locations, to be integrated onto the same physical structure while maintaining necessary physical spacing, thus laying the foundation for subsequent measurement methods.

[0041] The symmetrical critical dimension strip structure provided by this invention has broad applicability across process layers: First, it is applied to active area (AA) layer monitoring: This structure can be used to monitor the critical dimensions of the AA layer that defines the active region of a transistor. The width and spacing of the AA layer directly affect the transistor's drive current, leakage current, and isolation characteristics. Its dimensions are typically formed using shallow trench isolation (STI) technology, and their accuracy has a fundamental impact on the device's electrical performance. Second, it is applied to gate layer monitoring: This structure is also suitable for monitoring the gate length, which is the most critical factor determining transistor performance. This invention avoids gate CD (AEI) distortion caused by the direct transfer of photoresist shrinkage to polysilicon etching during ADI measurements, thus ensuring accurate assessment of circuit speed and power consumption performance. Finally, it is applied to metal interconnect (BEOL) layer monitoring: This structure can also represent a standard solution for monitoring metal linewidth and via dimensions in back-end processes. Its symmetrical design overcomes the limitations of traditional staggered layouts, making it possible to accurately analyze the impact of photolithography-etching deviations on interconnect RC delay, thereby contributing to the precise optimization of interconnect processes.

[0042] In summary, this invention addresses the inherent contradiction between data matching and measurement accuracy throughout the entire integrated circuit manufacturing process, from the AA layer and gate layer to multilayer metal interconnects. It proposes a universal and innovative critical dimension bar (CD Bar) design scheme and corresponding monitoring method. The specific embodiments of this invention will be described in detail below with reference to the accompanying drawings.

[0043] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0044] Figure 4 This is a schematic diagram of a critical dimension strip structure for process monitoring provided in this embodiment. Figure 4 As shown, the critical dimension strip structure 100 provided in this embodiment is formed based on the design rules of a specific integrated circuit process platform, and is typically fabricated in the scribe line of a wafer or other dedicated monitoring area. The critical dimension strip structure 100 adopts a vertically symmetrical configuration, enabling simultaneous ADI and AEI measurements at different locations within the critical dimension strip structure. Both the ADI and AEI measurements are performed using a scanning electron microscope.

[0045] Specifically, the critical dimension strip structure 100 exhibits mirror symmetry in the vertical direction (i.e., the Y-direction). This symmetry does not mean that every microscopic contour of the structure must be absolutely symmetrical, but rather that its core functional units used for measurement are symmetrically distributed in layout. In a preferred embodiment, the critical dimension strip structure 100 includes a pair of measurement units symmetrically arranged in the vertical direction, namely a first measurement unit 110 and a second measurement unit 120. The first measurement unit is used for ADI measurement, and the second measurement unit is used for AEI measurement.

[0046] The first measurement unit 110 is located in the upper region of the critical dimension strip structure 100 and is configured to perform measurements for post-development inspection (ADI). The first measurement unit 110 includes a typical strip pattern for CD-SEM imaging and algorithm analysis, and its width, spacing, and other characteristic dimensions are determined according to the critical dimensions of the process layer to be monitored. The second measurement unit 120 is located in the lower region of the critical dimension strip structure 100 and is arranged symmetrically to the first measurement unit 110 in a vertical direction. The second measurement unit 120 is configured to perform measurements for post-etch inspection (AEI). Its pattern design corresponds to that of the first measurement unit 110; ideally, its design dimensions are the same as those of the first measurement unit 110 when no process steps have been performed.

[0047] The first measurement unit 110 and the second measurement unit 120 are symmetrically arranged in the Y direction, meaning that the center lines of the first measurement unit 110 and the second measurement unit 120 are symmetrical about the horizontal center line M of the critical dimension strip structure 100. This design ensures a strict and precise spatial correspondence between the first measurement unit 110 and the second measurement unit 120, as they belong to a single, inseparable physical entity (i.e., a single imaging and patterning result within the same shot), rather than two independent, separate test structures. Here, "shot" refers to an exposure unit, i.e., the area covered by a single exposure of the lithography machine.

[0048] In one embodiment, to ensure the accuracy, stability, and repeatability of critical dimension measurements, five parallel bar-shaped patterns are provided within the first measurement unit 110 and the second measurement unit 120. Specifically, these consist of a long line located in the middle and four short lines symmetrically distributed on both sides of the long line. That is, the first long line 112 and the first short line 111 of the first measurement unit 110, and the second long line 122 and the second short line 121 of the second measurement unit 120.

[0049] The first long line 112 and the second long line 122 are both bar-shaped graphics extending in the vertical direction (Y direction). The first long line 112 and the second long line 122 are the main feature graphics for critical dimension measurement. The CD-SEM measurement algorithm will mainly extract and analyze the width of these long lines. The first short line 111 and the second short line 121 are also bar-shaped graphics extending in the Y direction.

[0050] In the first measuring unit 110, four first short lines 111 are located on both sides of the first long line 112 and are parallel to the first long line 112. The length of the first short lines 111 is significantly shorter than that of the first long lines 112. The first short lines 111 typically maintain the same design width as the first long line 112, but are symmetrically shortened in the length direction, that is, the length of the first long line 112 is greater than the length of the first short lines 111. The spacing between them and the first long line is also a key design dimension that needs to be monitored.

[0051] The second measuring unit 120 has a graphic structure that is completely mirror-symmetrical to the first measuring unit 110, that is, it also contains a second long line 122 and four second short lines 121, and its size and spacing are consistent with the corresponding graphic of the first measuring unit 110.

[0052] In the vertical direction, the lower end of the first measuring unit 110 is connected to the upper end of the second measuring unit 120. Specifically, the upper end of the second long line 122 of the second measuring unit 120 is connected to the lower end of the first long line 112 of the first measuring unit 110, and the second short line 121 of each second measuring unit 120 is symmetrically connected to a corresponding first short line 111 in the first measuring unit 110, that is, the upper end of the second short line 121 of each second measuring unit 120 is connected to the lower end of the corresponding first short line 111 in the first measuring unit 110.

[0053] Figure 5 Is adopted Figure 4 The diagram shows the locations for ADI and AEI measurements within the same structure. Figure 5 Point A in the diagram represents the ADI measurement position on the first measurement unit, and point B represents the AEI measurement position on the second measurement unit. For example... Figure 5As shown, within the same critical dimension strip structure 100, the center-to-center spacing or feature spacing (i.e., the spacing between the ADI measurement position and the AEI measurement position) s between the two patterned areas used for actual measurement, the first measurement unit 110 (for ADI measurement) and the second measurement unit 120 (for AEI measurement), is greater than the electron beam influence range of ADI, for example, not less than a preset value of 1 μm, to effectively keep the AEI measurement area away from the range where the electron beam mainly affects the photoresist. In other words, when performing ADI measurement on the first measurement unit 110, the side effects of the electron beam will hardly affect the photoresist morphology in the area where the second measurement unit 120 is located, thus ensuring that the process results will not be interfered with by the preceding measurement behavior when the photoresist in the area of ​​the second measurement unit 120 is used as a mask for subsequent etching. Of course, the value of the spacing s needs to be less than the sum of the short line length of the second measurement unit 120 and the short line length of the first measurement unit 110.

[0054] The critical dimension strip structure 100 in this embodiment offers high design flexibility and process adaptability. It can be integrated into various monitoring patterns on the chip. For example, it can be used for local sampling monitoring, where multiple critical dimension strip structures 100 are arranged at certain intervals within the dicing groove to perform sampling inspection (e.g., 9-point monitoring or 5-point monitoring) to evaluate wafer process uniformity. 9-point or 5-point monitoring, common wafer-level uniformity sampling methods in semiconductor manufacturing, correspond to selecting 9 or 5 representative measurement points on the wafer, respectively. Another example is its use in full-map monitoring. Since each critical dimension strip structure 100 can complete a complete and non-interfering ADI / AEI measurement, it can be arranged in a dense array within the monitoring grid of the entire wafer, achieving comprehensive process monitoring with high spatial resolution without concerns about layout conflicts or measurement interference.

[0055] This embodiment also provides a method for monitoring the critical dimensions of a critical dimension strip structure 100, including the following steps:

[0056] Step S1: Provide a wafer sample to be tested, wherein a photoresist layer is disposed on the surface of the wafer sample, and the photoresist layer has a key dimension strip structure 100 with a symmetrical configuration.

[0057] Step S2: Perform ADI measurement on the first measurement unit of the critical dimension strip structure 100;

[0058] Step S3: Perform an etching process using the photoresist layer as a mask to transfer the critical dimension strip structure 100 to the wafer;

[0059] Step S4: Perform AEI measurement on the second measurement unit located in the critical dimension strip structure 100 in the wafer.

[0060] Step S2 specifically includes: using a CD-SEM device to image and measure the dimensions of the first measurement unit 110 of the critical dimension strip structure 100. The critical dimension (CD_ADI) measured at this time reflects the size of the pattern after the photolithography process. Due to the scanning of the electron beam, the photoresist in the area of ​​the first measurement unit 110 will shrink as expected (e.g., 10%-15%).

[0061] Step S3 specifically includes: using the developed photoresist layer (including the shrunken first measurement unit 110 region and the unaffected second measurement unit 120 region) as a mask, etching the underlying material (such as dielectric, polysilicon, or metal) to transfer the pattern of the first measurement unit 110 and the second measurement unit 120 of the critical dimension strip structure 100 onto the substrate. Subsequently, the photoresist layer is removed.

[0062] Step S4 specifically includes: using a CD-SEM device (which can be the same or another device), imaging and dimensional measurement are performed on the second measurement unit 120 located in the substrate, which is the same critical dimension strip structure 100 measured by ADI in step S2. The critical dimension (CD_AEI) measured at this time reflects the size of the actual structure finally etched onto the substrate. Since the second measurement unit 120 was not directly scanned by the electron beam in step S2, the photoresist layer, which serves as the etching mask, retains its original morphology after development. Therefore, the etched structure is more consistent with the design intent, and the CD_AEI measurement value will not have a systematic positive deviation due to the previous measurement.

[0063] Following step S4, step S5 is included: pairing and analyzing the ADI and AEI data. Specifically, CD_ADI (from the first measurement unit 110) and CD_AEI (from the second measurement unit 120) data from the same physical structure (i.e., the critical dimension strip structure 100) are automatically paired to form one-to-one data pairs to analyze the critical dimension changes from the lithography process to the etching process. Since these two data sources originate from adjacent positions under the same manufacturing step (the same lithography exposure, the same etching process), their correlation is extremely high, perfectly reflecting the process conversion from lithographic pattern to final structure.

[0064] like Figure 6As shown, in the entire process described above, the measurements in steps S2 and S4 are completed within the same process exposure unit (i.e., the same shot). This eliminates the need to move the wafer stage to different shot locations to find different test structures, and also eliminates the need for complex mapping algorithms to correlate data from different locations. This greatly simplifies the operation process, improves monitoring efficiency, and fundamentally ensures the consistency of the data source.

[0065] The critical dimension strip structure 100 and critical dimension monitoring method provided in this embodiment fundamentally solve the data distortion problem and improve the accuracy of AEI measurement. Specifically, in the prior art, the root cause of the systematically large AEI measurement values ​​is that the measurement mask (photoresist) has been damaged by the electron beam used for ADI before measurement. This embodiment physically isolates the path of damage transmission by placing the AEI measurement position (second measurement unit 120) outside the electron beam's influence range (e.g., 1 μm). Figure 3 and Figure 6 As shown in the comparison, the traditional method obtains an overestimated AEI in the overlapping area, while the method in this embodiment measures the true AEI. This allows the AEI data to truly reflect the objective results of the etching process, providing a reliable basis for the accurate evaluation of the process window and the optimization of the etching formula.

[0066] This embodiment perfectly achieves strict spatial correspondence and traceability between ADI and AEI data. Specifically, existing technologies employ staggered shot measurements (e.g., Figure 3 This approach sacrifices the direct correspondence between the data. ADI and AEI data originate from two separate structures, both fabricated under the same process conditions. However, microscopic local process fluctuations (such as micro-load effects and local heating differences) can cause slight differences in the actual experiences of the two structures, introducing non-common-mode errors caused by local non-uniformity into the data analysis. This embodiment ensures that the ADI and AEI data originate from two symmetrical points within the same structure, spaced at a preset interval of 1 micrometer. These two points experience almost identical process environments, and any process fluctuations have a synchronous and equivalent impact on them. Therefore, the obtained data is matched and comparable to CD_ADI and CD_AEI, providing an unprecedented high-quality data foundation for in-depth process decomposition and root cause analysis.

[0067] This embodiment significantly simplifies the measurement process and improves monitoring efficiency and automation. Specifically, for operators or the factory's Manufacturing Execution System (MES), the method in this embodiment simplifies the process. There is no longer a need to specify different, potentially widely spaced, test structure coordinates for ADI and AEI. The monitoring procedure can be simply defined as measuring the upper and lower features at the same coordinate point. This reduces the complexity of program editing, lowers the risk of errors (such as measuring the wrong location), and facilitates faster and smoother fully automated measurements.

[0068] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0069] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A key-dimensional strip structure for process monitoring, characterized in that, The critical dimension strip structure is a vertically symmetrical structure, which enables simultaneous ADI and AEI measurements at different positions of the critical dimension strip structure. The critical dimension strip structure includes a first measurement unit and a second measurement unit symmetrically arranged in the vertical direction. The first measurement unit is used for ADI measurement, and the second measurement unit is used for AEI measurement. Both the first measuring unit and the second measuring unit include a long line and four short lines symmetrically placed on both sides of the long line, and both the long line and the short lines are bar-shaped graphics; In the vertical direction, the long line of the first measuring unit is connected to the long line of the second measuring unit, and each short line of the first measuring unit is connected to a corresponding short line in the second measuring unit.

2. The key dimension strip structure as described in claim 1, characterized in that, The center-to-center distance between the first measuring unit and the second measuring unit in the vertical direction is not less than a preset value.

3. The key dimension strip structure as described in claim 2, characterized in that, The preset value is 1 micrometer.

4. The key dimension strip structure as described in claim 1, characterized in that, The critical dimension strip structure is suitable for monitoring the critical dimensions of at least one of the active layer, gate layer, and metal interconnect layer.

5. The key dimension strip structure as described in any one of claims 1 to 4, characterized in that, The critical dimension strip structure is set in the dicing groove or monitoring area of ​​the wafer.

6. A method for monitoring critical dimensions, characterized in that, Includes the following steps: A wafer sample to be tested is provided, wherein a photoresist layer is disposed on the surface of the wafer sample, and the photoresist layer has a critical dimension strip structure as described in claim 1; ADI measurement was performed on the first measuring unit of the critical dimension strip structure; An etching process is performed using the photoresist layer as a mask to transfer the critical dimension strip structure to the wafer; AEI measurement is performed on the second measurement unit located in the critical dimension strip structure in the wafer.

7. The critical dimension monitoring method as described in claim 6, characterized in that, The center-to-center distance between the first measuring unit and the second measuring unit in the vertical direction is not less than a preset value.

8. The critical dimension monitoring method as described in claim 7, characterized in that, The preset value is 1 micrometer.

9. The critical dimension monitoring method as described in claim 6, characterized in that, Following AEI measurement are: The ADI measurement data and AEI measurement data were matched and analyzed.

10. The critical dimension monitoring method as described in claim 7, characterized in that, Both the ADI and AEI measurements were performed using a scanning electron microscope.

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