Reuse methods for semiconductor devices and substrates

Abstract

This invention relates to a method for reusing a semiconductor device and a substrate. According to one embodiment, a method for manufacturing a semiconductor device includes: forming a first semiconductor layer on a first substrate, the first semiconductor layer containing impurity atoms of a first concentration; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer containing impurity atoms of a second concentration higher than the first concentration; and forming a porous layer, the porous layer being formed by porousening at least a portion of the second semiconductor layer. The method further includes: forming a first film on the porous layer, the first film containing a first element; preparing a second substrate, the second substrate having a second film containing a second element disposed thereon; and bonding the first substrate and the second substrate in a manner separating the first film and the second film. The method further includes: separating the first substrate and the second substrate such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

Description

[0001] Related information of divisional application This case is a divisional application. The parent application of this divisional application is the invention patent application filed on January 22, 2021, with application number 202110087368.6 and title "Semiconductor device, method for manufacturing a semiconductor device and method for reusing a substrate".

[0002] [Citation of relevant applications] This application asserts priority based on the priority of a prior Japanese patent application No. 2020-138800 filed on August 19, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, and a method for reusing a substrate. Background Technology

[0004] It is generally believed that after substrates are bonded together with layers on these substrates in between, one substrate is peeled off from the other substrate or the layer to separate the substrates from each other. In this case, a method that can effectively separate these substrates from each other is desired. Summary of the Invention

[0005] One embodiment provides a semiconductor device capable of effectively separating bonded substrates from each other, a method for manufacturing the semiconductor device, and a method for reusing the substrates.

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes: forming a first semiconductor layer on a first substrate, the first semiconductor layer comprising a first concentration of impurity atoms; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a second concentration of impurity atoms higher than the first concentration; and forming a porous layer, the porous layer being formed by porousening at least a portion of the second semiconductor layer. The method further includes: forming a first film on the porous layer, the first film comprising a first element; preparing a second substrate, the second substrate having a second film comprising a second element disposed thereon; and bonding the first substrate and the second substrate in a manner separating the first film and the second film. The method further includes: separating the first substrate and the second substrate such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

[0007] According to the aforementioned configuration, a semiconductor device capable of effectively separating bonded substrates from each other, a method for manufacturing the semiconductor device, and a method for reusing the substrates can be provided. Attached Figure Description

[0008] Figure 1 (a) to (c) are cross-sectional views (1 / 4) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0009] Figure 2 (a) to (c) are cross-sectional views (2 / 4) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figures 3(a) to 3(c) are cross-sectional views (3 / 4) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 4 (a) to (c) are cross-sectional views (4 / 4) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 5 (a) to (c) are cross-sectional views (1 / 2) of the manufacturing method of the semiconductor device of the comparative example of the first embodiment.

[0013] Figure 6 (a) to (c) are cross-sectional views (2 / 2) of the manufacturing method of the semiconductor device of the comparative example of the first embodiment.

[0014] Figure 7 This is a graph used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0015] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0016] Figure 9 This is a cross-sectional view showing the structure of the columnar portion in the second embodiment.

[0017] Figure 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1-10 In Chinese, identical components are marked with the same symbol, and repeated descriptions are omitted.

[0019] (First Embodiment) Figures 1-4 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. In this embodiment, the semiconductor device is manufactured by bonding the following wafer 1 and wafer 2 together.

[0020] Figures 1-4The X, Y, and Z directions are shown as mutually perpendicular. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. Furthermore, the -Z direction may or may not align with the direction of gravity.

[0021] First, prepare substrate 11 for wafer 1 ( Figure 1 (a)). Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. In this embodiment, substrate 11 is a P-type substrate containing boron (B) atoms as P-type impurity atoms, but it may also be a P-type substrate containing other P-type impurity atoms, or an N-type substrate containing N-type impurity atoms. Substrate 11 is an example of a first substrate.

[0022] Next, a semiconductor layer 12 and a semiconductor layer 13 are sequentially formed on the substrate 11. Figure 1 (b) Semiconductor layer 12 is, for example, a layer containing a semiconductor element and doped with impurity atoms. An example of the semiconductor element is Si (silicon), and an example of the impurity atom is a P-type impurity atom such as B atoms. Semiconductor layer 12 is, for example, a monocrystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer doped with impurity atoms. Semiconductor layer 13 is, for example, a layer containing a semiconductor element and doped with impurity atoms. An example of the semiconductor element is Si, and an example of the impurity atom is a P-type impurity atom such as B atoms. Semiconductor layer 13 is, for example, a monocrystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer doped with impurity atoms. Semiconductor layer 12 and semiconductor layer 13 contain impurity atoms of the same type (element) as B atoms, but may also contain impurity atoms of different types. One or both of semiconductor layer 12 and semiconductor layer 13 may contain P-type impurity atoms other than B atoms, or may contain N-type impurity atoms. Semiconductor layer 12 is an example of a first semiconductor layer. Semiconductor layer 13 is an example of a second semiconductor layer.

[0023] In this embodiment, semiconductor layer 12 and semiconductor layer 13 have different impurity concentrations. Specifically, the concentration of impurity atoms in semiconductor layer 13 is higher than the concentration of impurity atoms in semiconductor layer 12. The concentration of impurity atoms in semiconductor layer 12 is, for example, 1.6 × 10⁻⁶. 16 cm -3 The concentration of impurity atoms within semiconductor layer 13 is, for example, 8.5 × 10⁻⁶. 18 cm -3 The preferred value is 1.0 × 10⁴. 19 cm -3 The above describes an example of the first concentration of impurity atoms within semiconductor layer 12. The description of the second concentration of impurity atoms within semiconductor layer 13 is also provided.

[0024] In this embodiment, semiconductor layer 12 and semiconductor layer 13 have different resistivities due to different impurity concentrations. Specifically, the resistivity of semiconductor layer 13 is lower than that of semiconductor layer 12. The resistivity of semiconductor layer 12 is, for example, 0.1 Ω·cm or higher. The resistivity of semiconductor layer 13 is, for example, 0.01 Ω·cm or lower. The resistivity of semiconductor layer 12 is an example of a first resistivity. The resistivity of semiconductor layer 13 is an example of a second resistivity.

[0025] The thickness of semiconductor layer 12 is, for example, 1 to 10 μm. Similarly, the thickness of semiconductor layer 13 is, for example, 1 to 10 μm. The thicknesses of semiconductor layer 12 and semiconductor layer 13 can be the same or different. In this embodiment, the thickness of semiconductor layer 13 is greater than the thickness of semiconductor layer 12.

[0026] Furthermore, the concentration of impurity atoms in the substrate 11 can be higher or lower than the concentration of impurity atoms in the semiconductor layer 12. For example, the concentration of impurity atoms in the substrate 11 is 1.0 × 10⁻⁶. 16 cm -3 Furthermore, the resistivity of substrate 11 may be higher or lower than that of semiconductor layer 12. For example, the resistivity of substrate 11 may be 1.0 Ω·cm or higher.

[0027] Secondly, the semiconductor layer 13 is made porous (polyporous). Figure 1 (c)). As a result, semiconductor layer 13 is transformed into porous semiconductor layer 14 as a porous layer (porous material layer). The porosification of semiconductor layer 13 can be carried out by any method, such as wet etching with a metal catalyst or anodizing. Porous semiconductor layer 14 is an example of a second semiconductor layer and an example of a porous layer.

[0028] In this embodiment, only semiconductor layer 13 of semiconductor layer 13 and semiconductor layer 12 is porous, but both semiconductor layer 13 and semiconductor layer 12 may also be porous. When both semiconductor layer 13 and semiconductor layer 12 are porous, only a portion of semiconductor layer 12 may be porous, or the entire semiconductor layer 12 may be porous. Furthermore, in this embodiment, the entire semiconductor layer 13 is porous, but only a portion of semiconductor layer 13 may be porous.

[0029] When making semiconductor layer 13 porous, for example, semiconductor layer 13 is heated. At this time, if semiconductor layer 13 is an amorphous silicon layer, it can be transformed into a polycrystalline silicon layer by changing the amorphous silicon layer into a polycrystalline silicon layer, and the porous semiconductor layer 14 can also be transformed into a polycrystalline silicon layer. The same applies to the case of making semiconductor layer 12 porous.

[0030] Furthermore, the lower the resistivity of semiconductor layer 13 and semiconductor layer 12 in this embodiment, the easier it is to achieve porosity. Therefore, according to this embodiment, by setting the resistivity of semiconductor layer 13 to be lower than that of semiconductor layer 12, it is possible to selectively porosize only semiconductor layer 13 in semiconductor layer 13 and semiconductor layer 12.

[0031] In this embodiment, the impurity concentration, resistivity, and thickness of the porous semiconductor layer 14 are unlikely to change significantly due to porosity, becoming values ​​similar to those of the semiconductor layer 13. Therefore, the various conditions described for the semiconductor layer 13 generally also apply to the porous semiconductor layer 14. That is, the concentration of impurity atoms in the porous semiconductor layer 14 becomes higher than that in the semiconductor layer 12; for example, the concentration of impurity atoms in the porous semiconductor layer 14 becomes 8.5 × 10⁻⁶. 18 cm -3 The above (preferably 1.0×10) 19 cm -3 (Above). Furthermore, the resistivity of the porous semiconductor layer 14 becomes lower than that of the semiconductor layer 12, for example, becoming 0.01 Ω·cm or less. Additionally, the thickness of the porous semiconductor layer 14 is, for example, 1 to 10 μm. The same applies to the case where the semiconductor layer 12 of this embodiment is made porous.

[0032] Secondly, an anti-diffusion layer 15 is formed on the porous semiconductor layer 14. Figure 2 (a)). In this embodiment, the anti-diffusion layer 15 is formed to prevent impurity atoms from diffusing from the porous semiconductor layer 14, the semiconductor layer 12, and the substrate 11 to the layer subsequently formed on the anti-diffusion layer 15. The anti-diffusion layer 15 is, for example, a silicon oxide film, a silicon nitride film, or an aluminum oxide film. The thickness of the anti-diffusion layer 15 is, for example, 10 to 100 nm. The anti-diffusion layer is an example of a third film.

[0033] Secondly, an element layer 16 is formed on the anti-diffusion layer 15. Figure 2 (b)). Element layer 16 is a layer that contains elements that are components of the semiconductor device of this embodiment. Element layer 16 may contain, for example, a memory cell array of a three-dimensional memory as such an element. Element layer 16 is an example of a first film, and the element is an example of a first element.

[0034] Next, prepare a substrate 17 for wafer 2, and form a device layer 18 on the substrate 17. Figure 2(c)). Substrate 17 is, for example, a semiconductor substrate such as a silicon substrate. In this embodiment, substrate 17 is a P-type substrate containing B atoms as P-type impurity atoms, but it may also be a P-type substrate containing other P-type impurity atoms, or an N-type substrate containing N-type impurity atoms. Element layer 18 is a layer containing elements that are components of the semiconductor device of this embodiment. Element layer 18 may, for example, contain a control circuit that controls the operation of the memory cell array. Substrate 17 is an example of a second substrate. Furthermore, element layer 18 is an example of a second film, and the element is an example of a second element.

[0035] Next, wafer 1 and wafer 2 are bonded together (Fig. 3(a)). Specifically, substrate 11 and substrate 17 are bonded together with semiconductor layer 12, porous semiconductor layer 14, anti-diffusion layer 15, device layer 16, and device layer 17 separated by these layers. Thus, substrate 11 and substrate 17 are bonded together with device layer 16 and device layer 17 in contact with each other. Alternatively, device layer 16 and device layer 17 may be facing each other without contacting each other, but instead facing each other through other layers. In Fig. 3(a), wafer 1 is bonded to wafer 2 with its top and bottom orientation reversed.

[0036] Figure 3(a) shows a multilayer structure comprising wafer 1 and wafer 2. This multilayer structure is then divided into multiple chips through a subsequent dicing step. Each chip is, for example, a three-dimensional memory. This multilayer structure and the diced chips are examples of semiconductor devices.

[0037] Next, wafer 1 and wafer 2 are separated again (Fig. 3(b)). However, in this embodiment, wafer 1 and wafer 2 are not separated at the interface between element layer 16 and element layer 18, but rather at the surface within the porous semiconductor layer 14. Fig. 3(b) shows porous semiconductor layer 14a, which is part of porous semiconductor layer 14, and porous semiconductor layer 14b, which is the remaining part of porous semiconductor layer 14. In this embodiment, wafer 1 and wafer 2 are separated such that porous semiconductor layer 14 is divided into porous semiconductor layer 14a and porous semiconductor layer 14b. Porous semiconductor layer 14a is an example of the first part, and porous semiconductor layer 14b is an example of the second part.

[0038] In this embodiment, the substrates 11 and 17 bonded in step 3(a) are separated again in step 3(b). At this time, the porous semiconductor layer 14 is divided into porous semiconductor layer 14a and porous semiconductor layer 14b as described above. As a result, semiconductor layer 12 and porous semiconductor layer 14a remain on substrate 11, and element layer 18, element layer 16, anti-diffusion layer 15, and porous semiconductor layer 14b remain on substrate 17.

[0039] In other words, in the step shown in Figure 3(b), the substrate 11, semiconductor layer 12, and porous semiconductor layer 14a are peeled off from the substrate 17 together. The peeling surface at this time is the surface inside the porous semiconductor layer 14, that is, the surface between the porous semiconductor layer 14a and the porous semiconductor layer 14b.

[0040] Compared to the unpored semiconductor layer 13, the porous semiconductor layer 14 has a reduced physical hardness. Therefore, according to this embodiment, in the step of FIG. 3(b), wafer 1 and wafer 2 can be easily separated using a surface within the porous semiconductor layer 14 as a boundary. This surface can be located at any location within the porous semiconductor layer 14.

[0041] Next, the porous semiconductor layer 14b is removed from wafer 2 (FIG. 3(c)). Subsequently, wafer 2 is diced into multiple chips via a dicing step. Each chip in this embodiment is, for example, a three-dimensional memory containing a memory cell array within element layer 16 and control circuitry within element layer 18.

[0042] Figure 4 (a) represents wafer 1, which has been separated from wafer 2. In this method, next, the porous semiconductor layer 14a is removed from wafer 1. Figure 4 (b)). The porous semiconductor layer 14a is removed, for example, by wet etching. The solution used in this wet etching is, for example, a mixed aqueous solution containing HF (hydrofluoric acid), HNO3 (nitric acid) and CH3COOH (acetic acid).

[0043] In this embodiment, because the resistivity of semiconductor layer 13 is set to be lower than that of semiconductor layer 12, the resistivity of porous semiconductor layer 14a becomes lower than that of semiconductor layer 12. Verification shows that the etching rates of semiconductor layer 12 and porous semiconductor layer 14a decrease as the resistivity of semiconductor layer 12 and porous semiconductor layer 14a increases. Therefore, according to this embodiment, by making the resistivity of porous semiconductor layer 14a lower than that of semiconductor layer 12, the etching rate of porous semiconductor layer 14a can be made higher than that of semiconductor layer 12, thus enabling… Figure 4 In step (b), the porous semiconductor layer 14a is selectively removed. Therefore, in Figure 4 In step (b), the semiconductor layer 12 can remain and the porous semiconductor layer 14a can be removed.

[0044] Secondly, on the semiconductor layer 12 remaining on the substrate 11, a semiconductor layer 13' identical to the semiconductor layer 13 is formed. Figure 4 (c) Subsequently, using wafer 1 containing semiconductor layer 13', the process is repeated. Figure 1 (c) to Figure 4Step (b) is then performed. Thus, the wafer 1 can be reused with the substrate 11 for the manufacture of semiconductor devices. For example, by repeatedly implementing the method of this embodiment using one substrate 11 and N substrates 17, multiple chips (three-dimensional memory) (N being an integer of 2 or more) can be manufactured from each of the N substrates 17.

[0045] Figure 5 and Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example of the first embodiment.

[0046] Figure 5 (a) is the sectional view corresponding to Figure 3(a). Figure 5 In (a), wafer 1 and wafer 2 are bonded together. Note that wafer 1 in this comparative example does not contain semiconductor layer 12.

[0047] Secondly, wafer 1 and wafer 2 are separated again. Figure 5 (b)). In this comparative example, wafer 1 and wafer 2 are also separated by the inner surface of the porous semiconductor layer 14. Therefore, the porous semiconductor layer 14 is divided into porous semiconductor layer 14a and porous semiconductor layer 14b. As a result, porous semiconductor layer 14a remains on substrate 11, and device layer 18, device layer 16, anti-diffusion layer 15 and porous semiconductor layer 14b remain on substrate 17.

[0048] Secondly, the porous semiconductor layer 14b is removed from wafer 2. Figure 5 (c) Subsequently, wafer 2 is divided into multiple chips through a dicing step.

[0049] Figure 6 (a) represents wafer 1, which has been separated from wafer 2. In this method, next, the porous semiconductor layer 14a is removed from wafer 1. Figure 6 (b)). The porous semiconductor layer 14a is removed, for example, by wet etching.

[0050] At this point, the surface of substrate 11 is exposed through wet etching, and therefore the surface of substrate 11 may be subject to some adverse effects such as damage caused by wet etching. Furthermore, if the concentration of boron atoms in substrate 11 is higher than the concentration of boron atoms in porous semiconductor layer 14a, the resistivity of substrate 11 becomes lower than that of porous semiconductor layer 14a, and the etching rate of substrate 11 becomes higher than that of porous semiconductor layer 14a. As a result, substrate 11 may become thinner due to wet etching. Figure 6 (b) indicates the case where the thickness of substrate 11 is reduced by thickness D due to thinning.

[0051] Secondly, a semiconductor layer 13' identical to the semiconductor layer 13 is formed on the substrate 11. Figure 6(c) Subsequently, using wafer 1 containing semiconductor layer 13', the process is repeated. Figure 5 (a) to Figure 6 Step (b) is then performed. In this case, if the surface of the substrate 11 is damaged by wet etching or if the substrate 11 becomes thinner, it may hinder the reuse of the substrate 11. In this embodiment, a porous semiconductor layer 14a is provided on the substrate 11 through the interposer semiconductor layer 12. As a result, surface damage to the substrate 11 or thinning of the substrate 11 caused by wet etching can be suppressed. Therefore, the porous semiconductor layer 14a can be removed from the substrate 11 to facilitate the reuse of the substrate 11.

[0052] Figure 7 This is a graph used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0053] exist Figure 7 In the figure, the horizontal axis represents the resistivity of semiconductor layer 12 and porous semiconductor layer 14a, and the vertical axis represents the etching rate of semiconductor layer 12 and porous semiconductor layer 14a. Figure 7 This illustrates the relationship between resistivity and etching rate when etching semiconductor layer 12 and porous semiconductor layer 14a using a mixed aqueous solution containing HF, HNO3, and CH3COOH. For example... Figure 7 As shown, the etching rates of semiconductor layer 12 and porous semiconductor layer 14a decrease as the resistivity of semiconductor layer 12 and porous semiconductor layer 14a increases. Therefore, according to this embodiment, it is possible to... Figure 4 In step (b), the porous semiconductor layer 14a is selectively removed.

[0054] It should be noted that, according to Figure 7 It is known that the etching rate changes significantly as the resistivity changes from 0.01 Ω·cm to 0.1 Ω·cm. Therefore, according to this embodiment, by setting the resistivity of semiconductor layer 12 to 0.1 Ω·cm or higher and the resistivity of semiconductor layer 13 to 0.01 Ω·cm or lower, the removal of semiconductor layer 12 can be effectively suppressed when removing porous semiconductor layer 14a.

[0055] As described above, in this embodiment, a semiconductor layer 13 is formed on the substrate 11 through a semiconductor layer 12, thereby making the semiconductor layer 13 porous. Furthermore, after the substrate 11 and substrate 17 are bonded together, the substrate 11 and substrate 17 are separated. Therefore, according to this embodiment, the bonded substrate 11 and substrate 17 can be separated effectively. For example, the substrate 11 and substrate 17 can be easily separated along the surface within the porous semiconductor layer 14, or the porous semiconductor layer 14a can be removed from the substrate 11 in a manner suitable for reuse.

[0056] (Second Implementation)Figure 8 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. Figure 8 This illustrates an example of a semiconductor device manufactured using the method of the first embodiment. Figure 8 The semiconductor device is a three-dimensional memory formed by bonding an array region 1' from wafer 1 and a circuit region 2' from wafer 2.

[0057] Array region 1' includes a component layer 16. In this embodiment, the component layer 16 includes a memory cell array 16a containing multiple memory cells, an insulating film 16b on the memory cell array 16a, and an interlayer insulating film 16c below the memory cell array 16a. The insulating film 16b is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 16c is, for example, a silicon oxide film or a laminated film containing a silicon oxide film and other insulating films.

[0058] Circuit region 2' is disposed below array region 1'. The symbol S indicates the bonding surface between array region 1' and circuit region 2'. Circuit region 2' includes a component layer 18 and a substrate 17 beneath the component layer 18. In this embodiment, the component layer 18 has an interlayer insulating film 18a between the interlayer insulating film 16c and the substrate 17. The interlayer insulating film 18a is, for example, a silicon oxide film or a laminated film comprising a silicon oxide film and other insulating films.

[0059] The array region 1' has multiple word lines WL and source lines SL as multiple electrode layers within the memory cell array 16a. Figure 8 The stepped structure 21 of the memory cell array 16a is shown. Each word line WL is electrically connected to the word wiring layer 23 via contact plugs 22. Each columnar portion CL passing through multiple word lines WL is electrically connected to the bit line BL via dielectric plugs 24, and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 as a semiconductor layer and a second layer SL2 as a metal layer.

[0060] Circuit region 2' includes a plurality of transistors 31. Each transistor 31 includes: a gate electrode 32, a gate insulating film disposed on a substrate 17; and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 17. In addition, circuit region 2' includes: a plurality of contact plugs 33 disposed on the gate electrode 32, source diffusion layer or drain diffusion layer of these transistors 31; a wiring layer 34 disposed on these contact plugs 33, including a plurality of wirings; and a wiring layer 35 disposed on the wiring layer 34, including a plurality of wirings.

[0061] Circuit region 2' also includes: a wiring layer 36 disposed on wiring layer 35, comprising multiple wirings; multiple dielectric plugs 37 disposed on wiring layer 36; and multiple metal pads 38 disposed on these dielectric plugs 37. The metal pads 38 are, for example, Cu (copper) layers or Al (aluminum) layers. Circuit region 2' functions as a control circuit (logic circuit) for controlling the operation of array region 1'. This control circuit is composed of transistors 31, etc., and is electrically connected to the metal pads 38.

[0062] Array region 1' includes: a plurality of metal pads 41 disposed on metal pads 38; and a plurality of interlayer plugs 42 disposed on the metal pads 41. Furthermore, array region 1' includes: a wiring layer 43 disposed on these interlayer plugs 42, comprising a plurality of wirings; and a wiring layer 44 disposed on the wiring layer 43, comprising a plurality of wirings. The metal pads 41 are, for example, Cu layers or Al layers. The bit lines BL are contained in the wiring layer 44. Furthermore, the control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc.

[0063] The array region 1' also includes: a plurality of dielectric plugs 45 disposed on the wiring layer 44; metal pads 46 disposed on these dielectric plugs 45 and on the insulating film 16b; and a passivation film 47 disposed on the metal pads 46 and on the insulating film 16b. The metal pads 46 are, for example, Cu layers or Al layers, serving as... Figure 8 The external connection pads (bonding pads) of the semiconductor device function as such. The passivation film 47 is an insulating film, such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or other device via bonding wires, solder balls, metal bumps, etc., through the opening P.

[0064] Figure 9 This is a cross-sectional view showing the structure of the columnar portion CL in the second embodiment.

[0065] like Figure 9 As shown, the memory cell array 16a includes an interlayer insulating film 16c. Figure 8 The surface contains alternating layers of multiple word lines WL and multiple insulating layers 51. The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films.

[0066] The columnar portion CL sequentially comprises a barrier insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, a silicon nitride film, and the barrier insulating film 52 is formed on the sides of the word line WL and the insulating layer 51. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer, and the tunnel insulating film 54 is formed on the sides of the charge storage layer 53. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0067] Figure 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment.

[0068] Figure 10 Wafer 1, containing multiple array regions 1', and wafer 2, containing multiple circuit regions 2', are shown. Wafer 1 is referred to as an array wafer or memory wafer, and wafer 2 is referred to as a circuit wafer or CMOS (Complementary Metal-Oxide Semiconductor) wafer.

[0069] It is important to note that Figure 10 The orientation of wafer 1 and Figure 8 The array regions 1' are oriented in opposite directions. In this embodiment, a semiconductor device is manufactured by bonding wafer 1 and wafer 2 together. Figure 10 This shows wafer 1 before its orientation is reversed for bonding. Figure 8 The array region 1' after being reversing its orientation and then being bonded and cut is shown.

[0070] exist Figure 10 In the diagram, symbol S1 represents the upper surface of wafer 1, and symbol S2 represents the upper surface of wafer 2. It should be noted that wafer 1 has a substrate 11, which is disposed under the insulating film 16b, separated by an anti-diffusion layer 15, a porous semiconductor layer 14, and a semiconductor layer 12.

[0071] In this embodiment, firstly, as Figure 10 As shown, a semiconductor layer 12, a porous semiconductor layer 14, an anti-diffusion layer 15, an insulating film 16b, a memory cell array 16a, an interlayer insulating film 16b, a stepped structure portion 21, and a metal pad 41 are formed on the substrate 11 of wafer 1. An interlayer insulating film 18a, a transistor 31, and a metal pad 38 are formed on the substrate 17 of wafer 2. For example, an interlayer plug 45, a wiring layer 44, a wiring layer 43, an interlayer plug 42, and a metal pad 41 are sequentially formed on the substrate 11. Furthermore, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, an interlayer plug 37, and a metal pad 38 are sequentially formed on the substrate 17.

[0072] Secondly, such as Figure 8 As shown, wafer 1 and wafer 2 are bonded together by mechanical pressure. This bonds interlayer insulating film 16c and interlayer insulating film 18a. Next, wafer 1 and wafer 2 are annealed at 400°C. This bonds metal pad 41 and metal pad 38.

[0073] Subsequently, using the inner surface of the porous semiconductor layer 14 as a boundary, the substrate 11 and substrate 17 are separated, and the substrate 17 and its various layers are cut into multiple chips. This is how they are manufactured. Figure 8 The semiconductor device. In addition, the metal pad 46 and the passivation film 47 are formed on the insulating film 16b, for example, after separating the substrate 11 and the substrate 17 and removing the porous semiconductor layer 14b and the anti-diffusion layer 15 on the substrate 17.

[0074] As described above, according to this embodiment, a semiconductor device comprising an array region 1' from wafer 1 and a circuit region 2' from wafer 2 can be manufactured using the method of the first embodiment. According to this embodiment, when manufacturing such a semiconductor device, the mating substrate 11 and substrate 17 can be well separated.

[0075] Several embodiments have been described above, but these embodiments are merely examples and are not intended to limit the scope of the invention. The novel apparatus and method described in this specification can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass all such embodiments and variations contained in the scope and spirit of the invention.

Claims

1. A semiconductor device comprising: First substrate; A first semiconductor layer is disposed on the first substrate and contains a first concentration of impurity atoms; A second semiconductor layer, serving as a porous layer, is disposed on the first semiconductor layer and contains impurity atoms at a second concentration higher than the first concentration; and The first film is disposed on the second semiconductor layer and contains the first element.

2. The semiconductor device according to claim 1, characterized in that: The first film separates the third film formed on the second semiconductor layer, and the third film prevents the impurity atoms from diffusing from the first and second semiconductor layers to the first film.

3. A semiconductor device comprising: First substrate; A first semiconductor layer is disposed on the first substrate and contains a first concentration of impurity atoms; A second semiconductor layer, serving as a porous layer, is disposed on the first semiconductor layer and contains impurity atoms at a second concentration higher than the first concentration; and A third film is disposed on the second semiconductor layer to prevent the diffusion of impurity atoms from the first and second semiconductor layers.

4. The semiconductor device according to claim 3, characterized in that: It also includes a first membrane disposed on the third membrane, which contains a first element.

5. The semiconductor device according to claim 4, characterized in that: The first membrane includes a storage cell array as the first element.

6. The semiconductor device according to claim 1 or 3, characterized in that: The concentration of the impurity atoms in the first semiconductor layer is 1.6 × 10⁻⁶. 16 cm -3 the following.

7. The semiconductor device according to claim 1 or 3, characterized in that: The concentration of the impurity atoms in the second semiconductor layer is 8.5 × 10⁻⁶. 18 cm -3 above.

8. The semiconductor device according to claim 1 or 3, characterized in that: The impurity atoms in the first semiconductor layer and the impurity atoms in the second semiconductor layer are of the same type.

9. The semiconductor device according to claim 1 or 3, characterized in that: The first semiconductor layer has a first resistivity, and the second semiconductor layer has a second resistivity that is lower than the first resistivity.

10. The semiconductor device according to claim 9, characterized in that: The first resistivity is 0.1 Ω·cm or higher.

11. The semiconductor device according to claim 9, characterized in that: The second resistivity is below 0.01 Ω·cm.

12. The semiconductor device according to claim 1 or 3, characterized in that: The second semiconductor layer is an amorphous layer.

13. The semiconductor device according to claim 1 or 3, characterized in that: The second semiconductor layer is a polycrystalline layer.

14. A semiconductor device comprising: Substrate; A second film is disposed on the substrate and includes a second element; A first membrane, disposed on the second membrane, includes a first element; and The third membrane is disposed on the first membrane and functions as an anti-diffusion layer.

15. The semiconductor device according to claim 14, characterized in that... It also has: A semiconductor layer, disposed on the third film, includes a porous portion.

16. The semiconductor device according to claim 1 or 14, characterized in that: The first membrane includes a storage cell array as the first element.

17. The semiconductor device according to claim 14, characterized in that: The second membrane includes a control circuit for controlling the memory cell array as the second element.

18. The semiconductor device according to any one of claims 2, 3, and 14, characterized in that: The third film is a silicon oxide film, a silicon nitride film, or an aluminum oxide film.

19. A semiconductor device comprising: First substrate; The first semiconductor layer is disposed under the first substrate and contains impurity atoms of a first concentration; The second semiconductor layer, which is a porous layer, is disposed below the first semiconductor layer and contains impurity atoms at a second concentration higher than the first concentration. The first film is disposed under the second semiconductor layer and contains the first element; A second membrane, disposed beneath the first membrane, includes a second element; and The second substrate is disposed under the second film.

20. The semiconductor device according to claim 19, characterized in that: The concentration of the impurity atoms in the first semiconductor layer is 1.6 × 10⁻⁶. 16 cm -3 the following.

21. The semiconductor device according to claim 19, characterized in that: The concentration of the impurity atoms in the second semiconductor layer is 8.5 × 10⁻⁶. 18 cm -3 above.

22. The semiconductor device according to claim 19, characterized in that: The first semiconductor layer has a first resistivity; and The second semiconductor layer has a second resistivity that is lower than the first resistivity.

23. The semiconductor device according to claim 22, characterized in that: The first resistivity is 0.1 Ω·cm or higher.

24. The semiconductor device according to claim 22, characterized in that: The second resistivity is below 0.01 Ω·cm.

25. The semiconductor device according to claim 19, characterized in that: The second semiconductor layer is an amorphous layer.

26. The semiconductor device according to claim 19, characterized in that: The second semiconductor layer is a polycrystalline layer.

27. The semiconductor device according to claim 19, characterized in that: The first membrane includes a storage cell array as the first element.

28. The semiconductor device according to claim 27, characterized in that: The second membrane includes a control circuit for controlling the memory cell array as the second element.

29. The semiconductor device according to claim 19, characterized in that: It also includes a third film disposed between the first film and the second semiconductor layer to prevent the impurity atoms from diffusing from the first and second semiconductor layers to the first film.

30. A method for reusing a substrate, comprising: A first semiconductor layer is formed on a first substrate, the first semiconductor layer containing a first concentration of impurity atoms; A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer containing a second concentration of impurity atoms that is higher than the first concentration; A porous layer is formed, wherein at least a portion of the second semiconductor layer is porousized; The first substrate and the second substrate are bonded together with the first semiconductor layer and the porous layer in between; The first substrate and the second substrate are separated such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate. as well as The first portion is removed from the first substrate, and the first substrate is reused.

31. The method for reusing a substrate according to claim 30, wherein the first film comprises a memory cell array as the first element.

32. The method for reusing a substrate according to claim 30, wherein the second film includes control circuitry for controlling the memory cell array as the second element.

33. The method for reusing a substrate according to claim 30, wherein the first film separates the third film formed on the second semiconductor layer, and the third film prevents the impurity atoms from diffusing from the first and second semiconductor layers to the first film.

34. The method for reusing a substrate according to claim 30, wherein the second semiconductor layer is an amorphous layer.

35. The method for reusing a substrate according to claim 30, wherein the second semiconductor layer is a polycrystalline layer.

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