Process for grounding a low pressure gallium nitride device substrate

Abstract

The application discloses a process method for low-voltage gallium nitride device substrate grounding. Before forming source-drain ohmic contact metal, the method etches through the epitaxial structure and exposes the substrate contact hole of the silicon substrate in the sealing ring area around the chip unit; the ohmic contact metal is formed in the source-drain ohmic area and the substrate contact hole at the same time in the same metal deposition, and the metal in the hole and the silicon substrate form a stable ohmic contact through the same rapid thermal annealing; then, the substrate contact point is connected to the top metal through the dielectric layer contact hole, the interconnection metal and the through-hole interconnection, and is electrically connected with the annular sealing ring metal and the grounding metal structure. The scheme avoids occupying the active area, reduces the substrate contact resistance dispersion and improves the substrate potential uniformity, and reduces the etching depth of the through hole and the photolithography cost.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device manufacturing, and in particular to a process method for grounding a low-voltage gallium nitride device substrate. Background Technology

[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, possesses excellent properties such as a high critical breakdown electric field and a high electron saturation drift velocity. Among them, silicon-based gallium nitride technology has become one of the mainstream technologies for power semiconductor devices due to the low cost of large-size silicon wafers and mature process advantages.

[0003] In practical applications of GaN power devices on silicon substrates, it is essential to effectively connect the silicon substrate to the zero potential of the chip (typically the source potential or ground potential). This is primarily due to the "substrate bias effect" (or back gate effect) present in GaN devices. Specifically, when the device is in switching mode, the high-frequency, drastic changes in the drain voltage induce a substrate bias voltage relative to the heterojunction's two-dimensional electron gas on the silicon substrate through the parasitic capacitance coupling of the epitaxial layer. The electric field effect generated by this substrate bias voltage is similar to that of a back gate, depleting the heterojunction's two-dimensional electron gas within the channel. This leads to an abnormally high dynamic on-resistance, resulting in current collapse. Simultaneously, fluctuations in the substrate bias voltage below the gate cause threshold voltage drift, preventing the device from switching as expected and severely impacting system efficiency and reliability.

[0004] To address the aforementioned issues, the conventional process used in the prior art is to form several (usually 2 to 5) contact vias that extend to the silicon substrate in the active region of the chip using dry etching, and then use metal interconnects to bring the ground potential to the substrate through these vias, in order to uniformly clamp the substrate potential within the chip to zero potential.

[0005] However, the existing substrate interconnection process still has significant limitations and defects in practical applications, specifically in the following aspects: First, the sacrifice of active area leads to an increase in specific on-resistance. Since the substrate potential contact vias are directly located within the active area of ​​the chip, the entire GaN active area structure at the via location must be etched away to avoid the vias and ensure insulation reliability. This directly reduces the effective active area available for conducting current, resulting in increased specific on-resistance for the same chip size and degrading device performance.

[0006] Second, unstable contact resistance leads to poor potential clamping. Current substrate via processes are typically fabricated after the front-end ohmic contacts and some interconnect processes. Due to the already formed metal structure on the chip, this stage cannot undergo high-temperature rapid thermal annealing. The lack of annealing makes it difficult to form a good ohmic contact between the metal within the contact hole and the silicon substrate, resulting in high and inconsistent contact resistance. This, in turn, prevents the substrate potential from being stably clamped, affecting the stability of device operation.

[0007] Third, substrate potential uniformity remains insufficient. Due to the inherent bulk resistance of the silicon substrate, and the fact that existing solutions only incorporate a limited number (e.g., 2-5) of contact holes within the active region, lateral current diffusion within the substrate is hindered. This means that substrate potential fluctuations may still occur in areas far from the contact holes, making it difficult to fundamentally guarantee potential uniformity across the entire back side of the chip.

[0008] Fourth, the process is complex and the manufacturing cost is high. This via fabrication section is located after the interlayer dielectric or interconnect layer, requiring etching through a relatively thick dielectric layer and epitaxial layer to reach the substrate, resulting in a significant etching depth. This not only poses challenges to the uniformity and morphology control of the etching process but also necessitates the use of a thicker photoresist as a mask, significantly increasing the cost of photolithography materials and the load on the etching equipment.

[0009] In summary, there is an urgent need for a new structure or process that can achieve substrate potential connection of gallium nitride power devices on silicon substrates without sacrificing the active area, ensuring low contact resistance and high potential uniformity. Summary of the Invention

[0010] The purpose of this invention is to overcome the problems of unstable grounding path and poor process consistency of low-voltage gallium nitride device substrates in the prior art, and to provide a process method for grounding low-voltage gallium nitride device substrates.

[0011] To achieve the above objectives, the first aspect of the present invention provides a process method for grounding a low-voltage gallium nitride device substrate, comprising the following steps: S1: Provide a gallium nitride epitaxial wafer on a silicon substrate, and form a p-GaN gate structure on the gallium nitride epitaxial wafer; S2: Forming a first layer of field plate metal and a second layer of field plate metal on the gallium nitride epitaxial wafer; S3: Before forming the ohmic contact metals of the source and drain, photolithographic patterning and etching are performed on the sealing ring area around the chip unit of the gallium nitride epitaxial wafer to form at least one substrate contact hole, which penetrates the gallium nitride epitaxial structure and exposes the silicon substrate. S4: Perform ohmic contact windowing and deposit ohmic contact metal. The ohmic contact metal is formed simultaneously in the ohmic contact regions of the source and drain and in the substrate contact hole during the same deposition process, and the ohmic contact metal in the substrate contact hole is in direct contact with the silicon substrate. S5: Anneal the ohmic contact metal; S6: Form a dielectric layer; form a contact hole in the dielectric layer and form a first metal interconnect layer; form an interlayer dielectric layer; form a via interconnect in the interlayer dielectric layer and form a top metal layer; wherein, the ohmic contact metal in the substrate contact hole is electrically connected to the first metal interconnect layer through the contact hole, and is electrically connected to the top metal layer through the via interconnect; S7: A sealing ring metal is formed around the chip unit in the top metal layer, and a grounding metal structure is formed in the top metal layer, wherein the grounding metal structure is electrically connected to the sealing ring metal; The sealing ring metal is electrically connected to the ohmic contact metal within the substrate contact hole via the top metal layer, the through-hole interconnect, the first metal interconnect layer, and the contact hole, and the ohmic contact metal within the substrate contact hole is electrically connected to the silicon substrate.

[0012] As a further improvement of the present invention, the substrate contact hole is located outside the active region of the device and within the area covered by the projection of the sealing ring metal onto the chip plane.

[0013] As a further improvement of the present invention, the number of substrate contact holes is 2 to 5, and they are distributed circumferentially along the sealing ring region.

[0014] As a further improvement of the present invention, the etching depth of the substrate contact hole is 0.5 to 2.0 micrometers, and the bottom of the substrate contact hole is the exposed silicon substrate surface.

[0015] As a further improvement of the present invention, the sidewall of the substrate contact hole is an inclined sidewall, and the angle between the inclined sidewall and the wafer surface is 30° to 80°.

[0016] As a further improvement of the present invention, the ohmic contact metal is a multilayer metal stack, which includes a Ti layer, an Al layer and an upper protective metal layer.

[0017] As a further improvement of the present invention, the upper protective metal layer is selected from one of TiN / Au stack and Ni / Au stack.

[0018] As a further improvement of the present invention, the annealing treatment is rapid thermal annealing, with an annealing temperature of 750℃~875℃, an annealing time of 20~60 seconds, and an annealing atmosphere of nitrogen.

[0019] The second aspect of the present invention provides a method for fabricating a low-voltage silicon-based gallium nitride device as described above, comprising: silicon substrate; A gallium nitride epitaxial structure located on the silicon substrate and a device active region located within the gallium nitride epitaxial structure; The sealing ring metal is located around the active region of the device, and the sealing ring metal is a ring-shaped metal pattern in the top metal layer; At least one substrate contact hole is located outside the active region of the device and within the metal region of the sealing ring, the substrate contact hole penetrates the gallium nitride epitaxial structure and exposes the silicon substrate; An ohmic contact metal is located within the contact hole of the substrate, and the ohmic contact metal is in direct contact with the silicon substrate; Contact holes in the dielectric layer, the first metal interconnect layer, through-hole interconnects in the interlayer dielectric layer, and the top metal layer; Wherein, the ohmic contact metal in the substrate contact hole is electrically connected to the first metal interconnect layer through the contact hole, and electrically connected to the top metal layer through the through-hole interconnect, and the ohmic contact metal in the substrate contact hole is electrically connected to the sealing ring metal; A grounded metal structure in the top metal layer, wherein the grounded metal structure is electrically connected to the sealing ring metal.

[0020] As a further improvement of the present invention, the number of substrate contact holes is 2 to 5, and they are distributed circumferentially along the sealing ring metal.

[0021] The present invention, by adopting the above technical solution, has the following beneficial effects: In this invention, the formation sequence of the substrate contact structure is advanced in the wafer-level manufacturing process, preceding the formation of the source and drain ohmic contact metals. Furthermore, the ohmic contact metals are simultaneously formed in the source and drain ohmic contact regions and within the substrate contact holes during the same deposition process, followed by a single annealing treatment. Because the substrate contact points and the source / drain ohmic contact points use the same metal system and undergo the same heat treatment process, the reaction state and microstructure of the substrate contact interface are more consistent across batches. This helps reduce the dispersion and drift of substrate contact resistance, while also mitigating the risk of interface discontinuities introduced by multiple depositions or different annealing windows, thereby improving the stability and repeatability of the substrate contact.

[0022] This invention constructs a continuous conductive link from the ohmic contact metal within the substrate contact hole to the multilayer interconnect metal and then to the top layer metal through the interconnection of contact holes in the dielectric layer and through-holes in the interlayer dielectric layer. This conductive link is then electrically connected to the annular sealing ring metal surrounding the chip unit. This provides a clear structural path for the electrical connection between the silicon substrate and the surrounding metal network, reducing the uncertainty of the grounding loop caused by reliance on uncontrolled parasitic paths. It also helps to reduce potential fluctuations and noise coupling caused by the substrate's floating state, making the device's reference potential and electric field distribution more stable, thereby suppressing leakage current dispersion and abnormal failures under low-voltage operating conditions.

[0023] This invention confines the substrate contact holes outside the active region of the device and within the metal coverage area of ​​the sealing ring. This spatially isolates the substrate contact structure from the critical electric field region of the device, reducing the disturbance of the substrate contact holes to the active region layout and electric field boundaries. Simultaneously, by incorporating the substrate contact points into the ring-shaped metal network surrounding the chip, it facilitates substrate potential pulling without altering the core unit structure of the device. When the substrate contact holes are distributed circumferentially and multiple in number, multiple parallel conductive paths are formed between the substrate and the metal network. This reduces the impact of single-point contact defects on the overall substrate grounding continuity, improves the redundancy and reliability of the substrate grounding structure, and reduces the risks of thermal stress and electromigration caused by localized current density concentrations.

[0024] This invention employs inclined sidewalls and limits their angle range in the substrate contact hole sidewalls, which helps improve the continuity of metal coverage at the hole opening and sidewalls, reducing the probability of open circuits and high-resistance contacts caused by metal fractures, voids, or weak coverage. Combined with an ohmic contact metal stack structure including a titanium layer, an aluminum layer, and an upper protective metal layer, and rapid thermal annealing window control, the upper protective metal layer helps maintain the surface morphology and chemical stability of the ohmic metal after annealing, reducing the risk of corrosion and reaction to the ohmic metal during subsequent dielectric deposition, hole opening, and interconnect formation. This improves the structural integrity and long-term stability of the substrate grounding path after multilayer interconnect processing. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a chip using existing technology.

[0026] Figure 2 for Figure 1 A sectional view of section AA in the middle.

[0027] Figure 3 This is a schematic diagram of the chip in Example 1.

[0028] Figure 4 for Figure 3 A sectional view of section BB in the middle.

[0029] Figure descriptions: 1. Silicon substrate; 2. Gallium nitride epitaxial structure; 3. Deposited dielectric layer; 4. Ohmic metal layer; 5. First metal interconnect layer; 6. Deposited top metal layer; 7. Via; 8. Metal connecting to chip ground potential; 9. Deposited interlayer dielectric layer; 11. Active region; 12. Sealing ring; 13. Substrate contact hole. Detailed Implementation

[0030] The following provides a detailed description of specific embodiments of the present invention. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0031] Unless otherwise defined, all scientific and technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art.

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0034] The present invention will now be described in detail with reference to specific embodiments, which are intended to understand rather than limit the invention.

[0035] Example 1 This embodiment discloses a process method for grounding the substrate of a low-voltage silicon-based gallium nitride device, the specific steps of which are as follows: S1 epitaxial wafer preparation and gate structure formation: An 8-inch silicon substrate gallium nitride epitaxial wafer is provided. The epitaxial structure, from bottom to top, includes a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-type GaN gate layer. The gate region pattern is formed using photolithography. The p-type GaN gate layer is then removed from the non-gate region using dry etching. The etching process employs ICP (Inductively Coupled Plasma) with etching gases of Cl2 30 sccm, BCl 320 sccm, and Ar 10 sccm. The cavity pressure is 3.0 Pa, the ICP power is 600 W, the bias power is 90 W, and the etching time is 35 s. After resist removal, a p-type GaN gate structure is formed in the gate region.

[0036] S2 first and second layer field plate metal formation: A first dielectric passivation layer is deposited on the wafer surface, followed by PECVD deposition of SiN with a thickness of 200 nm. Photolithography is performed to etch openings to form contact windows corresponding to the first field plate. Subsequently, the first field plate metal is deposited by sputtering, with a metal stack of Ti 20 nm, Al 600 nm, and TiN 50 nm. The metal is then patterned using a photolithography-wet etching method to obtain the first field plate metal.

[0037] A second dielectric passivation layer is deposited on top of the first field metal layer. SiN with a thickness of 300 nm is deposited using PECVD. The photolithography opening and metal deposition patterning process is repeated to form the second field metal layer. The second field metal layer is composed of Ti 20 nm, Al 900 nm, and TiN 60 nm.

[0038] S3 substrate contact hole formation: Photolithography was performed on the sealing ring area surrounding the chip unit, with a photoresist thickness of 2.8 μm, a hot plate baking temperature of 125℃, and a time of 90 s. ICP etching was used to form substrate contact holes, penetrating the passivation dielectric layer and the gallium nitride epitaxial structure to expose the silicon substrate. Simultaneously, etching continued in the silicon substrate to form a hole bottom morphology with a recess depth of 1.0 μm. A segmented etching formula was used to control the sidewall angle. The first stage of etching used Cl2 35 sccm, BCl3 25 sccm, and Ar 10 sccm, with a chamber pressure of 3.0 Pa, an ICP power of 650 W, a bias power of 100 W, and a time of 55 s, for etching the epitaxial layer. The second stage of etching used SF6 40 sccm and O2 5 sccm, with a chamber pressure of 2.5 Pa, an ICP power of 550 W, a bias power of 60 W, and a time of 18 s, for etching the silicon substrate and controlling the hole bottom recess depth. The sidewall angle of the formed substrate contact hole is 60°. After removing the adhesive, the substrate contact hole is obtained located in the sealing ring area. In this embodiment, the number of substrate contact holes is set to 4, distributed circumferentially.

[0039] S4 Ohmic Contact Windowing and Ohmic Contact Metal Deposition: Photolithography and etching of windows were performed in the source and drain regions. The window etching used Cl225 sccm, BCl315 sccm, and Ar 10 sccm. The cavity pressure was 3.0 Pa, the ICP power was 500 W, the bias power was 80 W, and the time was 20 s. This was used to remove the surface dielectric in the windowed areas and prepare the channel contact interface.

[0040] In the same metal deposition process, ohmic contact metals are deposited simultaneously on the source and drain ohmic contact regions and the substrate contact holes. The ohmic contact metal stack consists of Ti 25 nm, Al 150 nm, TiN 60 nm, and Au 80 nm. After deposition, a stripping process is performed, retaining the metal within the substrate contact holes, allowing the ohmic contact metal within the substrate contact holes to directly contact the silicon substrate.

[0041] S5 Ohmic Annealing: The ohmic contact metal was subjected to rapid thermal annealing at a temperature of 830 °C for 30 s under a nitrogen atmosphere. After annealing, the source-drain ohmic contact region and the metal within the substrate contact hole were simultaneously heat-treated.

[0042] S6 dielectric layer, contact holes, first layer metal interconnect, interlayer dielectric and via interconnect, top layer metal formation: The deposition medium layer is SiO2 deposited by PECVD with a thickness of 800 nm. Contact holes are formed in the deposition medium layer by photolithography and dry etching. The contact holes open to the source and drain ohmic contact metals and the ohmic contact metal above the substrate contact holes, respectively.

[0043] A first metal interconnect layer of AlCu with a thickness of 1.2 μm is deposited by sputtering and patterned. The first metal interconnect layer is electrically connected to the ohmic contact metal inside the substrate contact hole above the substrate contact hole through the contact hole.

[0044] The interlayer dielectric layer was deposited using PECVD to deposit SiO2 with a thickness of 1.5 μm. Through-hole interconnects were formed in the interlayer dielectric layer by photolithography and dry etching, connecting the first metal interconnect layer with the top metal layer.

[0045] A top metal layer of AlCu with a thickness of 3.0 μm was deposited and patterned.

[0046] S7 Sealing Ring Metal and Grounding Metal Structure Formation and Conductivity: A ring-shaped sealing metal is formed around the perimeter of the chip cell within the top metal layer deposition layer. Simultaneously, ground metal traces and ground pads are formed within the top metal layer deposition layer, electrically connecting the sealing ring metal to the ground pads. The sealing ring metal is electrically connected to the ohmic contact metal within the substrate contact holes through the top metal layer deposition layer, via interconnects, the first metal interconnect layer, and the contact holes in the deposited dielectric layer, thereby achieving electrical connection between the silicon substrate and the ground pads.

[0047] Through the above steps, the substrate contact hole in the sealing ring area around the chip forms a defined electrical connection link with the sealing ring metal, and the metal in the substrate contact hole and the source / drain ohmic metal are deposited and annealed under the same process conditions.

[0048] The low-voltage silicon-based gallium nitride (GaN) device fabricated using the above process includes a silicon substrate 1, a GaN epitaxial structure 2 located on the silicon substrate 1, and an active region 11. The GaN epitaxial structure 2 includes a buffer layer, a channel layer, and a barrier layer located on the silicon substrate 1. The active region 11 is formed in the epitaxial structure, and a p-type GaN gate structure is disposed in the active region 11. A first field plate metal layer and a second field plate metal layer are sequentially formed on the device surface.

[0049] The device has an annular sealing ring 12 metal disposed around the chip cell surrounding the active region 11. The sealing ring 12 metal is located in the top metal layer and is continuously distributed along the circumference of the chip cell. At least one substrate contact hole 13 is disposed in the region corresponding to the sealing ring 12 metal. The substrate contact hole 13 penetrates the gallium nitride epitaxial structure 2 and exposes the surface of the silicon substrate 1 at the bottom of the hole. The substrate contact hole 13 is filled with ohmic contact metal, which is in direct contact with the silicon substrate 1. The ohmic contact metal is formed in the same deposition and annealing process as the ohmic contact metals of the source and drain electrodes.

[0050] The ohmic contact metal within the substrate contact hole 13 is electrically connected to the first metal interconnect layer 5 through contact holes in the dielectric layer, and is electrically connected to the top metal layer through vias 7 in the interlayer dielectric layer. The top metal layer is electrically connected to the sealing ring 12, thereby forming a continuous conductive link between the silicon substrate 1 and the sealing ring 12. A grounding metal structure is further formed in the top metal layer, and the grounding metal structure is electrically connected to the sealing ring 12, enabling the silicon substrate 1 to be grounded via the ohmic contact metal within the substrate contact hole 13, the interconnect metal, and the sealing ring 12.

[0051] In this embodiment, there are four substrate contact holes 13, which are distributed circumferentially along the metal of the sealing ring 12.

[0052] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A process for grounding a substrate of a low-voltage gallium nitride device, characterized in that, Includes the following steps: S1: Provide a gallium nitride epitaxial wafer on a silicon substrate, and form a p-GaN gate structure on the gallium nitride epitaxial wafer; S2: Forming a first layer of field plate metal and a second layer of field plate metal on the gallium nitride epitaxial wafer; S3: Before forming the ohmic contact metals of the source and drain, photolithographic patterning and etching are performed on the sealing ring area around the chip unit of the gallium nitride epitaxial wafer to form at least one substrate contact hole, which penetrates the gallium nitride epitaxial structure and exposes the silicon substrate. S4: Perform ohmic contact windowing and deposit ohmic contact metal. The ohmic contact metal is formed simultaneously in the ohmic contact regions of the source and drain and in the substrate contact hole during the same deposition process, and the ohmic contact metal in the substrate contact hole is in direct contact with the silicon substrate. S5: Anneal the ohmic contact metal; S6: Form a dielectric layer; form a contact hole in the dielectric layer and form a first metal interconnect layer; form an interlayer dielectric layer; form a via interconnect in the interlayer dielectric layer and form a top metal layer; wherein, the ohmic contact metal in the substrate contact hole is electrically connected to the first metal interconnect layer through the contact hole, and is electrically connected to the top metal layer through the via interconnect; S7: A sealing ring metal is formed around the chip unit in the top metal layer, and a grounding metal structure is formed in the top metal layer, wherein the grounding metal structure is electrically connected to the sealing ring metal; The sealing ring metal is electrically connected to the ohmic contact metal in the substrate contact hole through the top metal layer, the through-hole interconnect, the first metal interconnect layer, the contact hole, and the substrate contact hole, and the ohmic contact metal in the substrate contact hole is electrically connected to the silicon substrate.

2. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The substrate contact hole is located outside the active region of the device and within the area covered by the projection of the sealing ring metal onto the chip plane.

3. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The number of substrate contact holes is 2 to 5, and they are distributed circumferentially along the sealing ring region.

4. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The etching depth of the substrate contact hole is 0.5 to 2.0 micrometers, and the bottom of the substrate contact hole is the exposed silicon substrate surface.

5. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The sidewalls of the substrate contact holes are inclined sidewalls, and the angle between the inclined sidewalls and the wafer surface is 30° to 80°.

6. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The ohmic contact metal is a multilayer metal stack, which includes a Ti layer, an Al layer, and an upper protective metal layer.

7. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The upper protective metal layer is selected from either TiN / Au stack or Ni / Au stack.

8. The process method for grounding a low-voltage gallium nitride device substrate according to claim 1, characterized in that, The annealing process is rapid thermal annealing, with an annealing temperature of 750℃~875℃, an annealing time of 20~60 seconds, and an annealing atmosphere of nitrogen.

9. A low-voltage silicon-based gallium nitride device, characterized in that, include: silicon substrate; A gallium nitride epitaxial structure located on the silicon substrate and a device active region located within the gallium nitride epitaxial structure; The sealing ring metal is located around the active region of the device, and the sealing ring metal is a ring-shaped metal pattern in the top metal layer; At least one substrate contact hole is located outside the active region of the device and within the metal region of the sealing ring, the substrate contact hole penetrates the gallium nitride epitaxial structure and exposes the silicon substrate; An ohmic contact metal is located within the contact hole of the substrate, and the ohmic contact metal is in direct contact with the silicon substrate; Contact holes in the dielectric layer, the first metal interconnect layer, through-hole interconnects in the interlayer dielectric layer, and the top metal layer; Wherein, the ohmic contact metal in the substrate contact hole is electrically connected to the first metal interconnect layer through the contact hole, and electrically connected to the top metal layer through the through-hole interconnect, and the ohmic contact metal in the substrate contact hole is electrically connected to the sealing ring metal; A grounded metal structure in the top metal layer, wherein the grounded metal structure is electrically connected to the sealing ring metal.

10. The low-voltage silicon-based gallium nitride device according to claim 9, characterized in that, The number of substrate contact holes is 2 to 5, and they are distributed circumferentially along the sealing ring metal.

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