A power delivery structure and method of formation

Abstract

This disclosure relates to semiconductor technology, and more particularly to a power transmission structure and its formation method. The power transmission structure provided by this disclosure includes multiple semiconductor structures stacked along a first direction. A first conductive via is formed on the substrate of each semiconductor structure along the first direction, and the first conductive via is used to transmit power signals. Multiple conductive material layers and multiple dielectric material layers are coaxially nested within the first conductive via. Each conductive material layer is surrounded by a dielectric material layer, and each dielectric material layer is surrounded by a conductive material layer. Adjacent conductive material layers and dielectric material layers located between adjacent conductive material layers together form a capacitor. The capacitance values ​​of the different capacitors formed by the first conductive via are different, so that power signals of different frequencies are distributed to the corresponding conductive material layers. This solves the limitation of existing fixed power transmission architectures that cannot autonomously switch power supply paths, saving chip space and wiring resources.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a power transmission structure and a method of forming it. Background Technology

[0002] The power transmission path of the three-dimensional power supply network is composed of complementary vertical power paths and horizontal power paths: the horizontal path is responsible for the distribution of power within the layer, while the vertical path undertakes the transmission across layers and is the key to the energy connection between layers.

[0003] In this design, the vertical power supply path enables cross-layer current transmission via through-silicon vias (TSVs). Current is introduced from the bottom-layer power supply TSV and flows upwards, forming a vertical path that runs through the entire stack of TSVs to power the functional units in each layer. Existing vertical power supply architectures use a fixed TSV connection topology, which makes it difficult to cope with TSV failures, adapt to dynamic load fluctuations between layers, meet differentiated power supply needs, and suffer from reduced energy efficiency and limited overall performance. Summary of the Invention

[0004] This disclosure provides a power transmission structure that utilizes different capacitors in the same conductive hole to achieve precise distribution of power signals of different frequencies, thereby optimizing the path and stability of power signal transmission.

[0005] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a power transmission structure, the power transmission structure including a plurality of semiconductor structures stacked along a first direction, the substrate of the semiconductor structures having a first conductive hole formed along the first direction, the first conductive hole being used to transmit power signals; The first conductive hole is provided with multiple coaxially nested conductive material layers and multiple dielectric material layers; each conductive material layer is surrounded by a dielectric material layer, and each dielectric material layer is surrounded by a conductive material layer. The adjacent conductive material layers and the dielectric material layer located between the adjacent conductive material layers together form a capacitor. The different capacitors formed in the first conductive hole have different capacitance values, so that the power signals of different frequencies are distributed to the corresponding conductive material layers.

[0006] In some embodiments, the semiconductor structure further includes a redistribution layer, the substrate and the redistribution layer are distributed along a first direction, and the redistribution layer includes a plurality of redistribution lines; different conductive material layers are connected to different redistribution lines.

[0007] In some embodiments, one or more of the following parameters differ among the different conductive material layers: (1) Ingredients; (2) The thickness is different along the second direction; Different dielectric material layers may have one or more of the following parameters that differ: (1) Dielectric constant; (2) The thickness is different along the second direction, which is perpendicular to the first direction; (3) Ingredients.

[0008] In some embodiments, a second conductive hole is formed on the substrate along a first direction. The second conductive hole is provided with a dielectric material layer and a conductive material layer nested coaxially, and the conductive material layer surrounds the dielectric material layer. For the first conductive hole, a portion of the conductive material layer is connected to the second conductive hole in the same semiconductor structure via the redistribution layer; For the first conductive hole, another portion of the conductive material layer is connected to the second conductive holes of other semiconductor structures via the redistribution layer.

[0009] In some embodiments, the plurality of conductive holes in each of the semiconductor structures are aligned along the projection of a first direction; Each of the first conductive holes is connected to a second conductive hole in the same semiconductor structure, and each of the first conductive holes is also electrically connected to different second conductive holes in adjacent semiconductor structures to conduct the power signal to different lines in adjacent semiconductor structures based on the frequency of the power signal.

[0010] In some embodiments, the conductive material layer includes a columnar conductive material layer, a first annular conductive material layer, and a second annular conductive material layer; The dielectric material layer includes a first dielectric material layer, a second dielectric material layer, and a third dielectric material layer; The cylindrical conductive material layer is disposed in the central region of the first conductive hole; the cylindrical conductive material layer surrounds the first dielectric material layer; the first dielectric material layer surrounds the first annular conductive material layer; the first annular conductive material layer surrounds the second dielectric material layer; the second dielectric layer surrounds the second annular conductive material layer; the second annular conductive material layer surrounds the third dielectric material layer; the third dielectric material layer is attached to the inner wall of the first conductive hole. The cylindrical conductive material layer, the first dielectric material layer, and the first annular conductive material layer together form a first capacitor; the first annular conductive material layer, the second dielectric material layer, and the second annular conductive material layer together form a second capacitor; the second annular conductive material layer, the third dielectric material layer, and the inner wall of the first conductive hole together form a third capacitor. The first, second, and third capacitors have different capacitance values, so that power signals of different frequencies are distributed to the corresponding conductive material layers.

[0011] On the other hand, this disclosure provides a method for forming a semiconductor structure. Provide a base; The substrate is subjected to deep hole etching to create a first etched hole; Multiple conductive material layers and multiple dielectric material layers are sequentially deposited in the first etched hole; a dielectric material layer is deposited around each of the conductive material layers, and a conductive material layer is deposited around each of the dielectric material layers, to obtain the first conductive hole; The adjacent conductive material layers and the dielectric material layer located between the adjacent conductive material layers together form a capacitor. The capacitance values ​​of the different capacitors formed in the first conductive hole are different, so that the power signals of different frequencies are distributed to the corresponding conductive material layers.

[0012] In some embodiments, the method further includes: A redistribution layer is formed on the surface of the substrate away from the deep hole etching, and different conductive material layers of the first conductive hole are connected to the redistribution layer with different redistribution lines.

[0013] In some embodiments, the deep-hole etching process performed on the substrate to generate a plurality of first etched holes further includes: After deep hole etching is performed on the substrate, multiple etched holes are generated simultaneously, and the multiple etched holes are arranged in parallel along a first direction of the substrate; A dielectric material layer and a seed layer are deposited on the etched hole to obtain the etched hole to be filled; After depositing a conductive material layer on the etched hole to be filled, a conductive hole is obtained. A portion of the conductive holes are selected as the second conductive hole, and another portion of the conductive holes are selected as the first intermediate conductive hole. The conductive material layer in the first intermediate conductive hole is etched to obtain the first etched hole.

[0014] Thirdly, this disclosure provides an electronic device that includes the power transmission structure described in any of the above embodiments.

[0015] This disclosure provides a power transmission structure including multiple semiconductor structures stacked along a first direction. Each semiconductor structure substrate has a first conductive via. The via employs a coaxial nesting design, with multiple conductive material layers and dielectric material layers alternately arranged. Adjacent conductive material layers and intermediate dielectric material layers form a capacitor, and the capacitance values ​​differ among the different capacitors. Utilizing the filtering characteristics of different capacitance values ​​for different frequency signals, power signals of different frequencies are precisely guided to the corresponding conductive material layers. That is, without changing the physical topology, the power signal frequency can dynamically change, autonomously guiding the power signal to the appropriate conductive layer, achieving path switching. It also overcomes the limitation of existing fixed power transmission architectures in achieving differentiated power supply. By integrating multiple transmission channels within the same conductive via, the addition of redundant power transmission structures is avoided, saving chip space and wiring resources. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a power transmission structure provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a dielectric material layer and a conductive material layer structure provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of a redistribution layer structure provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a cross-sectional structure of a redistribution layer provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a second conductive hole connection provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of one of the power transmission paths provided in an embodiment of this disclosure; Figure 8 This is a second schematic diagram of a power transmission path provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of the formation process of a semiconductor structure provided in an embodiment of this disclosure; Figure 10 This disclosure provides a schematic diagram of a semiconductor structure formation process including a second conductive hole. Figure 11 This disclosure provides a schematic diagram of an electronic device structure.

[0017] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. It should also be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit the disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first, second, third, fourth" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, fourth" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0020] In existing three-dimensional power supply networks, redundant TSVs will occupy the limited wiring resources within the chip, increase the difficulty of wiring between and within layers, and may lead to increased interference between signal interconnects and power interconnects. On the other hand, the integration of redundant TSVs will occupy additional chip area, further compress the layout space of functional modules, and increase the manufacturing cost of the chip.

[0021] In addition to the constraints mentioned above, existing vertical power supply architectures also suffer from core limitations such as a lack of autonomous power path switching capabilities and insufficient flexibility. Current mainstream vertical power supply architectures all employ fixed TSV connection topologies. Once the chip is manufactured, the energy transmission paths between layers are completely fixed and cannot be dynamically adjusted according to actual operating scenarios. Current research largely focuses on improving static performance such as TSV layout optimization, impedance reduction, or noise suppression, with few solutions addressing power path switching. Related technologies also largely rely on pre-defined fixed path designs, lacking the ability to adaptively adjust to complex operating conditions. This "statically fixed" design pattern makes the power supply network difficult to cope with the challenges of practical applications. For example, when a TSV in a certain path experiences faults such as electromigration or open circuit, it cannot automatically switch to a backup path, which can easily lead to power interruption or voltage fluctuations in the corresponding chip layer, causing system operation errors or even overall collapse. Faced with dynamic load fluctuations in different chip layers, it is impossible to achieve precise energy allocation through path adjustment, which may cause local power redundancy or insufficiency and reduce system energy efficiency. At the same time, in the three-dimensional chip architecture, the power supply requirements of different functional layers are different, and the fixed path cannot adapt to these differentiated requirements, which restricts the full realization of system performance.

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] In some embodiments of this disclosure, such as Figure 1 As shown, this embodiment provides a power transmission structure 11, which includes a plurality of semiconductor structures stacked along a first direction. Figure 1 The example shown uses four semiconductor structures. It should be understood that the number of semiconductor structures is merely illustrative and does not constitute any limitation on the technical solution of the present invention. In other embodiments, the number of semiconductor structures may also be set to three, five or more. All of the aforementioned configurations are within the protection scope of the present invention.

[0024] The four semiconductor structures illustrated in this embodiment are named as first semiconductor structure 11a, second semiconductor structure 11b, third semiconductor structure 11c, and fourth semiconductor structure 11d, respectively.

[0025] like Figure 2 As shown, each semiconductor structure has a substrate 110. The first direction is parallel to the top surface of the substrate 110, that is, the stacking state of multiple semiconductor structures is horizontal. The substrates 110 of adjacent semiconductor structures are mechanically fixed and electrically connected through bonding layers. The bonding layers can adopt metal-to-metal bonding or dielectric-to-dielectric bonding to ensure the stability of the stacked structure and the reliability of interconnection, which is not limited here.

[0026] like Figure 2As shown, each of the semiconductor structures has a first conductive hole 20 extending through the substrate 110 along the first direction. The first conductive hole 20 extends in the same direction as the first direction, that is, it extends through the substrate 110 in a horizontal state. Its two ends are respectively connected to two opposite sides of the substrate 110, forming a power signal transmission channel between the horizontally stacked semiconductor structures. It is specifically used to carry and transmit power signals including power supply voltage signals and ground signals.

[0027] The first conductive hole 20 contains multiple coaxially nested conductive material layers 21 and multiple dielectric material layers 22. Each conductive material layer 21 is surrounded by a complete dielectric material layer 22, and each dielectric material layer 22 is surrounded by a complete conductive material layer 21. This ensures that the material layers are concentrically nested in a ring shape from the center of the first conductive hole 20 to the hole wall, without any offset or misalignment. The conductive material layers 21 can be made of conductive metals such as copper, aluminum, or tungsten, and are prepared using processes such as electroplating or chemical vapor deposition. The dielectric material layers 22 can be made of insulating materials such as silicon dioxide, silicon nitride, or low-k dielectric materials, and are prepared using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition, ensuring electrical isolation between adjacent conductive material layers 21.

[0028] Furthermore, any two adjacent (i.e., closest) conductive material layers 21, and the dielectric material layer 22 sandwiched between them, together constitute an independent capacitor structure. It can be understood that the two adjacent conductive material layers 21 serve as the two plates of the capacitor, and the intermediate dielectric material layer 22 serves as the dielectric layer. Based on the principle of parallel plate capacitor formation, a capacitor unit with energy storage and frequency selection characteristics is formed. For multiple capacitor units formed within the same first conductive hole 20, the capacitance values ​​of each capacitor unit are different. Capacitors with larger capacitance values ​​have lower capacitive reactance for low-frequency signals, making it easier for low-frequency signals to be transmitted through the corresponding conductive material layer 21. Capacitors with smaller capacitance values ​​have lower capacitive reactance for high-frequency signals, making it easier for high-frequency signals to be transmitted through the corresponding conductive material layer 21. Based on this, in this embodiment, capacitor units with different capacitance values ​​within the first conductive hole 20 can achieve frequency sorting of power signals, allowing mixed-frequency power signals input to the first conductive hole 20 to be allocated to the corresponding conductive material layer 21 for transmission according to their own frequency characteristics.

[0029] In some embodiments of this disclosure, such as Figure 2As shown, the semiconductor structure also includes a redistribution layer 111, which is distributed along a first direction and is a horizontal direction parallel to the top surface of the substrate 110. The redistribution layer 111 includes multiple independent redistribution lines, each of which is made of a low-resistance conductive metal material such as copper or aluminum. Different conductive material layers 21 are connected to different redistribution lines to form a one-to-one electrical connection relationship. Specifically, one end of each conductive material layer 21 away from the center of the first conductive hole 20 extends to form a metal lead-out end. The metal lead-out end and the end of the redistribution line are made into ohmic contact through a metal bonding process to ensure that the power signal transmitted by the conductive material layer 21 can be stably introduced into the corresponding redistribution line.

[0030] In some embodiments of this disclosure, different conductive material layers 21 may use different compositions, such as copper for the inner layer and aluminum for the outer layer; conductive material layers 21 of different thicknesses may also be used, that is, by controlling the process, the thickness of different conductive material layers 21 is different along a second direction perpendicular to the first direction, that is, in the vertical direction, for example, the thickness of the inner layer is less than that of the outer layer.

[0031] Different dielectric material layers 22 can have different dielectric constants. For example, the inner periphery can use a low-k dielectric and the outer periphery can use silicon nitride; they can also have different thicknesses; or they can have different compositions, directly selecting different types of insulating dielectric materials.

[0032] These parameter differences can be achieved through conventional process control. The ultimate goal is to ensure that the capacitors formed by different conductive material layers 21 and adjacent dielectric material layers 22 have preset capacitance differences, thereby accurately allocating power signals of different frequencies and improving transmission stability.

[0033] In some embodiments of this disclosure, the number of multiple conductive material layers 21 and multiple dielectric material layers 22 can be two, four, five, or even more. For example, in some embodiments of this disclosure... Figure 3 As shown, taking three conductive material layers 21 and three dielectric material layers 22 as an example, the multiple conductive material layers 21 are respectively a cylindrical conductive material layer 21a, a first annular conductive material layer 21b and a second annular conductive material layer 21c, and the multiple dielectric material layers 22 are respectively a first dielectric material layer 22a, a second dielectric material layer 22b and a third dielectric material layer 22c.

[0034] The material layers are arranged coaxially and nested along the radial direction of the first conductive hole 20, specifically in the following order: the cylindrical conductive material layer 21a is disposed in the central region of the first conductive hole 20; the cylindrical conductive material layer 21a surrounds the first dielectric material layer 22a; the first dielectric material layer 22a surrounds the first annular conductive material layer 21b; the first annular conductive material layer 21b surrounds the second dielectric material layer 22b; the second dielectric material layer 22b surrounds the second annular conductive material layer 21c; the second annular conductive material layer 21c surrounds the third dielectric material layer 22c; finally, the outer periphery of the third dielectric material layer 22c is tightly attached to the inner wall of the first conductive hole 20.

[0035] Based on the above nested structure, three independent capacitor units can be formed: the cylindrical conductive material layer 21a, the first dielectric material layer 22a, and the first annular conductive material layer 21b together constitute the first capacitor; the first annular conductive material layer 21b, the second dielectric material layer 22b, and the second annular conductive material layer 21c together constitute the second capacitor; and the second annular conductive material layer 21c, the third dielectric material layer 22c, and the inner wall of the first conductive hole 20 together constitute the third capacitor. The capacitance values ​​of the first, second, and third capacitors are different from each other, allowing for precise allocation to the corresponding cylindrical conductive material layer 21a, the first annular conductive material layer 21b, or the second annular conductive material layer 21c based on the capacitive reactance adaptation characteristics of power signals at different frequencies, ensuring frequency-oriented transmission of the power signals.

[0036] For specific details, please refer to the following formula for determining capacitance: ………………………………………………………….(1) In the formula, For the nth capacitance value, Let be the dielectric constant of the nth annular dielectric material layer 22. The height of the cylindrical conductive material layer 21a is... Let be the radius of the nth annular conductive material layer 21. Let be the radius of the cylindrical conductive material layer 21a. Let n be the thickness of the nth annular dielectric layer 22; where n∈N ＋ .

[0037] In this embodiment, the first capacitor is C1, the second capacitor is C2, and the third capacitor is C3. ;in This makes C1 > C2 > C3.

[0038] In some embodiments of this disclosure, such as Figure 2As shown, in addition to the first conductive hole 20 formed along the first direction, a second conductive hole 30 is also formed on the substrate 110 of the semiconductor structure along the same first direction.

[0039] The second conductive hole 30 has a coaxial nested structure, specifically including a dielectric material layer 22 and a conductive material layer, with the dielectric material layer 22 surrounding the outside of the conductive material. The conductive material layer 21 inside the first conductive hole 20 is connected to the second conductive hole 30 through a redistribution layer.

[0040] Specifically, a portion of the conductive material layer 21 in the first conductive hole 20 establishes an electrical connection with each of the second conductive holes 30 in the same semiconductor structure via a redistribution layer, while another portion of the conductive material layer 21 achieves an electrical connection with other second conductive holes 30 in the semiconductor structure stacked along the first direction via a redistribution layer.

[0041] To make the description clearer, the following explanation is provided with examples. These examples are merely illustrative and do not constitute a limitation on the scope of protection of this disclosure. The pinout configuration of the redistribution layer 111 described in this disclosure can be implemented in various ways. For example... Figures 4-5 As shown, the redistribution layer 111, corresponding to the cylindrical conductive material layer 21a, the first annular conductive material layer 21b, and the second annular conductive material layer 21c, is provided with a first lead-out terminal 111a, a second lead-out terminal 111b, and a third lead-out terminal 111c. The first lead-out terminal 111a, the second lead-out terminal 111b, and the third lead-out terminal 111c are respectively integrally formed from the corresponding conductive material layer 21; correspondingly, as... Figure 6 As shown, the second conductive hole 30 includes a second conductive hole 30a, a second conductive hole 30b, and a second conductive hole 30c corresponding to the first lead-out terminal 111a, the second lead-out terminal 111b, and the third lead-out terminal 111c.

[0042] like Figure 7 As shown in A and B in the figure, in the semiconductor structure described in this embodiment, the columnar conductive material layer 21a in the first conductive hole 20 can serve as a power signal receiving carrier. It should be understood that the specific configuration of the power signal receiving carrier described above is only an illustrative example and does not constitute any limitation on the technical solution of the present invention. In actual applications, it can be flexibly adjusted according to the specific circuit design requirements.

[0043] The transmission path of the power signal is determined according to the matching relationship between the signal frequency characteristics and the corresponding capacitor. Specifically, when the power signal is an intermediate frequency signal, the frequency characteristics of the intermediate frequency signal are matched with the capacitance parameter of the second capacitor. At this time, the intermediate frequency power signal is directly transmitted to the corresponding target functional element through the second lead-out terminal 111b along path 1. When the power signal is a high frequency signal, the frequency characteristics of the high frequency signal are matched with the capacitance parameter of the third capacitor. At this time, the high frequency power signal is transmitted through the third lead-out terminal 111c along path 2, and is transmitted to another semiconductor structure 11d stacked vertically along the first direction through the second conductive hole 30c, and finally delivered to the corresponding target functional element.

[0044] It should be noted that the technical solutions of the embodiments of the present invention are not limited to the above exemplary transmission path configurations. For example, the power signal can be transmitted horizontally within the same semiconductor structure by preset circuit parameters. At the same time, the placement of the second conductive hole 30 is not limited to the same semiconductor structure. All of the above configurations can be flexibly set according to actual circuit design requirements. All of these are within the protection scope of the present invention.

[0045] The above connection design achieves layered and regional transmission of power signals of different frequencies through the differentiated layout of different paths in the redistribution layer 111. This not only ensures the precise power supply of different functional units within the same semiconductor structure, but also supports power interaction between stacked semiconductor structures, thereby improving the adaptability and flexibility of the power transmission architecture.

[0046] In some embodiments of this disclosure, such as Figure 8 As shown, the multiple conductive holes on the substrate 110 of the semiconductor structure are aligned along the projection of the first direction. Specifically, when all conductive holes in the same semiconductor structure are projected along the first direction, i.e. the stacking direction of the semiconductor structure, the projection areas are completely overlapped and aligned; and in adjacent semiconductor structures stacked along the first direction, the projections of the conductive holes of the previous semiconductor structure and the conductive holes of the next semiconductor structure are also aligned.

[0047] The first conductive via 20 is connected to the second conductive via 30 in the same semiconductor structure, specifically through a redistribution layer. Each first conductive via 20 is also electrically connected to a corresponding second conductive via 30 in an adjacent semiconductor structure, so as to transmit the power signal to different lines in the adjacent semiconductor structure based on the frequency of the power signal.

[0048] Reference Figure 8This embodiment exemplarily illustrates a semiconductor chip with four layers of substrate 110, namely a first semiconductor structure 11a, a second semiconductor structure 11b, a third semiconductor structure 11c, and a fourth semiconductor structure 11d. Each semiconductor structure is stacked along a first direction, and the conductive holes of each layer are precisely aligned. It should be understood that the number of layers and stacking method of the above semiconductor structure are merely illustrative and do not constitute a limitation on the technical solution of the present invention. They can be adjusted according to actual application requirements.

[0049] like Figure 8 As shown in A and B, when the columnar conductive material layer 21a within the first conductive hole 20 of the third semiconductor structure 11c can serve as a receiving carrier for power signals, bidirectional selective transmission of signals can be achieved due to the difference in capacitance values ​​adapted to power signals of different frequencies. Specifically, when a power signal is received, the power signal is conducted upwards along path 3 through the second conductive hole 30b of the third semiconductor structure 11c to the second conductive hole 30b of the fourth semiconductor structure 11d, and then transmitted to the target element. Figure 8 As shown in C and D, when a power signal of another frequency is received, the power signal is conducted upward along path 4 through the second annular conductive material layer 21c of the third semiconductor structure 11c to the second annular conductive material layer 21c of the fourth semiconductor structure 11d, and then transmitted to the target element, thereby realizing the switching of the power supply path between the stacked semiconductor structures.

[0050] This embodiment provides a method for forming a semiconductor structure. The specific processes involved are not limited. For example, etching can be performed using plasma etching, wet etching, etc., and deposition can be performed using chemical vapor deposition, atomic layer deposition, electroplating, etc. It should be noted that in other embodiments, the conductive material can also be gold (Au), silver (Ag), aluminum (Al), etc.; the dielectric material can also be other insulating dielectric materials such as alumina and aluminum nitride. This embodiment does not limit the conductive and dielectric materials. It should be noted that in this embodiment, the semiconductor substrate 110 is a silicon substrate. In other embodiments, it can be other types of substrates such as silicon carbide and gallium nitride. This embodiment does not limit the substrate.

[0051] Taking the semiconductor structure that forms three types of capacitors as an example, such as Figure 9 As shown, the specific steps are as follows: S401, As shown in Figure A, a substrate 110 is provided: A semiconductor substrate 110 is provided. The surface of the substrate 110 is pretreated by conventional cleaning to remove impurities, which lays the foundation for subsequent processes.

[0052] S402. As shown in B in the figure, the substrate 110 is subjected to deep hole etching to generate a plurality of first etched holes 402d. The substrate 110 is subjected to deep hole etching based on a preset pattern to form a plurality of first etched holes 402d that penetrate the substrate 110 along a first direction.

[0053] S403. As shown in Figure C, multiple conductive material layers 21 and multiple dielectric material layers 22 are sequentially deposited in the first etched hole 402d. A dielectric material layer 22 is deposited around each conductive material layer 21, and a conductive material layer 21 is deposited around each dielectric material layer 22. Conductive material layers 21 and dielectric layers 22 are sequentially and alternately deposited within the first etched hole 402d, ultimately forming a nested structure of columnar conductive material layer 21a, first annular conductive material layer 21b, second annular conductive material layer 21c, and first dielectric layer 22a, second dielectric layer 22b, and third dielectric layer 22c. The specific process is as follows: First, a cylindrical conductive material layer 21a is deposited in the central region of the first etched hole 402d. Then, a first dielectric material layer 22a is deposited around the cylindrical conductive material layer 21a. Next, a first annular conductive material layer 21b is deposited around the first dielectric material layer 22a. The above deposition logic is then repeated sequentially. A second dielectric material layer 22b is deposited around the first annular conductive material layer 21b. A second annular conductive material layer 21c is deposited around the second dielectric material layer 22b. A third dielectric material layer 22c is deposited around the second annular conductive material layer 21c. Finally, the third dielectric material layer 22c adheres to the inner wall of the first etched hole 402d.

[0054] During the deposition process, the capacitance values ​​of the formed capacitors are made different by adjusting the process parameters: for example, adjusting the thickness of each dielectric material layer 22, selecting dielectric materials with different dielectric constants, etc., so that the first capacitor formed by the cylindrical conductive material layer 21a and the first annular conductive material layer 21b and the first dielectric material layer 22a between them, the second capacitor formed by the first annular conductive material layer 21b and the second annular conductive material layer 21c and the second dielectric material layer 22b between them, and the third capacitor formed by the second annular conductive material layer 21c and the inner wall of the first etched hole 402d and the third dielectric material layer 22c between them have different capacitance values.

[0055] After deposition, the first etched hole 402d port is subjected to conventional planarization treatment, such as chemical mechanical polishing, to remove excess deposited material, making the surface of the substrate 110 flat and obtaining a semiconductor structure.

[0056] In some embodiments of this disclosure, the method further includes: S404, as... Figure 9As shown in D, a redistribution layer is formed on the surface of the substrate 110 away from the deep hole etching. When forming the redistribution layer, conventional metal deposition and patterning processes can be used. First, a metal layer is deposited on the surface of the substrate 110 away from the deep hole etching, and then metal wiring with a preset pattern is formed through photolithography, etching and other processes. The two ends of the metal wiring are respectively connected to the ends of the first conductive hole 20 and the second conductive hole 30, so that the redistribution layer can realize the transmission of electrical signals between the first conductive hole 20 and the second conductive hole 30, or lead out the electrical signals of the two conductive holes to the external circuit.

[0057] In some embodiments of this disclosure, such as Figure 10 As shown, the deep hole etching process performed on the substrate 110 in S402 to generate multiple first etched holes 402d includes the following steps: S4021, i.e. Figure 10 As shown in Figure A, after deep hole etching is performed on the substrate 110, multiple etched holes 402a are generated simultaneously, and the multiple etched holes 402a are arranged in parallel along the first direction of the substrate 110. S4022, i.e. Figure 10 As shown in B, a dielectric material layer 22 and a seed layer are deposited on the etched hole 402a to obtain the etched hole 402b to be filled; S4023, i.e. Figure 10 As shown in C, after depositing a conductive material layer 21 on the etched hole 402a to be filled, a conductive hole is obtained. A portion of the conductive holes is selected as the second conductive hole 30, and another portion of the conductive holes is selected as the first intermediate conductive hole 402c. S4024, i.e. Figure 10 As shown in Figure D, the conductive material layer 21 in the first intermediate conductive hole 402c is etched to obtain the first etched hole 402d. It should be noted that the etching object in this step is merely an example and does not constitute any constraint on the technical solution of this invention. In actual operation, depending on specific process requirements, it is possible to choose to etch only the conductive material layer 21 in the first intermediate conductive hole 402c, or to etch both the conductive material layer 21 and the dielectric material layer 22 in the first intermediate conductive hole simultaneously. Both of these etching methods are within the protection scope of this invention.

[0058] In some embodiments of this disclosure, such as Figure 11 As shown, the electronic device 50 includes at least the power transmission structure 11 described in the foregoing embodiments.

[0059] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0060] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0061] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0062] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0063] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0064] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A power transmission structure, characterized in that, The power transmission structure includes a plurality of semiconductor structures stacked along a first direction. The substrate of the semiconductor structure has a first conductive hole formed along the first direction. The first conductive hole is used to transmit power signals. The first conductive hole is provided with multiple coaxially nested conductive material layers and multiple dielectric material layers; each conductive material layer is surrounded by a dielectric material layer, and each dielectric material layer is surrounded by a conductive material layer. The adjacent conductive material layers and the dielectric material layer located between the adjacent conductive material layers together form a capacitor. The different capacitors formed in the first conductive hole have different capacitance values, so that the power signals of different frequencies are distributed to the corresponding conductive material layers.

2. The power transmission structure according to claim 1, characterized in that, The semiconductor structure further includes a redistribution layer, the substrate and the redistribution layer are distributed along a first direction, and the redistribution layer includes a plurality of redistribution lines; different conductive material layers are connected to different redistribution lines.

3. The power transmission structure according to claim 1, characterized in that, Different conductive material layers may have one or more of the following parameters that differ: (1) Ingredients; (2) The thickness is different along the second direction; Different dielectric material layers may have one or more of the following parameters that differ: (1) Dielectric constant; (2) The thickness is different along the second direction, which is perpendicular to the first direction; (3) Ingredients.

4. The power transmission structure according to claim 1, characterized in that, A second conductive hole is formed on the substrate along a first direction. The second conductive hole has a dielectric material layer and a conductive material layer nested coaxially, and the conductive material layer surrounds the dielectric material layer. For the first conductive hole, a portion of the conductive material layer is connected to the second conductive hole in the same semiconductor structure via the redistribution layer; For the first conductive hole, another portion of the conductive material layer is connected to the second conductive holes of other semiconductor structures via the redistribution layer.

5. The power transmission structure according to claim 1, characterized in that, The projections of the plurality of conductive holes in each of the semiconductor structures are aligned along a first direction; Each of the first conductive holes is connected to a second conductive hole in the same semiconductor structure, and each of the first conductive holes is also electrically connected to different second conductive holes in adjacent semiconductor structures to conduct the power signal to different lines in adjacent semiconductor structures based on the frequency of the power signal.

6. The power transmission structure according to claim 1, characterized in that, The conductive material layer includes a columnar conductive material layer, a first annular conductive material layer, and a second annular conductive material layer. The dielectric material layer includes a first dielectric material layer, a second dielectric material layer, and a third dielectric material layer; The cylindrical conductive material layer is disposed in the central region of the first conductive hole; the cylindrical conductive material layer surrounds the first dielectric material layer; the first dielectric layer surrounds the first annular conductive material layer. The first annular conductive material layer is surrounded by a second dielectric material layer; the second dielectric layer is surrounded by a second annular conductive material layer. The second annular conductive material layer surrounds the third dielectric material layer; the outer periphery of the third dielectric material layer is attached to the inner wall of the first conductive hole; The cylindrical conductive material layer, the first dielectric material layer, and the first annular conductive material layer together form a first capacitor; the first annular conductive material layer, the second dielectric material layer, and the second annular conductive material layer together form a second capacitor; the second annular conductive material layer, the third dielectric material layer, and the inner wall of the first conductive hole together form a third capacitor. The first, second, and third capacitors have different capacitance values, so that power signals of different frequencies are distributed to the corresponding conductive material layers.

7. A method for forming a semiconductor structure, characterized in that, Provide a base; The substrate is subjected to deep hole etching to create a first etched hole; Multiple conductive material layers and multiple dielectric material layers are sequentially deposited in the first etched hole; a dielectric material layer is deposited around each of the conductive material layers, and a conductive material layer is deposited around each of the dielectric material layers, to obtain the first conductive hole; The adjacent conductive material layers and the dielectric material layer located between the adjacent conductive material layers together form a capacitor. The capacitance values ​​of the different capacitors formed in the first conductive hole are different, so that the power signals of different frequencies are distributed to the corresponding conductive material layers.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The method further includes: A redistribution layer is formed on the surface of the substrate away from the deep hole etching, and different conductive material layers of the first conductive hole are connected to the redistribution layer with different redistribution lines.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The deep-hole etching process performed on the substrate to create multiple first etched holes also includes: After deep hole etching is performed on the substrate, multiple etched holes are generated simultaneously, and the multiple etched holes are arranged in parallel along a first direction of the substrate; A dielectric material layer and a seed layer are deposited on the etched hole to obtain the etched hole to be filled; After depositing a conductive material layer on the etched hole to be filled, a conductive hole is obtained. A portion of the conductive holes are selected as the second conductive hole, and another portion of the conductive holes are selected as the first intermediate conductive hole. The conductive material layer in the first intermediate conductive hole is etched to obtain the first etched hole.

10. An electronic device, characterized in that, The electronic device includes the power transmission structure according to any one of claims 1 to 8.

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