A semiconductor structure, a method for forming it, and a packaging structure.

Abstract

This application provides a semiconductor structure, a method for forming it, and a packaging structure. The semiconductor structure includes: a substrate; a dielectric layer located on the substrate; solder pads located within the dielectric layer; a bump structure and a connection structure, wherein the bump structure and the connection structure located between some adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; and a through-silicon via (TSV), which penetrates the substrate and extends to the dielectric layer, and is electrically connected to the bump structure via solder pads. The TSV includes a main via and a pseudo via, and the bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via via through the connection structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure, a method of forming it, and a packaging structure. Background Technology

[0002] As memory chips evolve towards higher density and higher bandwidth, 3D stacking technology is widely used. In existing stacking structures, multiple chips are vertically interconnected via through-silicon vias (TSVs) and bumps. However, the small chip spacing and concentrated heat sources easily lead to localized overheating and decreased signal integrity. Simultaneously, process differences and uneven interconnect parasitic parameters between different chips exacerbate read / write latency and power consumption imbalances, limiting the overall performance of stacked products. Therefore, effectively managing thermal effects, balancing interconnect load, and reducing inter-chip interference in a stacked architecture have become key issues for improving memory bandwidth and energy efficiency. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for forming it, and a packaging structure to shorten critical signal paths, balance power distribution, and reduce the risk of thermomechanical failure, thereby effectively improving the overall performance of stacked memory products.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a semiconductor structure, comprising: a substrate; a dielectric layer located on the substrate; bonding pads located within the dielectric layer; a bump structure and a connection structure, wherein the bump structure and the connection structure located between partially adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; and a through-silicon via (TSV), wherein the TSV penetrates the substrate and extends to the dielectric layer, and is electrically connected to the bump structure via the bonding pads, the TSV including a main via and a pseudo via, and the bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via via through the connection structure.

[0005] In some embodiments, the bump structure includes a first conductive layer, a second conductive layer, a first metal layer, and a second metal layer stacked sequentially along a direction perpendicular to the substrate; the first metal layer includes a first metal portion and a second metal portion located on the first metal portion, the first metal portion covering a portion of the sidewall of the second conductive layer.

[0006] In some embodiments, the width of the second conductive layer is smaller than the width of the first metal portion and larger than the width of the second metal portion, and the width of the second metal portion is equal to the width of the second metal layer.

[0007] In some embodiments, the first metal layer and the second conductive layer of the bump structure, which are respectively connected to the main via in a direction parallel to the substrate, and the first metal layer and the second conductive layer of the bump structure, which are respectively connected to the pseudo via, are connected at both ends of the connection structure.

[0008] In some embodiments, the connection structure includes a first connection layer and a second connection layer stacked sequentially along a direction perpendicular to the substrate; at both ends of the first connection layer, a second conductive layer of the bump structure corresponding to the main via is connected along a direction parallel to the substrate, and a second conductive layer of the bump structure corresponding to the pseudo via is connected; at both ends of the second connection layer, a first metal layer of the bump structure corresponding to the main via is connected along a direction parallel to the substrate, and a first metal layer of the bump structure corresponding to the pseudo via is connected.

[0009] In some embodiments, the main via is electrically connected to another main via through the connection structure and the bump structure.

[0010] In some embodiments, the bump structures are arranged in an array on the substrate, and the interconnected bump structures are arranged in a straight line along a direction parallel to the substrate.

[0011] In some embodiments, the semiconductor structure further includes: a test bump and a thermally conductive structure; the main via and the pseudo via are connected through the connection structure and the bump structure, and are also connected to the test bump through the thermally conductive structure.

[0012] In some embodiments, the two ends of the thermally conductive structure are connected to the test bump along a direction parallel to the substrate, and at least one of the first metal layer, the second metal layer, and the second conductive layer of the bump structure is connected to the main via.

[0013] In some embodiments, the thermally conductive structure includes a first thermally conductive portion, a second thermally conductive portion, and a third thermally conductive portion stacked sequentially along a direction perpendicular to the substrate; a bump structure and a test bump connection wherein the two ends of the first thermally conductive portion, the second thermally conductive portion, and the third thermally conductive portion are respectively connected to the main via in a direction parallel to the substrate.

[0014] In a second aspect, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a through-silicon via (TSV), a dielectric layer, and a bonding pad; wherein the dielectric layer is located on the substrate; the bonding pad is located within the dielectric layer; the TSV penetrates the substrate and extends to the dielectric layer; the TSV includes a main via and a pseudo via; forming a bump structure and a connection structure; wherein the bump structure and the connection structure located between some adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; the bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via through the connection structure.

[0015] In some embodiments, the bump structure includes a first conductive layer, a second conductive layer, a first metal layer, and a second metal layer stacked sequentially along a direction perpendicular to the substrate; the connection structure includes a first connection layer and a second connection layer stacked sequentially along a direction perpendicular to the substrate. The formation of the bump structure and the connection structure includes: A first conductive material layer and a second conductive material layer are sequentially deposited on the surfaces of the dielectric layer and the solder pad; A first photoresist mask is formed on the second conductive material layer; wherein the first photoresist mask is used to define the pattern of the connection structure; a first connection layer and a second connection layer are sequentially deposited in a first opening exposed by the first photoresist mask; a second photoresist mask is formed; wherein the second photoresist mask is used to define the pattern of the bump structure; a second metal layer and a third metal layer are deposited in a second opening exposed by the second photoresist mask; a first hard mask is formed, and the first conductive material layer and the second conductive material layer are etched along the first hard mask to form the first conductive layer and the second conductive layer; wherein the first hard mask is used to define the pattern of the connection structure and the bump structure.

[0016] Thirdly, embodiments of this application provide a packaging structure, including: a plurality of first chips and a plurality of second chips; wherein, the first chips include the semiconductor structure described in any of the above embodiments; the first chips and the second chips are stacked alternately along a first direction; and the microbumps of the second chips are independently disposed.

[0017] This application provides a semiconductor structure in which through-silicon vias (TSVs) include main vias and pseudo vias. The bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via through a connecting structure. The pseudo via, which does not have electrical connection function, is connected to the main via, which has electrical connection function, through the connecting structure and the bump structure. This allows the pseudo via to provide redundant conductive or heat-conducting paths for the main via connected to it, further improving the flexibility of signal transmission and heat dissipation efficiency. At the same time, this application can further disperse the TSVs (i.e., main vias) for transmitting signals through the connecting structure, avoiding dense coupling of TSVs for transmitting signals and causing signal crosstalk. Attached Figure Description

[0018] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of this application; Figure 2 The semiconductor structure provided in one embodiment of this application is along the structural line Figure 1 Cross-sectional view along the A-A' direction; Figure 3 The semiconductor structure provided in one embodiment of this application is along the structural line Figure 1 Cross-sectional view along the B-B' direction; Figure 4 This is a top view of the semiconductor structure arrangement provided in an embodiment of this application. Figure 1 ; Figure 5 This is a top view of the semiconductor structure arrangement provided in an embodiment of this application. Figure 2 ; Figure 6 This is a top view of the semiconductor structure arrangement provided in an embodiment of this application. Figure 3 ; Figure 7 This is a top view of the thermally conductive structure and test bump provided in one embodiment of this application; Figure 8 The thermally conductive structure and test bump provided in one embodiment of this application are along... Figure 7 Cross section in the C-C' direction Figure 1 ; Figure 9 The thermally conductive structure and test bump provided in one embodiment of this application are along... Figure 7 Cross section in the C-C' direction Figure 2 ; Figure 10 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of this application; Figure 11 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 1 ; Figure 12 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 2 ; Figure 13 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 3 ; Figure 14 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 4 ; Figure 15 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 5 ; Figure 16 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 6 ; Figure 17 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 7 ; Figure 18 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 8 ; Figure 19 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 9 ; Figure 20 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 10 ; Figure 21 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 10 one; Figure 22 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 10 two; Figure 23 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 10 three; Figure 24 This is the structure corresponding to the method for forming a semiconductor structure provided in one embodiment of this application. Figure 10 Four; Figure 25 This is a structural diagram corresponding to a method for forming a semiconductor structure provided in an embodiment of this application; Figure 26 This is a schematic diagram of a semiconductor stacking structure provided in an embodiment of this application; Figure 27This is a schematic diagram of the bump structure in a semiconductor stacking structure provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] As memory chips continue to evolve towards higher density and higher bandwidth, 3D stacking technology has been widely applied in advanced packaging. In existing 3D stacking structures, multiple chips are vertically interconnected primarily through through-silicon vias (TSVs) and bump structures. However, due to the smaller chip spacing and highly concentrated heat sources, local hot spots are easily generated, leading to increased thermomechanical stress and decreased signal integrity. At the same time, inconsistencies in parasitic interconnect parameters caused by process variations between different chips further exacerbate the imbalance in read / write latency and power consumption distribution, severely restricting the overall performance of stacked memory products in terms of bandwidth, energy efficiency, and reliability.

[0021] Therefore, in a three-dimensional stacked architecture, how to effectively manage thermal effects, reduce inter-layer signal interference, and achieve signal path optimization and flexible configuration of redundant conductive / thermal paths has become a key issue for further improving storage bandwidth, energy efficiency, and reliability of the stacked system.

[0022] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of this application. Figure 2 The semiconductor structure provided in one embodiment of this application is along the structural line Figure 1 Cross-sectional view along the A-A' direction. Figure 3 The semiconductor structure provided in one embodiment of this application is along the structural line Figure 1 Cross-sectional view along the B-B' direction.

[0023] To address the aforementioned problems, this application proposes a semiconductor structure 100, with reference to... Figures 1-3The semiconductor structure 100 includes a substrate 10, a dielectric layer 20, bump structures 31, interconnect structures 32, pads 40, and through-silicon vias (TSVs) 50. The semiconductor structure 100 can be bonded and electrically connected to other chips via the bump structures 31. Both the bump structures 31 and the interconnect structures 32 located between partially adjacent bump structures 31 are located on the dielectric layer 20, and the interconnect structures 32 extend in a direction parallel to the substrate 10. The semiconductor structure 100 also includes through-silicon vias 50, which penetrate the substrate 10 and extend to the dielectric layer 20. The through-silicon vias 50 are electrically connected to the bump structures 31 via the pads 40, thereby forming a transmission channel through the substrate 10. The through-silicon vias 50 include a main via 50a and a dummy TSV 50b. For example, the main via 50a can be a functional vertical interconnect channel penetrating the chip substrate 10, directly connected to the core circuit signal or power network. It is electrically connected to the bump structure 31 via the pad 40, serving as a signal carrier to transmit data, clock, or control signals. It can also serve as a power distribution node to provide stable voltage / current to the stacked chip layers. The pseudo via 50b is structurally similar to the main via 50a, but it is not directly connected to the circuit signal or power network. The bump structure 31 corresponding to the main via 50a is electrically connected to the bump structure 31 corresponding to the pseudo via 50b via the connection structure 32.

[0024] In this embodiment, the pseudo-via 50b is connected to the main via 50a through the connection structure 32 and the bump structure 31. This allows the pseudo-via 50b to provide redundant conductive paths or signal channels for the main via 50a connected to it. It can form parallel paths with the pseudo-via 50b or other main vias to achieve dynamic topology. Furthermore, the connection structure 32 extends along a direction parallel to the surface of the substrate 10 (Y direction) to form a physical isolation barrier between adjacent silicon vias 50. This structure can significantly reduce mutual capacitance and suppress signal crosstalk caused by the dense arrangement of vias in three-dimensional stacking by blocking the electric field diffusion path between the main via 50a and the pseudo-via 50b.

[0025] In some embodiments, reference Figure 2The bump structure 31 includes a first conductive layer 311, a second conductive layer 312, a first metal layer 313, and a second metal layer 314 stacked sequentially along a direction perpendicular to the substrate 10. The first conductive layer 311 can be made of materials with adhesion properties such as titanium (Ti), titanium-tungsten (TiW), and tantalum (Ta). The first conductive layer 311 can enhance the bonding force between the solder pad 40 and the second conductive layer 312. The second conductive layer 312 can be made of a metal such as copper (Cu). The first metal layer 313 can be made of a metal such as nickel (Ni) to prevent the diffusion of the material (e.g., copper) from the second conductive layer 312, avoiding problems such as contamination and leakage. The second metal layer 314 can be made of a metal with wetting properties such as gold (Au). During the bonding process between the semiconductor structure 100 and other chips, the second metal layer 314 can provide a wetting surface to the bumps of other chips, facilitating uniform solder spread on the bumps of other chips and thus improving the stability of the bonding structure.

[0026] The first metal layer 313 includes a first metal portion 3131 and a second metal portion 3132 located on the first metal portion 3131. The first metal portion 3131 covers part of the sidewall of the second conductive layer 312, thereby ensuring that the sidewall of the second conductive layer 312 is completely covered by the first metal layer 313, preventing the second conductive layer 312 from being damaged in subsequent processes. At the same time, in this embodiment, the first metal layer 313 covers the sidewall of the second conductive layer 312, further increasing the surface area of ​​the bump structure 31 and improving the heat dissipation efficiency.

[0027] In some embodiments, reference Figure 2 The width of the second conductive layer 312 is smaller than the width of the first metal portion 3131 and larger than the width of the second metal portion 3132, and the width of the second metal portion 3132 is equal to the width of the second metal layer 314. For example, refer to... Figure 2 The widths of the second metal portion 3132 and the second metal layer 314 are both L3. The width L3 of the second metal portion 3132 and the second metal layer 314 is smaller than the width L2 of the second conductive layer 312, and the width L1 of the first metal portion 3131 is larger than the width L2 of the second conductive layer 312. This ensures that the width of the second conductive layer 312 is more easily controlled during the etching process to form the second conductive layer 312, reducing process errors (such as over-etching or incomplete etching) and improving yield. At the same time, by setting the width of the second conductive layer 312 to be smaller than the width of the first metal portion 3131 and larger than the width of the second metal portion 3132, the mechanical strength of the bump structure 31 can be enhanced, preventing deformation or delamination during the bonding process.

[0028] In some embodiments, reference Figures 2-3The different bump structures 31 have the same height in the direction perpendicular to the substrate 10, so that the top surface of each bump structure 31 is located on the same horizontal plane, ensuring that uniform contact is formed between the corresponding bump structures 31 during the bonding process, avoiding stress concentration or poor connection caused by thickness difference, thereby improving bonding yield and connection reliability.

[0029] In some embodiments, reference Figures 1-3 The first metal layer 313 and the second conductive layer 312 of the bump structure 31, which are connected to the main via 50a at both ends of the connecting structure 32 along a direction parallel to the substrate 10, and the first metal layer 313 and the second conductive layer 312 of the bump structure 31, which are connected to the pseudo via 50b, are respectively connected. After the bump structure 31 corresponding to the pseudo via 50b is electrically interconnected with the bump structure 31 corresponding to the main via 50a through the connecting structure 32, the pseudo via 50b can be activated as a redundant conductive path or signal channel, and can form a parallel path with the pseudo via 50b or other main vias to realize dynamic topology.

[0030] In some embodiments, reference Figure 1-3 The connection structure 32 includes a first connection layer 321 and a second connection layer 322 stacked sequentially along a direction perpendicular to the substrate 10. At both ends of the first connection layer 321, a second conductive layer 312 of a first bump structure 31a corresponding to the main via 50a and a second conductive layer 312 of a second bump structure 31b corresponding to the pseudo via 50b are connected along a direction parallel to the substrate 10. At both ends of the second connection layer 322, a first metal layer 313 of the first bump structure 31a corresponding to the main via 50a and a first metal layer 313 of the second bump structure 31b corresponding to the pseudo via 50b are connected along a direction parallel to the substrate 10. The first connecting layer 321 has better conductivity than the second connecting layer 322, and the second connecting layer 322 has better oxidation resistance and corrosion resistance than the first connecting layer 321. By setting the second connecting layer 322 to cover the first connecting layer 321, the second connecting layer 322 can protect the first connecting layer 321 and avoid structural damage to the first connecting layer 321 by subsequent processes.

[0031] It should be noted that the bump structure 31 may include a first bump structure 31a and a second bump structure 31b. The two are only used to distinguish whether they are connected to the main through hole, and there is no substantial difference in their structure. The first bump structure 31a and the second bump structure 31b mentioned below can be understood with reference to the bump structure 31.

[0032] In some embodiments, the connection structure 32 may also be a multi-layer structure. Specifically, the connection structure 32 may also include a third connection layer 323. The third connection layer 323 may be used to connect the first conductive layer 311 of the bump structure 31. By setting the third connection layer 323 to be directly connected to the bump structure 31, it is beneficial to integral molding and simplify the manufacturing process.

[0033] In some embodiments, the thickness H1 of the first connecting layer 321 in the direction perpendicular to the substrate 10 can be less than or equal to the thickness H3 of the second conductive layer 312 of the bump structure 31. For example, by setting the thickness of the first connecting layer 321 in the direction perpendicular to the substrate to be equal to the thickness of the second conductive layer 312 of the bump structure 31, the first connecting layer 321 and the second conductive layer 312 are integrally formed, thereby simplifying the process flow and enhancing the mechanical strength of the contact area between the bump structure 31 and the connecting structure 32. The material of the first connecting layer 321 can be the same as the material of the second conductive layer 312.

[0034] In some embodiments, the thickness H2 of the second interconnect layer 322 in the direction perpendicular to the substrate can be less than or equal to the thickness H4 of the first metal layer 313 of the bump structure 31. The material of the second interconnect layer 322 can be the same as the material of the first metal layer 313. For example, the thickness of the second interconnect layer 322 in the direction perpendicular to the substrate can be set to be less than the thickness of the second metal portion 3132 of the first metal layer 313 of the bump structure 31, and equal to the thickness of the first metal portion 3131 of the first metal layer 313 of the bump structure 31. While ensuring that the second interconnect layer 322 and the first metal layer 313 are integrally formed, the thickness of the second interconnect layer 322 is reduced, thereby simplifying the process, enhancing the mechanical strength of the bump structure 31, and saving the volume of the formed semiconductor structure.

[0035] In some embodiments, the first connecting layer 321 of the connecting structure 32 may cover the second conductive layer 312 of the interconnected bump structures 31, and the second connecting layer 322 of the connecting structure 32 may cover the sidewalls and top of the second conductive layer 312. The first metal layer 313 and the second metal layer 314 of the interconnected bump structures 31 may be independently disposed on the second connecting layer 322, thereby further enhancing the mechanical strength of the bump structures 31 by embedding the connecting structure 32 into the bump structures 31.

[0036] In some embodiments, a main via 50a is electrically connected to another main via 50a via a connection structure 32 and a bump structure 31, thereby utilizing the connection structure 32 as a redistribution layer to reconstruct the connection relationship of multiple main vias 50a. Interconnected main vias 50a form parallel transmission channels, while non-interconnected main vias 50a form independent transmission channels. In the event of congestion or failure in any of the parallel transmission channels, the signals transmitted in the parallel transmission channels can be switched via the connection structure, thereby improving the flexibility of signal transmission and preventing the entire chip from being scrapped due to the failure of a single transmission channel. Furthermore, compared to independent transmission channels, the parallel transmission channels formed in this embodiment can reduce the total equivalent resistance and total equivalent inductance. Therefore, applying parallel transmission channels to power and signal transmission can effectively reduce DC voltage drop and switching noise while reducing insertion loss and signal reflection, thus improving signal transmission characteristics.

[0037] In some embodiments, reference Figures 4-6 , Figures 4-6 This is a top view of different arrangements of a semiconductor structure provided in one embodiment of this application. The bump structures 31 are arranged in an array on the substrate 10. Along a direction parallel to the substrate 10, the interconnected bump structures 31 are arranged in a straight line. This straight-line arrangement of the bump structures 31 reduces the wiring complexity of the connection structure 32, effectively improving the reliability and yield of the semiconductor structure. It should be noted that the number of bump structures 31 connected by the connection structure can be designed according to actual conditions and is not limited here. For example, each first bump structure 31a is connected to 1, 2, 4, or 6 second bump structures 31b through the connection structure 32.

[0038] In some embodiments, continue to refer to Figure 6 The connecting structure 32 covers the insulating dielectric layer 20 located between the first bump structure 31a and the second bump structure 31b along a direction parallel to the substrate 10, thereby increasing the area of ​​the connecting structure 32 while connecting the bump structure 31 and improving the heat dissipation efficiency.

[0039] Figure 7 This is a top view of the thermally conductive structure and test bump provided in one embodiment of this application; Figure 8 The thermally conductive structure and test bump provided in one embodiment of this application are along... Figure 7 Cross-sectional view along the C-C' direction.

[0040] In some embodiments, reference Figures 7-8The semiconductor structure 100 also includes a test bump 33 and a thermally conductive structure 34. The main via 50a and the pseudo via 50b are connected via the connection structure 32 and the bump structure 31, and can also be connected to the test bump 33 via the thermally conductive structure 34. The test bump 33 is a bump structure without connected vias, used to provide a test channel for functional testing to detect chip defects and interconnect faults. The test bump 33 may include an under-bump metal 331, a conductive pillar 332, a first test metal layer 333, and a second test metal layer 334. The test bump 33 and the thermally conductive structure 34 can provide redundant heat conduction paths for the semiconductor structure 100, thereby further improving the heat dissipation efficiency of the semiconductor structure 100.

[0041] In some embodiments, reference Figures 7-8 The two ends of the heat-conducting structure 34 are connected along a direction parallel to the substrate 10 to at least one of the first metal layer 313, the second metal layer 314, and the second conductive layer 312 of the bump structure 31, which are respectively connected to the test bump 33 and the main via 50a. Exemplarily, the first metal layer 313, the second metal layer 314, and the second conductive layer 312 can all be connected to the heat-conducting structure 34. In other embodiments, the number of layers of the bump structure 31 used to connect the heat-conducting structure can be set according to actual conditions and is not limited here.

[0042] In some embodiments, the thermally conductive structure 34 includes a first thermally conductive portion 341, a second thermally conductive portion 342, and a third thermally conductive portion 343 stacked sequentially along a direction perpendicular to the substrate 10. The first thermally conductive portion 341 may be made of a material with adhesive properties such as titanium (Ti), titanium-tungsten (TiW), and tantalum (Ta); the second thermally conductive portion 342 may be made of a metal such as copper (Cu); and the third thermally conductive portion 343 may be made of a metal such as nickel (Ni). No specific limitations are imposed here.

[0043] refer to Figure 8Along a direction parallel to the substrate 10, the two ends of the first thermally conductive portion 341, the second thermally conductive portion 342, and the third thermally conductive portion 343 are respectively connected to the bump structure 31 and the test bump 33 corresponding to the main via 50a. For example, the two ends of the first thermally conductive portion 341, along a direction parallel to the substrate, are respectively connected to the first conductive layer 311 of the first bump structure 31a corresponding to the main via 50a, and to the under-bump metal 331 of the test bump 33. The two ends of the second thermally conductive portion 342, along a direction parallel to the substrate, are respectively connected to the second conductive layer 312 of the first bump structure 31a corresponding to the main via 50a, and to the conductive post 332 of the test bump 33. The two ends of the third thermally conductive portion 343, along a direction parallel to the substrate, are respectively connected to the first metal layer 313 of the first bump structure 31a corresponding to the main via 50a, and to the first test metal layer 333 of the test bump 33. Each heat-conducting part of the heat-conducting structure 34 is connected to a corresponding bump structure, which effectively enhances the mechanical strength of the contact area between the bump structure 31 and the heat-conducting structure 34, thereby preventing problems such as breakage and delamination of the semiconductor structure during the bonding process.

[0044] In some embodiments, the materials of the first heat-conducting part 341, the second heat-conducting part 342, and the third heat-conducting part 343 can all be the same as the materials of the first conductive layer 311 of the first bump structure 31a and the under-bump metal 331 of the test bump, thereby enabling the heat-conducting structure 34 to be formed simultaneously during the formation of the bump structure 31 and the test bump 33, simplifying the manufacturing process.

[0045] In some embodiments, continue to refer to Figure 8 In the direction perpendicular to the substrate 10, the thickness of the first thermally conductive portion 341 of the thermally conductive structure 34 can be less than or equal to the thickness of the first conductive layer 311 of the bump structure 31 or the under-bump metal 331 of the test bump 33. For example, by setting the thickness of the first thermally conductive portion 341 of the thermally conductive structure 34 in the direction perpendicular to the substrate 10 to be equal to the thickness of the first conductive layer 311 of the first bump structure 31a or the under-bump metal 331 of the test bump 33, the first thermally conductive portion 341 is integrally formed with the first conductive layer 311 of the first bump structure 31a and the under-bump metal 331 of the test bump 33, thereby simplifying the process flow and enhancing the structural strength of the bump structure 31 and the thermally conductive structure 34.

[0046] The thickness of the second thermally conductive portion 342 can be less than or equal to the thickness of the second conductive layer 312 of the bump structure 31 or the conductive post 332 of the test bump 33. For example, by setting the thickness of the second thermally conductive portion 342 of the thermally conductive structure 34 in the direction perpendicular to the substrate 10 to be less than the thickness of the second conductive layer 312 of the first bump structure 31a or the conductive post 332 of the test bump 33, the second thermally conductive portion 342 is integrally formed with the second conductive layer 312 of the first bump structure 31a or the conductive post 332 of the test bump 33, simplifying the process flow and enhancing the structural strength of the bump structure 31 and the thermally conductive structure 34.

[0047] The thickness of the third thermally conductive portion 343 can be less than or equal to the thickness of the first metal layer 313 of the bump structure 31a or the first test metal layer 333 of the test bump 33. For example, by providing that the thickness of the third thermally conductive portion 343 of the thermally conductive structure 34 in the direction perpendicular to the substrate 10 is less than the thickness of the first metal layer 313 of the first bump structure 31a or the first test metal layer 333 of the test bump 33, the third thermally conductive portion 343 is integrally formed with the first metal layer 313 of the bump structure 31 or the first test metal layer 333 of the test bump 33, simplifying the process flow. Furthermore, because the thickness of the third thermally conductive portion 343 is less than the thickness of the first metal layer 313 of the bump structure 31 or the first test metal layer 333 of the test bump 33, the volume of the semiconductor structure is saved.

[0048] Figure 9 Another embodiment of this application provides a thermally conductive structure and a test bump along... Figure 7 A cross-sectional view along the C-C' direction. In some embodiments, refer to Figure 9 By setting the thickness of the second thermally conductive portion 342 of the thermally conductive structure 34 in the direction perpendicular to the substrate 10 to be equal to the thickness of the second conductive layer 312 of the first bump structure 31a or the conductive pillar 332 of the test bump 33, the second thermally conductive portion 342 is integrally formed with the second conductive layer 312 of the bump structure 31 or the conductive pillar 332 of the test bump 33, simplifying the process flow. Furthermore, since the thickness of the second thermally conductive portion 342 is equal to the thickness of the second conductive layer 312 of the bump structure 31 or the conductive pillar 332 of the test bump 33, the heat dissipation efficiency of the semiconductor structure 100 is further increased.

[0049] Figure 10 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of this application; Figures 11-25 This is a structural diagram corresponding to a method for forming a semiconductor structure provided in an embodiment of this application. Figure 10 The formation method shown can be used to form the semiconductor structure 100 in the above embodiments, and will be described in conjunction with each step.

[0050] S101, Provide substrate.

[0051] S102, forming a through-silicon via, a dielectric layer, and a bonding pad; wherein, the dielectric layer is located on the substrate; the bonding pad is located within the dielectric layer; the through-silicon via penetrates the substrate and extends to the dielectric layer; the through-silicon via includes a main via and a pseudo via.

[0052] Figure 11 and Figure 12 Specifically, the example shows the pad 40 and the dielectric layer 20. Before forming the pad 40 and the dielectric layer 20, a through-silicon via (TSV) can be formed through the substrate 10. The TSV includes a main via 50a and a pseudo via 50b.

[0053] In this embodiment of the application, reference is made to Figure 11 The substrate 10 may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.) and at least one III... V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), at least one II VI. The compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, SiC substrates, etc.

[0054] In this embodiment of the application, reference is made to Figure 11 and Figure 12 After forming the bonding pads 40 on the surface of the substrate 10, an insulating layer made of a material such as silicon dioxide can be deposited on the surface of the substrate 10, and the insulating layer can be etched to expose the bonding pads 40, forming a layer such as... Figure 11 and Figure 12 The dielectric layer 20 shown has openings. The openings in the dielectric layer 20 expose the solder pads 40.

[0055] In this embodiment, "deposition" can be achieved by any combination of one or more processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and electroplating. The specific process selected can be chosen based on the properties of the material being deposited, and no restrictions are imposed here. The deposition process in the embodiments below can be understood with reference to this document, and will not be described again here.

[0056] S103, forming a bump structure and a connection structure; wherein the bump structure and the connection structure located between some adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; the bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via through the connection structure.

[0057] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a schematic diagram of the optional semiconductor structure formation process provided in the embodiments of this application. It should be noted that... Figure 13 , Figure 15 and Figure 17 This is a front view. Figure 14 , Figure 16 and Figure 18 This is a top view. The bump structure 31 may include a first conductive layer 311 (such as...). Figure 13 and Figure 14 As shown), the second conductive layer 312 (as shown) Figure 15 and Figure 16 As shown), and the first metal layer 313 and the second metal layer 314 (as shown). Figure 17 and Figure 18 (As shown). The connection structure 32 may include a first connection layer 321 (as shown). Figure 15 and Figure 16 As shown), the second connection layer 322 (as shown) Figure 17 and Figure 18 (as shown) and the third connection layer 323 (as shown) Figure 13 and Figure 14 (As shown).

[0058] In this embodiment of the application, combined with Figure 11 and Figure 13 A first conductive material layer made of materials such as titanium is deposited on the surfaces of the dielectric layer 20 and the solder pad 40. Then, the first conductive material layer is etched to form a layer as shown in the image. Figure 13 and Figure 14 The first conductive layer 311 is shown. The first conductive layer 311 is used to form Figures 1 to 3 The bump structure 31 shown.

[0059] In this embodiment, "etching" can be achieved by any combination of dry etching and wet etching processes, and no limitation is imposed here. The "etching" in the following embodiments can be understood with reference to this, and will not be described again.

[0060] In some embodiments, after forming the first conductive layer 311, deposition can continue to form such as Figure 14 The third interconnecting layer 323 is shown. The third interconnecting layer 323 covers the interconnected silicon vias corresponding to the first conductive structure 311a, while the second conductive structures 311b are independent of each other. The third interconnecting layer 323 is used to form... Figures 1 to 3 The connection structure 32 is shown.

[0061] In this embodiment of the application, combined with Figure 13 and Figure 15 A conductive material layer made of copper or similar material is deposited on the surface of the first conductive layer 311. Then, the conductive material layer is etched to form a layer as shown in the image. Figure 15 and Figure 16 The second conductive layer 312 is shown. The second conductive layer 312 is used to form Figures 1 to 3 The bump structure 31 is shown. Then, a structure like the one shown is deposited on the second conductive layer 312. Figure 15 and Figure 16 The first interconnect layer 321 is shown. The first interconnect layer 321 covers the interconnected silicon vias and the corresponding second conductive layer 312. The first interconnect layer 321 is used to form... Figures 1 to 3 The connection structure 32 is shown.

[0062] In this embodiment of the application, combined with Figure 15 and Figure 17 A barrier material layer made of materials such as nickel is deposited on the surface of the second conductive layer 312, and then the barrier material layer is etched to form a layer such as... Figure 17 and Figure 18 The second connecting layer 322 is shown. The second connecting layer 322 is used to form Figures 1 to 3 The connection structure 32 is shown.

[0063] Then, a barrier material layer made of materials such as nickel is deposited on the surface of the second connecting layer 322. The barrier material layer is then etched to form a layer as shown in the image. Figure 17 and Figure 18 The first metal layer 313 is shown. The first metal layer 313 includes a first barrier structure 313a and a second barrier structure 313b that are independently disposed on the second connecting layer 322. The first barrier structure 313a and the second barrier structure 313b are used to form... Figures 1 to 3 The bump structure 31 is shown. The thickness of the first blocking structure 313a in the third direction Z is less than that of the second blocking structure 313b, thereby avoiding inconsistent heights of the bump structure 31.

[0064] Finally, a wetting material layer made of gold or other materials is deposited on the surface of the first metal layer 313, and then the wetting material layer is etched to form a layer such as... Figures 1 to 3 The second metal layer 314 is shown.

[0065] It is understood that in this embodiment, the interconnect structure is used as a redistribution layer to interconnect the independent bump structures of the semiconductor structure. Thus, in this embodiment, the pseudo-vias 50b, which lack electrical connection functionality, are connected to the main vias 50a, which do have electrical connection functionality, through the interconnect structure 32 and the bump structure 31. This allows the pseudo-vias 50b to provide redundant conductive or heat-conducting paths for the connected main vias 50a, further improving the flexibility of signal transmission and heat dissipation efficiency. Simultaneously, the interconnect structure 32 can provide shielding in the horizontal plane (the extension plane containing the second direction Y and the third direction Z), thereby reducing mutual capacitance and suppressing signal crosstalk. Furthermore, in this embodiment, the interconnect structure 32 can further disperse the silicon vias transmitting signals, avoiding dense coupling of silicon vias that could cause signal crosstalk.

[0066] In some embodiments of this application, S103 in the figure can also be implemented by S201~S206, which will be described in conjunction with each step.

[0067] S201. A first conductive material layer and a second conductive material layer are sequentially deposited on the surfaces of the dielectric layer and the solder pad.

[0068] Figure 19 This is a schematic diagram of the optional semiconductor structure formation process provided in the embodiments of this application. It should be noted that... Figure 19 The front view specifically illustrates the first conductive material layer 60 and the second conductive material layer 71. The first conductive material layer 60 is used to form... Figure 13 and Figure 14 The first conductive layer 311 and the second conductive material layer 71 are used to form Figure 15 and Figure 16 The second conductive layer 312.

[0069] In this embodiment of the application, combined with Figure 11 and Figure 19 A first conductive material layer 60 and a second conductive material layer 71 are deposited on the surfaces of the dielectric layer 20 and the solder pad 40.

[0070] S202. A first photoresist mask is formed on the second conductive material layer; wherein the first photoresist mask is used to define the pattern of the connection structure.

[0071] S203. Within the first opening exposed by the first photoresist mask, a first interconnect layer and a second interconnect layer are deposited sequentially.

[0072] Figure 20 , Figure 21 and Figure 22 This is a schematic diagram of the optional semiconductor structure formation process provided in the embodiments of this application. It should be noted that... Figure 20 and Figure 21 This is a front view. Figure 22 This is a top view. Figure 20 The first photoresist mask 81 is shown as a specific example. Figure 21 and Figure 22 The first connection layer 321 and the second connection layer 322 are specifically illustrated.

[0073] In this embodiment of the application, combined with Figure 19 and Figure 20 A first photoresist layer is coated on the second conductive material layer 71, and a first photoresist mask 81 is formed through exposure, development, and other steps. The first opening 82 of the first photoresist mask 81 is used to define the pattern of the connection structure 32 to be formed. Then, conductive material and barrier material are sequentially deposited within the exposed first opening 82 of the first photoresist mask 81. Finally, the first photoresist mask 81 is removed to form... Figure 21 and Figure 22 The first connecting layer 321 and the second connecting layer 322 shown herein form, i.e.: Figures 1 to 3 The connection structure 32 is shown.

[0074] S204. Form a second photoresist mask; wherein the second photoresist mask is used to define the pattern of the bump structure.

[0075] S205. Deposit a second metal layer and a third metal layer within the second opening exposed by the second photoresist mask.

[0076] Figure 23 and Figure 24 This is a schematic diagram of the optional semiconductor structure formation process provided in the embodiments of this application. It should be noted that... Figure 23 and Figure 24 This is a front view. Figure 23 The second photoresist mask 83 is shown as a specific example. Figure 24 The specific example shows the second metal layer 314, and, Figure 17 and Figure 18 The first metal layer 313 is shown. The first metal layer 313 may include a barrier structure 313a and a barrier structure 313b.

[0077] In this embodiment of the application, combined with Figure 23 and Figure 24 A second photoresist layer is coated on the second conductive material layer 71, and a second photoresist mask 83 is formed through exposure and development steps. The second opening 84 of the second photoresist mask 83 is used to define the pattern of the bump structure 31 to be formed. Then, conductive material and barrier material are sequentially deposited in the exposed second opening 84 of the second photoresist mask 83, and then the second photoresist mask 83 is removed to form... Figure 24 The first metal layer 313 and the second metal layer 314 are shown.

[0078] S206. A first hard mask is formed, and a first conductive material layer and a second conductive material layer are etched along the first hard mask to form a first conductive layer and a second conductive layer; wherein, the first hard mask is used to define the pattern of the connection structure and the bump structure.

[0079] Figure 25 This is a schematic diagram of the optional semiconductor structure formation process provided in the embodiments of this application. It should be noted that... Figure 25 This is a front view. Figure 25 The first hard mask 85 is specifically shown, which is used to define the pattern of the connection structure 32 and the bump structure 31.

[0080] In this embodiment of the application, combined with Figure 24 and Figure 25 The second conductive material layer 71 and the first conductive material layer 60 are etched along the first hard mask 85 to form Figure 13 The first conductive layer 311 shown and Figure 15 The second conductive layer 312 is shown. The second conductive material layer 71 is etched to form... Figure 15 and Figure 16 The second conductive layer 312 is shown. The first conductive material layer 60 is etched to form... Figure 13 and Figure 14 The first conductive layer 311 is shown.

[0081] In some embodiments, the formation of the test bump can be understood according to the bump structure of the above embodiments, and the formation of the heat-conducting structure can be understood according to the connection structure of the above embodiments, which will not be described again here.

[0082] Figure 26 This is a schematic diagram of a semiconductor stacking structure provided in an embodiment of this application; Figure 27 This is a schematic diagram of the bump structure in a semiconductor stacking structure provided in an embodiment of this application.

[0083] It should be noted that, Figure 26 In the example, the first chip 210 and the second chip 220 are stacked alternately along the third direction Z. The first chip 210 and the second chip 220 can also be stacked in other ways, which are not limited here. Figure 26 The base die 240 shown is located at the bottom of the package structure 200. The base die 240 can be a logic chip, directly connected to the interposer or SoC (System-on-a-Chip). The top die 230 is located at the top of the package structure 200. The top die 230 can be a memory chip, which does not require through-silicon vias (TSVs), but only requires independent microbumps for bonding. Figure 27Example Figure 26 The specific structure of the second chip 220 bonded to the first chip 210. Figure 26 The bonding structure of the remaining chips can be referenced. Figure 27 This will be understood in more detail here.

[0084] In this embodiment of the application, combined with Figure 26 and Figure 27 The package structure 200 includes a plurality of first chips 210 and a plurality of second chips 220. The first chips 210 include the semiconductor structure 100 of any of the above embodiments. The first chips 210 and second chips 220 are alternately stacked along a direction perpendicular to the substrate (third direction Z). The first chips 210 and second chips 220 are bonded to each other. The microbumps 252 of the second chips 220 are independently disposed. Figure 27 The bonding structure 251 shown is the structure formed by bonding the bump structure of the first chip 210. Figure 27 The bonding structure 251 shown acts as a redistribution layer, reconstructing the connection relationships of the through-silicon vias (TSVs). Thus, the bump structure of the first chip 210 can function as a redistribution layer, providing lateral connectivity that allows signals to fan out horizontally, simultaneously transmitting an input signal to multiple vertical channels formed by the TSVs, meeting the signal distribution requirements of multiple target nodes in a three-dimensional stack. Simultaneously, the signal can dynamically adjust its direction by selecting the optimal vertical exit path in the horizontal layer based on real-time transmission conditions or pre-configured logic. This avoids multi-level jumps in the vertical direction, reducing the complexity and length of the overall transmission path. The signal can choose the shortest path exit in the horizontal layer, avoiding multi-level stacking jumps or long-distance detours in the vertical direction, thereby shortening the overall electrical path length and reducing transmission delay.

[0085] In some application embodiments, references Figure 26 The first chip 210 and the second chip 220 are of the same type, for example, both are memory chips. For instance, the memory chip can be a dynamic random access memory (DRAM). In other embodiments, the first chip 210 and the second chip 220 may be of different types, for example, the first chip 210 is a memory chip and the second chip 220 is a logic chip.

[0086] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A dielectric layer, the dielectric layer being located on the substrate; solder pads, wherein the solder pads are located within the dielectric layer; The bump structure and the connection structure located between some adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; A through-silicon via (TSV) penetrates the substrate and extends to the dielectric layer, and is electrically connected to the bump structure via the pad. The TSV includes a main via and a pseudo via. The bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via via the connection structure.

2. The semiconductor structure according to claim 1, characterized in that, The bump structure includes a first conductive layer, a second conductive layer, a first metal layer, and a second metal layer stacked sequentially along a direction perpendicular to the substrate; the first metal layer includes a first metal portion and a second metal portion located on the first metal portion, the first metal portion covering a portion of the sidewall of the second conductive layer.

3. The semiconductor structure according to claim 2, characterized in that, The width of the second conductive layer is smaller than the width of the first metal portion but larger than the width of the second metal portion, and the width of the second metal portion is equal to the width of the second metal layer.

4. The semiconductor structure according to claim 2, characterized in that, The first metal layer and the second conductive layer of the bump structure, which are connected to the main via in a direction parallel to the substrate at both ends of the connection structure, and the first metal layer and the second conductive layer of the bump structure, which are connected to the pseudo via, are connected to the main via.

5. The semiconductor structure according to claim 2, characterized in that, The connection structure includes a first connection layer and a second connection layer stacked sequentially along a direction perpendicular to the substrate; The first connecting layer has two ends connected to the second conductive layer of the bump structure corresponding to the main via in a direction parallel to the substrate, and the second conductive layer of the bump structure corresponding to the pseudo via is connected to the first conductive layer. The two ends of the second connecting layer are respectively connected to the first metal layer of the bump structure corresponding to the main via in a direction parallel to the substrate, and to the first metal layer of the bump structure corresponding to the pseudo via.

6. The semiconductor structure according to claim 2, characterized in that, The main through hole is electrically connected to another main through hole through the connecting structure and the bump structure.

7. The semiconductor structure according to claim 2, characterized in that, The bump structures are arranged in an array on the substrate, and the interconnected bump structures are arranged in a straight line along a direction parallel to the substrate.

8. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes: a test bump and a thermally conductive structure; the main via and the pseudo via are connected through the connection structure and the bump structure, and are also connected to the test bump through the thermally conductive structure.

9. The semiconductor structure according to claim 8, characterized in that, The two ends of the thermally conductive structure are connected to the test bump along a direction parallel to the substrate, and at least one of the first metal layer, the second metal layer, and the second conductive layer of the bump structure is connected to the main via.

10. The semiconductor structure according to claim 8, characterized in that, The thermally conductive structure includes a first thermally conductive part, a second thermally conductive part, and a third thermally conductive part stacked sequentially along a direction perpendicular to the substrate; Along a direction parallel to the substrate, the bump structure and the test bump connection are respectively connected at both ends of the first thermally conductive part, the second thermally conductive part and the third thermally conductive part to the main through hole.

11. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A through-silicon via (TSV), a dielectric layer, and solder pads are formed; wherein the dielectric layer is located on the substrate; the solder pads are located within the dielectric layer; the TSV penetrates the substrate and extends to the dielectric layer; the TSV includes a main via and a pseudo via; A bump structure and a connection structure are formed; wherein the bump structure and the connection structure located between some adjacent bump structures are both located on the dielectric layer, and the connection structure extends in a direction parallel to the substrate; the bump structure corresponding to the main via is electrically connected to the bump structure corresponding to the pseudo via through the connection structure.

12. The forming method according to claim 11, characterized in that, The bump structure includes a first conductive layer, a second conductive layer, a first metal layer, and a second metal layer stacked sequentially along a direction perpendicular to the substrate; the connection structure includes a first connection layer and a second connection layer stacked sequentially along a direction perpendicular to the substrate. The formation of the bump structure and the connection structure includes: A first conductive material layer and a second conductive material layer are sequentially deposited on the surfaces of the dielectric layer and the solder pad; A first photoresist mask is formed on the second conductive material layer; wherein the first photoresist mask is used to define the pattern of the connection structure; Within the first opening exposed by the first photoresist mask, a first interconnect layer and a second interconnect layer are sequentially deposited; A second photoresist mask is formed; wherein the second photoresist mask is used to define the pattern of the bump structure; A second metal layer and a third metal layer are deposited within the second opening exposed by the second photoresist mask; A first hard mask is formed, and the first conductive material layer and the second conductive material layer are etched along the first hard mask to form the first conductive layer and the second conductive layer; wherein, the first hard mask is used to define the pattern of the connection structure and the bump structure.

13. A packaging structure, characterized in that, include: Multiple first chips and multiple second chips; among them, The first chip includes the semiconductor structure according to any one of claims 1 to 10; The first chip and the second chip are stacked alternately along a first direction; the microbumps of the second chip are set independently.

Images