A packaging frame, packaging structure, and heat dissipation device for SiC MOS applications

By introducing a stepped height difference transition and a top heat dissipation design into the SiC MOS package structure, electrical safety and thermal management issues are solved, achieving reliability and efficient heat dissipation for high-power SiC devices.

CN122138725APending Publication Date: 2026-06-02YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
Filing Date
2026-03-31
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Existing SiC MOS packaging structures have significant shortcomings in electrical safety, molding processability, and thermomechanical reliability, making it difficult to meet the packaging requirements of high power density SiC devices. In particular, they are prone to electrical short circuits, injection molding defects, and insufficient thermal management in high-voltage scenarios.

Method used

The package frame design adopts a stepped height difference transition structure, which isolates the base island and pins in three-dimensional space, increases the creepage distance and optimizes the flow of molding compound. At the same time, the top heat dissipation design creates an efficient heat conduction path.

Benefits of technology

It improves electrical withstand voltage, reduces the risk of electrical short circuits, enhances the molding bond strength, improves thermal management capabilities, reduces thermal resistance, and meets the high-temperature and high-pressure operating requirements of high-power SiC devices.

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Abstract

This invention relates to the field of semiconductor technology, and more particularly to a packaging frame, packaging structure, and heat dissipation device for SiC MOS applications. It includes: a first frame comprising a heat dissipation island and a first pin portion connected in sequence; the top surface of the heat dissipation island is located above the first pin portion, and a chip carrier area is provided at its bottom; a stepped area is provided at the edge of the top surface of the heat dissipation island; a chamfered step is provided between the stepped area and the first pin portion; the thickness of the heat dissipation island is greater than the thickness of the first pin portion; and a second frame is spaced apart and disposed on the side of the first frame. This invention achieves decoupling of electrical connections and heat conduction paths, significantly improving thermal management capabilities, enhancing heat dissipation capabilities, and reducing system thermal resistance. The top heat dissipation design improves Rth(j-a) by approximately 20% and Rth(j-h) by approximately 50% compared to traditional bottom heat dissipation; it also addresses the requirement of achieving a maximum operating junction temperature of 175~200℃ for SiC chips.
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