Packaging and methods for microelectronic devices with back-side cavities in semiconductor dies

Abstract

This disclosure relates to a microelectronic device package and method having a back-side cavity in a semiconductor die. The described example device (FIG. 2B, 100) comprises: at least one semiconductor die (105) mounted on a die pad (142) of a package substrate (111), the at least one semiconductor die having a cavity (141) extending into a back-side surface and having an edge surrounding the cavity on the back-side surface; a die attachment material (108) bonding the at least one semiconductor die to the die pad, the die attachment material being located within the cavity and directly contacting a device-side surface of the die pad around the edge of the cavity; an electrical connection (158) between a bonding pad (102) on the device-side surface of the at least one semiconductor die and a lead (144) of the package substrate; and a molding compound (123) covering the semiconductor die, the electrical connection, and a portion of the package substrate.

Description

Technical Field

[0001] This disclosure generally relates to microelectronic device packaging, and more specifically to a method for manufacturing a microelectronic device package, the microelectronic device package incorporating a semiconductor die with die attachment material mounted thereon. Background Technology

[0002] Semiconductor dies for use in electronic circuits are produced by forming semiconductor dies on the device-side surface of semiconductor wafers using semiconductor wafer fabrication facilities (sometimes called "wafer fabs"). Examples of semiconductor wafer materials include silicon, germanium, gallium arsenide, gallium nitride, sapphire, silicon carbide, and indium phosphide, with silicon being the most commonly used. Examples of wafer fabrication processes used to manufacture semiconductor dies include ion implantation, thermal annealing, thermal oxidation, chemical vapor deposition, dielectric deposition, conductor deposition, sputtering, damascene deposition, chemical mechanical polishing, and passivation layer deposition.

[0003] Once the semiconductor dies are complete, individual devices are removed from the semiconductor wafer through a process known as "dicing". After the semiconductor wafer is diced into individual semiconductor dies, the individual semiconductor dies can be mounted onto a packaging substrate to form a microelectronic device package. In an example process, individual semiconductor dies are mounted onto die pads, with the bonding pads on the semiconductor die facing away from each other. Die attachment films or die attachment epoxy can be used to attach the semiconductor dies to the die pads. Electrical connections can be formed between the leads of the semiconductor die and the packaging substrate; for example, wire bonds can be formed to couple the bonding pads on the semiconductor die to the leads of the packaging substrate. In some microelectronic device packages, the die pads are used as ground. When wire bonding is performed on the bonding pads of the semiconductor die, some connections are "under-bonding" connections to the die pads. The need for these connections creates "no-entry zones" on the die pads—the spaces on the die pads where wire bonding will occur. Crucial for reliable wire bonding is the absence of other materials within these "no-entry zones" of the KOZ (Know Your Customer). Die attachment materials can be used to attach semiconductor dies to the die pads. One cost-effective method is to deposit die attachment epoxy as a liquid, mount the die using the epoxy, and then allow the epoxy to cure. The die attachment epoxy extends beyond the edges of the rectangular semiconductor die. However, problems arise when the die attachment epoxy diffuses into the no-entry zones on the die pads through a phenomenon known as "epoxy bleed-out." Wire bonding elements need to be formed away from the die attachment epoxy. As the size of increasingly integrated semiconductor dies increases, the area of ​​the semiconductor die also increases. If, for these larger semiconductor dies, a large space is required outside the die area to prevent epoxy resin attached to the die from seeping into the no-entry zone, the die pad area will inevitably increase, and the overall package size will also increase. This conflicts with the growing demand for packages of smaller devices. Furthermore, some microelectronic device packages mount multiple semiconductor dies, and the increased area required to prevent epoxy resin attached to the die from interfering with wire bonding further increases the die pad area of ​​these packages. In addition, the number of different die pad sizes required for various packages leads to a large inventory of different packaging substrates required for different semiconductor dies, thereby increasing costs.

[0004] After the electrical connections are formed, molding compounds can be used to form the package body. For example, a transfer molding process can be used to cover portions of the semiconductor die, electrical connections, and package substrate with molding compounds, while exposing portions of the leads from the molding compounds to form terminals for a microelectronic device package.

[0005] Improvements are needed to produce reliable and robust microelectronic device packages in which the semiconductor die area is attached to the package substrate using die-attach epoxy resin, eliminating the need to increase the area of ​​the die pads to avoid epoxy resin leakage defects, and at a reasonable cost. Summary of the Invention

[0006] In the described example arrangement, an apparatus includes: at least one semiconductor die mounted on a die pad of a package substrate, the at least one semiconductor die having a device-side surface and an opposing back-side surface, the at least one semiconductor die having a cavity extending into the back-side surface and having an edge surrounding the cavity on the back-side surface; a die attachment material that bonds the at least one semiconductor die to the die pad, the die attachment material being positioned within the cavity extending into the back-side surface, the edge surrounding the cavity directly contacting the device-side surface of the die pad; an electrical connection between a bonding pad on the device-side surface of the at least one semiconductor die and a lead formed in a device-side layer of the package substrate, the lead having a terminal-forming portion and a board-side surface; and a molding compound covering the semiconductor die, the electrical connection, and a portion of the package substrate, while the board-side surface of the terminal is exposed from the molding compound, the molding compound forming a body for a microelectronic device package of the at least one semiconductor die.

[0007] In the described example method arrangement, the method includes: forming a semiconductor die on a device-side surface of a semiconductor substrate, the semiconductor substrate having a back-side surface opposite to the device-side surface; forming a cavity extending into the back-side surface of the semiconductor substrate, the cavity extending into the back-side surface of the semiconductor die and surrounded by an edge of the back-side surface of the semiconductor die; separating the semiconductor dies from each other by dicing the semiconductor substrate into individual semiconductor dies; applying die attachment epoxy to die pads of unit lead frames on a lead frame array, the unit lead frames having leads spaced apart from the die pads and arranged for electrical connection; and positioning the semiconductor die on the die pads of the unit lead frames. The method involves: mounting the semiconductor die onto the die pads using die-attachment epoxy resin, the die-attachment epoxy resin being located within a cavity extending into the back surface of the semiconductor die, wherein the edge of the back surface contacts the device-side surface of the die pads; forming an electrical connection between the bonding pads on the semiconductor die and the leads of the lead frame; covering the semiconductor die, the electrical connection, and portions of the unit lead frame with molding compound, the molding compound forming a body for a microelectronic device package, and exposing portions of the leads from the molding compound to form terminals for the microelectronic device package; and separating the unit lead frames from each other and from the lead frame array to form individual microelectronic device packages.

[0008] In another example method, the method includes: forming a semiconductor die on a device-side surface of a semiconductor substrate, the semiconductor substrate having a back-side surface opposite the device-side surface; forming a cavity extending into the back-side surface of the semiconductor substrate, the cavity extending into the back-side surface of the semiconductor die and surrounded by an edge of the back-side surface of the semiconductor die; applying a die-attachment epoxy resin to the cavity on the back-side surface of the semiconductor substrate, the die-attachment epoxy resin being accommodated within the cavity, the edge of the back-side surface of the semiconductor die not having die-attachment epoxy resin; separating the semiconductor dies from each other by dicing the semiconductor substrate into individual semiconductor dies; positioning the semiconductor dies above die pads of a unit lead frame of a lead frame array, the unit lead frame... The device has leads spaced apart from the die pads and arranged for electrical connection; the semiconductor die is mounted to the die pads using die attachment epoxy resin extending into the cavity of the back surface of the semiconductor die, wherein the edge of the back surface contacts the device-side surface of the die pad; an electrical connection is formed between the bonding pads on the semiconductor die and the leads of the unit lead frame; portions of the semiconductor die, the electrical connection, and the unit lead frame are covered with molding compound forming a body for a microelectronic device package, and portions of the leads of the unit lead frame are exposed from the molding compound to form terminals for the microelectronic device package; and the unit lead frames are separated from each other and from the lead frame array to form individual microelectronic device packages. Attached Figure Description

[0009] Figure 1A-1B Semiconductor wafers and individual semiconductor dies are shown in projected views.

[0010] Figure 2A-2B Examples of microelectronic device package arrangements are shown in top-view projection and cross-sectional views.

[0011] Figure 3A-3G The selected steps for forming the arrangement are illustrated in a series of cross-sectional views.

[0012] Figures 4A-4E Another series of cross-sectional views illustrate selected steps for forming a microelectronic device package in another arrangement.

[0013] Figures 5A-5D The selected steps for forming the additional alternative arrangement are illustrated in additional cross-sectional views.

[0014] Figures 6A-6E Additional details of the layout are shown in the floor plan.

[0015] Figures 7A-7DAlternative arrangements are shown in plan view and corresponding cross-sectional view.

[0016] Figure 8 The selected steps of the method for forming the layout are illustrated in a flowchart.

[0017] Figure 9 Another flowchart illustrates the selected steps of the method for forming an alternative arrangement. Detailed Implementation

[0018] Unless otherwise specified, corresponding labels and symbols in different drawings generally refer to the corresponding parts. Drawings are not necessarily drawn to scale.

[0019] The term "scribe line" is used in this document. A scribe line is the section of a semiconductor wafer between semiconductor dies. The term "dicing line" is sometimes used in related literature. Once processing is complete and the semiconductor device is finished, the semiconductor wafer is cut along the scribe lines, separating the semiconductor device into individual semiconductor dies. The separated dies can then be removed and managed individually for further processing, including packaging. This process of removing dies from the wafer is called "dicing" or sometimes "cutting". The scribe lines are arranged on the four sides of the semiconductor die, and when the dies are diced together, rectangular semiconductor dies are formed.

[0020] This document uses the term "packaging substrate." A packaging substrate is a substrate containing conductive leads arranged to couple to and support a semiconductor die within a semiconductor device package. Examples of packaging substrates that can be used with said arrangement include lead frames, pre-molded lead frames ("PMLF"), molded interconnect substrates ("MIS"), partially etched or half-etched lead frames, and multilayer substrates comprising, for example, additively deposited substrates formed from Ajinomoto stacked film ("ABF"), commercially available from Ajinomoto Co., Inc. in Tokyo, Japan, as well as other laminated substrates. In examples that can be used with said arrangement, the packaging substrate is provided with strips of device units, each arranged to provide leads and support for a semiconductor die to be packaged as a semiconductor device package. It should be noted that although a device cell can be part of a leadframe, the “frame” portion of the leadframe is removed during packaging to separate the individual leads from each other. Therefore, to avoid any misunderstanding or confusion, the term “device cell” is used herein to refer to a single unit of a package substrate strip that contains leads and supports the semiconductor die during packaging and in the semiconductor device package. A package substrate strip can be a leadframe strip with a unit leadframe, but it can also be a molded interconnect substrate strip, a layable leadframe strip, or other substrate strips used for packaging semiconductor devices.

[0021] The term "microelectronic device package" is used in this document. A microelectronic device package is a package that provides protection for one or more devices, which may contain semiconductor dies, several semiconductor dies, or passive components such as diodes, capacitors, resistors, inductors, transformers, coils, and sensors. Semiconductor dies may be mounted to a package substrate and may be spaced apart from each other or stacked vertically. In some instances, passive components may be integrated within the semiconductor die or may be in a discrete package mounted together with the semiconductor die to form a packaged device within a package. A semiconductor device package containing a single semiconductor die is also a microelectronic device package. In the example arrangement, a quad flat no-lead (QFN) package is described. QFN packages are increasingly used for microelectronic device packaging. A QFN package has terminals exposed from a molding compound that forms the protective body of the package on the board-side surface for mounting to a system board or module. The quad flat no-lead package has terminals on four sides. The terminals extend approximately along the sides of the package body, thus reducing the board area required to mount the QFN package (compared to a "leaded" microelectronic device package where the terminals extend away from the package body). Other package types can be used with this arrangement, such as dual in-line packages ("DIP") with leads extending from two sides, quad plastic packages with leads extending from four sides, and other leadless packages with exposed terminals for mounting, for example, on only two board-side surfaces of the package.

[0022] This document uses the term "cut track". A cut track is a region on a packaging substrate between semiconductor device packages that provides space for sawing between the semiconductor device packages.

[0023] The components are described as “coupled” in this document. As used herein, the term “coupled” includes components that are directly connected, and even components that are electrically connected by intermediate components or wires are considered coupled.

[0024] The term "semiconductor die" is used in this document. A semiconductor die can be a discrete semiconductor device, such as a bipolar transistor, a plurality of discrete devices, such as a pair of power field-effect transistor (FET) switches fabricated together on a single semiconductor die, or an integrated circuit having multiple semiconductor devices in a circuit (e.g., multiple capacitors in an A / D converter). A semiconductor die can contain passive devices such as resistors, inductors, and filters, or active devices such as transistors. A semiconductor die can be an integrated circuit having hundreds or thousands of transistors coupled to form functional circuitry such as a microprocessor or memory semiconductor device. A semiconductor die can be a passive device such as a sensor, example of a sensor comprising a photovoltaic cell, transducer, and charge-coupled device (CCD), or a micromechanical device such as a digital micromirror device (DMD) or a microelectromechanical system (MEMS) device.

[0025] This document uses the term "underbonding." In wire-bonded packaging, "underbonding" refers to the bonding wire connection between bonding pads on the device-side surface of a semiconductor die and die pads, forming the bonding wire connection rather than forming an electrical connection to the package leads. In an example arrangement, underbonding connections are formed between semiconductor dies and die pads, or between semiconductor dies and power rails in the package substrate. One advantage of using this arrangement compared to existing methods is that die-attach epoxy will not be present in the wire-bonding area on the die pads or penetrate into the area where the underbonding connection will be formed. The advantages of this arrangement include improved underbonding reliability in wire-bonded microelectronic device packages.

[0026] exist Figure 1A In the diagram, a semiconductor substrate (which is a semiconductor wafer 101) is shown as an array of semiconductor dies 105 arranged in rows and columns. The semiconductor dies 105 can be formed using manufacturing processes in a semiconductor manufacturing facility (sometimes referred to as a "wafer fab"), which may include ion implantation for carrier doping of the semiconductor substrate, annealing, oxidation, dielectric and conductor deposition, photolithography, patterning, etching, chemical mechanical polishing (CMP), electroplating, via formation, and other processes used in the manufacture of semiconductor devices. During the manufacturing process, devices (not shown for clarity) are formed on the device-side surface of the semiconductor dies 105. Cleaves 103 and 104, perpendicular to each other and extending in parallel across the semiconductor substrate wafer 101, separate the rows and columns of the completed semiconductor dies 105, and cleaves 103 and 104 provide areas for dicing the wafer to separate the semiconductor dies 105 from each other.

[0027] Figure 1B Show from a projected view Figure 1A The semiconductor die 105 is a single semiconductor die 105 of the semiconductor wafer 101, wherein bonding pads 102 are on the device-side surface, and the bonding pads 102 are conductive pads electrically coupled to a device (not shown for simplicity) formed in the semiconductor die 105. The semiconductor die 105 can be separated from the semiconductor wafer 101 by wafer dicing, and is referred to as "dicing" each other using cleavage ridges 103, 104 (see See [link to documentation]). Figure 1A ).

[0028] A dicing process can be used to cut the die 105 from the semiconductor wafer 101. Mechanical sawing can be used. Plasma cutting can also be used. Plasma cutting requires a significantly smaller minimum kerf width than laser cutting or mechanical sawing, thus increasing the number of semiconductor dies that can be formed on a single semiconductor wafer and increasing yield, thereby reducing unit cost. However, other types of wafer cutting can be used with the arrangement, including laser cutting. The sides of the semiconductor die 105 may have varying appearances depending on the type of cutting used. When plasma cutting is used, the sides of the material etched during plasma cutting may have a “scalloped” appearance due to the repetitive process used, as further described below. Laser cutting can produce stress lines or cracks that will appear on the sides of the cut semiconductor die. Mechanical cutting using a rotary saw blade can leave polished features or saw marks along the sides of the semiconductor die after cutting.

[0029] Figure 1B The semiconductor die 105 is shown having bonding pads 102 ready for wire bonding. The bonding pads 102 are fabricated to be electrically connected to conductive leads of the package substrate by forming wire bonds. Wire bonds can be formed using bonding wires that bond to the bonding pads 102 and couple the bonding pads to conductive portions of the leads, such as lead frames, of the package substrate.

[0030] Figure 2A A microelectronic device package is shown in a projected view, illustrating an example arrangement. Figure 2B Shown in cross-sectional view Figure 2A Packaging of microelectronic devices.

[0031] exist Figure 2A In the image, a microelectronic device package 100 is shown in a projected view taken from the top side surface. The microelectronic device package 100 is a QFN type package. A molding compound 123 forms the package body, which covers and protects at least one semiconductor die (in...). Figure 2A Not visible in the text, but see [link / reference] Figure 2B The semiconductor die 105 and the leads from the semiconductor die to the package substrate form an electrical connection. In the illustrated example, the leads of the package substrate are partially covered by molding compound 123, wherein the exposed surfaces of the leads form terminals 144. Terminals 144 have surfaces exposed on at least one board-side surface of the microelectronic device package 100. Terminals 144 can be used to mount a device to a board or module using surface mount technology (“SMT”), which uses solder to form physical and electrical connections between the microelectronic device package terminals 144 and conductive platforms on the board or module.

[0032] Figure 2B Shown in cross-sectional view Figure 2A 100 microelectronic device packages. Figure 2B In this example, at least one semiconductor die 105 is shown mounted to a package substrate 111, which is a conductive lead frame in this arrangement. In addition to... Figure 2B In addition to the example arrangement with a single semiconductor die shown, in alternative arrangements, additional passive components or additional semiconductor dies may also be mounted in the microelectronic device package 100.

[0033] Semiconductor die 105 is shown attached to die pad 142 of package substrate 111 via die attachment material 108. In this arrangement, die attachment material 108 may be epoxy resin, which is placed in a cavity 141 extending into the back surface of semiconductor die 105. Die attachment material 108 contacts the interior of cavity 141 and the device-side surface of die pad 142. Cavity 141 has a side extending from the back surface into semiconductor die and has an inner bottom surface. Die attachment epoxy resin 108 is contained by each side of cavity 141 in semiconductor die 105 such that during die mounting processes that mount semiconductor die 105 to die pad 142 of package substrate 111, die attachment epoxy resin 108 does not seep onto die pad 142 outside the area of ​​semiconductor die 105. In one method of forming the arrangement, individual semiconductor dies 105 having cavities 141 are mounted to die pads 142 using die attachment epoxy previously deposited on die pads 142, the cavities 141 containing die attachment epoxy 108 during mounting. The die attachment epoxy 108 has a back-side surface that is coplanar with the edge of the device-side surface of the semiconductor die 105 surrounding the cavity 141. In another method, the arrangement is formed in a wafer-level process, wherein cavities on the back side of semiconductor dies on a semiconductor wafer are filled with Class B die attachment epoxy at the wafer processing stage, and then the semiconductor dies are diced from the semiconductor wafer, each semiconductor die containing die attachment epoxy in a back-side cavity, and then the semiconductor dies are mounted to die pads of a packaging substrate using Class B die attachment epoxy.

[0034] Return to Figure 2B The electrical connection (in this example, wire bond 158) is shown attached to the bonding pad 102 via solder ball bond 160. In an alternative arrangement, a ribbon bond can be used to form the electrical connection. For example, a protective dielectric layer such as polyimide (PI) 156 covers the device-side surface of the semiconductor die 105, while the bonding pad 102 is exposed from the PI layer 156. The wire bond 158 extends to and is electrically connected to the device-side surface 146 of the terminal 144. A molding compound 123 covers the electrical connection 158, wherein the terminal 144 has at least one board-side surface exposed from the molding compound 123.

[0035] The arrangement retains the die attachment epoxy 108 within the area of ​​the semiconductor die 105. This advantageously allows for the use of the same packaging substrate or a common leadframe design for various microelectronic device packages to mount different semiconductor dies, reducing the number of leadframe designs required to support packages with multiple semiconductor dies. One advantage provided by this arrangement is that the packaging substrate design can be reused for various semiconductor die sizes. Reusing the packaging substrate design for different semiconductor dies reduces the need to manufacture, test, and store many different packaging substrates; in fact, various semiconductor dies can be mounted on the same leadframe design, thereby reducing costs.

[0036] Figure 3A-3G A series of cross-sectional views illustrate selected steps that can be used to form the instance arrangement. Figure 3A The image shows a semiconductor wafer 301 in a back-side etching process. In an example etching process that can be used with the arrangement described, the semiconductor wafer 301 is first processed in a front-end process within a wafer fabrication facility to form a device on the device-side surface (not shown for simplicity). Figure 3A The image shows a semiconductor wafer 301 in a back-side plasma etching process. The semiconductor wafer 301 has a photoresist layer 343 applied to its back-side surface. In one example process that can be used with the arrangement, the photoresist 343 may be a dry film layer. The photoresist 343 has been patterned to define an exposed area corresponding to a cavity 341, which is shown extending into the back-side surface of each of a plurality of semiconductor dies formed on the semiconductor wafer 301. In an example semiconductor plasma etching process that can be used with the arrangement, the Bosch plasma etching process can be used. Because plasma etching processes tend to be anisotropic, the Bosch process was developed to be able to form etch openings with more or less vertical sides. In the Bosch process, the gas used in the plasma chamber is varied to alternately deposit protective material and perform plasma etching, such that as the etch openings deepen into the semiconductor wafer in repeated etch cycles, the sidewalls are protected to maintain a vertical shape by depositing material between etch cycles. In the repeated process, the opening is deepened, with each side of the etched cavity remaining more or less vertical (the back side surface is shown in the figure as being horizontally oriented compared to the back side surface). Due to the repeated cycles of protective material deposition and wafer etching, each side of the cavity 341 formed in the Bosch process may have scalloped sidewalls (not visible in the figure).

[0037] Figure 3B Showing applications Figure 3AThe photoresist removal step for the components. After plasma etching is complete, a photoresist removal process, such as a dry film photoresist stripping step, can be used to remove the photoresist 343 from the wafer. Alternative photoresist removal processes that can be used include plasma ashing to remove the photoresist 343. Figures 3A-3B The plasma etching process forms cavities 341 in the back side of semiconductor dies 3051, 3053, 3055, etc., formed in the semiconductor wafer 301. The semiconductor wafer 301 may have dozens, hundreds, or even thousands of semiconductor dies arranged in rows and columns (see, for example...). Figure 1A (and semiconductor dies 105 disposed on semiconductor wafer 101). In the arrangement, cavities (e.g., one of cavities 341) are formed on the back surface of each of semiconductor dies 3051, 3053, etc.

[0038] Figure 3C Another cross-sectional view shows the process after the additional process steps. Figure 3B Components. In Figure 3C In the design, semiconductor wafer 301 has a front surface mounted to a back-side polishing belt 345, which supports and stabilizes the semiconductor wafer 301 while exposing the back-side surface for further processing. Cavity 341 is shown on the back-side surface.

[0039] Figure 3D Another cross-sectional view illustrates the additional processing steps. The back-side grinding process is used to thin the semiconductor wafer 301 by removing a portion of it from the back side. In an example process that can be used to form an arrangement, a mechanical grinding tool 385 can be used to remove semiconductor material. The cavity 341 then becomes shallower as the back side of the semiconductor wafer 301 is processed. The depth of the cavity 341 can be further controlled by controlling the amount of wafer thinning used.

[0040] Figure 3E Another cross-sectional view shows the semiconductor wafer 301 after being mounted to the dicing tape 350 on the back side. Figure 3D The component. The dicing tape 350 can be disposed in a frame or mounting component 352 that supports the dicing tape 350. The back-side grinding tape 345 is shown being removed from the device side of the semiconductor wafer 301.

[0041] Figure 3F Another cross-sectional view shows the process during the wafer dicing operation. Figure 3EThe components. A mechanical saw blade 360 ​​is shown cutting through semiconductor dies (e.g., 3051) formed in rows and columns on a semiconductor wafer 301. Semiconductor dies such as semiconductor die 3051 have cavities 341 extending into the back side. A cutting band 350 supports and holds the semiconductor dies, such as semiconductor die 3051, during and after the saw blade 360 ​​passes through the kerf in the semiconductor wafer 301. A frame 352 may support the cutting band 350. Alternative methods for wafer cutting may be used with the arrangement, such as plasma cutting or laser cutting. The sides of semiconductor dies 3051, 3053, etc., will have different surface coatings depending on the type of cut used to cleave the wafer. A rotary mechanical saw blade may leave abrasive marks on each side, while a plasma cutting tool may leave scalloped sides as described above.

[0042] Figure 3G Shown in Figure 3F The illustrated single semiconductor die 305 is obtained from semiconductor wafer 301 after the die-cutting process. Semiconductor die 305 has a cavity 341 extending into its back surface. The cavity 341 has sidewalls on four sides, such that when the semiconductor die 305 is subsequently mounted to a package substrate using die attachment material, the die attachment material can be contained within the cavity 341. Therefore, these arrangements prevent epoxy resin leakage problems that can occur when using existing die mounting methods. The semiconductor die 305 has an edge 351 surrounding the cavity 341 on its back surface.

[0043] Figures 4A-4E Another series of cross-sectional views illustrate the steps that can be used to form a microelectronic device package using semiconductor dies arranged as described.

[0044] exist Figure 4A The cross-sectional view shows a unit portion of the package substrate 311. In this illustrated example, a conductive lead frame is used for the package substrate 311, which has die pads 342 and leads 344 spaced apart from the die pads 342. Die-attach epoxy 380 is shown deposited on the device-side surface of the die pads 342. In one method that can be used with the arrangement described, a needle applicator can be used to deposit the die-attach epoxy 380. On-demand drop or inkjet printing applicators can be used. A stencil can be used. Depending on the application, the die-attach epoxy 380 can be an electrical conductor or an electrical insulator. In the example arrangement, a commercially available die-attach epoxy, as well as other die-attach epoxys, can be used. Brand names that can be used with the aforementioned arrangement include LOCTITE® AbelStik bare die-attach epoxy resin, which is commercially available from Henkel, and other similar commercially available bare die-attach epoxy resins.

[0045] Figure 4B Another cross-sectional view shows the results after additional processing. Figure 4A The encapsulation substrate and die shown are attached with epoxy resin material. Figure 4B In the diagram, the component is shown as a semiconductor die 305 mounted to die pads 342 using die attachment epoxy 380. A cavity 341 in the semiconductor die 305 surrounds and accommodates the die attachment epoxy 380. An edge 351 on the back side of the semiconductor die 305 is in direct contact with the die pads 342 and is free of die attachment epoxy 380. This arrangement advantageously prevents die attachment epoxy 380 from seeping onto the surface of the die pads 342, thereby keeping the surface of the die pads 342 outside the area of ​​the semiconductor die 305 available for wire bonding connections, thus preventing defects that may occur when mounting conventional die mounting processes and conventional method dies formed without this arrangement. The use of a cavity on the back side of the semiconductor die in this arrangement advantageously prevents these defects.

[0046] Figure 4C Another cross-sectional view shows the process after the in-line bonding process. Figure 4B The component. Bond wire 358 is shown forming a line bond connection between the device-side surface of semiconductor die 305 and package substrate 311. Bond wire 358 forms a connection to lead 344. In an example arrangement, additional bond wire 359 forms a lower bond connection between semiconductor die 305 and die pad 342. In some example arrangements, die pad 342 may be used as a ground plane or may be placed at another potential. Bond wire 359 couples the bond pads on semiconductor die 305 to the die pads, and thus to the potential. Because the use of cavities in the semiconductor die in the arrangement prevents die-attach epoxy 380 from seeping onto the device-side surface of die pad 342 in areas outside the area of ​​semiconductor die 305, the lower bond connection to die pad 342 formed by bond wire 359 is unaffected by the die-attach epoxy. In existing packaging processes, die-attach epoxy can "bleed" into the wire bonding area of ​​the die pads and can cause non-stick ("NSOL") wire bonding defects. Unlike these existing packaging processes, the arrangement described above advantageously reduces or eliminates these problems by containing die-attach epoxy during the die mounting process.

[0047] Figure 4D This is shown after additional processing steps. Figure 4C Another additional cross-sectional view of the component. In Figure 4DIn this design, molding compound 323 is shown formed over a portion of the package substrate 311, over the semiconductor die 305, and over bonding wires 358 and 359 to form a protective body for a microelectronic device package. In example molding processes that can be used with this arrangement, transfer molding can be used. In a transfer molding process, the molding compound (e.g., epoxy molding compound) is provided in solid form at room temperature, either in spheres or as powder. The molding compound is heated to a liquid state in a pot within a molding tool. Hydraulic pressure is used to force the molding compound through channels into a mold surrounding the package substrate, the semiconductor die, and the bonding wires. Molding compound 323 can be a thermosetting material that transforms into a solid state. Epoxy molding compounds can be used. After removal of the molded device from the molding tool, a sawing operation can separate the device, which can be provided in strip, array, or grid form, and the saw can cut through the package substrate (which may be, for example, a copper lead frame) and the molding compound in sawing passes between the unit devices to cut the completed microelectronic device package devices into individual units.

[0048] Figure 4E Another cross-sectional view is shown in Figure 4D The microelectronic device package 300 is formed after a single-chopping process is performed on the packaging substrate 311. The microelectronic device package 300 is a quad flat no-lead (QFN) package. Figure 4E In this embodiment, a microelectronic device package 300 can be formed by sawing a package substrate 311 along a sawing path between unit devices. The sawing operation cuts through the molding compound and package substrate material; in this example, a copper lead frame can be used to form individual microelectronic device packages. A semiconductor die 305 is shown mounted to a die pad 342 via a die attachment epoxy 380. The edge 351 of the back surface of the semiconductor die 305 surrounding the die cavity is in direct contact with the die pad 342 and is not in contact with the die attachment epoxy 380. The die attachment epoxy 380 has a back surface coplanar with the device-side surface of the edge 351 of the back surface of the semiconductor die 305. Bonding wires 358 are shown as leads 344 coupling the semiconductor die to the package substrate 311, and bonding wires 359 form a lower bonding connection to the die pad 342 (note that in...). Figure 4C-4E In the cross-section, the lower bonding connection is not visible. The arrangement allows the die-attach epoxy 380 to be housed within the cavity of the semiconductor die 305, ensuring that no die-attach epoxy is present on the device-side surface of the die pads 342 outside the cavity in the semiconductor die 305. This arrangement eliminates lead non-bonding defects and interference with the wire bonding process that can occur with conventional die mounting methods.

[0049] Figures 5A-5D A series of cross-sectional images illustrate alternative methods for forming arrangements using wafer-level die attachment deposition processes. Figure 5AIn this diagram, a semiconductor wafer 501 is shown mounted on a back-side polishing belt 545 for support. A polishing tool 551 is shown, which can be used to remove material from the semiconductor wafer 501 from the back-side surface. Grade B die-attach epoxy 509 is shown deposited in a cavity on the back-side surface of the semiconductor wafer 501. The Grade B die-attach epoxy has two curing steps. Because the Grade B die-attach material can be partially cured in an initial deposition step and then subsequently cured to a final stage, the material can be deposited and stabilized in a first process step, and then the Grade B epoxy allows for additional processing in a later stage, thus allowing for a change in the order of steps used to assemble the assembly. Figure 5A In the example shown, the use of Class B die-attachment epoxy 509 allows die-attachment deposition across the entire wafer prior to wafer dicing. For example, die-attachment material 509 can be deposited using pin deposition, screen printing, stenciling, or drop-on-demand processes. A first curing step can be performed to stabilize the die-attachment material 509 for further processing. Class B die-attachment epoxy that can be used with the arrangement is commercially available from Henkel and other suppliers. In some formulations, Class B die-attachment epoxy can be cured in a first curing stage by thermosetting or UV curing, and die bonding can be completed using a final thermosetting step after die mounting.

[0050] Figure 5B This shows semiconductor wafer 501 after further processing. Figure 5B In the image, the back surface of the semiconductor wafer 501 is shown facing down and mounted in a frame 552 with a dicing tape 550 in preparation for wafer dicing. A back-side polishing tape 545 is shown being removed from the device-side surface of the semiconductor wafer 501 during a de-taping process.

[0051] Figure 5C Another cross-sectional view shows the result after additional processing. Figure 5B Components. In Figure 5C The image shows a wafer dicing process used to cut individual semiconductor dies from semiconductor wafer 501. A dicing saw 560 cuts along the scribe line (…). Figure 5C Not shown in the text, but see [link / reference]. Figure 1A The dicing lines 103 and 104 are shown on the semiconductor wafer 101 (between semiconductor dies 105) while simultaneously cutting through the semiconductor wafer 501. The semiconductor die has a die attachment epoxy resin 509 in a cavity on the back surface.

[0052] Figure 5D Another cross-sectional view shows the source Figure 5CThe semiconductor wafer 501 is mounted onto an individual semiconductor die 505 on a packaging substrate 311. The packaging substrate 311 may be a conductive lead frame, such as a copper lead frame. A Class B die attachment epoxy resin 509 is used to mount the semiconductor die 505. The Class B die attachment epoxy resin 509 can be thermosetting to bond the semiconductor die 505 to the die pad 342, thereby completing the process of mounting the semiconductor die 505 onto the packaging substrate 311. After the die mounting process, the semiconductor die 505 and the packaging substrate 311 are ready to be mounted, for example, as described above. Figure 4C , Figure 4D and Figure 4E The process shown involves wire bonding, molding, and packaging dicing to complete the packaging of microelectronic devices.

[0053] This is different from attaching the bare die to the individual cells deposited on the packaging substrate (as mentioned above). Figures 4A-4B Compared to the previously described arrangement, the use of Class B die attachment epoxy 509 in this alternative arrangement allows for die attachment epoxy application at the wafer level. Any of these methods can be used to form microelectronic device packages using the aforementioned arrangement, wherein the semiconductor die has cavities on its back-side surface to accommodate die attachment material, thereby achieving the advantages of the aforementioned arrangement.

[0054] Figures 6A-6B The cross-sectional view illustrates details of an alternative arrangement using multiple cavities extending into the back surface of a semiconductor die. Figure 6C-6E An alternative arrangement with vents extending from the dorsal cavity is shown in an additional cross-sectional view.

[0055] exist Figure 6A In this study, the die mounting operation is shown as part of a process for forming an alternative arrangement. Depending on the die size, cavity size, and the properties of the die attachment material used, air may be trapped in the back cavity during die mounting in some instances, resulting in voids. Figures 6A-6B The example arrangement shown reduces the likelihood of air forming cavities in the bare die attachment material within the back cavity, thereby reducing or eliminating the possibility of voids. Figure 6A In this embodiment, semiconductor die 605 is shown having a plurality of cavities 641 formed and extending into the back surface. For example, by using Figures 3A-3DThe plasma etching cavity formation process shown can be used to form these cavities 641 using a plasma etching process applied to the back side of a semiconductor wafer. The cavity side can have a scallop-shaped shape formed by the plasma etching process (not shown for clarity). By patterning multiple cavities extending into the back surface of the semiconductor die, the volume of each cavity is reduced, which eliminates or reduces the possibility of air forming pits during die mounting operations. The surface area of ​​the semiconductor die material contacting the die to attach the epoxy resin is increased, thereby increasing adhesion, while the volume of the individual, now smaller cavities is reduced. Figure 6A In the image, semiconductor die 605 is shown as a device mounting surface facing die pad 342 of a package substrate 311, which may be, for example, a copper lead frame. Die attachment epoxy 680 is shown deposited on the die pad 342 in preparation for die mounting.

[0056] Figure 6B Another cross-sectional view shows the process after die mounting. Figure 6A The semiconductor die 605 is shown as a device mounting surface of die pads 342 on a package substrate 311, wherein die attachment epoxy 680 fills multiple cavities on the back side of the semiconductor die 605. An edge 651 of the back side surface of the semiconductor die 605 contacts the device side surface of the die pads 342 on the package substrate 311, and the die attachment epoxy 380 is not present on the die pads 342 outside the area covered by the semiconductor die 605. The use of this arrangement reduces or eliminates any epoxy outside the cavity area in the semiconductor die. By using this arrangement, epoxy bleed-out that may occur in conventional die mounting processes can be reduced or eliminated.

[0057] Figure 6C-6E Another alternative arrangement is shown in three views. Figure 6C In the cross-sectional view, a semiconductor die 606 is shown, wherein die attachment epoxy 680 mounts the semiconductor die 606 to die pads 342 of a package substrate 311. The semiconductor die 606 includes vent holes 683. Vent holes 683 can be formed in cavities (see example...) Figure 3B During the plasma etching process of cavity 341, an open trench is formed on the back side of the semiconductor die. Vent hole 683 may be formed by a trench in the back surface of semiconductor die 606, and then the trench is covered by the device side of die pad 342 when semiconductor die 606 is mounted.

[0058] Figure 6D-6E Shown in side and bottom views Figure 6C Additional details regarding the arrangement. The 606 semiconductor die in... Figure 6DThe image shows a side view of the vent 683. A bottom view of the semiconductor die 606 is also shown. Figure 6E The diagram is shown in (for clarity, in...). Figure 6E The packaging substrate 311 is omitted in the figure, wherein the vent 683 is shown as a trench extending from the periphery of the semiconductor die 606 to the cavity 641.

[0059] Through Figure 6C-6E The arrangement provides vents extending into cavity 641, during which the die is attached to epoxy resin (see [reference]). Figure 6C 680 in the middle) can fill the cavity (see Figure 6E The cavity 641 is provided, and during the die mounting process, any air can be expelled from the cavity through the vent 683. After the die attachment epoxy has cured and the die mounting process is completed, the vent 683 is sealed at the end of the cavity by the cured die attachment epoxy and can be filled with die attachment epoxy.

[0060] Figures 7A-7D Additional details of the instance layout are shown in the floor plan and side view. Figure 7A In the diagram, a package substrate 711 (which may be a copper lead frame) is shown in plan view from the device side, with leads 744 spaced apart from die pads 742. Power rails 743 surround and are spaced apart from the die pads 742. A semiconductor die 705 is shown mounted to the device-side surface of the die pads 742. Die attachment epoxy 780 is shown in dashed lines because it is located within the back cavity of the semiconductor die and is housed within the area of ​​the semiconductor die 705. Bond wires 758 couple the bonding pads of the semiconductor die 705 (not shown for simplicity) to the leads 744 of the package substrate. Additional lower bonding wire connections couple the semiconductor die 705 to the die pads 742 and the power rails 743. Bond wire 759 connects the semiconductor die 705 to the die pads 742. Bond wire 768 connects the semiconductor die 705 to the power rails 743. In a typical application, die pad 742 can be coupled to a potential such as ground. Power ring 743 can be coupled to another potential, such as a power supply potential. Semiconductor die 705 can be, for example, a power device that couples high-current signals to an output. Multiple bond wire connections, such as 759 and 768, can be made to provide low-resistance connections from power supply and / or ground to semiconductor die 705.

[0061] Figure 7B Shown in side view Figure 7AThe components are shown. The package substrate 711 is shown having leads 744. The die pad 742 is shown having a semiconductor die 705 mounted to the device-side surface of the die pad 742 via die attachment epoxy 780. A wire bond connection 758 connects the semiconductor die 705 to the leads 744. A wire bond connection 759 is shown coupling the semiconductor die 705 to the die pad 742, thereby forming a lower bonding connection. A wire bond connection 768 is shown coupling the semiconductor die 705 to a power rail. Using this arrangement, the die attachment epoxy 780 is contained within a back-side cavity in the semiconductor die 705, and the die attachment epoxy does not leak into the wire bonding area of ​​the die pad 742. In stark contrast to existing methods for mounting semiconductor dies, these arrangements reduce the total area required for die pads 742 to ensure that the lower bonding wire bonding connections are not adversely affected by the die-attached epoxy.

[0062] Figure 7C The additional layout is shown in the floor plan. Figure 7C In the middle, the packaging substrate 711 and Figure 7A The same packaging substrate is used in this arrangement. The advantage of using a semiconductor die with a back-side cavity in this arrangement is that the same packaging substrate design can be used with semiconductor dies of various sizes. Because conventional die attachment processes require a margin between the wire bonding area (“forbidden zone”) reserved for the underbonding to the die pads and the area where conventional die attachment epoxy may diffuse during die mounting, this is not required when using this arrangement. Therefore, the same leadframe can be used to mount dies of various sizes and for different pin outputs without modification. Using a common leadframe for multiple applications reduces costs, decreases leadframe inventory and design time, and simplifies fabrication.

[0063] exist Figure 7C In the package, the substrate 711, lead 744, die pad 742, and power rail 743 are for mounting the semiconductor die 706 ( Figure 7C (as shown) and the smaller semiconductor die 705 ( Figures 7A-7B (As shown) are all the same. Semiconductor dies all include a back-side cavity that contains die-attach epoxy resin during the die mounting process, thereby eliminating the epoxy resin bleeding problem found in existing methods of mounting dies using die-attach epoxy resin.

[0064] Figure 7D Shown in side view Figure 7CThe arrangement shown is illustrated. The package substrate 711 is shown having leads 744, die pads 742, and power rings 743. The semiconductor die 706 is shown mounted to the device side of the package substrate 711 using die attachment epoxy 781. During die mounting, the die attachment epoxy 781 is contained within a cavity in the back side of the semiconductor die 706, and the use of this arrangement prevents epoxy leakage, thereby allowing reliable underbonding to the die pads 742.

[0065] Figure 8 A flowchart illustrates a method for forming an arrangement of microelectronic device packages. The method begins at step 801, where a semiconductor die is formed on a device-side surface of a semiconductor substrate having a back-side surface opposite the device-side surface. (See, for example, [link to relevant documentation]). Figure 1A-1B The semiconductor substrate wafer 101 has semiconductor dies 105 formed in rows and columns on the device-side surface.

[0066] The method continues at step 803, forming a cavity extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die. (See example) Figures 3A-3B (Where cavity 341 is formed in the back side of semiconductor substrate 301.)

[0067] The method then continues at step 805, wherein the semiconductor dies are separated from each other by dicing the semiconductor substrate into individual semiconductor dies. (See example) Figure 3E-3G (In this process, semiconductor die 305 is cut from semiconductor substrate 301).

[0068] At step 807, the method continues by applying die attachment epoxy to the die pads of the unit lead frames on the lead frame array, the unit lead frames having leads spaced apart from the die pads and arranged for electrical connection. (See, for example) Figure 4A The die-attachment epoxy resin 380 is applied to the packaging substrate 311 on the device side of the die pad 342.

[0069] At step 809, the method continues by positioning the semiconductor die above the die pads of the cell lead frame. At step 811, the method continues by mounting the semiconductor die onto the die pads using die attachment epoxy, which is positioned within a cavity extending into the back surface of the semiconductor die, wherein the edge of the back surface contacts the device-side surface of the die pads. (See, for example, [reference needed]) Figure 4BIn this embodiment, a semiconductor die 305 is mounted to a packaging substrate 311, and a die pad 342 is shown having a die attachment epoxy 380 within a cavity on the back side of the semiconductor die 305. An edge 351 of the semiconductor die 305 is shown contacting the die pad 342.

[0070] At step 813, the method continues by forming an electrical connection between the bonding pads on the semiconductor die and the leads of the lead frame. (See, for example, [link to relevant documentation]). Figure 4C Bonding wires 358 and 359 are located between semiconductor die 305 and lead 344.

[0071] At step 815, the method continues by covering portions of the semiconductor die, electrical connections, and cell lead frames with molding compound, which forms the body for a microelectronic device package, and portions of the leads are exposed from the molding compound to form terminals for the microelectronic device package. (See, for example) Figure 4D The molding compound 323 covers a portion of the semiconductor die, electrical connections, and packaging substrate 311, wherein terminals 344 are exposed on the plate-side surface of the molding compound 323.

[0072] At step 817, the method is accomplished by separating the unit lead frames from each other and from the lead frame array to form individual microelectronic device packages. (See, for example) Figure 4E This illustrates a microelectronic device package 500 after the lead frame and molding compound have been cut and separated to cut the package into individual pieces.

[0073] Figure 9 An alternative method for forming the arrangement is illustrated in another flowchart. Figure 9 As described above, the method uses wafer-level die attachment deposition instead of attaching the die to the package substrate after the semiconductor die has been cut from the semiconductor substrate.

[0074] exist Figure 9 In this method, the process begins at step 901, where a semiconductor die is formed on the device-side surface of a semiconductor substrate, the semiconductor substrate having a back-side surface opposite to the device-side surface. (See example...) Figure 1A-1B (where the semiconductor die 105 is cut from the semiconductor substrate 101).

[0075] At step 903, the method forms a cavity extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die. (See example) Figure 3B-3C (wherein cavity 341 is formed in semiconductor substrate 301).

[0076] At step 905, the method continues by applying die-attachment epoxy resin into a cavity on the back surface of the semiconductor substrate, the die-attachment epoxy resin being accommodated within the cavity, and the edges of the back surface of the semiconductor die not having die-attachment epoxy resin. (See, for example) Figure 5A In this example, the die-attachment epoxy resin 509 is shown as deposited in a cavity on the back side of the semiconductor substrate 501.

[0077] At step 907, the method continues by separating the semiconductor dies from each other by cutting the semiconductor substrate into individual semiconductor dies. (See example) Figure 5C The example shows blade 560 being used to separate a semiconductor die from a semiconductor substrate 501.

[0078] At step 909, the method continues by positioning the semiconductor die above the die pads of the unit lead frames of the lead frame array, the unit lead frames having leads spaced apart from the die pads and arranged for electrical connection. At step 911, the method continues by mounting the semiconductor die to the die pads using die attachment epoxy in a cavity extending into the back surface of the semiconductor die, wherein the edge of the back surface contacts the device-side surface of the die pad. (See, for example...) Figure 5D (The semiconductor die 505 is shown as a die pad 342 mounted on the package substrate 311.)

[0079] At step 913, the method continues by forming an electrical connection between the bonding pads on the semiconductor die and the leads of the unit lead frame. (See example...) Figure 4C The bonding wires 358 and 359 are shown in the example.

[0080] At step 915, the method continues by covering portions of the semiconductor die, electrical connections, and cell lead frame with molding compound, the molding compound forming the body for a microelectronic device package, and portions of the leads of the cell lead frame exposed from the molding compound to form terminals for the microelectronic device package. (See also...) Figure 4D (Among them, molding compound 323 is shown).

[0081] At step 917, Figure 9 The method shown is accomplished by separating the unit lead frames from each other and from the lead frame array to form individual microelectronic device packages.

[0082] The use of a back-side cavity in the semiconductor die arrangement advantageously prevents the die attachment epoxy from "bleeding" and interfering with the lower bonding connections on the die pads by containing the epoxy. By using this arrangement, the area required for wire bonding connections from the outside of the semiconductor die to the die pad surface is reduced because the die attachment epoxy is completely contained and does not seep into areas where wire bonding might occur, thus reducing or eliminating the need for a buffer zone between the die mounting area and the wire bonding area. Because the die attachment epoxy is contained within the semiconductor die area, the package substrate design can be used with both large and small semiconductor dies without modifying the die pad design, thereby reducing the need for custom package substrate designs for each semiconductor die. Using the back-side cavity of this arrangement to contain the die attachment epoxy allows the arrangement to be used without modifying existing dicing, dicing, and wire bonding tools, thereby reducing the cost of adopting this arrangement in the packaging process.

[0083] With careful consideration, modifications and variations can be made to the described arrangement, and other alternative arrangements within the scope of the claims are possible.

Claims

1. An apparatus comprising: At least one semiconductor die is mounted on a die pad of a package substrate, the at least one semiconductor die having a device-side surface and an opposing back-side surface, the at least one semiconductor die having a cavity extending into the back-side surface and having an edge surrounding the cavity on the back-side surface; A die attachment material that bonds the at least one semiconductor die to the die pad, the die attachment material being positioned within a cavity extending into the back side surface, the die attachment material contacting the inner surface of the cavity and the die pad, the edge of the at least one semiconductor die surrounding the cavity directly contacting the device side surface of the die pad, wherein the back side surface of the die attachment material is coplanar with a plane truncated along the edge of the at least one semiconductor die; An electrical connection is provided between a bonding pad on the device-side surface of the at least one semiconductor die and a lead formed in the device-side layer of the package substrate, the lead having a terminal portion and a board-side surface. as well as A molding compound covering a portion of the at least one semiconductor die, the electrical connection, and the packaging substrate, while the board-side surface of the terminals is exposed from the molding compound, the molding compound forming the body of a microelectronic device package for the at least one semiconductor die.

2. The device of claim 1, wherein the microelectronic device package comprises a quad flat no-lead QFN microelectronic device package having terminals on each of the four sides.

3. The device according to claim 1, wherein the electrical connection is a wire-bonded connection.

4. The device of claim 3, further comprising the at least one semiconductor die covering a portion of the die pad of the package substrate, wherein a portion of the device-side surface of the die pad is outside the portion covered by the at least one semiconductor die, and at least one lower bonding electrical connection is located between a bonding pad on the at least one semiconductor die and the device-side surface of the die pad.

5. The device according to claim 1, wherein the packaging substrate is a copper lead frame.

6. The device according to claim 1, wherein the die attachment material is conductive die attachment epoxy resin.

7. The device of claim 1, wherein the die attachment material is a non-conductive die attachment epoxy resin.

8. The device according to claim 1, wherein the electrical connection is a copper bonding wire.

9. The device according to claim 1, wherein the microelectronic device package is a quad flat no-lead package.

10. The device of claim 1, wherein the electrical connection is a wire bond connection, and the device further comprises the at least one semiconductor die covering a portion of the die pad of the package substrate, and a portion of the device-side surface of the die pad is outside the portion covered by the at least one semiconductor die, and at least one lower bond electrical connection is located between the bonding pad on the at least one semiconductor die and the device-side surface of the die pad.

11. The device of claim 10, further comprising the package substrate having power rails surrounding and spaced apart from the die pads, and additional wire bonding connections, the additional wire bonding connections being lower bonding connections between bonding pads on the at least one semiconductor die and the power rails.

12. The device of claim 1, wherein the cavity further comprises a plurality of die cavities, each die cavity receiving a portion of the die attachment material.

13. The device of claim 1, wherein the cavity has a sidewall extending from the back surface into the semiconductor die, and the sidewall has a scalloped side.

14. The device of claim 1, wherein the at least one semiconductor die has sides extending between the device side surface and the back side surface, the sides having a scalloped shape.

15. The device of claim 1, wherein the at least one semiconductor die has sides extending between the device side surface and the back side surface, the sides having stress lines formed during laser cutting.

16. The device of claim 1, wherein the at least one semiconductor die has sides extending between the device side surface and the back side surface, each side having a polished surface formed by mechanical cutting by a rotating blade.

17. A method comprising: A semiconductor die is formed on the device-side surface of a semiconductor substrate, the semiconductor substrate having a back-side surface opposite to the device-side surface; A cavity is formed extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die; The semiconductor wafers are separated from each other by cutting the semiconductor substrate into individual semiconductor wafers; A bare die attachment epoxy resin is applied to the bare die pads of a unit lead frame on a lead frame array, the unit lead frame having leads spaced apart from the bare die pads, the leads being arranged for electrical connection. Position the semiconductor die above the die pad of the unit lead frame; The semiconductor die is mounted onto the die pad using the die attachment epoxy resin, the die attachment epoxy resin being positioned within and in contact with the surface of the cavity of the semiconductor die and the device-side surface of the die pad, wherein the edge of the back surface of the semiconductor die is in direct contact with the device-side surface of the die pad. An electrical connection is formed between the bonding pads on the semiconductor die and the leads of the unit lead frame; A portion of the semiconductor die, the electrical connection, and the unit lead frame is covered with a molding compound that forms the body for a microelectronic device package, and portions of the leads are exposed from the molding compound to form terminals for the microelectronic device package. as well as The unit lead frames are separated from each other and from the lead frame array to form individual microelectronic device packages.

18. The method of claim 17, wherein forming the cavity extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die, further comprises performing plasma etching on the back surface of the semiconductor substrate.

19. The method of claim 18, wherein the plasma etching comprises a Bosch process.

20. The method of claim 17, wherein forming an electrical connection further comprises forming a wire bond between the bonding pads of the semiconductor die and the leads of the unit lead frame.

21. The method of claim 20, further comprising having a portion of the die pad of the unit lead frame covered by the semiconductor die, and another portion of the die pad outside the portion covered by the semiconductor die, and forming a lower bonding line bonding connection between the bonding pad on the semiconductor die and the other portion of the die pad.

22. The method of claim 21, further comprising forming an additional lower bonding wire bonding connection between another bonding pad on the semiconductor die and a power rail of the unit lead frame, the power rail being spaced apart from and surrounding the die pad.

23. The method of claim 17, wherein the die-attached epoxy is a conductive die-attached epoxy.

24. The method of claim 17, wherein the die-attached epoxy is a non-conductive die-attached epoxy.

25. The method of claim 17, wherein after mounting the semiconductor die, the edge of the back surface of the semiconductor die is free of die-attached epoxy resin, and the edge of the back surface directly contacts the device-side surface of the die pad.

26. A method comprising: A semiconductor die is formed on the device-side surface of a semiconductor substrate, the semiconductor substrate having a back-side surface opposite to the device-side surface; A cavity is formed extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die; A die-attachment epoxy resin is applied to a cavity on the back surface of the semiconductor substrate, the die-attachment epoxy resin is contained within the cavity, and the edge of the back surface of the semiconductor die is not covered by the die-attachment epoxy resin. The semiconductor wafers are separated from each other by cutting the semiconductor substrate into individual semiconductor wafers; The semiconductor die is positioned above the die pad of a unit lead frame of a lead frame array, the unit lead frame having leads spaced apart from the die pad and arranged for electrical connection. The semiconductor die is mounted to the die pad by using the die attachment epoxy resin in the cavity extending into the back side surface of the semiconductor die, wherein the edge of the back side surface contacts the device side surface of the die pad. An electrical connection is formed between the bonding pads on the semiconductor die and the leads of the unit lead frame; A molding compound is used to cover portions of the semiconductor die, the electrical connection, and the unit lead frame, the molding compound forming a body for a microelectronic device package, and portions of the leads of the unit lead frame are exposed from the molding compound to form terminals for the microelectronic device package. as well as The unit lead frames are separated from each other and from the lead frame array to form individual microelectronic device packages.

27. The method of claim 26, wherein applying the die-attachment epoxy resin to the cavity on the back side surface of the semiconductor substrate further comprises applying a Class B die-attachment epoxy resin and performing a first curing to solidify the Class B die-attachment epoxy resin.

28. The method of claim 27, wherein the die attachment epoxy is used in the cavity extending into the back surface of the semiconductor die, wherein the edge of the back surface contacts the device-side surface of the die pad, further comprising performing a second curing of the Class B die attachment epoxy to mount the semiconductor die to the die pad.

29. The method of claim 27, wherein forming a cavity extending into the back surface of the semiconductor substrate, the cavity extending into the back surface of the semiconductor die and surrounded by the edge of the back surface of the semiconductor die, further comprising performing plasma etching on the back surface of the semiconductor substrate, the cavity having sidewalls extending into the back surface of the semiconductor substrate, the sidewalls having a scalloped shape on each side.

30. The method of claim 29, wherein performing plasma etching further comprises performing a Bosch process.

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