Display substrate and display device

Abstract

A display substrate and a display device are disclosed. The display substrate includes a substrate and a driving module disposed on the substrate. The driving module includes a multi-stage driving circuit. The driving circuit includes multiple devices, each including multiple transistors and at least one capacitor. The display substrate also includes multiple signal lines disposed on the substrate, including at least three clock signal lines and at least two first voltage lines. The orthographic projection of the signal lines on the substrate at least partially overlaps with the orthographic projection of at least one device on the substrate. By increasing the number of clock signal lines, the load on the clock signal lines is reduced, thereby improving and regulating the output capability of the driving circuit.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] With the development of intelligent display devices, consumers have higher and higher requirements for the display devices in terms of picture quality, power consumption and the like. Therefore, it is important to improve the picture quality and endurance of the display devices, and improving and optimizing the driving circuit is one of the directions. For example, reducing the loading of the clock signal line, improving the output capability of the driving circuit buffer tube through voltage adjustment, improving the stability of the output, and the like can improve the comprehensive performance of the display device.

[0003] SUMMARY

[0004] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a substrate and a driving module disposed on the substrate, the driving module includes a multi-stage driving circuit; the driving circuit includes a plurality of devices, the plurality of devices include a plurality of transistors and at least one capacitor; the display substrate further includes a plurality of signal lines disposed on the substrate, the plurality of signal lines include at least three clock signal lines and at least two first voltage lines.

[0005] The orthographic projection of the signal line on the substrate at least partially overlaps the orthographic projection of the at least one device on the substrate.

[0006] In at least one embodiment of the present disclosure, the driving circuit includes a driving output circuit.

[0007] The driving output circuit is electrically connected with a first node, a first first voltage line and a driving output terminal respectively, and is configured to control the driving output terminal to be in communication or disconnected with the first first voltage line under the control of the potential of the first node.

[0008] The active pattern of at least one transistor included in the driving output circuit at least partially overlaps the orthographic projection of the first first voltage line on the substrate.

[0009] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit and a second node control circuit.

[0010] The first node control circuit is electrically connected with a first clock signal line, the first node and a second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of a first clock signal provided by the first clock signal line.

[0011] The second node control circuit is electrically connected with the first clock signal line, the second node and a third node respectively, and is configured to control an electric potential of the second node according to a first clock signal provided by the first clock signal line under control of an electric potential of the third node, and control the electric potential of the second node according to the electric potential of the third node.

[0012] The second node control circuit includes at least one capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the first clock signal line on the substrate.

[0013] In at least one embodiment of the present disclosure, the first node control circuit includes at least one transistor, and an active pattern of the transistor on the substrate at least partially overlaps a projection of the second clock signal line on the substrate.

[0014] The second node control circuit includes at least one transistor, and an active pattern of the transistor on the substrate at least partially overlaps a projection of the second clock signal line on the substrate.

[0015] In at least one embodiment of the present disclosure, the first node control circuit includes a first transistor, and a gate of the first transistor is electrically connected with the first clock signal line.

[0016] The gate of the first transistor is electrically connected with a first connection pattern, the first connection pattern is electrically connected with a second connection pattern, the first connection pattern and the second connection pattern are arranged in different layers, the second connection pattern is arranged in a layer different from the first clock signal line, and the second connection pattern is electrically connected with the first clock signal line.

[0017] In at least one embodiment of the present disclosure, the second node control circuit includes a first capacitor.

[0018] The plate of the first capacitor on the substrate at least partially overlaps a projection of the second connection pattern on the substrate, and the plate of the first capacitor on the substrate at least partially overlaps a projection of the first clock signal line on the substrate.

[0019] In at least one embodiment of the present disclosure, the second first voltage line is arranged between the second clock signal line and the first clock signal line.

[0020] The second first voltage line, the second clock signal line and the first clock signal line are arranged in the same layer.

[0021] In at least one embodiment of the present disclosure, the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node.

[0022] The active pattern of at least one transistor included in the first node control circuit has a projection on the substrate that at least partially overlaps a projection of the second clock signal line on the substrate.

[0023] In at least one embodiment of the present disclosure, the drive circuit includes a first node potential maintaining circuit; the first node potential maintaining circuit is configured to maintain the potential of the first node.

[0024] The first node potential maintaining circuit includes a second capacitor; a projection of a plate of the second capacitor on the substrate at least partially overlaps a projection of a third clock signal line on the substrate.

[0025] The display substrate according to at least one embodiment of the present disclosure further includes a first second voltage line and a second second voltage line disposed on the substrate; the drive circuit includes a third node control circuit and a fifth node control circuit.

[0026] The third node control circuit is electrically connected with the second second voltage line, the third node and the fifth node respectively, and is configured to control the potential of the third node according to the potential of the fifth node under the control of a voltage signal provided by the second second voltage line.

[0027] The fifth node control circuit is electrically connected with a fourth clock signal line, a fourth node and a fifth node respectively, and is configured to control the potential of the fifth node according to a fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node.

[0028] The active pattern of at least one transistor included in the third node control circuit has a projection on the substrate that at least partially overlaps a projection of the fourth clock signal line on the substrate.

[0029] The active pattern of at least one transistor included in the fifth node control circuit has a projection on the substrate that at least partially overlaps a projection of the fourth clock signal line on the substrate.

[0030] The display substrate according to at least one embodiment of the present disclosure further includes a first second voltage line and a second second voltage line disposed on the substrate.

[0031] The drive circuit further includes a fourth node control circuit and a seventh node control circuit.

[0032] The fourth node control circuit is electrically connected with an input terminal, a third clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input terminal into the fourth node under the control of a third clock signal provided by the third clock signal line.

[0033] The seventh node control circuit is electrically connected with the second second voltage line, the fourth node and the seventh node respectively, and is configured to control the potential of the seventh node according to the potential of the fourth node under the control of a voltage signal provided by the second second voltage line.

[0034] The active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the orthogonal projection of the fourth clock signal line on the substrate.

[0035] The active pattern of at least one transistor included in the seventh node control circuit at least partially overlaps the orthogonal projection of the fourth clock signal line on the substrate.

[0036] In at least one embodiment of the present disclosure, the active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the orthogonal projection of the fourth clock signal line on the substrate.

[0037] The active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the orthogonal projection of the fourth clock signal line on the substrate.

[0038] In at least one embodiment of the present disclosure, the driving circuit includes a fifth node control circuit; the fifth node control circuit is electrically connected with the fifth node, the third clock signal line and the second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the fifth node under the control of a third clock signal provided by the third clock signal line.

[0039] The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the orthogonal projection of the second second voltage line on the substrate and the orthogonal projection of the fourth clock signal line on the substrate.

[0040] In at least one embodiment of the present disclosure, the driving circuit includes a sixth node control circuit;

[0041] The sixth node control circuit is electrically connected with the sixth node, the first first voltage line, the fifth node, the second clock signal line and the seventh node respectively, and is configured to write a second clock signal provided by the second clock signal line into the sixth node under the control of the potential of the seventh node, and write a voltage signal provided by the first first voltage line into the sixth node under the control of the potential of the fifth node.

[0042] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0043] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0044] The display substrate also includes a seventh node control circuit in at least one embodiment of the present disclosure; the seventh node control circuit is electrically connected with the sixth node and the seventh node respectively, and is used for controlling an electric potential of the seventh node according to an electric potential of the sixth node.

[0045] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0046] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0047] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0048] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0049] In at least one embodiment of the present disclosure, the drive circuit includes an output reset circuit; and the plurality of signal lines further include a first second voltage line.

[0050] The output reset circuit is electrically connected with the seventh node, a drive output terminal and the first second voltage line respectively, and is used for writing a voltage signal provided by the first second voltage line into the drive output terminal under control of an electric potential of the seventh node.

[0051] A positive projection of an active pattern of at least one transistor included in the output reset circuit on the substrate at least partially overlaps a positive projection of the first first voltage line on the substrate.

[0052] In at least one embodiment of the present disclosure, the first second voltage line is arranged on a side of a transistor included in the output reset circuit close to a display area; and no other transistor or capacitor is arranged between the first second voltage line and the transistor included in the output reset circuit.

[0053] In at least one embodiment of the present disclosure, the drive circuit includes a first node control circuit.

[0054] The first node control circuit is electrically connected with the fourth clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of a fourth clock signal provided by the fourth clock signal line.

[0055] The active pattern of at least one transistor included in the first node control circuit at least partially overlaps the projection of the second clock signal line on the substrate.

[0056] In at least one embodiment of the present disclosure, the first node control circuit includes a first transistor, and the gate of the first transistor is electrically connected with the fourth clock signal line.

[0057] The gate of the first transistor is electrically connected with a first connection pattern, the first connection pattern is electrically connected with a second connection pattern, the first connection pattern and the second connection pattern are arranged in different layers, the second connection pattern is arranged in a layer different from the fourth clock signal line, and the second connection pattern is electrically connected with the fourth clock signal line.

[0058] In at least one embodiment of the present disclosure, the driving circuit includes a fifth node control circuit.

[0059] The fifth node control circuit is electrically connected with the fourth clock signal line, the fourth node and the fifth node respectively, and is configured to control the potential of the fifth node according to the fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node.

[0060] The active pattern of a transistor included in the fifth node control circuit at least partially overlaps the projection of the fourth clock signal line on the substrate.

[0061] The second connection pattern is electrically connected with the fourth clock signal line through a first via hole.

[0062] The projection of the boundary of the first via hole on the substrate does not overlap the projection of the channel of a transistor included in the fifth node control circuit on the substrate.

[0063] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit and a second node control circuit.

[0064] The first node control circuit is electrically connected with the second clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of a second clock signal provided by the second clock signal line.

[0065] The second node control circuit is electrically connected with the second clock signal line, the second node and a third node respectively, and is configured to control an electric potential of the second node according to a second clock signal provided by the second clock signal line under control of an electric potential of the third node, and control the electric potential of the second node according to the electric potential of the third node.

[0066] The second node control circuit includes at least one capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the second first voltage line on the substrate.

[0067] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; and the first node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps a projection of the control line on the substrate.

[0068] In at least one embodiment of the present disclosure, the driving circuit includes a fourth node control circuit; and the plurality of signal lines further include a control line.

[0069] The fourth node control circuit is electrically connected with the control line, the second first voltage line and a fourth node respectively, and is configured to write a voltage signal provided by the second first voltage line into the fourth node under control of a control signal provided by the control line.

[0070] The fourth node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps a projection of the control line on the substrate.

[0071] The fourth node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps a projection of the first clock signal line on the substrate.

[0072] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; and the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node.

[0073] The first node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps a projection of the control line on the substrate.

[0074] In at least one embodiment of the present disclosure, the driving circuit includes a first node electric potential maintaining circuit; and the first node electric potential maintaining circuit is configured to maintain an electric potential of the first node.

[0075] The first node potential maintaining circuit includes a second capacitor; a positive projection of a plate of the second capacitor on the substrate at least partially overlaps a positive projection of a fourth clock signal line on the substrate;

[0076] A positive projection of a part of the plate of the second capacitor on the substrate is arranged between a positive projection of a first clock signal line on the substrate and a positive projection of the fourth clock signal line on the substrate.

[0077] In at least one embodiment of the present disclosure, the driving circuit includes a third node control circuit and a fifth node control circuit;

[0078] The third node control circuit is electrically connected with a first second voltage line, the third node and the fifth node respectively, and is configured to control the potential of the third node according to the potential of the fifth node under the control of a voltage signal provided by the first second voltage line;

[0079] The fifth node control circuit is electrically connected with a third clock signal line, a fourth node and a fifth node respectively, and is configured to control the potential of the fifth node according to a third clock signal provided by the third clock signal line under the control of the potential of the fourth node;

[0080] A positive projection of an active pattern of at least one transistor included in the third node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate;

[0081] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate.

[0082] In at least one embodiment of the present disclosure, the driving circuit further includes a fourth node control circuit and a seventh node control circuit;

[0083] The fourth node control circuit is electrically connected with an input terminal, a fourth clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input terminal into the fourth node under the control of a fourth clock signal provided by the fourth clock signal line;

[0084] The seventh node control circuit is electrically connected with a first second voltage line, the fourth node and a seventh node respectively, and is configured to control the potential of the seventh node according to the potential of the fourth node under the control of a voltage signal provided by the first second voltage line;

[0085] A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of a second clock signal line on the substrate;

[0086] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0087] In at least one embodiment of the present disclosure, the driving circuit includes a fifth node control circuit; the fifth node control circuit is electrically connected with a fifth node, a fourth clock signal line and a first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the fifth node under control of a fourth clock signal provided by the fourth clock signal line.

[0088] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0089] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; the driving circuit includes a sixth node control circuit.

[0090] The sixth node control circuit is electrically connected with a sixth node, a first first voltage line, a fifth node, a first clock signal line and a seventh node respectively, and is configured to write a first clock signal provided by the first clock signal line into the sixth node under control of a potential of the seventh node, and write a voltage signal provided by the first first voltage line into the sixth node under control of a potential of the fifth node.

[0091] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0092] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

[0093] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; the driving circuit further includes a seventh node control circuit; the seventh node control circuit is electrically connected with a sixth node and a fifth node respectively, and is configured to control a potential of the seventh node according to a potential of the sixth node.

[0094] A positive projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate.

[0095] A positive projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of a second first voltage line on the substrate.

[0096] A positive projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

[0097] A positive projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0098] In at least one embodiment of the present disclosure, the driving circuit includes an output reset circuit; and the display substrate further includes a second second voltage line.

[0099] The output reset circuit is electrically connected with the seventh node, the driving output end and the second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the driving output end under control of a potential of the seventh node.

[0100] A positive projection of an active pattern of at least one transistor included in the driving output circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0101] A positive projection of an active pattern of at least one transistor included in the output reset circuit on the substrate at least partially overlaps a positive projection of the first first voltage line on the substrate.

[0102] A positive projection of an active pattern of at least one transistor included in the output reset circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0103] In at least one embodiment of the present disclosure, the driving circuit includes a driving output circuit; the plurality of signal lines include a first first voltage line, the first first voltage line includes a first voltage line part and a second voltage line part, the first voltage line part and the second voltage line part both extend along a first direction; and the plurality of signal lines further include a first second voltage line.

[0104] The driving output circuit is electrically connected with the first node, the first first voltage line and the driving output end respectively, and is configured to control the driving output end to be in communication or disconnected with the first first voltage line under control of a potential of the first node.

[0105] A positive projection of an active pattern of at least one transistor included in the driving output circuit on the substrate at least partially overlaps a positive projection of the first voltage line part on the substrate.

[0106] A positive projection of an active pattern of at least one transistor included in the driving output circuit on the substrate at least partially overlaps a positive projection of the first second voltage line on the substrate.

[0107] In at least one embodiment of the present disclosure, the driving circuit comprises an output reset circuit;

[0108] The output reset circuit is electrically connected with the seventh node, the driving output end and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the driving output end under the control of the potential of the seventh node;

[0109] The active pattern of at least one transistor included in the output reset circuit at least partially overlaps the active pattern of at least one transistor included in the first node control circuit on the substrate;

[0110] The active pattern of at least one transistor included in the output reset circuit at least partially overlaps the active pattern of at least one transistor included in the first node control circuit on the substrate.

[0111] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit and a second node control circuit;

[0112] The first node control circuit is electrically connected with the first clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of a first clock signal provided by the first clock signal line;

[0113] The second node control circuit is electrically connected with the first clock signal line, the second node and the third node respectively, and is configured to control the potential of the second node according to the first clock signal provided by the first clock signal line under the control of the potential of the third node, and control the potential of the second node according to the potential of the third node;

[0114] The active pattern of at least one capacitor included in the second node control circuit at least partially overlaps the active pattern of at least one capacitor included in the third node control circuit on the substrate;

[0115] The active pattern of at least one capacitor included in the second node control circuit at least partially overlaps the active pattern of at least one capacitor included in the third node control circuit on the substrate.

[0116] In at least one embodiment of the present disclosure, the plurality of signal lines further comprise a control line;

[0117] At least part of the active pattern of at least one transistor included in the first node control circuit is arranged between the active pattern of the control line on the substrate and the active pattern of the second voltage line on the substrate;

[0118] A positive projection of an active pattern of at least one transistor included in the second node control circuit on the substrate at least partially overlaps a positive projection of the second first voltage line on the substrate.

[0119] In at least one embodiment of the present disclosure, the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node.

[0120] A positive projection of an active pattern of at least one transistor included in the first node control circuit on the substrate is at least partially arranged between a positive projection of the second first voltage line on the substrate and a positive projection of the control line on the substrate.

[0121] In at least one embodiment of the present disclosure, the driving circuit includes a first node electric potential maintaining circuit; the first node electric potential maintaining circuit is configured to maintain an electric potential of the first node.

[0122] The first node electric potential maintaining circuit includes a second capacitor; a positive projection of a plate of the second capacitor on the substrate at least partially overlaps a positive projection of the second voltage line part on the substrate.

[0123] In at least one embodiment of the present disclosure, the driving circuit includes a third node control circuit and a fifth node control circuit.

[0124] The third node control circuit is electrically connected with a second second voltage line, the third node and the fifth node respectively, and is configured to control an electric potential of the third node according to an electric potential of the fifth node under control of a voltage signal provided by the second second voltage line.

[0125] The fifth node control circuit is electrically connected with a fourth clock signal line, a fourth node and a fifth node respectively, and is configured to control an electric potential of the fifth node according to a fourth clock signal provided by the fourth clock signal line under control of an electric potential of the fourth node.

[0126] A positive projection of an active pattern of at least one transistor included in the third node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0127] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0128] The display substrate in at least one embodiment of the present disclosure further includes a first second voltage line and a second second voltage line arranged on the substrate.

[0129] The driving circuit further comprises a fourth node control circuit and a seventh node control circuit;

[0130] The fourth node control circuit is electrically connected with an input end, a third clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input end into the fourth node under control of a third clock signal provided by the third clock signal line;

[0131] The seventh node control circuit is electrically connected with a second second voltage line, the fourth node and a seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the fourth node under control of a voltage signal provided by the second second voltage line;

[0132] The active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the orthogonal projection of the fourth clock signal line on the substrate;

[0133] The active pattern of at least one transistor included in the seventh node control circuit at least partially overlaps the orthogonal projection of the second first voltage line on the substrate.

[0134] In at least one embodiment of the present disclosure, the driving circuit comprises a fifth node control circuit; the fifth node control circuit is electrically connected with a fifth node, a third clock signal line and a second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the fifth node under control of a third clock signal provided by the third clock signal line;

[0135] The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the orthogonal projection of the first clock signal line on the substrate.

[0136] In at least one embodiment of the present disclosure, the driving circuit comprises a sixth node control circuit;

[0137] The sixth node control circuit is electrically connected with a sixth node, a second first voltage line, a fifth node, a second clock signal line and an eighth node respectively, and is configured to write a second clock signal provided by the second clock signal line into the sixth node under control of a potential of the eighth node, and write a voltage signal provided by the second first voltage line into the sixth node under control of a potential of the fifth node;

[0138] The active pattern of at least one transistor included in the sixth node control circuit at least partially overlaps the orthogonal projection of the third clock signal line on the substrate.

[0139] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0140] The display substrate also includes an eighth node control circuit in at least one embodiment of the present disclosure. The eighth node control circuit is electrically connected to the sixth node and the eighth node, respectively, and is configured to control a potential of the eighth node according to a potential of the sixth node. The plurality of signal lines also includes a first second voltage line.

[0141] A positive projection of a plate of a capacitor included in the eighth node control circuit on the substrate at least partially overlaps a positive projection of the second second voltage line on the substrate.

[0142] A positive projection of a plate of a capacitor included in the eighth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0143] A positive projection of a plate of a capacitor included in the eighth node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate.

[0144] A positive projection of a plate of a capacitor included in the eighth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0145] In at least one embodiment of the present disclosure, the driving circuit includes a fourth node control circuit. The plurality of signal lines also includes a control line.

[0146] The fourth node control circuit is electrically connected to the control line, a second first voltage line, and a fourth node, respectively, and is configured to write a voltage signal provided by the second first voltage line into the fourth node under control of a control signal provided by the control line.

[0147] At least a part of an active pattern of at least one transistor included in the fourth node control circuit is disposed between a positive projection of the second first voltage line on the substrate and a positive projection of the control line on the substrate.

[0148] In at least one embodiment of the present disclosure, the driving circuit also includes an input control circuit.

[0149] The input control circuit is electrically connected to an input terminal, a third clock signal line, a second second voltage line, a ninth node, and an eighth node, respectively, and is configured to write an input signal provided by the input terminal into the ninth node under control of a third clock signal provided by the third clock signal line, and control communication between the ninth node and the eighth node under control of a voltage signal provided by the second second voltage line.

[0150] A positive projection of an active pattern of at least one transistor included in the input control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0151] A positive projection of an active pattern of at least one transistor included in the input control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0152] In at least one embodiment of the present disclosure, the driving circuit further includes a seventh node voltage control circuit.

[0153] The seventh node voltage control circuit is electrically connected with an eighth node and the seventh node respectively, and is configured to control an electric potential of the seventh node according to an electric potential of the eighth node.

[0154] A positive projection of at least one transistor included in the seventh node voltage control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate.

[0155] A positive projection of at least one transistor included in the seventh node voltage control circuit on the substrate at least partially overlaps a positive projection of the second first voltage line on the substrate.

[0156] In at least one embodiment of the present disclosure, the driving circuit includes an output reset circuit.

[0157] The output reset circuit is electrically connected with the seventh node, a driving output terminal and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the driving output terminal under control of an electric potential of the seventh node.

[0158] The output reset circuit includes a second transistor.

[0159] A gate of the second transistor is electrically connected with a first conductive pattern, a first electrode of the second transistor is electrically connected with the first second voltage line, and a second electrode of the second transistor is electrically connected with the driving output terminal through a second conductive pattern.

[0160] A positive projection of the first conductive pattern on the substrate at least partially overlaps a positive projection of the second conductive pattern on the substrate, and the first conductive pattern and the second conductive pattern are arranged in different layers.

[0161] In a second aspect, embodiments of the present disclosure provide a display device including the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0162] FIG. 1A and FIG. 1B are structural diagrams of at least one embodiment of a driving circuit in at least one embodiment of the present disclosure.

[0163] FIG. 2A and FIG. 2B are circuit diagrams of at least one embodiment of the driving circuit;

[0164] FIG. 2C is a timing diagram of the clock signal provided by CK1 in FIG. 2A, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in at least one embodiment of the present disclosure;

[0165] FIG. 2D is a timing diagram of the clock signal provided by CK1 in FIG. 2A, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in at least one embodiment of the present disclosure;

[0166] FIG. 2E is a timing diagram of the clock signal provided by CK1 in FIG. 2A, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in at least one embodiment of the present disclosure;

[0167] FIG. 3 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0168] FIG. 4 is a layout diagram of a semiconductor layer in FIG. 3;

[0169] FIG. 5 is a layout diagram of a first gate metal layer in FIG. 3;

[0170] FIG. 6 is a layout diagram of a second gate metal layer in FIG. 3;

[0171] FIG. 7 is a layout of a first source-drain metal layer in FIG. 3;

[0172] FIG. 8 is a layout diagram of a second source-drain metal layer in FIG. 3;

[0173] FIG. 9 is a layout diagram of a semiconductor layer and a first gate metal layer in FIG. 3;

[0174] FIG. 10 is a layout diagram of a first gate metal layer and a second gate metal layer in FIG. 3;

[0175] FIG. 11 is a layout diagram of a second gate metal layer and a first source-drain metal layer in FIG. 3;

[0176] FIG. 12 is a layout diagram of a first source-drain metal layer and a second source-drain metal layer in FIG. 3;

[0177] FIG. 13 is a circuit diagram of at least one embodiment of the driving circuit;

[0178] FIG. 14 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure;

[0179] FIG. 15 is a layout diagram of a semiconductor layer in FIG. 14;

[0180] FIG. 16 is a layout diagram of a first gate metal layer in FIG. 14;

[0181] FIG. 17 is a layout view of the second gate metal layer in FIG. 14;

[0182] FIG. 18 is a layout view of the first source-drain metal layer in FIG. 14;

[0183] FIG. 19 is a layout view of the second source-drain metal layer in FIG. 14;

[0184] FIG. 20 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 14;

[0185] FIG. 21 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 14;

[0186] FIG. 22 is a cross-sectional view of the first gate metal layer and the first source-drain metal layer in FIG. 14;

[0187] FIG. 23 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer in FIG. 14;

[0188] FIG. 24 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer in FIG. 14;

[0189] FIG. 25A and FIG. 25B are structural diagrams of at least one embodiment of a driving circuit in at least one embodiment of the present disclosure;

[0190] FIG. 26A and FIG. 26B are circuit diagrams of at least one embodiment of the driving circuit;

[0191] FIG. 26C is a timing diagram of a clock signal provided by CK1, a clock signal provided by CK2, a clock signal provided by CK3, and a clock signal provided by CK4 in FIG. 26A in at least one embodiment of the present disclosure;

[0192] FIG. 26D is a timing diagram of a clock signal provided by CK1, a clock signal provided by CK2, a clock signal provided by CK3, and a clock signal provided by CK4 in FIG. 26A in at least one embodiment of the present disclosure;

[0193] FIG. 26E is a timing diagram of a clock signal provided by CK1, a clock signal provided by CK2, a clock signal provided by CK3, and a clock signal provided by CK4 in FIG. 26A in at least one embodiment of the present disclosure;

[0194] FIG. 27 is a layout view of a display substrate in at least one embodiment of the present disclosure;

[0195] FIG. 28 is a layout view of a semiconductor layer in FIG. 27;

[0196] FIG. 29 is a layout view of a first gate metal layer in FIG. 27;

[0197] FIG. 30 is a layout view of a second gate metal layer in FIG. 27;

[0198] FIG. 31 is a layout view of the first source-drain metal layer in FIG. 27;

[0199] FIG. 32 is a layout view of the second source-drain metal layer in FIG. 27;

[0200] FIG. 33 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 27;

[0201] FIG. 34 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 27;

[0202] FIG. 35 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer in FIG. 27;

[0203] FIG. 36 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer in FIG. 27;

[0204] FIGS. 37A and 37B are structural diagrams of at least one embodiment of a driving circuit in at least one embodiment of the present disclosure;

[0205] FIGS. 38A and 38B are circuit diagrams of at least one embodiment of the driving circuit;

[0206] FIG. 38C is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A in at least one embodiment of the present disclosure;

[0207] FIG. 38D is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A in at least one embodiment of the present disclosure;

[0208] FIG. 38E is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A in at least one embodiment of the present disclosure;

[0209] FIG. 39 is a layout view of a display substrate in at least one embodiment of the present disclosure;

[0210] FIG. 40 is a layout view of a semiconductor layer in FIG. 39;

[0211] FIG. 41 is a layout view of a first gate metal layer in FIG. 39;

[0212] FIG. 42 is a layout view of a second gate metal layer in FIG. 39;

[0213] FIG. 43 is a layout view of a first source-drain metal layer in FIG. 39;

[0214] FIG. 44 is a layout view of a second source-drain metal layer in FIG. 39;

[0215] FIG. 45 is a cross-sectional view of the semiconductor layer and the first gate metal layer in FIG. 39;

[0216] FIG. 46 is a layout view of the first gate metal layer and the second gate metal layer in FIG. 39;

[0217] FIG. 47 is a cross-sectional view of the second gate metal layer and the first source-drain metal layer in FIG. 39;

[0218] FIG. 48 is a cross-sectional view of the first source-drain metal layer and the second source-drain metal layer in FIG. 39. DETAILED DESCRIPTION

[0219] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0220] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0221] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode can be a drain electrode and the second electrode can be a source electrode; or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0222] The display substrate in the embodiments of the present disclosure includes a substrate and a driving module disposed on the substrate, the driving module includes a multi-stage driving circuit; the driving circuit includes a plurality of devices, the plurality of devices include a plurality of transistors and at least one capacitor; the display substrate further includes a plurality of signal lines disposed on the substrate, the plurality of signal lines include at least three clock signal lines and at least two first voltage lines;

[0223] The orthogonal projection of the signal line on the substrate at least partially overlaps the orthogonal projection of at least one of the devices on the substrate.

[0224] Optionally, the first voltage line can be a high voltage line.

[0225] As shown in FIG. 1A, the driving circuit according to at least one embodiment of the present disclosure includes a driving output circuit 10, a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, a sixth node control circuit 16, a first node potential maintaining circuit 21, a seventh node control circuit 17, and an output reset circuit 20.

[0226] The driving output circuit 10 is electrically connected with a first node N1, a first high voltage line VGH1, and a driving output terminal OT, respectively, and is configured to control the driving output terminal OT to be in communication or disconnected with the first high voltage line VGH1 under the control of the potential of the first node N1.

[0227] The first node control circuit 11 is electrically connected with a third clock signal terminal CK3, the first node N1, and a second node N2, respectively, and is configured to control the potential of the first node N1 according to the potential of the second node N2 under the control of a clock signal provided by the third clock signal terminal CK3.

[0228] The first node control circuit 11 is further electrically connected with a fourth node N4 and a second high voltage line VGH2, respectively, and is configured to control the first node N1 to be in communication with the second high voltage line VGH2 under the control of the potential of the fourth node N4.

[0229] The second node control circuit 12 is electrically connected with the third clock signal terminal CK3, the second node N2, and a third node N3, respectively, and is configured to control the potential of the second node N2 according to the clock signal provided by the third clock signal terminal CK3 under the control of the potential of the third node N3, and to control the potential of the second node N2 according to the potential of the third node N3.

[0230] The third node control circuit 13 is electrically connected with a second low voltage line VGL2, the third node N3, and a fifth node N5, respectively, and is configured to control the potential of the third node N3 according to the potential of the fifth node N5 under the control of a second low voltage signal provided by the second low voltage line VGL2.

[0231] The fifth node control circuit 15 is electrically connected with a first clock signal terminal CK1, the fourth node N4, and the fifth node N5, respectively, and is configured to control the potential of the fifth node N5 according to a first clock signal provided by the first clock signal terminal CK1 under the control of the potential of the fourth node N4.

[0232] The fifth node control circuit 15 is electrically connected with the fifth node N5, the fourth clock signal terminal CK4 and the second low voltage line VGL2 respectively, and is configured to write the second low voltage signal provided by the second low voltage line VGL2 into the fifth node N5 under the control of the clock signal provided by the fourth clock signal line CK4;

[0233] The fourth node control circuit 14 is electrically connected with the input terminal I1, the fourth clock signal terminal CK4 and the fourth node N4 respectively, and is configured to write the input signal provided by the input terminal I1 into the fourth node N4 under the control of the clock signal provided by the fourth clock signal terminal CK4;

[0234] The seventh node control circuit 17 is electrically connected with the second low voltage line VGL2, the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0235] The sixth node control circuit 16 is electrically connected with the sixth node N6, the first high voltage line VGH1, the fifth node N5, the second clock signal terminal CK2 and the seventh node N7 respectively, and is configured to write the clock signal provided by the second clock signal terminal CK2 into the sixth node N6 under the control of the potential of the seventh node N7, and write the first high voltage signal provided by the first high voltage line VGH1 into the sixth node N6 under the control of the potential of the fifth node N5;

[0236] The seventh node control circuit 17 is electrically connected with the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4;

[0237] The first node potential maintaining circuit 21 is configured to maintain the potential of the first node N1;

[0238] The output reset circuit 20 is electrically connected with the seventh node N7, the driving output terminal OT and the first low voltage line VGL1 respectively, and is configured to write the first low voltage signal provided by the first low voltage line VGL1 into the driving output terminal OT under the control of the potential of the seventh node N7.

[0239] As shown in FIG. 1B, the driving circuit includes the driving output circuit 10, the first node control circuit 11, the second node control circuit 12, the third node control circuit 13, the fourth node control circuit 14, the fifth node control circuit 15, the sixth node control circuit 16, the first node potential maintaining circuit 21, the seventh node control circuit 17 and the output reset circuit 20.

[0240] The driving output circuit 10 is electrically connected with the first node N1, the first high voltage line VGH1 and the driving output terminal OT respectively, for controlling the communication or disconnection between the driving output terminal OT and the first high voltage line VGH1 under the control of the potential of the first node N1;

[0241] The first node control circuit 11 is electrically connected with the first clock signal line CLK1, the first node N1 and the second node N2 respectively, for controlling the potential of the first node N1 according to the potential of the second node N2 under the control of the first clock signal provided by the first clock signal line CLK1;

[0242] The first node control circuit 11 is further electrically connected with the fourth node N4 and the second high voltage line VGH2 respectively, for controlling the communication between the first node N1 and the second high voltage line VGH2 under the control of the potential of the fourth node N4;

[0243] The second node control circuit 12 is electrically connected with the first clock signal line CLK1, the second node N2 and the third node N3 respectively, for controlling the potential of the second node N2 according to the first clock signal provided by the first clock signal line CLK1 under the control of the potential of the third node N3, and controlling the potential of the second node N2 according to the potential of the third node N3;

[0244] The third node control circuit 13 is electrically connected with the second low voltage line VGL2, the third node N3 and the fifth node N5 respectively, for controlling the potential of the third node N3 according to the potential of the fifth node N5 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0245] The fifth node control circuit 15 is electrically connected with the fourth clock signal line CLK4, the fourth node N4 and the fifth node N5 respectively, for controlling the potential of the fifth node N5 according to the fourth clock signal provided by the fourth clock signal line CLK4 under the control of the potential of the fourth node N4;

[0246] The fifth node control circuit 15 is further electrically connected with the fifth node N5, the third clock signal line CLK3 and the second low voltage line VGL2 respectively, for writing the second low voltage signal provided by the second low voltage line VGL2 into the fifth node N5 under the control of the third clock signal provided by the third clock signal line CLK3;

[0247] The fourth node control circuit 14 is electrically connected with the input terminal I1, the third clock signal line CLK3 and the fourth node N4 respectively, and is configured to write an input signal provided by the input terminal I1 into the fourth node N4 under the control of a third clock signal provided by the third clock signal line CLK3.

[0248] The seventh node control circuit 17 is electrically connected with the second low voltage line VGL2, the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of a second low voltage signal provided by the second low voltage line VGL2.

[0249] The sixth node control circuit 16 is electrically connected with the sixth node N6, the first high voltage line VGH1, the fifth node N5, the second clock signal line CLK2 and the seventh node N7 respectively, and is configured to write a second clock signal provided by the second clock signal line CLK2 into the sixth node N6 under the control of the potential of the seventh node N7, and write a first high voltage signal provided by the first high voltage line VGH1 into the sixth node N6 under the control of the potential of the fifth node N5.

[0250] The seventh node control circuit 17 is electrically connected with the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4.

[0251] The first node potential maintaining circuit 21 is configured to maintain the potential of the first node N1.

[0252] The output reset circuit 20 is electrically connected with the seventh node N7, the driving output terminal OT and the first low voltage line VGL1 respectively, and is configured to write a first low voltage signal provided by the first low voltage line VGL1 into the driving output terminal OT under the control of the potential of the seventh node N7.

[0253] In at least one embodiment shown in FIG. 1B, on the basis of at least one embodiment shown in FIG. 1A, the first clock signal terminal CK1 is the fourth clock signal line CLK4, the second clock signal terminal CK2 is the second clock signal line CLK2, the third clock signal terminal CK3 is the first clock signal line CLK1, and the fourth clock signal terminal CK4 is the third clock signal line CLK3.

[0254] As shown in FIG. 2A, on the basis of at least one embodiment of the driving circuit shown in FIG. 1A, the first node control circuit includes a first transistor T1 and a third transistor T3; the second node control circuit includes a first capacitor C1 and a fourth transistor T4; and the output reset circuit includes a second transistor T2.

[0255] The gate of the first transistor T1 is electrically connected with a third clock signal terminal CK3, the first electrode of the first transistor T1 is electrically connected with a second node N2, and the second electrode of the first transistor T1 is electrically connected with a first node N1;

[0256] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with a second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node;

[0257] The gate of the second transistor T2 is electrically connected with a seventh node N7, the first electrode of the second transistor T2 is electrically connected with a driving output terminal OT, and the second electrode of the second transistor T2 is electrically connected with a first low voltage line VGL1;

[0258] The first plate of the first capacitor C1 is electrically connected with a third node N3, and the second plate of the first capacitor C1 is electrically connected with the second node N2;

[0259] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the third clock signal terminal CK3, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2;

[0260] The third node control circuit 13 comprises a fifth transistor T5;

[0261] The gate of the T5 is electrically connected with a second low voltage line VGL2, the first electrode of the T5 is electrically connected with a fifth node N5, and the second electrode of the T5 is electrically connected with the third node N3;

[0262] The fourth node control circuit 14 comprises a sixth transistor T6;

[0263] The gate of the T6 is electrically connected with a fourth clock signal terminal CK4, the first electrode of the T6 is electrically connected with an input terminal I1, and the second electrode of the T6 is electrically connected with the fourth node N4;

[0264] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0265] The gate of the T7 is electrically connected with the fourth node N4, the first electrode of the T7 is electrically connected with a first clock signal terminal CK1, and the second electrode of the T7 is electrically connected with the fifth node N5;

[0266] The gate of the T8 is electrically connected with the fourth clock signal terminal CK4, the first electrode of the T8 is electrically connected with the second low voltage line VGL2, and the second electrode of the T8 is electrically connected with the fifth node N5;

[0267] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0268] A gate of the T9 is electrically connected with the fifth node N5, a first electrode of the T9 is electrically connected with the first high voltage line VGH1, and a second electrode of the T9 is electrically connected with the sixth node N6;

[0269] A gate of the T10 is electrically connected with the seventh node N7, a first electrode of the T10 is electrically connected with the sixth node N6, and a second electrode of the T10 is electrically connected with the second clock signal terminal CK2;

[0270] The first node potential maintaining circuit includes a second capacitor C2;

[0271] A first plate of the C2 is electrically connected with the first node N1, and a second plate of the C2 is electrically connected with the first high voltage line VGH1;

[0272] The seventh node control circuit includes an eleventh transistor T11 and a third capacitor C3;

[0273] A gate of the T11 is electrically connected with the second low voltage line VGL2, a first electrode of the T11 is electrically connected with the fourth node N4, and a second electrode of the T11 is electrically connected with the seventh node N7;

[0274] A first plate of the C3 is electrically connected with the sixth node N6, and a second plate of the C3 is electrically connected with the seventh node N7;

[0275] The drive output circuit includes a twelfth transistor T12;

[0276] A gate of the T12 is electrically connected with the first node N1, a first electrode of the T12 is electrically connected with the first high voltage line VGH1, and a second electrode of the T12 is electrically connected with the drive output terminal OT.

[0277] FIG. 2C is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 2A in at least one embodiment of the present disclosure;

[0278] FIG. 2D is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 2A in at least one embodiment of the present disclosure;

[0279] FIG. 2E is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 2A in at least one embodiment of the present disclosure.

[0280] In at least one embodiment of the present disclosure, the drive module can include a multi-stage drive circuit;

[0281] The first clock signal end of the 4a-3 level driving circuit can be electrically connected with the first clock signal line, the second clock signal end of the 4a-3 level driving circuit can be electrically connected with the second clock signal line, the third clock signal end of the 4a-3 level driving circuit can be electrically connected with the third clock signal line, and the fourth clock signal end of the 4a-3 level driving circuit can be electrically connected with the fourth clock signal line.

[0282] The first clock signal end of the 4a-2 level driving circuit can be electrically connected with the second clock signal line, the second clock signal end of the 4a-2 level driving circuit can be electrically connected with the third clock signal line, the third clock signal end of the 4a-2 level driving circuit can be electrically connected with the fourth clock signal line, and the fourth clock signal end of the 4a-2 level driving circuit can be electrically connected with the first clock signal line.

[0283] The first clock signal end of the 4a-1 level driving circuit can be electrically connected with the third clock signal line, the second clock signal end of the 4a-1 level driving circuit can be electrically connected with the fourth clock signal line, the third clock signal end of the 4a-1 level driving circuit can be electrically connected with the first clock signal line, and the fourth clock signal end of the 4a-1 level driving circuit can be electrically connected with the second clock signal line.

[0284] The first clock signal end of the 4a level driving circuit can be electrically connected with the fourth clock signal line, the second clock signal end of the 4a level driving circuit can be electrically connected with the first clock signal line, the third clock signal end of the 4a level driving circuit can be electrically connected with the second clock signal line, and the fourth clock signal end of the 4a level driving circuit can be electrically connected with the third clock signal line.

[0285] a is a positive integer.

[0286] As shown in FIG. 2B, on the basis of at least one embodiment of the driving circuit shown in FIG. 1B, the first node control circuit includes a first transistor T1 and a third transistor T3; the second node control circuit includes a first capacitor C1 and a fourth transistor T4; and the output reset circuit includes a second transistor T2.

[0287] The gate of the first transistor T1 is electrically connected with the first clock signal line CLK1, the first electrode of the first transistor T1 is electrically connected with the second node N2, and the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0288] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with the second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node.

[0289] The gate of the second transistor T2 is electrically connected with the seventh node N7, the first electrode of the second transistor T2 is electrically connected with the driving output end OT, and the second electrode of the second transistor T2 is electrically connected with the first low-voltage line VGL1;

[0290] The first plate of the first capacitor C1 is electrically connected with the third node N3, and the second plate of the first capacitor C1 is electrically connected with the second node N2;

[0291] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the first clock signal line CLK1, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2;

[0292] The third node control circuit 13 comprises a fifth transistor T5;

[0293] The gate of the T5 is electrically connected with the second low-voltage line VGL2, the first electrode of the T5 is electrically connected with the fifth node N5, and the second electrode of the T5 is electrically connected with the third node N3;

[0294] The fourth node control circuit 14 comprises a sixth transistor T6;

[0295] The gate of the T6 is electrically connected with the third clock signal line CLK3, the first electrode of the T6 is electrically connected with the input end I1, and the second electrode of the T6 is electrically connected with the fourth node N4;

[0296] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0297] The gate of the T7 is electrically connected with the fourth node N4, the first electrode of the T7 is electrically connected with the fourth clock signal line CLK4, and the second electrode of the T7 is electrically connected with the fifth node N5;

[0298] The gate of the T8 is electrically connected with the third clock signal line CLK3, the first electrode of the T8 is electrically connected with the second low-voltage line VGL2, and the second electrode of the T8 is electrically connected with the fifth node N5;

[0299] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0300] The gate of the T9 is electrically connected with the fifth node N5, the first electrode of the T9 is electrically connected with the first high-voltage line VGH1, and the second electrode of the T9 is electrically connected with the sixth node N6;

[0301] The gate of the T10 is electrically connected with the seventh node N7, the first electrode of the T10 is electrically connected with the sixth node N6, and the second electrode of the T10 is electrically connected with the second clock signal line CLK2;

[0302] The first node potential maintaining circuit comprises a second capacitor C2;

[0303] a first node N1 of the first plate of C2 is electrically connected, and a second plate of C2 is electrically connected with a first high voltage line VGH1;

[0304] The seventh node control circuit includes an eleventh transistor T11 and a third capacitor C3.

[0305] A gate of T11 is electrically connected with a second low voltage line VGL2, a first electrode of T11 is electrically connected with a fourth node N4, and a second electrode of T11 is electrically connected with a seventh node N7.

[0306] A first plate of C3 is electrically connected with a sixth node N6, and a second plate of C3 is electrically connected with the seventh node N7.

[0307] The drive output circuit includes a twelfth transistor T12.

[0308] A gate of T12 is electrically connected with the first node N1, a first electrode of T12 is electrically connected with the first high voltage line VGH1, and a second electrode of T12 is electrically connected with a drive output terminal OT.

[0309] In at least one embodiment shown in FIG. 2B, on the basis of at least one embodiment shown in FIG. 2A, the first clock signal terminal CK1 is a fourth clock signal line CLK4, the second clock signal terminal CK2 is a second clock signal line CLK2, the third clock signal terminal CK3 is a first clock signal line CLK1, and the fourth clock signal terminal CK4 is a third clock signal line CLK3.

[0310] In at least one embodiment of the present disclosure, the drive circuit includes a drive output circuit.

[0311] The drive output circuit is electrically connected with the first node, the first first voltage line and the drive output terminal respectively, and is used for controlling the drive output terminal to be in communication or disconnected with the first first voltage line under the control of the potential of the first node.

[0312] The active pattern of at least one transistor included in the drive output circuit has a normal projection on the substrate that at least partially overlaps with a normal projection of the first first voltage line on the substrate.

[0313] Optionally, the first first voltage line can be a first high voltage line, and the second first voltage line can be a second high voltage line.

[0314] FIG. 3 is a layout of a display substrate according to at least one embodiment of the present disclosure. In at least one embodiment shown in FIG. 3, the display substrate includes at least one embodiment of the driving circuit shown in FIG. 2B. FIG. 4 is a layout of a semiconductor layer in FIG. 3, FIG. 5 is a layout of a first gate metal layer in FIG. 3, FIG. 6 is a layout of a second gate metal layer in FIG. 3, FIG. 7 is a layout of a first source-drain metal layer in FIG. 3, FIG. 8 is a layout of a second source-drain metal layer in FIG. 3, FIG. 9 is a layout of a semiconductor layer and a first gate metal layer in FIG. 3, FIG. 10 is a layout of a first gate metal layer and a second gate metal layer in FIG. 3, FIG. 11 is a layout of a second gate metal layer and a first source-drain metal layer in FIG. 3, and FIG. 12 is a layout of a first source-drain metal layer and a second source-drain metal layer in FIG. 3.

[0315] At least one embodiment of the display substrate shown in FIG. 3 of the present disclosure can increase the number of clock signal lines to reduce the loading of the clock signal lines, improve and adjust the output capacity of the driving circuit, and change the conventional design of two clock signal lines, one first voltage line and one second voltage line to the design of four clock signal lines, two first voltage lines and two second voltage lines without changing the width of the driving circuit.

[0316] In at least one embodiment of the present disclosure, the first voltage line can be a high voltage line, and the second voltage line can be a low voltage line.

[0317] The design of double high voltage lines and double low voltage lines in the embodiments of the present disclosure can be individually debugged by setting different high voltage signals and different low voltage signals, and the output capacity of the GOA circuit can be improved and adjusted.

[0318] In at least one embodiment of the present disclosure, the line width of the first first voltage line can be the same as the line width of the second first voltage line, or the line width of the first first voltage line can be different from the line width of the second first voltage line.

[0319] The line width of the first second voltage line can be the same as the line width of the second second voltage line, or the line width of the first second voltage line can be different from the line width of the second second voltage line.

[0320] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit and a second node control circuit.

[0321] The first node control circuit is electrically connected to the first clock signal line, the first node and the second node, respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of a first clock signal provided by the first clock signal line.

[0322] The second node control circuit is electrically connected with the first clock signal line, the second node and a third node respectively, and is configured to control an electric potential of the second node according to a first clock signal provided by the first clock signal line under control of an electric potential of the third node, and control the electric potential of the second node according to the electric potential of the third node.

[0323] The second node control circuit includes at least one capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the first clock signal line on the substrate.

[0324] As shown in FIGS. 3-12, the second node control circuit includes a first capacitor C1.

[0325] A projection of a first plate C1a of C1 on the substrate at least partially overlaps a projection of the first clock signal line CLK1 on the substrate.

[0326] A projection of a second plate C1b of C1 on the substrate at least partially overlaps a projection of the first clock signal line CLK1 on the substrate.

[0327] This can save horizontal space and facilitate narrow frame implementation.

[0328] As shown in FIGS. 3-12, C1a is formed in the first gate metal layer, and C1b is formed in the second gate metal layer.

[0329] In at least one embodiment of the present disclosure, a projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a projection of the second clock signal line on the substrate.

[0330] A projection of an active pattern of at least one transistor included in the second node control circuit on the substrate at least partially overlaps a projection of the second first voltage line on the substrate.

[0331] As shown in FIGS. 3-12, the first node control circuit includes a first transistor T1.

[0332] A projection of an active pattern A7 of T7 on the substrate at least partially overlaps a projection of the second clock signal line CLK2 on the substrate, so as to save horizontal space and facilitate narrow frame implementation.

[0333] The active pattern A7 of T7 is formed in the semiconductor layer.

[0334] Optionally, the first node control circuit includes a first transistor, and a gate of the first transistor is electrically connected with the first clock signal line.

[0335] The gate of the first transistor is electrically connected with a first connection pattern; the first connection pattern is electrically connected with a second connection pattern, and the first connection pattern and the second connection pattern are arranged in different layers; the second connection pattern is arranged in a different layer from the first clock signal line; and the second connection pattern is electrically connected with the first clock signal line.

[0336] As shown in FIGS. 3-12, the first node control circuit includes a first transistor T1;

[0337] The gate G1 of T1 is electrically connected with a first connection pattern L1, and the first connection pattern L1 is formed in a first gate metal layer;

[0338] The first connection pattern L1 is electrically connected with a second connection pattern L2, and the second connection pattern L2 is formed in a first source-drain metal layer; the first connection pattern L1 and the second connection pattern L2 are arranged in different layers;

[0339] The second connection pattern L2 is arranged in a different layer from the first clock signal line CLK1, the first clock signal line CLK1 is formed in a second source-drain metal layer, and the second connection pattern L2 is electrically connected with the first clock signal line CLK1.

[0340] In at least one embodiment of the present disclosure, the second node control circuit includes a first capacitor;

[0341] The projection of the plate of the first capacitor on the substrate at least partially overlaps the projection of the second connection pattern on the substrate, and the projection of the plate of the first capacitor on the substrate at least partially overlaps the projection of the first clock signal line on the substrate.

[0342] As shown in FIGS. 3-12, the second node control circuit includes a first capacitor C1;

[0343] The projection of the first plate C1a of C1 on the substrate at least partially overlaps the projection of the second connection pattern L2 on the substrate, and the projection of the second plate C1b of C1 on the substrate at least partially overlaps the projection of the second connection pattern L2 on the substrate;

[0344] The projection of the first plate C1a of C1 on the substrate at least partially overlaps the projection of the first clock signal line CLK1 on the substrate, and the projection of the second plate C1b of C1 on the substrate at least partially overlaps the projection of the first clock signal line CLK1 on the substrate.

[0345] By adopting the above arrangement, the lateral space can be saved, and narrow frame can be achieved.

[0346] Optionally, the second first voltage line is arranged between the second clock signal line and the first clock signal line.

[0347] The second first voltage line, the second clock signal line and the first clock signal line are arranged in the same layer.

[0348] As shown in FIGS. 3-12, the second high voltage line VGH2 is arranged between the second clock signal line CLK2 and the first clock signal line CLK1, so as to reasonably layout the second high voltage line VGH2, the first clock signal line CLK1 and the second clock signal line CLK2.

[0349] The second high voltage line VGH2, the second clock signal line CLK2 and the first clock signal line CLK1 are arranged in the same layer.

[0350] In at least one embodiment shown in FIGS. 3-12, the second first voltage line is the second high voltage line VGH2.

[0351] In at least one embodiment of the present disclosure, the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node.

[0352] The active pattern of at least one transistor included in the first node control circuit has a projection on the substrate that at least partially overlaps a projection of the second clock signal line on the substrate.

[0353] As shown in FIGS. 3-12, the first node control circuit includes a third transistor T3.

[0354] The active pattern A3 of T3 has a projection on the substrate that at least partially overlaps a projection of the second clock signal line CLK2 on the substrate, so as to save horizontal space and facilitate narrow frame implementation.

[0355] In at least one embodiment of the present disclosure, the driving circuit includes a first node potential maintaining circuit; the first node potential maintaining circuit is configured to maintain an electric potential of the first node.

[0356] The first node potential maintaining circuit includes a second capacitor; a plate of the second capacitor has a projection on the substrate that at least partially overlaps a projection of the third clock signal line on the substrate.

[0357] As shown in FIGS. 3-12, the first node potential maintaining circuit includes a second capacitor C2.

[0358] The first plate C2a of C2 has a projection on the substrate that at least partially overlaps a projection of the third clock signal line CLK3 on the substrate; the second plate C2b of C2 has a projection on the substrate that at least partially overlaps a projection of the third clock signal line CLK3 on the substrate, so as to save horizontal space and facilitate narrow frame implementation.

[0359] As shown in FIGS. 3-12, the first electrode plate C2a of C2 is formed in the first gate metal layer, and the second electrode plate C2b of C2 is formed in the second gate metal layer.

[0360] The display substrate also includes a first second voltage line and a second second voltage line disposed on the substrate.

[0361] The third node control circuit is electrically connected with the second second voltage line, the third node and the fifth node, respectively, and is configured to control the potential of the third node according to the potential of the fifth node under the control of a voltage signal provided by the second second voltage line.

[0362] The fifth node control circuit is electrically connected with the third clock signal line, the fourth node and the fifth node, respectively, and is configured to control the potential of the fifth node according to a fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node.

[0363] The active pattern of at least one transistor included in the third node control circuit at least partially overlaps the active pattern of the fourth clock signal line on the substrate.

[0364] The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the active pattern of the fourth clock signal line on the substrate.

[0365] As shown in FIGS. 3-12, the third node control circuit includes a fifth transistor T5, and the fifth node control circuit includes a seventh transistor T7.

[0366] The active pattern A5 of T5 at least partially overlaps the active pattern of the fourth clock signal line CLK4 on the substrate and at least partially overlaps the active pattern of the first clock signal line CLK1 on the substrate.

[0367] The active pattern A7 of T7 at least partially overlaps the active pattern of the fourth clock signal line CLK4 on the substrate.

[0368] By adopting the above arrangement, the horizontal space can be saved, and narrow frame can be achieved.

[0369] The display substrate also includes a first second voltage line and a second second voltage line disposed on the substrate.

[0370] The driving circuit further includes a fourth node control circuit and a seventh node control circuit.

[0371] The fourth node control circuit is electrically connected with the input end, the third clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input end into the fourth node under control of a third clock signal provided by the third clock signal line;

[0372] The seventh node control circuit is electrically connected with the second voltage line, the fourth node and the seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the fourth node under control of a voltage signal provided by the second voltage line;

[0373] The active pattern of the at least one transistor included in the fourth node control circuit at least partially overlaps the fourth clock signal line on the substrate in a normal projection;

[0374] The active pattern of the at least one transistor included in the seventh node control circuit at least partially overlaps the fourth clock signal line on the substrate in a normal projection.

[0375] As shown in FIGS. 3-12, the fourth node control circuit includes a sixth transistor T6, and the seventh node control circuit includes an eleventh transistor T11;

[0376] The active pattern A6 of the T6 at least partially overlaps the fourth clock signal line CLK4 on the substrate in a normal projection;

[0377] The active pattern A1 of the T11 at least partially overlaps the fourth clock signal line CLK4 on the substrate in a normal projection;

[0378] By using the above arrangement, the horizontal space can be saved, and a narrow frame can be achieved.

[0379] In at least one embodiment of the present disclosure, a part of the active pattern of the at least one transistor included in the fourth node control circuit is arranged between the fourth clock signal line on the substrate in a normal projection and the second voltage line on the substrate in a normal projection;

[0380] A part of the active pattern of the at least one transistor included in the fourth node control circuit is arranged between the fourth clock signal line on the substrate in a normal projection and the second voltage line on the substrate in a normal projection.

[0381] Optionally, the second voltage line can be a second low voltage line.

[0382] As shown in FIGS. 3-12, the part of the active pattern A6 of T6 in the orthographic projection of the substrate is arranged between the orthographic projection of the fourth clock signal line CLK4 on the substrate and the orthographic projection of the second low voltage line VGL2 on the substrate;

[0383] The part of the active pattern A11 of T11 in the orthographic projection of the substrate is arranged between the orthographic projection of the fourth clock signal line CLK4 on the substrate and the orthographic projection of the second low voltage line VGL2 on the substrate.

[0384] Through the above arrangement, T6, T11, CLK4 and VGL2 are reasonably laid out.

[0385] In at least one embodiment of the present disclosure, the driving circuit comprises a fifth node control circuit; the fifth node control circuit is electrically connected with a fifth node, a first clock signal line and a second second voltage line respectively, and is used for writing a voltage signal provided by the second second voltage line into the fifth node under the control of a first clock signal provided by the first clock signal line.

[0386] The active pattern of at least one transistor included in the fifth node control circuit in the orthographic projection of the substrate is arranged between the orthographic projection of the second low voltage line on the substrate and the orthographic projection of the fourth clock signal line on the substrate.

[0387] As shown in FIGS. 3-12, the fifth node control circuit comprises an eighth transistor T8.

[0388] The active pattern A3 of T3 in the orthographic projection of the substrate is arranged between the second low voltage line VGL2 and the orthographic projection of the fourth clock signal line CLK4 on the substrate, so as to reasonably lay out VGL2, CLK4 and A3.

[0389] VGL2 is formed in the first source-drain metal layer, and CLK4 is formed in the second source-drain metal layer.

[0390] In at least one embodiment of the present disclosure, the driving circuit comprises a sixth node control circuit.

[0391] The sixth node control circuit is electrically connected with a sixth node, a first first voltage line, a fifth node, a second clock signal line and a seventh node respectively, and is used for writing a second clock signal provided by the second clock signal line into the sixth node under the control of the potential of the seventh node, and writing a voltage signal provided by the first first voltage line into the sixth node under the control of the potential of the fifth node.

[0392] The active pattern of at least one transistor included in the sixth node control circuit in the orthographic projection of the substrate at least partially overlaps with the orthographic projection of the second clock signal line on the substrate.

[0393] A projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a projection of the second high voltage line on the substrate.

[0394] Optionally, the first voltage line can be a first high voltage line.

[0395] As shown in FIGS. 3-12, the sixth node control circuit includes a ninth transistor T9 and a tenth transistor T10;

[0396] A projection of an active pattern A9 of T9 on the substrate at least partially overlaps a projection of CLK2 on the substrate;

[0397] A projection of an active pattern A10 of T10 on the substrate at least partially overlaps a projection of the second high voltage line VGH2 on the substrate.

[0398] The display substrate described in at least one embodiment of the present disclosure further includes a seventh node control circuit; the seventh node control circuit is electrically connected with the sixth node and the seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the sixth node;

[0399] A projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a projection of the fourth clock signal line on the substrate;

[0400] A projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a projection of the first clock signal line on the substrate;

[0401] A projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a projection of the second first voltage line on the substrate;

[0402] A projection of a plate of a capacitor included in the seventh node control circuit on the substrate at least partially overlaps a projection of the second clock signal line on the substrate.

[0403] Optionally, the second first voltage line can be a second high voltage line.

[0404] As shown in FIGS. 3-12, the seventh node control circuit includes a third capacitor C3;

[0405] A projection of a first plate C3a of C3 on the substrate at least partially overlaps a projection of the fourth clock signal line CLK4 on the substrate; a projection of a second plate C3b of C3 on the substrate at least partially overlaps a projection of the fourth clock signal line CLK4 on the substrate;

[0406] A first electrode plate C3a of the C3 has a projection on the substrate that at least partially overlaps a projection of the first clock signal line CLK1 on the substrate; a second electrode plate C3b of the C3 has a projection on the substrate that at least partially overlaps a projection of the first clock signal line CLK1 on the substrate;

[0407] A first electrode plate C3a of the C3 has a projection on the substrate that at least partially overlaps a projection of the second high voltage line VGH2 on the substrate; a second electrode plate C3b of the C3 has a projection on the substrate that at least partially overlaps a projection of the second high voltage line VGH2 on the substrate;

[0408] A first electrode plate C3a of the C3 has a projection on the substrate that at least partially overlaps a projection of the second clock signal line CLK2 on the substrate; a second electrode plate C3b of the C3 has a projection on the substrate that at least partially overlaps a projection of the second clock signal line CLK2 on the substrate.

[0409] In at least one embodiment of the present disclosure, the driving circuit comprises an output reset circuit; the plurality of signal lines further comprises a first second voltage line;

[0410] The output reset circuit is electrically connected with the seventh node, the driving output end and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the driving output end under control of a potential of the seventh node;

[0411] An active pattern of at least one transistor comprised in the output reset circuit has a projection on the substrate that at least partially overlaps a projection of the first first voltage line on the substrate.

[0412] As shown in FIGS. 3-12, the output reset circuit comprises a second transistor T2;

[0413] An active pattern A2 of the T2 has a projection on the substrate that at least partially overlaps a projection of the first high voltage line VGH1 on the substrate, so as to save a lateral space of the driving circuit and facilitate realization of a narrow frame.

[0414] Optionally, the first second voltage line is arranged on a side of a transistor comprised in the output reset circuit close to the display area; and no other transistor and capacitor is arranged between the first second voltage line and the transistor comprised in the output reset circuit.

[0415] In at least one embodiment of the present disclosure, the first second voltage line can be a first low voltage line, and the second second voltage line can be a second low voltage line.

[0416] As shown in FIGS. 3-12, the first low voltage line VGL1 is arranged at the side of the second transistor T2 close to the display area, and no other transistor and capacitor is arranged between the first low voltage line VGL1 and the second transistor T2, so as to communicate between T2 and the first low voltage line VGL1.

[0417] As shown in FIGS. 3-12, the fourth clock signal line CLK4, the first clock signal line CLK1, the second high voltage line VGH2, the second clock signal line CLK2, the third clock signal line CLK3, the first high voltage line VGH1 and the low voltage line VSS are made of the second source-drain metal layer;

[0418] The CLK4, CLK1, VGH2, CLK2, CLK3, VGH1 and VSS all extend along the vertical direction;

[0419] The CLK4, CLK1, VGH2, CLK2, CLK3, VGH1 and VSS are arranged in sequence along the direction close to the display area.

[0420] As shown in FIGS. 3-12, the first high voltage line VGH1, the second high voltage line VGH2, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are arranged at the side of the source base of the transistors and capacitors included in the driving circuit, so as to layout two high voltage lines and four clock signal lines under the premise of realizing narrow frame.

[0421] As shown in FIGS. 3-12, the gate of T1 is electrically connected with the fourth clock signal line CLK4, and the first electrode of T4 is electrically connected with the first clock signal line CLK1; the first electrode of T7 is electrically connected with the fourth clock signal line CLK4, so according to the principle of proximity, the CLK4 and CLK1 are arranged at the place close to the gate of T1, the first electrode of T4 and the first electrode of T7, so as to avoid overlapping and save space.

[0422] As shown in FIGS. 3-12, the gate G1 of T1 is electrically connected with the first connection pattern L1, the first connection pattern L1 is electrically connected with the second connection pattern L2, and the second connection pattern L2 is electrically connected with the first clock signal line CLK1 through the second via hole H2, so as to provide the first clock signal provided by the first clock signal line CLK1 to the gate of T1, and the second via hole H2 is arranged above C1.

[0423] As shown in FIGS. 3-12, the VGL2 is arranged at the side of the driving circuit away from the display area, and the VGL1 is arranged at the side of the driving circuit close to the display area;

[0424] The at least one embodiment of the present disclosure adopts two high voltage lines: the first high voltage line VGH1 and the second high voltage line VGH2;

[0425] Since the first electrode of T3 is electrically connected with the second high voltage line VGH2, the first electrode of T9 is electrically connected with the first high voltage line VGH1, and the first electrode of T12 is electrically connected with the first high voltage line VGH1, according to the principle of proximity, VGH1 is arranged on the side of T12 away from the substrate, and VGH2 is arranged between CLK2 and CLK1, and the second high voltage signal is provided to the first electrode of T3 through the via hole electrically connected with the first electrode of T3.

[0426] In FIG. 4, A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, and A12 is the active pattern of T12.

[0427] The difference between at least one embodiment of the driving circuit shown in FIG. 13 and at least one embodiment of the driving circuit shown in FIG. 2B is as follows:

[0428] The gate of T8 is electrically connected with the second clock signal line CLK2; the gate of T6 is electrically connected with the second clock signal line CLK2; the first electrode of T7 is electrically connected with the first clock signal line CLK1; the second electrode of T10 is electrically connected with the third clock signal line CLK3; the first electrode of T4 is electrically connected with the fourth clock signal line CLK4; and the gate of T1 is electrically connected with the fourth clock signal line CLK4.

[0429] In at least one embodiment shown in FIG. 13, on the basis of at least one embodiment shown in FIG. 2A, the first clock signal terminal CK1 is the first clock signal line CLK1, the second clock signal terminal CK2 is the third clock signal line CLK3, the third clock signal terminal CK3 is the fourth clock signal line CLK4, and the fourth clock signal terminal CK4 is the second clock signal line CLK2.

[0430] FIG. 14 is a layout diagram of a display substrate according to at least one embodiment of the present disclosure. In at least one embodiment shown in FIG. 14, the display substrate comprises at least one embodiment of the driving circuit shown in FIG. 13.

[0431] Fig. 15 is a layout of the semiconductor layer in Fig. 14, Fig. 16 is a layout of the first gate metal layer in Fig. 14, Fig. 17 is a layout of the second gate metal layer in Fig. 14, Fig. 18 is a layout of the first source-drain metal layer in Fig. 14, Fig. 19 is a layout of the second source-drain metal layer in Fig. 14, Fig. 20 is a layout of the semiconductor layer and the first gate metal layer in Fig. 14, Fig. 21 is a layout of the first gate metal layer and the second gate metal layer in Fig. 14, Fig. 22 is a layout of the first gate metal layer and the first source-drain metal layer in Fig. 14, Fig. 23 is a layout of the second gate metal layer and the first source-drain metal layer in Fig. 14, and Fig. 24 is a layout of the first source-drain metal layer and the second source-drain metal layer in Fig. 14.

[0432] In at least one embodiment of the present disclosure, the driving circuit comprises a first node control circuit;

[0433] The first node control circuit is electrically connected with the fourth clock signal line, the first node and the second node respectively, and is configured to control the electric potential of the first node according to the electric potential of the second node under the control of the fourth clock signal provided by the fourth clock signal line.

[0434] The active pattern of at least one transistor included in the first node control circuit has a projection on the substrate that at least partially overlaps with the projection of the second clock signal line on the substrate.

[0435] As shown in Figs. 14-24, the first node control circuit comprises a first transistor T1.

[0436] The active pattern A1 of T1 has a projection on the substrate that at least partially overlaps with the projection of the second clock signal line CLK2 on the substrate, so as to save horizontal space and facilitate the realization of narrow frame.

[0437] Optionally, the first node control circuit comprises a first transistor; the gate of the first transistor is electrically connected with the fourth clock signal line.

[0438] The gate of the first transistor is electrically connected with a first connection pattern; the first connection pattern is electrically connected with a second connection pattern; the first connection pattern and the second connection pattern are arranged in different layers; the second connection pattern is arranged in a layer different from the fourth clock signal line; and the second connection pattern is electrically connected with the fourth clock signal line.

[0439] As shown in Figs. 14-24, the first node control circuit comprises a first transistor T1.

[0440] The gate G1 of T1 is electrically connected with a first connection pattern L1, and L1 is electrically connected with a second connection pattern L2; L1 is formed in the first gate metal layer, and L2 is formed in the first source-drain metal layer.

[0441] L2 is electrically connected with CLK4.

[0442] In at least one embodiment of the present disclosure, the driving circuit comprises a fifth node control circuit;

[0443] The fifth node control circuit is electrically connected with the fourth clock signal line, the fourth node and the fifth node respectively, and is configured to control the electric potential of the fifth node according to the fourth clock signal provided by the fourth clock signal line under the control of the electric potential of the fourth node.

[0444] The active pattern of the transistor included in the fifth node control circuit at least partially overlaps with the active pattern of the fourth clock signal line on the substrate.

[0445] The second connection pattern is electrically connected with the fourth clock signal line through the first via hole;

[0446] The boundary of the first via hole on the substrate does not overlap with the channel of the transistor included in the fifth node control circuit on the substrate.

[0447] As shown in FIGS. 14-24, the fifth node control circuit comprises a seventh transistor T7.

[0448] The active pattern A7 of T7 at least partially overlaps with the active pattern of the fourth clock signal line CLK4 on the substrate, so as to save the lateral space and facilitate the realization of narrow frame.

[0449] L2 is electrically connected with CLK4 through the first via hole H1.

[0450] The boundary of H1 on the substrate does not overlap with the channel of T7 on the substrate, so as to avoid affecting the characteristics of T7.

[0451] As shown in FIGS. 14-24, the channel of T7 comprises a first channel pattern GX1 and a second channel pattern GX2, T7 is a double-gate transistor, the first gate of T7 is labeled as G71, and the second gate of T7 is labeled as G72.

[0452] As shown in FIGS. 14-24, the first via hole H1 can be placed between G71 and G72 to avoid affecting T7, and the first clock signal can be transmitted to the first electrode of T7 through the wire formed in the first source-drain metal layer and the first electrode of T7 being electrically connected.

[0453] As shown in FIGS. 14-24, the first low-voltage line VGL1 and the second low-voltage line VGL2 are formed in the first source-drain metal layer; the first low-voltage line VGL1 is formed on the side of the driving circuit far away from the display area, and the second low-voltage line is arranged on the side of the driving circuit close to the display area;

[0454] In at least one embodiment of the present disclosure, two high-voltage lines are adopted. Since the first electrode of T3 is electrically connected with the second high-voltage line VGH2, and the first electrode of T12 and the first electrode of T9 are electrically connected with the first high-voltage line VGH1, the VGH1 is arranged on the side of T12 far away from the substrate according to the principle of proximity, and the VGH2 is arranged between CLK2 and CLK1 and is electrically connected with the first electrode of T3 through a via hole to transmit the signal of the second high-voltage line to the first electrode of T3. As shown in FIGS. 14-24, CLK4, CLK1, VGH2, CLK2, CLK3, VGH1 and the low-voltage line VSS all extend in the vertical direction, and CLK4, CLK1, VGH2, CLK2, CLK3, VGH1 and VSS are all formed in the second source-drain metal layer and are arranged in the direction close to the display area in sequence.

[0455] As shown in FIG. 25A, the driving circuit according to at least one embodiment of the present disclosure includes a driving output circuit 10, a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, a sixth node control circuit 16, a first node potential maintaining circuit 21, a seventh node control circuit 17 and an output reset circuit 20.

[0456] The driving output circuit 10 is electrically connected with the first node N1, the first high-voltage line VGH1 and the driving output end OT respectively, and is used to control the communication or disconnection between the driving output end OT and the first high-voltage line VGH1 under the control of the potential of the first node N1.

[0457] The first node control circuit 11 is electrically connected with the first clock signal end CK1, the first node N1 and the second node N2 respectively, and is used to control the potential of the first node N1 according to the potential of the second node N2 under the control of the clock signal provided by the first clock signal end CK1.

[0458] The first node control circuit 11 is also electrically connected with the fourth node N4 and the second high-voltage line VGH2 respectively, and is used to control the communication between the first node N1 and the second high-voltage line VGH2 under the control of the potential of the fourth node N4.

[0459] The second node control circuit 12 is electrically connected with the first clock signal terminal CK1, the second node N2 and the third node N3 respectively, and is used for controlling the potential of the second node N2 according to the clock signal provided by the first clock signal terminal CK1 under the control of the potential of the third node N3, and controlling the potential of the second node N2 according to the potential of the third node N3;

[0460] The third node control circuit 13 is electrically connected with the first low voltage line VGL1, the third node N3 and the fifth node N5 respectively, and is used for controlling the potential of the third node N3 according to the potential of the fifth node N5 under the control of the first low voltage signal provided by the first low voltage line VGL1;

[0461] The fifth node control circuit 15 is electrically connected with the third clock signal terminal CK3, the fourth node N4 and the fifth node N5 respectively, and is used for controlling the potential of the fifth node N5 according to the clock signal provided by the third clock signal terminal CK3 under the control of the potential of the fourth node N4;

[0462] The fifth node control circuit 15 is also electrically connected with the fifth node N5, the second clock signal terminal CK2 and the first low voltage line VGL1 respectively, and is used for writing the first low voltage signal provided by the first low voltage line VGL1 into the fifth node N5 under the control of the clock signal provided by the second clock signal line C2K2;

[0463] The fourth node control circuit 14 is electrically connected with the input terminal I1, the second clock signal terminal CK2 and the fourth node N4 respectively, and is used for writing the input signal provided by the input terminal I1 into the fourth node N4 under the control of the clock signal provided by the second clock signal terminal CK2;

[0464] The fourth node control circuit 14 is also electrically connected with the control line VEL and the second high voltage line VGH2 respectively, and is used for writing the second high voltage signal provided by the second high voltage line VGH2 into the fourth node N4 under the control of the control signal provided by the control line VEL;

[0465] The seventh node control circuit 17 is electrically connected with the first low voltage line VGL1, the fourth node N4 and the seventh node N7 respectively, and is used for controlling the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0466] The sixth node control circuit 16 is electrically connected with the sixth node N6, the second high voltage line VGH2, the fifth node N5, the fourth clock signal terminal CK4 and the seventh node N7 respectively, and is configured to write a clock signal provided by the fourth clock signal terminal CK4 into the sixth node N6 under the control of the potential of the seventh node N7, and write a second high voltage signal provided by the second high voltage line VGH2 into the sixth node N6 under the control of the potential of the fifth node N5;

[0467] The seventh node control circuit 17 is electrically connected with the sixth node N6 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the sixth node N6;

[0468] The first node potential maintaining circuit 21 is configured to maintain the potential of the first node N1;

[0469] The output reset circuit 20 is electrically connected with the seventh node N7, the drive output terminal OT and the second low voltage line VGL2 respectively, and is configured to write a second low voltage signal provided by the second low voltage line VGL2 into the drive output terminal OT under the control of the potential of the seventh node N7.

[0470] As shown in FIG. 25B, the driving circuit includes the drive output circuit 10, the first node control circuit 11, the second node control circuit 12, the third node control circuit 13, the fourth node control circuit 14, the fifth node control circuit 15, the sixth node control circuit 16, the first node potential maintaining circuit 21, the seventh node control circuit 17 and the output reset circuit 20.

[0471] The drive output circuit 10 is electrically connected with the first node N1, the first high voltage line VGH1 and the drive output terminal OT respectively, and is configured to control the communication or disconnection between the drive output terminal OT and the first high voltage line VGH1 under the control of the potential of the first node N1;

[0472] The first node control circuit 11 is electrically connected with the second clock signal line CLK2, the first node N1 and the second node N2 respectively, and is configured to control the potential of the first node N1 according to the potential of the second node N2 under the control of a second clock signal provided by the second clock signal line CLK2;

[0473] The first node control circuit 11 is also electrically connected with the fourth node N4 and the second high voltage line VGH2 respectively, and is configured to control the communication between the first node N1 and the second high voltage line VGH2 under the control of the potential of the fourth node N4;

[0474] The second node control circuit 12 is electrically connected with the second clock signal line CLK2, the second node N2 and the third node N3 respectively, and is configured to control the potential of the second node N2 according to the second clock signal provided by the second clock signal line CLK2 under the control of the potential of the third node N3, and control the potential of the second node N2 according to the potential of the third node N3;

[0475] The third node control circuit 13 is electrically connected with the first low voltage line VGL1, the third node N3 and the fifth node N5 respectively, and is configured to control the potential of the third node N3 according to the potential of the fifth node N5 under the control of the first low voltage signal provided by the first low voltage line VGL1;

[0476] The fifth node control circuit 15 is electrically connected with the third clock signal line CLK3, the fourth node N4 and the fifth node N5 respectively, and is configured to control the potential of the fifth node N5 according to the third clock signal provided by the third clock signal line CLK3 under the control of the potential of the fourth node N4;

[0477] The fifth node control circuit 15 is further electrically connected with the fifth node N5, the fourth clock signal line CLK4 and the first low voltage line VGL1 respectively, and is configured to write the first low voltage signal provided by the first low voltage line VGL1 into the fifth node N5 under the control of the fourth clock signal provided by the fourth clock signal line CLK4;

[0478] The fourth node control circuit 14 is electrically connected with the input terminal I1, the fourth clock signal line CLK4 and the fourth node N4 respectively, and is configured to write the input signal provided by the input terminal I1 into the fourth node N4 under the control of the fourth clock signal provided by the fourth clock signal line CLK4;

[0479] The fourth node control circuit 14 is further electrically connected with the control line VEL and the second high voltage line VGH2 respectively, and is configured to write the second high voltage signal provided by the second high voltage line VGH2 into the fourth node N4 under the control of the control signal provided by the control line VEL;

[0480] The seventh node control circuit 17 is electrically connected with the first low voltage line VGL1, the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0481] The sixth node control circuit 16 is electrically connected with the sixth node N6, the second high voltage line VGH2, the fifth node N5, the first clock signal line CLK1 and the seventh node N7 respectively, and is configured to write the first clock signal provided by the first clock signal line CLK1 into the sixth node N6 under the control of the potential of the seventh node N7, and write the second high voltage signal provided by the second high voltage line VGH2 into the sixth node N6 under the control of the potential of the fifth node N5;

[0482] The seventh node control circuit 17 is electrically connected with the sixth node N6 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the sixth node N6.

[0483] The first node potential maintaining circuit 21 is configured to maintain the potential of the first node N1.

[0484] The output reset circuit 20 is electrically connected with the seventh node N7, the drive output end OT and the second low voltage line VGL2 respectively, and is configured to write the second low voltage signal provided by the second low voltage line VGL2 into the drive output end OT under the control of the potential of the seventh node N7.

[0485] In at least one embodiment shown in FIG. 25B, on the basis of at least one embodiment shown in FIG. 25A, the first clock signal end CK1 is the second clock signal line CLK2, the second clock signal end CK2 can be the fourth clock signal line CLK4, the third clock signal end CK3 can be the third clock signal line CLK3, and the fourth clock signal end CK4 can be the first clock signal line CLK1.

[0486] In at least one embodiment of the present disclosure, the driving module can include a plurality of driving circuits;

[0487] The first clock signal end of the 4a-3 level driving circuit can be electrically connected with the first clock signal line, the second clock signal end of the 4a-3 level driving circuit can be electrically connected with the second clock signal line, the third clock signal end of the 4a-3 level driving circuit can be electrically connected with the third clock signal line, and the fourth clock signal end of the 4a-3 level driving circuit can be electrically connected with the fourth clock signal line.

[0488] The first clock signal end of the 4a-2 level driving circuit can be electrically connected with the second clock signal line, the second clock signal end of the 4a-2 level driving circuit can be electrically connected with the third clock signal line, the third clock signal end of the 4a-2 level driving circuit can be electrically connected with the fourth clock signal line, and the fourth clock signal end of the 4a-2 level driving circuit can be electrically connected with the first clock signal line.

[0489] The first clock signal end of the 4a-1 level driving circuit can be electrically connected with the third clock signal line, the second clock signal end of the 4a-1 level driving circuit can be electrically connected with the fourth clock signal line, the third clock signal end of the 4a-1 level driving circuit can be electrically connected with the first clock signal line, and the fourth clock signal end of the 4a-1 level driving circuit can be electrically connected with the second clock signal line.

[0490] The first clock signal end of the 4a level driving circuit can be electrically connected with the fourth clock signal line, the second clock signal end of the 4a level driving circuit can be electrically connected with the first clock signal line, the third clock signal end of the 4a level driving circuit can be electrically connected with the second clock signal line, and the fourth clock signal end of the 4a level driving circuit can be electrically connected with the third clock signal line.

[0491] a is a positive integer.

[0492] As shown in FIG. 26A, on the basis of at least one embodiment of the driving circuit shown in FIG. 25A, the first node control circuit includes a first transistor T1 and a third transistor T3; the second node control circuit includes a first capacitor C1 and a fourth transistor T4; and the output reset circuit includes a second transistor T2.

[0493] The gate of the first transistor T1 is electrically connected with the first clock signal end CK1, the first electrode of the first transistor T1 is electrically connected with the second node N2, and the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0494] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with the second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node N1.

[0495] The gate of the second transistor T2 is electrically connected with the seventh node N7, the first electrode of the second transistor T2 is electrically connected with the driving output end OT, and the second electrode of the second transistor T2 is electrically connected with the second low voltage line VGL2.

[0496] The first electrode of the first capacitor C1 is electrically connected with the third node N3, and the second electrode of the first capacitor C1 is electrically connected with the second node N2.

[0497] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the first clock signal end CK1, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2.

[0498] The third node control circuit 13 includes a fifth transistor T5.

[0499] A gate of the T5 is electrically connected with the first low voltage line VGL1, a first electrode of the T5 is electrically connected with the fifth node N5, and a second electrode of the T5 is electrically connected with the third node N3;

[0500] The fourth node control circuit 14 comprises a sixth transistor T6 and a thirteenth transistor T13;

[0501] A gate of the T6 is electrically connected with the second clock signal terminal CK2, a first electrode of the T6 is electrically connected with the input terminal I1, and a second electrode of the T6 is electrically connected with the fourth node N4;

[0502] A gate of the T13 is electrically connected with the control line VEL, a first electrode of the T13 is electrically connected with the second high voltage line VGH2, and a second electrode of the T13 is electrically connected with the fourth node N4;

[0503] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0504] A gate of the T7 is electrically connected with the fourth node N4, a first electrode of the T7 is electrically connected with the third clock signal terminal CK3, and a second electrode of the T7 is electrically connected with the fifth node N5;

[0505] A gate of the T8 is electrically connected with the second clock signal terminal CK2, a first electrode of the T8 is electrically connected with the first low voltage line VGL1, and a second electrode of the T8 is electrically connected with the fifth node N5;

[0506] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0507] A gate of the T9 is electrically connected with the fifth node N5, a first electrode of the T9 is electrically connected with the second high voltage line VGH2, and a second electrode of the T9 is electrically connected with the sixth node N6;

[0508] A gate of the T10 is electrically connected with the seventh node N7, a first electrode of the T10 is electrically connected with the sixth node N6, and a second electrode of the T10 is electrically connected with the fourth clock signal terminal CK4;

[0509] The first node potential maintaining circuit comprises a second capacitor C2;

[0510] A first plate of the C2 is electrically connected with the first node N1, and a second plate of the C2 is electrically connected with the first high voltage line VGH1;

[0511] The seventh node control circuit comprises an eleventh transistor T11 and a third capacitor C3;

[0512] A gate of the T11 is electrically connected with the first low voltage line VGL1, a first electrode of the T11 is electrically connected with the fourth node N4, and a second electrode of the T11 is electrically connected with the seventh node N7;

[0513] The first electrode plate of C3 is electrically connected with the sixth node N6, and the second electrode plate of C3 is electrically connected with the seventh node N7.

[0514] The driving output circuit comprises a twelfth transistor T12.

[0515] The gate of T12 is electrically connected with the first node N1, the first electrode of T12 is electrically connected with the first high voltage line VGH1, and the second electrode of T12 is electrically connected with the driving output terminal OT.

[0516] FIG. 26C is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 26A, according to an embodiment of the present disclosure;

[0517] FIG. 26D is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 26A, according to an embodiment of the present disclosure;

[0518] FIG. 26E is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 26A, according to an embodiment of the present disclosure.

[0519] As shown in FIG. 26B, on the basis of at least one embodiment of the driving circuit shown in FIG. 25B, the first node control circuit comprises a first transistor T1 and a third transistor T3; the second node control circuit comprises a first capacitor C1 and a fourth transistor T4; and the output reset circuit comprises a second transistor T2.

[0520] The gate of the first transistor T1 is electrically connected with the second clock signal line CLK2, the first electrode of the first transistor T1 is electrically connected with the second node N2, and the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0521] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with the second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node N1.

[0522] The gate of the second transistor T2 is electrically connected with the seventh node N7, the first electrode of the second transistor T2 is electrically connected with the driving output terminal OT, and the second electrode of the second transistor T2 is electrically connected with the second low voltage line VGL2.

[0523] The first electrode plate of the first capacitor C1 is electrically connected with the third node N3, and the second electrode plate of the first capacitor C1 is electrically connected with the second node N2.

[0524] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the second clock signal line CLK2, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2;

[0525] The third node control circuit 13 comprises a fifth transistor T5;

[0526] The gate of the fifth transistor T5 is electrically connected with the first low voltage line VGL1, the first electrode of the fifth transistor T5 is electrically connected with the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected with the third node N3;

[0527] The fourth node control circuit 14 comprises a sixth transistor T6 and a thirteenth transistor T13;

[0528] The gate of the sixth transistor T6 is electrically connected with the fourth clock signal line CLK4, the first electrode of the sixth transistor T6 is electrically connected with the input terminal I1, and the second electrode of the sixth transistor T6 is electrically connected with the fourth node N4;

[0529] The gate of the thirteenth transistor T13 is electrically connected with the control line VEL, the first electrode of the thirteenth transistor T13 is electrically connected with the second high voltage line VGH2, and the second electrode of the thirteenth transistor T13 is electrically connected with the fourth node N4;

[0530] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0531] The gate of the seventh transistor T7 is electrically connected with the fourth node N4, the first electrode of the seventh transistor T7 is electrically connected with the third clock signal line CLK3, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5;

[0532] The gate of the eighth transistor T8 is electrically connected with the fourth clock signal line CLK4, the first electrode of the eighth transistor T8 is electrically connected with the first low voltage line VGL1, and the second electrode of the eighth transistor T8 is electrically connected with the fifth node N5;

[0533] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0534] The gate of the ninth transistor T9 is electrically connected with the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected with the second high voltage line VGH2, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6;

[0535] The gate of the tenth transistor T10 is electrically connected with the seventh node N7, the first electrode of the tenth transistor T10 is electrically connected with the sixth node N6, and the second electrode of the tenth transistor T10 is electrically connected with the first clock signal line CLK1;

[0536] The first node potential maintaining circuit comprises a second capacitor C2;

[0537] The first plate of the second capacitor C2 is electrically connected with the first node N1, and the second plate of the second capacitor C2 is electrically connected with the first high voltage line VGH1;

[0538] The seventh node control circuit includes an eleventh transistor T11 and a third capacitor C3;

[0539] The gate of T11 is electrically connected with the first low voltage line VGL1, the first electrode of T11 is electrically connected with the fourth node N4, and the second electrode of T11 is electrically connected with the seventh node N7;

[0540] The first plate of C3 is electrically connected with the sixth node N6, and the second plate of C3 is electrically connected with the seventh node N7;

[0541] The drive output circuit includes a twelfth transistor T12;

[0542] The gate of T12 is electrically connected with the first node N1, the first electrode of T12 is electrically connected with the first high voltage line VGH1, and the second electrode of T12 is electrically connected with the drive output terminal OT.

[0543] In at least one embodiment shown in FIG. 26B, on the basis of at least one embodiment shown in FIG. 26A, the first clock signal terminal CK1 is the second clock signal line CLK2, the second clock signal terminal CK2 can be the fourth clock signal line CLK4, the third clock signal terminal CK3 can be the third clock signal line CLK3, and the fourth clock signal terminal CK4 can be the first clock signal line CLK1.

[0544] FIG. 27 is a layout of a display substrate according to at least one embodiment of the present disclosure. In at least one embodiment shown in FIG. 27, the display substrate includes at least one embodiment of the drive circuit shown in FIG. 26B.

[0545] FIG. 28 is a layout of a semiconductor layer in FIG. 27, FIG. 29 is a layout of a first gate metal layer in FIG. 27, FIG. 30 is a layout of a second gate metal layer in FIG. 27, FIG. 31 is a layout of a first source-drain metal layer in FIG. 27, FIG. 32 is a layout of a second source-drain metal layer in FIG. 27, FIG. 33 is a layout of a semiconductor layer and a first gate metal layer in FIG. 27, FIG. 34 is a layout of a first gate metal layer and a second gate metal layer in FIG. 27, FIG. 35 is a layout of a second gate metal layer and a first source-drain metal layer in FIG. 27, and FIG. 36 is a layout of a first source-drain metal layer and a second source-drain metal layer in FIG. 27.

[0546] At least one embodiment of the display substrate shown in FIG. 27 can increase the number of clock signal lines to reduce the loading of the clock signal lines, improve and adjust the output capacity of the drive circuit, and change the conventional design of two clock signal lines, one first voltage line, and one second voltage line to the design of four clock signal lines, two first voltage lines, and two second voltage lines without changing the width of the drive circuit.

[0547] In at least one embodiment of the present disclosure, the first voltage line can be a high voltage line, and the second voltage line can be a low voltage line.

[0548] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit and a second node control circuit.

[0549] The first node control circuit is electrically connected with the second clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of the second clock signal provided by the second clock signal line.

[0550] The second node control circuit is electrically connected with the second clock signal line, the second node and the third node respectively, and is configured to control the potential of the second node according to the second clock signal provided by the second clock signal line under the control of the potential of the third node, and control the potential of the second node according to the potential of the third node.

[0551] The second node control circuit includes at least one capacitor, and a normal projection of a plate of the capacitor on the substrate at least partially overlaps a normal projection of the second first voltage line on the substrate.

[0552] As shown in FIGS. 27-36, the second node control circuit includes a first capacitor C1.

[0553] A normal projection of a first plate C1a of C1 on the substrate at least partially overlaps a normal projection of VGH2 on the substrate, so as to save horizontal space and facilitate the realization of narrow frame.

[0554] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; and a normal projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a normal projection of the control line on the substrate.

[0555] As shown in FIGS. 27-36, the plurality of signal lines can further include a control line VEL; and the first node control circuit includes a first transistor T1.

[0556] A normal projection of an active pattern A1 of T1 on the substrate at least partially overlaps a normal projection of VEL on the substrate, so as to save horizontal space and facilitate the realization of narrow frame.

[0557] In at least one embodiment of the present disclosure, the driving circuit includes a fourth node control circuit; and the plurality of signal lines further include a control line.

[0558] The fourth node control circuit is electrically connected with the control line, the second first voltage line and the fourth node respectively, and is configured to write a voltage signal provided by the second first voltage line into the fourth node under control of a control signal provided by the control line.

[0559] A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

[0560] A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

[0561] As shown in FIGS. 27-36, the fourth node control circuit includes a thirteenth transistor T13.

[0562] A positive projection of an active pattern A13 of the T13 on the substrate at least partially overlaps a positive projection of the VEL on the substrate.

[0563] A positive projection of the active pattern A13 of the T13 on the substrate at least partially overlaps a positive projection of the first clock signal line CLK1 on the substrate.

[0564] With the above arrangement, the transverse space can be saved, and narrow frame can be achieved.

[0565] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node.

[0566] A positive projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

[0567] As shown in FIGS. 27-36, the first node control circuit includes a third transistor T3.

[0568] A positive projection of an active pattern A3 of the T3 on the substrate at least partially overlaps a positive projection of the VEL on the substrate, so as to save the transverse space and facilitate the realization of narrow frame.

[0569] In at least one embodiment of the present disclosure, the driving circuit includes a first node electric potential maintaining circuit; the first node electric potential maintaining circuit is configured to maintain an electric potential of the first node.

[0570] The first node potential maintaining circuit includes a second capacitor; a positive projection of a plate of the second capacitor on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate;

[0571] A positive projection of a part of the plate of the second capacitor on the substrate is arranged between a positive projection of the first clock signal line on the substrate and a positive projection of the fourth clock signal line on the substrate.

[0572] As shown in FIGS. 27-36, the first node potential maintaining circuit includes a second capacitor C2;

[0573] A positive projection of a first plate C2a of C2 on the substrate at least partially overlaps a positive projection of the fourth clock signal line CLK4 on the substrate; a positive projection of a part of the first plate C2a of C2 on the substrate is arranged between a positive projection of the first clock signal line CLK1 on the substrate and a positive projection of the fourth clock signal line CLK4 on the substrate;

[0574] A positive projection of a second plate C2b of C2 on the substrate at least partially overlaps a positive projection of the fourth clock signal line CLK4 on the substrate; a positive projection of a part of the second plate C2b of C2 on the substrate is arranged between a positive projection of the first clock signal line CLK1 on the substrate and a positive projection of the fourth clock signal line CLK4 on the substrate;

[0575] Through the above arrangement, transverse space can be saved, and narrow frame can be realized.

[0576] In at least one embodiment of the present disclosure, the driving circuit includes a third node control circuit and a fifth node control circuit;

[0577] The third node control circuit is electrically connected with a first second voltage line, the third node and the fifth node respectively, and is configured to control the potential of the third node according to the potential of the fifth node under the control of a voltage signal provided by the first second voltage line;

[0578] The fifth node control circuit is electrically connected with a third clock signal line, a fourth node and a fifth node respectively, and is configured to control the potential of the fifth node according to a third clock signal provided by the third clock signal line under the control of the potential of the fourth node;

[0579] A positive projection of an active pattern of at least one transistor included in the third node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate;

[0580] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate.

[0581] As shown in FIGS. 27-36, the third node control circuit includes a fifth transistor T5 and a seventh transistor T7;

[0582] A positive projection of an active pattern A5 of T5 on the substrate at least partially overlaps a positive projection of the third clock signal line CLK3 on the substrate;

[0583] A positive projection of an active pattern A7 of T7 on the substrate at least partially overlaps the positive projection of the third clock signal line CLK3 on the substrate;

[0584] Through the above arrangement, the lateral space can be saved, and narrow frame can be achieved.

[0585] In at least one embodiment of the present disclosure, the driving circuit further includes a fourth node control circuit and a seventh node control circuit;

[0586] The fourth node control circuit is electrically connected with the input end, a fourth clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input end into the fourth node under control of a fourth clock signal provided by the fourth clock signal line;

[0587] The seventh node control circuit is electrically connected with the first second voltage line, the fourth node and a seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the fourth node under control of a voltage signal provided by the first second voltage line;

[0588] A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of a second clock signal line on the substrate;

[0589] A positive projection of an active pattern of at least one transistor included in the seventh node control circuit on the substrate at least partially overlaps the positive projection of the second clock signal line on the substrate.

[0590] As shown in FIGS. 27-36, the fourth node control circuit includes a sixth transistor T6, and the seventh node control circuit includes an eleventh transistor T11;

[0591] A positive projection of an active pattern A6 of T6 on the substrate at least partially overlaps a positive projection of a second clock signal line CLK2 on the substrate;

[0592] A positive projection of an active pattern A11 of T11 on the substrate at least partially overlaps the positive projection of the second clock signal line CLK2 on the substrate;

[0593] Through the above arrangement, the lateral space can be saved, and narrow frame can be achieved.

[0594] In at least one embodiment of the present disclosure, the driving circuit comprises a fifth node control circuit; the fifth node control circuit is electrically connected with the fifth node, the fourth clock signal line and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the fifth node under control of a fourth clock signal provided by the fourth clock signal line;

[0595] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0596] As shown in FIGS. 27-36, the fifth node control circuit comprises an eighth transistor T8;

[0597] A positive projection of an active pattern A8 of T8 on the substrate at least partially overlaps a positive projection of the second clock signal line CLK2 on the substrate;

[0598] A part of A8 is arranged between a positive projection of VGL1 on the substrate and a positive projection of CLK2 on the substrate;

[0599] Through the above arrangement, transverse space can be saved, and narrow frame can be realized.

[0600] In at least one embodiment of the present disclosure, the plurality of signal lines further comprise a control line; the driving circuit comprises a sixth node control circuit;

[0601] The sixth node control circuit is electrically connected with the sixth node, the first first voltage line, the fifth node, the first clock signal line and the seventh node respectively, and is configured to write a first clock signal provided by the first clock signal line into the sixth node under control of a potential of the seventh node, and write a voltage signal provided by the first first voltage line into the sixth node under control of a potential of the fifth node;

[0602] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate;

[0603] A positive projection of an active pattern of at least one transistor included in the sixth node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate;

[0604] As shown in FIGS. 27-36, the sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0605] A positive projection of an active pattern A9 of T9 on the substrate at least partially overlaps a positive projection of the first clock signal line CLK1 on the substrate;

[0606] A10 is a positive projection of the active pattern of T10 on the substrate, and the positive projection of VEL on the substrate at least partially overlaps;

[0607] Through the above setting, the transverse space can be saved, and narrow frame can be realized.

[0608] In at least one embodiment of the present disclosure, the plurality of signal lines further include a control line; the driving circuit further includes a seventh node control circuit; the seventh node control circuit is electrically connected with the sixth node and the fifth node respectively, and is configured to control the potential of the seventh node according to the potential of the sixth node.

[0609] The positive projection of the plate of the capacitor included in the seventh node control circuit on the substrate at least partially overlaps the positive projection of the third clock signal line on the substrate;

[0610] The positive projection of the plate of the capacitor included in the seventh node control circuit on the substrate at least partially overlaps the positive projection of the second first voltage line on the substrate;

[0611] The positive projection of the plate of the capacitor included in the seventh node control circuit on the substrate at least partially overlaps the positive projection of the control line on the substrate;

[0612] The positive projection of the plate of the capacitor included in the seventh node control circuit on the substrate at least partially overlaps the positive projection of the first clock signal line on the substrate.

[0613] In at least one embodiment shown in FIGS. 27-36, the first first voltage line is a first high voltage line VGH1, and the second first voltage line is a second high voltage line VGH2.

[0614] As shown in FIGS. 27-36, the seventh node control circuit includes a third capacitor C3;

[0615] The positive projection of the first plate C3a of C3 on the substrate at least partially overlaps the positive projection of the third clock signal line CLK3 on the substrate; the positive projection of the first plate C3a of C3 on the substrate at least partially overlaps the positive projection of the second high voltage line VGH2 on the substrate; the positive projection of the first plate C3a of C3 on the substrate at least partially overlaps the positive projection of the control line VEL on the substrate; and the positive projection of the first plate C3a of C3 on the substrate at least partially overlaps the positive projection of the first clock signal line CLK1 on the substrate;

[0616] A second plate C3b of the C3 is at least partially overlapped with a projection of the third clock signal line CLK3 on the substrate;

[0617] By the above arrangement, the transverse space can be saved, and a narrow frame can be realized.

[0618] In at least one embodiment of the present disclosure, the driving circuit comprises an output reset circuit; and the display substrate further comprises a second second voltage line;

[0619] The output reset circuit is electrically connected with the seventh node, the driving output end and the second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the driving output end under the control of a potential of the seventh node;

[0620] An active pattern of at least one transistor included in the driving output circuit is at least partially overlapped with a projection of the fourth clock signal line on the substrate;

[0621] An active pattern of at least one transistor included in the output reset circuit is at least partially overlapped with a projection of the first first voltage line on the substrate;

[0622] An active pattern of at least one transistor included in the output reset circuit is at least partially overlapped with a projection of the fourth clock signal line on the substrate.

[0623] As shown in FIGS. 27-36, the display substrate further comprises a second low voltage line VGL2;

[0624] The driving output circuit comprises a twelfth transistor T12; and the output reset circuit comprises a second transistor T2;

[0625] An active pattern A12 of the T12 is at least partially overlapped with a projection of the fourth clock signal line CLK4 on the substrate;

[0626] An active pattern A2 of the T2 is at least partially overlapped with a projection of the first high voltage line VGH1 on the substrate;

[0627] An active pattern A2 of the T2 is at least partially overlapped with a projection of the fourth clock signal line CLK4 on the substrate;

[0628] Through the above arrangement, the transverse space can be saved, and narrow frame can be realized.

[0629] As shown in FIGS. 27-36, VGL1 and VGL2 are formed in the first source-drain metal layer, CLK2, CLK3, VGH2, VEL, CLK1, CLK4 and VGH1 are formed in the second source-drain metal layer.

[0630] VGL1, VGL2, CLK2, CLK3, VGH2, VEL, CLK1, CLK4 and VGH1 extend along the vertical direction.

[0631] CLK2, CLK3, VGH2, VEL, CLK1, CLK4 and VGH1 are arranged in sequence along the direction close to the display area.

[0632] As shown in FIGS. 27-36, the seventh transistor T7 is a double-gate transistor, when the first electrode of T7 is electrically connected with the third clock signal line CLK3, the position of the via needs to avoid the position of the channel of T7 to avoid affecting the characteristics of T7.

[0633] As shown in FIG. 37A, the driving circuit includes a driving output circuit 10, a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, a sixth node control circuit 16, a first node potential maintaining circuit 21, a seventh node control circuit 17, an eighth node control circuit 18, a seventh node voltage control circuit 19, an input control circuit 110 and an output reset circuit 20.

[0634] The driving output circuit 10 is electrically connected with the first node N1, the first high voltage line VGH1 and the driving output end OT respectively, for controlling the communication or disconnection between the driving output end OT and the first high voltage line VGH1 under the control of the potential of the first node N1.

[0635] The first node control circuit 11 is electrically connected with the third clock signal end CK3, the first node N1 and the second node N2 respectively, for controlling the potential of the first node N1 according to the potential of the second node N2 under the control of the clock signal provided by the third clock signal line CK3.

[0636] The first node control circuit 11 is also electrically connected with the fourth node N4 and the second high voltage line VGH2 respectively, for controlling the communication between the first node N1 and the second high voltage line VGH2 under the control of the potential of the fourth node N4.

[0637] The second node control circuit 12 is electrically connected with the third clock signal terminal CK3, the second node N2 and the third node N3 respectively, and is used for controlling the potential of the second node N2 according to the clock signal provided by the third clock signal terminal CK3 under the control of the potential of the third node N3, and controlling the potential of the second node N2 according to the potential of the third node N3;

[0638] The third node control circuit 13 is electrically connected with the second low voltage line VGL2, the third node N3 and the fifth node N5 respectively, and is used for controlling the potential of the third node N3 according to the potential of the fifth node N5 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0639] The fifth node control circuit 15 is electrically connected with the first clock signal terminal CK1, the fourth node N4 and the fifth node N5 respectively, and is used for controlling the potential of the fifth node N5 according to the clock signal provided by the first clock signal terminal CK1 under the control of the potential of the fourth node N4;

[0640] The fifth node control circuit 15 is also electrically connected with the fifth node N5, the fourth clock signal terminal CK4 and the second low voltage line VGL2 respectively, and is used for writing the second low voltage signal provided by the second low voltage line VGL2 into the fifth node N5 under the control of the clock signal provided by the fourth clock signal line CK4;

[0641] The fourth node control circuit 14 is electrically connected with the input terminal I1, the fourth clock signal terminal CK4 and the fourth node N4 respectively, and is used for writing the input signal provided by the input terminal I1 into the fourth node N4 under the control of the clock signal provided by the fourth clock signal terminal CK4;

[0642] The fourth node control circuit 14 is also electrically connected with the control line VEL and the second high voltage line VGH2 respectively, and is used for writing the second high voltage signal provided by the second high voltage line VGH2 into the fourth node N4 under the control of the control signal provided by the control line VEL;

[0643] The seventh node control circuit 17 is electrically connected with the second low voltage line VGL2, the fourth node N4 and the seventh node N7 respectively, and is used for controlling the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0644] The sixth node control circuit 16 is electrically connected with the sixth node N6, the second high voltage line VGH2, the fifth node N5, the second clock signal terminal CK2 and the eighth node N8 respectively, and is configured to write a clock signal provided by the second clock signal terminal CK2 into the sixth node under control of a potential of the eighth node N8, and write a second high voltage signal provided by the second high voltage line VGH2 into the sixth node N6 under control of a potential of the fifth node N5;

[0645] The eighth node control circuit 18 is electrically connected with the sixth node N6 and the eighth node N8 respectively, and is configured to control a potential of the eighth node N8 according to a potential of the sixth node N6;

[0646] The input control circuit 110 is electrically connected with the input terminal I1, the fourth clock signal terminal CK4, the second low voltage line VGL2, the ninth node N9 and the eighth node N8 respectively, and is configured to write an input signal provided by the input terminal I1 into the ninth node N9 under control of a clock signal provided by the fourth clock signal terminal CK4, and control communication between the ninth node N9 and the eighth node N8 under control of a second low voltage signal provided by the second low voltage line VGL2;

[0647] The seventh node voltage control circuit 19 is electrically connected with the eighth node N8 and the seventh node N7 respectively, and is configured to control a potential of the seventh node N7 according to a potential of the eighth node N8;

[0648] The first node potential maintaining circuit 21 is configured to maintain a potential of the first node N1;

[0649] The output reset circuit 20 is electrically connected with the seventh node N7, the drive output terminal OT and the first low voltage line VGL1 respectively, and is configured to write a first low voltage signal provided by the first low voltage line VGL1 into the drive output terminal OT under control of a potential of the seventh node N7.

[0650] In at least one embodiment of the present disclosure, the driving module can include a multi-stage driving circuit;

[0651] The first clock signal terminal of the 4a-3 stage driving circuit can be electrically connected with the first clock signal line, the second clock signal terminal of the 4a-3 stage driving circuit can be electrically connected with the second clock signal line, the third clock signal terminal of the 4a-3 stage driving circuit can be electrically connected with the third clock signal line, and the fourth clock signal terminal of the 4a-3 stage driving circuit can be electrically connected with the fourth clock signal line;

[0652] The first clock signal end of the 4a-2 level driving circuit can be electrically connected with the second clock signal line, the second clock signal end of the 4a-2 level driving circuit can be electrically connected with the third clock signal line, the third clock signal end of the 4a-2 level driving circuit can be electrically connected with the fourth clock signal line, and the fourth clock signal end of the 4a-2 level driving circuit can be electrically connected with the first clock signal line;

[0653] The first clock signal end of the 4a-1 level driving circuit can be electrically connected with the third clock signal line, the second clock signal end of the 4a-1 level driving circuit can be electrically connected with the fourth clock signal line, the third clock signal end of the 4a-1 level driving circuit can be electrically connected with the first clock signal line, and the fourth clock signal end of the 4a-1 level driving circuit can be electrically connected with the second clock signal line;

[0654] The first clock signal end of the 4a level driving circuit can be electrically connected with the fourth clock signal line, the second clock signal end of the 4a level driving circuit can be electrically connected with the first clock signal line, the third clock signal end of the 4a level driving circuit can be electrically connected with the second clock signal line, and the fourth clock signal end of the 4a level driving circuit can be electrically connected with the third clock signal line;

[0655] a is a positive integer.

[0656] As shown in FIG. 37B, the driving circuit includes a driving output circuit 10, a first node control circuit 11, a second node control circuit 12, a third node control circuit 13, a fourth node control circuit 14, a fifth node control circuit 15, a sixth node control circuit 16, a first node potential maintaining circuit 21, a seventh node control circuit 17, an eighth node control circuit 18, a seventh node voltage control circuit 19, an input control circuit 110, and an output reset circuit 20 according to at least one embodiment of the present disclosure.

[0657] The driving output circuit 10 is electrically connected with a first node N1, a first high voltage line VGH1, and a driving output terminal OT, respectively, and is configured to control the driving output terminal OT to be in communication or disconnected with the first high voltage line VGH1 under the control of the potential of the first node N1.

[0658] The first node control circuit 11 is electrically connected with a first clock signal line CLK1, the first node N1, and a second node N2, respectively, and is configured to control the potential of the first node N1 according to the potential of the second node N2 under the control of a first clock signal provided by the first clock signal line CLK1.

[0659] The first node control circuit 11 is also electrically connected with the fourth node N4 and the second high voltage line VGH2 respectively, for controlling the communication between the first node N1 and the second high voltage line VGH2 under the control of the potential of the fourth node N4;

[0660] The second node control circuit 12 is electrically connected with the first clock signal line CLK1, the second node N2 and the third node N3 respectively, for controlling the potential of the second node N2 according to the second clock signal provided by the first clock signal line CLK1 under the control of the potential of the third node N3, and controlling the potential of the second node N2 according to the potential of the third node N3;

[0661] The third node control circuit 13 is electrically connected with the second low voltage line VGL2, the third node N3 and the fifth node N5 respectively, for controlling the potential of the third node N3 according to the potential of the fifth node N5 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0662] The fifth node control circuit 15 is electrically connected with the fourth clock signal line CLK4, the fourth node N4 and the fifth node N5 respectively, for controlling the potential of the fifth node N5 according to the fourth clock signal provided by the fourth clock signal line CLK4 under the control of the potential of the fourth node N4;

[0663] The fifth node control circuit 15 is also electrically connected with the fifth node N5, the third clock signal line CLK3 and the second low voltage line VGL2 respectively, for writing the second low voltage signal provided by the second low voltage line VGL2 into the fifth node N5 under the control of the third clock signal provided by the third clock signal line CLK3;

[0664] The fourth node control circuit 14 is electrically connected with the input terminal I1, the third clock signal line CLK3 and the fourth node N4 respectively, for writing the input signal provided by the input terminal I1 into the fourth node N4 under the control of the third clock signal provided by the third clock signal line CLK3;

[0665] The fourth node control circuit 14 is also electrically connected with the control line VEL and the second high voltage line VGH2 respectively, for writing the second high voltage signal provided by the second high voltage line VGH2 into the fourth node N4 under the control of the control signal provided by the control line VEL;

[0666] The seventh node control circuit 17 is electrically connected with the second low voltage line VGL2, the fourth node N4 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the fourth node N4 under the control of the second low voltage signal provided by the second low voltage line VGL2;

[0667] The sixth node control circuit 16 is electrically connected with the sixth node N6, the second high voltage line VGH2, the fifth node N5, the second clock signal line CLK2 and the eighth node N8 respectively, and is configured to write the second clock signal provided by the second clock signal line CLK2 into the sixth node under the control of the potential of the eighth node N8, and write the second high voltage signal provided by the second high voltage line VGH2 into the sixth node N6 under the control of the potential of the fifth node N5.

[0668] The eighth node control circuit 18 is electrically connected with the sixth node N6 and the eighth node N8 respectively, and is configured to control the potential of the eighth node N8 according to the potential of the sixth node N6.

[0669] The input control circuit 110 is electrically connected with the input terminal I1, the third clock signal line CLK3, the second low voltage line VGL2, the ninth node N9 and the eighth node N8 respectively, and is configured to write the input signal provided by the input terminal I1 into the ninth node N9 under the control of the third clock signal provided by the third clock signal line CLK3, and control the communication between the ninth node N9 and the eighth node N8 under the control of the second low voltage signal provided by the second low voltage line VGL2.

[0670] The seventh node voltage control circuit 19 is electrically connected with the eighth node N8 and the seventh node N7 respectively, and is configured to control the potential of the seventh node N7 according to the potential of the eighth node N8.

[0671] The first node potential maintaining circuit 21 is configured to maintain the potential of the first node N1.

[0672] The output reset circuit 20 is electrically connected with the seventh node N7, the driving output terminal OT and the first low voltage line VGL1 respectively, and is configured to write the first low voltage signal provided by the first low voltage line VGL1 into the driving output terminal OT under the control of the potential of the seventh node N7.

[0673] In at least one embodiment shown in FIG. 37B, on the basis of at least one embodiment shown in FIG. 37A, the first clock signal terminal CK1 is the fourth clock signal line CLK4, the second clock signal terminal CK2 is the second clock signal line CLK2, the third clock signal terminal CK3 is the first clock signal line CLK1, and the fourth clock signal terminal CK4 is the third clock signal line CLK3.

[0674] As shown in FIG. 38A, on the basis of at least one embodiment of the driving circuit shown in FIG. 37A, the first node control circuit comprises a first transistor T1 and a third transistor T3; the second node control circuit comprises a first capacitor C1 and a fourth transistor T4; the output reset circuit comprises a second transistor T2;

[0675] The gate of the first transistor T1 is electrically connected with a third clock signal terminal CK3, the first electrode of the first transistor T1 is electrically connected with a second node N2, and the second electrode of the first transistor T1 is electrically connected with a first node N1;

[0676] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with a second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node N1;

[0677] The gate of the second transistor T2 is electrically connected with a seventh node N7, the first electrode of the second transistor T2 is electrically connected with a driving output terminal OT, and the second electrode of the second transistor T2 is electrically connected with a first low voltage line VGL1;

[0678] The first plate of the first capacitor C1 is electrically connected with a third node N3, and the second plate of the first capacitor C1 is electrically connected with the second node N2;

[0679] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the third clock signal terminal CK3, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2;

[0680] The third node control circuit 13 comprises a fifth transistor T5;

[0681] The gate of T5 is electrically connected with a second low voltage line VGL2, the first electrode of T5 is electrically connected with a fifth node N5, and the second electrode of T5 is electrically connected with the third node N3;

[0682] The fourth node control circuit 14 comprises a sixth transistor T6 and a thirteenth transistor T13;

[0683] The gate of T6 is electrically connected with a fourth clock signal terminal CK4, the first electrode of T6 is electrically connected with an input terminal I1, and the second electrode of T6 is electrically connected with the fourth node N4;

[0684] The gate of T13 is electrically connected with a control line VEL, the first electrode of T13 is electrically connected with the second high voltage line VGH2, and the second electrode of T13 is electrically connected with the fourth node N4;

[0685] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0686] The gate of the T7 is electrically connected with the fourth node N4, the first electrode of the T7 is electrically connected with the first clock signal terminal CK1, and the second electrode of the T7 is electrically connected with the fifth node N5;

[0687] The gate of the T8 is electrically connected with the fourth clock signal terminal CK4, the first electrode of the T8 is electrically connected with the second low voltage line VGL2, and the second electrode of the T8 is electrically connected with the fifth node N5;

[0688] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0689] The gate of the T9 is electrically connected with the fifth node N5, the first electrode of the T9 is electrically connected with the second high voltage line VGH2, and the second electrode of the T9 is electrically connected with the sixth node N6;

[0690] The gate of the T10 is electrically connected with the eighth node N8, the first electrode of the T10 is electrically connected with the sixth node N6, and the second electrode of the T10 is electrically connected with the second clock signal terminal CK2;

[0691] The first node potential maintaining circuit comprises a second capacitor C2;

[0692] The first plate of the C2 is electrically connected with the first node N1, and the second plate of the C2 is electrically connected with the first high voltage line VGH1;

[0693] The seventh node control circuit comprises an eleventh transistor T11;

[0694] The gate of the T11 is electrically connected with the second low voltage line VGL2, the first electrode of the T11 is electrically connected with the fourth node N4, and the second electrode of the T11 is electrically connected with the seventh node N7;

[0695] The eighth node control circuit comprises a third capacitor C3;

[0696] The first plate of the C3 is electrically connected with the sixth node N6, and the second plate of the C3 is electrically connected with the seventh node N7;

[0697] The input control circuit comprises a fourteenth transistor T14 and a fifteenth transistor T15;

[0698] The gate of the T14 is electrically connected with the fourth clock signal terminal CK4, the first electrode of the T14 is electrically connected with the input terminal I1, and the second electrode of the T14 is electrically connected with the ninth node N9;

[0699] The gate of the T15 is electrically connected with the second low voltage line VGL2, the first electrode of the T15 is electrically connected with the ninth node N9, and the second electrode of the T15 is electrically connected with the eighth node N8.

[0700] The seventh node voltage control circuit comprises a sixteenth transistor T16;

[0701] The gate of T16 and the first electrode of T16 are electrically connected with an eighth node N8, and the second electrode of T16 is electrically connected with the seventh node N7;

[0702] The drive output circuit comprises a twelfth transistor T12;

[0703] The gate of T12 is electrically connected with the first node N1, the first electrode of T12 is electrically connected with a first high voltage line VGH1, and the second electrode of T12 is electrically connected with the drive output terminal OT.

[0704] FIG. 38C is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A, according to at least one embodiment of the present disclosure;

[0705] FIG. 38D is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A, according to at least one embodiment of the present disclosure;

[0706] FIG. 38E is a timing diagram of the clock signal provided by CK1, the clock signal provided by CK2, the clock signal provided by CK3, and the clock signal provided by CK4 in FIG. 38A, according to at least one embodiment of the present disclosure.

[0707] As shown in FIG. 38B, on the basis of at least one embodiment of the drive circuit shown in FIG. 37B, the first node control circuit comprises a first transistor T1 and a third transistor T3; the second node control circuit comprises a first capacitor C1 and a fourth transistor T4; and the output reset circuit comprises a second transistor T2;

[0708] The gate of the first transistor T1 is electrically connected with a first clock signal line CLK1, the first electrode of the first transistor T1 is electrically connected with a second node N2, and the second electrode of the first transistor T1 is electrically connected with the first node N1;

[0709] The gate of the third transistor T3 is electrically connected with the fourth node N4, the first electrode of the third transistor T3 is electrically connected with a second high voltage line VGH2, and the second electrode of the third transistor T3 is electrically connected with the first node N1;

[0710] The gate of the second transistor T2 is electrically connected with the seventh node N7, the first electrode of the second transistor T2 is electrically connected with the drive output terminal OT, and the second electrode of the second transistor T2 is electrically connected with a first low voltage line VGL1;

[0711] The first plate of the first capacitor C1 is electrically connected with the third node N3, and the second plate of the first capacitor C1 is electrically connected with the second node N2;

[0712] The gate of the fourth transistor T4 is electrically connected with the third node N3, the first electrode of the fourth transistor T4 is electrically connected with the first clock signal line CLK1, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2;

[0713] The third node control circuit 13 comprises a fifth transistor T5;

[0714] The gate of the T5 is electrically connected with the second low voltage line VGL2, the first electrode of the T5 is electrically connected with the fifth node N5, and the second electrode of the T5 is electrically connected with the third node N3;

[0715] The fourth node control circuit 14 comprises a sixth transistor T6 and a thirteenth transistor T13;

[0716] The gate of the T6 is electrically connected with the third clock signal line CLK3, the first electrode of the T6 is electrically connected with the input terminal I1, and the second electrode of the T6 is electrically connected with the fourth node N4;

[0717] The gate of the T13 is electrically connected with the control line VEL, the first electrode of the T13 is electrically connected with the second high voltage line VGH2, and the second electrode of the T13 is electrically connected with the fourth node N4;

[0718] The fifth node control circuit 15 comprises a seventh transistor T7 and an eighth transistor T8;

[0719] The gate of the T7 is electrically connected with the fourth node N4, the first electrode of the T7 is electrically connected with the fourth clock signal line CLK4, and the second electrode of the T7 is electrically connected with the fifth node N5;

[0720] The gate of the T8 is electrically connected with the third clock signal line CLK3, the first electrode of the T8 is electrically connected with the second low voltage line VGL2, and the second electrode of the T8 is electrically connected with the fifth node N5;

[0721] The sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0722] The gate of the T9 is electrically connected with the fifth node N5, the first electrode of the T9 is electrically connected with the second high voltage line VGH2, and the second electrode of the T9 is electrically connected with the sixth node N6;

[0723] The gate of the T10 is electrically connected with the eighth node N8, the first electrode of the T10 is electrically connected with the sixth node N6, and the second electrode of the T10 is electrically connected with the second clock signal line CLK2;

[0724] The first node potential maintaining circuit comprises a second capacitor C2;

[0725] the first node N1 of the first plate of C2 is electrically connected, and the second plate of C2 is electrically connected with the first high voltage line VGH1;

[0726] the seventh node control circuit comprises an eleventh transistor T11;

[0727] the gate of T11 is electrically connected with the second low voltage line VGL2, the first electrode of T11 is electrically connected with the fourth node N4, and the second electrode of T11 is electrically connected with the seventh node N7;

[0728] the eighth node control circuit comprises a third capacitor C3;

[0729] the first plate of C3 is electrically connected with the sixth node N6, and the second plate of C3 is electrically connected with the seventh node N7;

[0730] the input control circuit comprises a fourteenth transistor T14 and a fifteenth transistor T15;

[0731] the gate of T14 is electrically connected with the third clock signal line CLK3, the first electrode of T14 is electrically connected with the input terminal I1, and the second electrode of T14 is electrically connected with the ninth node N9;

[0732] the gate of T15 is electrically connected with the second low voltage line VGL2, the first electrode of T15 is electrically connected with the ninth node N9, and the second electrode of T15 is electrically connected with the eighth node N8;

[0733] the seventh node voltage control circuit comprises a sixteenth transistor T16;

[0734] the gate of T16 and the first electrode of T16 are both electrically connected with the eighth node N8, and the second electrode of T16 is electrically connected with the seventh node N7;

[0735] the driving output circuit comprises a twelfth transistor T12;

[0736] the gate of T12 is electrically connected with the first node N1, the first electrode of T12 is electrically connected with the first high voltage line VGH1, and the second electrode of T12 is electrically connected with the driving output terminal OT.

[0737] In at least one embodiment shown in FIG. 38B, on the basis of at least one embodiment shown in FIG. 38A, the first clock signal terminal CK1 is the fourth clock signal line CLK4, the second clock signal terminal CK2 is the second clock signal line CLK2, the third clock signal terminal CK3 is the first clock signal line CLK1, and the fourth clock signal terminal CK4 is the third clock signal line CLK3.

[0738] FIG. 39 is a layout of a display substrate according to at least one embodiment of the present disclosure. In at least one embodiment of FIG. 39, the display substrate includes at least one embodiment of the driving circuit of FIG. 38B.

[0739] FIG. 40 is a layout of the semiconductor layer in FIG. 39, FIG. 41 is a layout of the first gate metal layer in FIG. 39, FIG. 42 is a layout of the second gate metal layer in FIG. 39, FIG. 43 is a layout of the first source-drain metal layer in FIG. 39, FIG. 44 is a layout of the second source-drain metal layer in FIG. 39, FIG. 45 is a layout of the semiconductor layer and the first gate metal layer in FIG. 39, FIG. 46 is a layout of the first gate metal layer and the second gate metal layer in FIG. 39, FIG. 47 is a layout of the second gate metal layer and the first source-drain metal layer in FIG. 39, and FIG. 48 is a layout of the first source-drain metal layer and the second source-drain metal layer in FIG. 39.

[0740] As shown in FIGS. 39-48, the first high-voltage line portion VGH11, the second high-voltage line portion VGH21, the second high-voltage line VGH2, the first low-voltage line VGL1, the second low-voltage line VGL2, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 are disposed on one side of the source base of the transistors and the capacitors included in the driving circuit, so as to layout three high-voltage lines, four clock signal lines, and two low-voltage lines under the premise of being able to achieve a narrow frame.

[0741] In at least one embodiment of the present disclosure, the driving circuit includes a driving output circuit; the plurality of signal lines includes a first first high-voltage line; the first first high-voltage line includes a first voltage line portion and a second voltage line portion; and the plurality of signal lines further includes a first second voltage line.

[0742] The driving output circuit is electrically connected with a first node, a first first voltage line, and a driving output terminal respectively, and is configured to control the driving output terminal to be in communication or disconnected with the first first voltage line under the control of the potential of the first node.

[0743] The active pattern of at least one transistor included in the driving output circuit at least partially overlaps the active pattern of at least one transistor included in the driving output circuit.

[0744] The active pattern of at least one transistor included in the driving output circuit at least partially overlaps the active pattern of at least one transistor included in the driving output circuit.

[0745] As shown in FIGS. 39-48, the plurality of signal lines includes a first high-voltage line, the first high-voltage line includes a first high-voltage line portion VGH11 and a first high-voltage line portion VGH21, and the plurality of signal lines further includes a first low-voltage line VGL1; VGH11 and VGH21 both extend along a vertical direction;

[0746] The driving output circuit includes a twelfth transistor T12;

[0747] A projection on a substrate of an active pattern A12 of T12 at least partially overlaps a projection on the substrate of VGH11;

[0748] A projection on the substrate of the active pattern A12 of T12 at least partially overlaps a projection on the substrate of VGL1;

[0749] Through the above arrangement, the transverse space can be saved, and narrow frame can be realized.

[0750] As shown in FIG. 39, the plurality of signal lines includes a first high-voltage line, the first high-voltage line includes a first high-voltage line portion VGH11 and a first high-voltage line portion VGH21, and VGH11 and VGH21 both extend along a vertical direction; by arranging the first high-voltage line to include two high-voltage line portions, the resistance of the first high-voltage line can be reduced, and the voltage drop on the first high-voltage line can be reduced.

[0751] In at least one embodiment of the present disclosure, the driving circuit includes an output reset circuit;

[0752] The output reset circuit is electrically connected with a seventh node, a driving output end, and a first second voltage line, and is configured to write a voltage signal provided by the first second voltage line into the driving output end under control of an electric potential of the seventh node;

[0753] A projection on a substrate of an active pattern of at least one transistor included in the output reset circuit at least partially overlaps a projection on the substrate of the first voltage line portion;

[0754] A projection on the substrate of the active pattern of the at least one transistor included in the output reset circuit at least partially overlaps a projection on the substrate of the first second voltage line.

[0755] Optionally, the first voltage line portion can be a first high-voltage line portion, and the second voltage line portion can be a second high-voltage line portion.

[0756] As shown in FIGS. 39-48, the output reset circuit includes a second transistor T2;

[0757] A projection on a substrate of an active pattern A9 of T9 at least partially overlaps a projection on the substrate of VGH11;

[0758] A9 is at least partially overlapped with the orthographic projection of VGL1 on the substrate;

[0759] By setting the first high-voltage line to include two columns of high-voltage line parts, the resistance of the first high-voltage line can be reduced, and the voltage drop on the first high-voltage line can be reduced.

[0760] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit and a second node control circuit;

[0761] The first node control circuit is electrically connected with the first clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of the first clock signal provided by the first clock signal line;

[0762] The second node control circuit is electrically connected with the first clock signal line, the second node and the third node respectively, and is configured to control the potential of the second node according to the first clock signal provided by the first clock signal line under the control of the potential of the third node, and control the potential of the second node according to the potential of the third node;

[0763] The orthographic projection of the at least one capacitor included in the second node control circuit on the substrate is at least partially overlapped with the orthographic projection of the third clock signal line on the substrate;

[0764] The orthographic projection of the at least one capacitor included in the second node control circuit on the substrate is at least partially overlapped with the orthographic projection of the second first voltage line on the substrate.

[0765] Optionally, the second first voltage line can be a second high-voltage line.

[0766] As shown in FIGS. 39-48, the second node control circuit includes a first capacitor C1;

[0767] The orthographic projection of the first plate C1a of C1 on the substrate is at least partially overlapped with the orthographic projection of the third clock signal line CLK3 on the substrate; and the orthographic projection of the first plate C1a of C1 on the substrate is at least partially overlapped with the orthographic projection of the second high-voltage line VGH2 on the substrate;

[0768] The orthographic projection of the second plate C1b of C1 on the substrate is at least partially overlapped with the orthographic projection of the third clock signal line CLK3 on the substrate; and the orthographic projection of the second plate C1b of C1 on the substrate is at least partially overlapped with the orthographic projection of the second high-voltage line VGH2 on the substrate;

[0769] Through the above arrangement, the transverse space can be saved, and narrow frame can be realized.

[0770] In at least one embodiment of the present disclosure, the plurality of signal lines further comprise a control line; at least part of the active pattern of at least one transistor comprised in the first node control circuit is arranged between the orthogonal projection of the control line on the substrate and the orthogonal projection of the second voltage line portion on the substrate;

[0771] The orthogonal projection of the active pattern of at least one transistor comprised in the second node control circuit on the substrate at least partially overlaps with the orthogonal projection of the second first voltage line on the substrate.

[0772] As shown in FIGS. 39-48, the plurality of signal lines further comprise a control line VEL; the first node control circuit comprises a first transistor T1;

[0773] At least part of the orthogonal projection of the active pattern A1 of T1 on the substrate is arranged between the orthogonal projection of the control line VEL on the substrate and the orthogonal projection of the second high voltage line portion VGH21 on the substrate;

[0774] The second node control circuit comprises a fourth transistor T4;

[0775] The orthogonal projection of the active pattern A4 of T4 on the substrate is between the orthogonal projection of the second high voltage line VGH2 on the substrate;

[0776] Through the above arrangement, the transverse space can be saved, and narrow frame can be achieved.

[0777] In at least one embodiment of the present disclosure, the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, for controlling the communication between the first node and the second first voltage line under the control of the potential of the fourth node;

[0778] At least part of the orthogonal projection of the active pattern of at least one transistor comprised in the first node control circuit on the substrate is arranged between the orthogonal projection of the second first voltage line on the substrate and the orthogonal projection of the control line on the substrate.

[0779] As shown in FIGS. 39-48, the first node control circuit comprises a third transistor T3;

[0780] At least part of the orthogonal projection of the active pattern A3 of T3 on the substrate is arranged between the orthogonal projection of the second high voltage line VGH2 on the substrate and the orthogonal projection of the control line VEL on the substrate, so as to save the transverse space and facilitate the realization of narrow frame.

[0781] In at least one embodiment of the present disclosure, the driving circuit comprises a first node potential maintaining circuit; the first node potential maintaining circuit is used for maintaining the potential of the first node;

[0782] The first node potential maintaining circuit includes a second capacitor; a positive projection of a plate of the second capacitor on the substrate at least partially overlaps a positive projection of the second voltage line portion on the substrate.

[0783] Optionally, the second voltage line portion can be a second high voltage line portion.

[0784] As shown in FIGS. 39-48, the first node potential maintaining circuit includes a second capacitor C2;

[0785] A positive projection of a first plate C2a of C2 on the substrate at least partially overlaps a positive projection of the second high voltage line portion VGH21 on the substrate, and a positive projection of a second plate C2b of C2 on the substrate at least partially overlaps a positive projection of the second high voltage line portion VGH21 on the substrate, so as to save a horizontal space and facilitate narrow frame implementation.

[0786] In at least one embodiment of the present disclosure, the driving circuit includes a third node control circuit and a fifth node control circuit;

[0787] The third node control circuit is electrically connected with the second voltage line, the third node and the fifth node respectively, and is configured to control the potential of the third node according to the potential of the fifth node under the control of a voltage signal provided by the second voltage line;

[0788] The fifth node control circuit is electrically connected with the fourth clock signal line, the fourth node and the fifth node respectively, and is configured to control the potential of the fifth node according to a fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node;

[0789] A positive projection of an active pattern of at least one transistor included in the third node control circuit on the substrate at least partially overlaps a positive projection of the fourth clock signal line on the substrate;

[0790] A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the second clock signal line on the substrate.

[0791] As shown in FIGS. 39-48, the third node control circuit includes a fifth transistor T5, and the fifth node control circuit includes a seventh transistor T7;

[0792] A positive projection of an active pattern A11 of T11 on the substrate at least partially overlaps a positive projection of the fourth clock signal line CLK4 on the substrate;

[0793] A positive projection of an active pattern A7 of T7 on the substrate at least partially overlaps a positive projection of the second clock signal line CLK2 on the substrate;

[0794] Through the above arrangement, transverse space can be saved, and narrow frame can be realized.

[0795] In the display substrate, the plurality of signal lines further include a first second voltage line and a second second voltage line arranged on the substrate.

[0796] The driving circuit further includes a fourth node control circuit and a seventh node control circuit.

[0797] The fourth node control circuit is electrically connected with an input end, a third clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input end into the fourth node under control of a third clock signal provided by the third clock signal line.

[0798] The seventh node control circuit is electrically connected with the second second voltage line, the fourth node and a seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the fourth node under control of a voltage signal provided by the second second voltage line.

[0799] An active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps a projection of the fourth clock signal line on the substrate.

[0800] An active pattern of at least one transistor included in the seventh node control circuit at least partially overlaps a projection of the second first voltage line on the substrate.

[0801] As shown in FIGS. 39-48, the plurality of signal lines further include a first low voltage line VGL1 and a second low voltage line VGL2 arranged on the substrate.

[0802] The fourth node control circuit includes a sixth transistor T6, and the seventh node control circuit includes an eleventh transistor T11.

[0803] An active pattern A1 of T1 at least partially overlaps a projection of the fourth clock signal line CLK4 on the substrate.

[0804] An active pattern A12 of T12 at least partially overlaps a projection of the second high voltage line VGH2 on the substrate.

[0805] Through the above arrangement, transverse space can be saved, and narrow frame can be realized.

[0806] In at least one embodiment of the present disclosure, the driving circuit comprises a fifth node control circuit; the fifth node control circuit is electrically connected with the fifth node, the third clock signal line and the second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the fifth node under the control of a third clock signal provided by the third clock signal line;

[0807] The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the active pattern of the first clock signal line on the substrate.

[0808] As shown in FIGS. 39-48, the fifth node control circuit comprises an eighth transistor T8;

[0809] At least part of the active pattern A8 of T8 at least partially overlaps the active pattern of the first clock signal line CLK1 on the substrate, so as to save the lateral space and facilitate the realization of narrow frame.

[0810] In at least one embodiment of the present disclosure, the driving circuit comprises a sixth node control circuit;

[0811] The sixth node control circuit is electrically connected with the sixth node, the second first voltage line, the fifth node, the second clock signal line and the eighth node respectively, and is configured to write a second clock signal provided by the second clock signal line into the sixth node under the control of the potential of the eighth node, and write a voltage signal provided by the second first voltage line into the sixth node under the control of the potential of the fifth node;

[0812] The active pattern of at least one transistor included in the sixth node control circuit at least partially overlaps the active pattern of the third clock signal line on the substrate.

[0813] The active pattern of at least one transistor included in the sixth node control circuit at least partially overlaps the active pattern of the first clock signal line on the substrate.

[0814] As shown in FIGS. 39-48, the sixth node control circuit comprises a ninth transistor T9 and a tenth transistor T10;

[0815] The active pattern A9 of T9 at least partially overlaps the active pattern of the third clock signal line CLK3 on the substrate;

[0816] The active pattern A10 of T10 at least partially overlaps the active pattern of the first clock signal line CLK1 on the substrate;

[0817] Through the above arrangement, the lateral space can be saved, and the realization of narrow frame is facilitated.

[0818] In at least one embodiment of the present disclosure, A1 is an active pattern of T1, A2 is an active pattern of T2, A3 is an active pattern of T3, A4 is an active pattern of T4, A5 is an active pattern of T5, A6 is an active pattern of T6, A7 is an active pattern of T7, A8 is an active pattern of T8, A9 is an active pattern of T9, A10 is an active pattern of T10, A11 is an active pattern of T11, A12 is an active pattern of T12, A13 is an active pattern of T13, A14 is an active pattern of T14, A15 is an active pattern of T15, and A16 is an active pattern of T16.

[0819] The display substrate in at least one embodiment of the present disclosure further includes an eighth node control circuit; the eighth node control circuit is electrically connected with the sixth node and the eighth node respectively, and is configured to control the potential of the eighth node according to the potential of the sixth node; and the plurality of signal lines further include a first second voltage line;

[0820] The eighth node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the second second voltage line on the substrate;

[0821] The eighth node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the first clock signal line on the substrate;

[0822] The eighth node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the fourth clock signal line on the substrate;

[0823] The eighth node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps a projection of the second clock signal line on the substrate.

[0824] As shown in FIGS. 39-48, the eighth node control circuit includes a third capacitor C3;

[0825] A projection of a first plate C3a of C3 on the substrate at least partially overlaps a projection of the first clock signal line CLK1 on the substrate; a projection of the first plate C3a of C3 on the substrate at least partially overlaps a projection of the second low voltage line VGL2 on the substrate; a projection of the first plate C3a of C3 on the substrate at least partially overlaps a projection of the fourth clock signal line CLK4 on the substrate; and a projection of the first plate C3a of C3 on the substrate at least partially overlaps a projection of the second clock signal line CLK2 on the substrate.

[0826] The orthogonal projection of the second plate C3b of the C3 on the substrate at least partially overlaps the orthogonal projection of the first clock signal line CLK1 on the substrate; the orthogonal projection of the second plate C3b of the C3 on the substrate at least partially overlaps the orthogonal projection of the second low voltage line VGL2 on the substrate; the orthogonal projection of the second plate C3b of the C3 on the substrate at least partially overlaps the orthogonal projection of the fourth clock signal line CLK4 on the substrate; the orthogonal projection of the second plate C3b of the C3 on the substrate at least partially overlaps the orthogonal projection of the second clock signal line CLK2 on the substrate;

[0827] Through the above arrangement, the transverse space can be saved, and narrow frame can be achieved.

[0828] In at least one embodiment of the present disclosure, the driving circuit comprises a fourth node control circuit; the plurality of signal lines further comprises a control line;

[0829] The fourth node control circuit is electrically connected with the control line, the second first voltage line and the fourth node respectively, and is configured to write a voltage signal provided by the second first voltage line into the fourth node under the control of a control signal provided by the control line.

[0830] At least part of the active pattern of at least one transistor included in the fourth node control circuit is arranged between the orthogonal projection of the second first voltage line on the substrate and the orthogonal projection of the control line on the substrate.

[0831] Optionally, the second first voltage line can be a second high voltage line.

[0832] As shown in FIGS. 39-48, the fourth node control circuit comprises a thirteenth transistor T13; the plurality of signal lines further comprises a control line VEL;

[0833] At least part of the orthogonal projection of the active pattern A13 of the T13 on the substrate is arranged between the orthogonal projection of the second high voltage line VGH2 on the substrate and the orthogonal projection of the VEL on the substrate, so as to save the transverse space and facilitate the realization of narrow frame.

[0834] In at least one embodiment of the present disclosure, the driving circuit further comprises an input control circuit;

[0835] The input control circuit is electrically connected with an input terminal, a third clock signal line, a second second voltage line, a ninth node and an eighth node respectively, and is configured to write an input signal provided by the input terminal into the ninth node under the control of a third clock signal provided by the third clock signal line, and control the communication between the ninth node and the eighth node under the control of a voltage signal provided by the second second voltage line.

[0836] A projection of at least one transistor included in the input control circuit on the substrate at least partially overlaps a projection of the second voltage line on the substrate;

[0837] A projection of an active pattern of at least one transistor included in the input control circuit on the substrate at least partially overlaps a projection of the first clock signal line on the substrate.

[0838] As shown in FIGS. 39-48, the input control circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0839] A projection of an active pattern A15 of T15 on the substrate at least partially overlaps a projection of VGL2 on the substrate;

[0840] A projection of an active pattern A14 of T14 on the substrate at least partially overlaps a projection of the first clock signal line CLK1 on the substrate;

[0841] Through the above arrangement, transverse space can be saved, and narrow frame can be achieved.

[0842] In at least one embodiment of the present disclosure, the driving circuit further includes a seventh node voltage control circuit;

[0843] The seventh node voltage control circuit is electrically connected with an eighth node and a seventh node respectively, and is configured to control an electric potential of the seventh node according to an electric potential of the eighth node;

[0844] A projection of at least one transistor included in the seventh node voltage control circuit on the substrate at least partially overlaps a projection of the third clock signal line on the substrate;

[0845] A projection of at least one transistor included in the seventh node voltage control circuit on the substrate at least partially overlaps a projection of the second first voltage line on the substrate.

[0846] As shown in FIGS. 39-48, the seventh node voltage control circuit includes a sixteenth transistor T16;

[0847] A projection of an active pattern A16 of T16 on the substrate at least partially overlaps a projection of the third clock signal line CLK3 on the substrate;

[0848] A projection of the active pattern A16 of T16 on the substrate at least partially overlaps a projection of the second high voltage line VGH2 on the substrate;

[0849] Through the above arrangement, transverse space can be saved, and narrow frame can be achieved. In at least one embodiment of the present disclosure, the driving circuit includes an output reset circuit;

[0850] The output reset circuit is electrically connected with the seventh node, the driving output end and the first second voltage line, and is used for writing a voltage signal provided by the first second voltage line into the driving output end under the control of the potential of the seventh node.

[0851] The output reset circuit comprises a second transistor.

[0852] The gate of the second transistor is electrically connected with the first conductive pattern, the first electrode of the second transistor is electrically connected with the first second voltage line, and the second electrode of the second transistor is electrically connected with the driving output end through the second conductive pattern.

[0853] The orthographic projection of the first conductive pattern on the substrate at least partially overlaps the orthographic projection of the second conductive pattern on the substrate; and the first conductive pattern and the second conductive pattern are arranged in different layers.

[0854] As shown in FIGS. 39-48, the output reset circuit comprises a second transistor T2.

[0855] The gate G2 of the second transistor T2 is electrically connected with the first conductive pattern DX1, and the second electrode D2 of the second transistor T2 is electrically connected with the driving output end OT through the second conductive pattern DX2.

[0856] The orthographic projection of DX1 on the substrate at least partially overlaps the orthographic projection of DX2 on the substrate; and the overlapping area between the orthographic projection of DX1 on the substrate and the orthographic projection of DX2 on the substrate is greater than 100 μm 2 , for example, the overlapping area between the orthographic projection of DX1 on the substrate and the orthographic projection of DX2 on the substrate can be 200 μm 2 .

[0857] DX1 and DX2 generate a larger parasitic capacitance, so as to improve the step of the falling edge of the driving signal of the OT driving, and improve the stability of the driving signal output.

[0858] As shown in FIGS. 39-48, DX1 is formed in the first gate metal layer, and DX2 is formed in the first source-drain metal layer.

[0859] As shown in FIGS. 39-48, according to the principle of proximity, four clock signal lines are placed on the left side where transistors are relatively dense, the second low voltage line VGL2 is placed on the leftmost side, the first low voltage line VGL1 is placed on the rightmost side, the second high voltage line VGH2 is placed in the middle, and VGH11 is placed on the side away from the substrate of T12, so as to maximize the length and difficulty of signal line connection, save layout space, and improve space utilization.

[0860] As shown in FIGS. 39-48, VGL2, CLK1, CLK4, CLK2, CLK3, VGH2, VEL, VGH21, VGH11, and VGL1 all extend in the vertical direction;

[0861] VGL2, CLK1, CLK4, CLK2, CLK3, VGH2, VEL, VGH21, VGH11, and VGL1 are arranged in order along the side close to the display area.

[0862] The display device described in the embodiments of the present disclosure includes the display substrate described above.

[0863] The above describes the preferred embodiments of the present disclosure. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a substrate and a driving module disposed on the substrate, the driving module comprising a multi-stage driving circuit; the driving circuit comprising a plurality of devices, the plurality of devices comprising a plurality of transistors and at least one capacitor; the display substrate further comprising a plurality of signal lines disposed on the substrate, the plurality of signal lines comprising at least three clock signal lines and at least two first voltage lines; a normal projection of the signal lines on the substrate at least partially overlaps a normal projection of at least one of the devices on the substrate. 2.The display substrate of claim 1, wherein, the driving circuit comprises a driving output circuit; the driving output circuit is electrically connected with a first node, a first first voltage line and a driving output terminal respectively, and is configured to control the driving output terminal to be in communication or disconnected with the first first voltage line under the control of a potential of the first node; a normal projection of an active pattern of at least one transistor included in the driving output circuit on the substrate at least partially overlaps a normal projection of the first first voltage line on the substrate. 3.The display substrate of claim 1, wherein, the driving circuit comprises a first node control circuit and a second node control circuit; the first node control circuit is electrically connected with a first clock signal line, the first node and a second node respectively, and is configured to control a potential of the first node according to a potential of the second node under the control of a first clock signal provided by the first clock signal line; the second node control circuit is electrically connected with the first clock signal line, the second node and a third node respectively, and is configured to control a potential of the second node according to the first clock signal provided by the first clock signal line under the control of a potential of the third node, and control the potential of the second node according to the potential of the third node; a normal projection of a plate of at least one capacitor included in the second node control circuit on the substrate at least partially overlaps a normal projection of the first clock signal line on the substrate. 4.The display substrate of claim 3, wherein, a normal projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a normal projection of a second clock signal line on the substrate; a normal projection of an active pattern of at least one transistor included in the second node control circuit on the substrate at least partially overlaps a normal projection of a second first voltage line on the substrate. 5.The display substrate of claim 4, wherein, the first node control circuit comprises a first transistor; a gate of the first transistor is electrically connected with a first clock signal line; the gate of the first transistor is electrically connected with a first connection pattern; the first connection pattern is electrically connected with a second connection pattern, the first connection pattern and the second connection pattern are disposed in different layers; the second connection pattern is disposed in a layer different from the first clock signal line; and the second connection pattern is electrically connected with the first clock signal line. 6.The display substrate of claim 5, wherein, the second node control circuit comprises a first capacitor; a normal projection of a plate of the first capacitor on the substrate at least partially overlaps a normal projection of the second connection pattern on the substrate, and a normal projection of the plate of the first capacitor on the substrate at least partially overlaps a normal projection of the first clock signal line on the substrate. ​ 7.The display substrate of claim 4, wherein, The second first voltage line is arranged between the second clock signal line and the first clock signal line; The second first voltage line, the second clock signal line and the first clock signal line are arranged in the same layer. 8.The display substrate of claim 7, wherein, The first node control circuit is electrically connected with the fourth node and the second first voltage line respectively, and is used for controlling the communication between the first node and the second first voltage line under the control of the potential of the fourth node. The active pattern of at least one transistor included in the first node control circuit at least partially overlaps the projection of the second clock signal line on the substrate. 9.The display substrate of claim 1, wherein, The driving circuit comprises a first node potential maintaining circuit; the first node potential maintaining circuit is used for maintaining the potential of the first node; The first node potential maintaining circuit comprises a second capacitor; the projection of the plate of the second capacitor on the substrate at least partially overlaps the projection of the third clock signal line on the substrate. 10.The display substrate of claim 1, wherein, The driving circuit further comprises a third node control circuit and a fifth node control circuit; The third node control circuit is electrically connected with the second second voltage line, the third node and the fifth node respectively, and is used for controlling the potential of the third node according to the potential of the fifth node under the control of the voltage signal provided by the second second voltage line; The fifth node control circuit is electrically connected with the fourth clock signal line, the fourth node and the fifth node respectively, and is used for controlling the potential of the fifth node according to the fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node; The active pattern of at least one transistor included in the third node control circuit at least partially overlaps the projection of the fourth clock signal line on the substrate; The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the projection of the fourth clock signal line on the substrate. 11.The display substrate of claim 1, wherein, The driving circuit further comprises a fourth node control circuit and a seventh node control circuit; The fourth node control circuit is electrically connected with an input end, a third clock signal line and the fourth node respectively, and is used for writing the input signal provided by the input end into the fourth node under the control of the third clock signal provided by the third clock signal line; The seventh node control circuit is electrically connected with the second second voltage line, the fourth node and the seventh node respectively, and is used for controlling the potential of the seventh node according to the potential of the fourth node under the control of the voltage signal provided by the second second voltage line; The active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the projection of the fourth clock signal line on the substrate; The active pattern of at least one transistor included in the seventh node control circuit at least partially overlaps the projection of the fourth clock signal line on the substrate. ​ 12.The display substrate of claim 11, wherein, The fourth node control circuit includes at least one transistor, and a part of a projection of an active pattern of the transistor on the substrate is arranged between a projection of the fourth clock signal line on the substrate and a projection of the second second voltage line on the substrate. The fourth node control circuit includes at least one transistor, and a part of a projection of an active pattern of the transistor on the substrate is arranged between a projection of the fourth clock signal line on the substrate and a projection of the second second voltage line on the substrate. 13.The display substrate of claim 11, wherein, The driving circuit includes a fifth node control circuit; the fifth node control circuit is electrically connected with a fifth node, a third clock signal line and a second second voltage line respectively, and is used for writing a voltage signal provided by the second second voltage line into the fifth node under control of a third clock signal provided by the third clock signal line. The fifth node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate is arranged between a projection of the second second voltage line on the substrate and a projection of the fourth clock signal line on the substrate. 14.The display substrate of claim 1, wherein, The driving circuit includes a sixth node control circuit. The sixth node control circuit is electrically connected with a sixth node, a first first voltage line, a fifth node, a second clock signal line and a seventh node respectively, and is used for writing a second clock signal provided by the second clock signal line into the sixth node under control of a potential of the seventh node, and writing a voltage signal provided by the first first voltage line into the sixth node under control of a potential of the fifth node. The sixth node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps with a projection of the second clock signal line on the substrate. The sixth node control circuit includes at least one transistor, and a projection of an active pattern of the transistor on the substrate at least partially overlaps with a projection of the second first voltage line on the substrate. 15.The display substrate of claim 1, wherein, The driving circuit further includes a seventh node control circuit; the seventh node control circuit is electrically connected with the sixth node and the seventh node respectively, and is used for controlling a potential of the seventh node according to a potential of the sixth node. The seventh node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps with a projection of the fourth clock signal line on the substrate. The seventh node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps with a projection of the first clock signal line on the substrate. The seventh node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps with a projection of the second first voltage line on the substrate. The seventh node control circuit includes a capacitor, and a projection of a plate of the capacitor on the substrate at least partially overlaps with a projection of the second clock signal line on the substrate. The driving circuit includes an output reset circuit; and the plurality of signal lines further include a first second voltage line. 16.The display substrate of claim 1, wherein, The output reset circuit is electrically connected with the seventh node, a driving output end and the first second voltage line respectively, and is used for writing a voltage signal provided by the first second voltage line into the driving output end under control of a potential of the seventh node. ​ The active pattern of at least one transistor included in the output reset circuit at least partially overlaps the normal projection of the first voltage line on the substrate.

17. The display substrate of claim 16, wherein, The first second voltage line is arranged on the side of the transistor included in the output reset circuit close to the display area; no other transistor or capacitor is arranged between the first second voltage line and the transistor included in the output reset circuit. 18.The display substrate of claim 1, wherein, The driving circuit includes a first node control circuit; The first node control circuit is electrically connected with the fourth clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of the fourth clock signal provided by the fourth clock signal line. The active pattern of at least one transistor included in the first node control circuit at least partially overlaps the normal projection of the second clock signal line on the substrate.

19. The display substrate of claim 18, wherein, The first node control circuit includes a first transistor; the gate of the first transistor is electrically connected with the fourth clock signal line; The gate of the first transistor is electrically connected with a first connection pattern; the first connection pattern is electrically connected with a second connection pattern, and the first connection pattern and the second connection pattern are arranged in different layers; the second connection pattern is arranged in a layer different from the fourth clock signal line; and the second connection pattern is electrically connected with the fourth clock signal line.

20. The display substrate of claim 19, wherein, The driving circuit includes a fifth node control circuit; The fifth node control circuit is electrically connected with the fourth clock signal line, the fourth node and the fifth node respectively, and is configured to control the potential of the fifth node according to the fourth clock signal provided by the fourth clock signal line under the control of the potential of the fourth node. The active pattern of the transistor included in the fifth node control circuit at least partially overlaps the normal projection of the fourth clock signal line on the substrate. The second connection pattern is electrically connected with the fourth clock signal line through a first via hole; The normal projection of the boundary of the first via hole on the substrate does not overlap the normal projection of the channel of the transistor included in the fifth node control circuit on the substrate.

21. The display substrate of claim 1, wherein, The driving circuit includes a first node control circuit and a second node control circuit; The first node control circuit is electrically connected with the second clock signal line, the first node and the second node respectively, and is configured to control the potential of the first node according to the potential of the second node under the control of the second clock signal provided by the second clock signal line. The second node control circuit is electrically connected with the second clock signal line, the second node and the third node respectively, and is configured to control the potential of the second node according to the second clock signal provided by the second clock signal line under the control of the potential of the third node, and to control the potential of the second node according to the potential of the third node. The active pattern of at least one capacitor included in the second node control circuit at least partially overlaps the normal projection of the second first voltage line on the substrate. ​ 22. The display substrate of claim 21, wherein, The plurality of signal lines further include a control line; a positive projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

23. The display substrate of claim 1, wherein, The driving circuit includes a fourth node control circuit; the plurality of signal lines further include a control line; The fourth node control circuit is electrically connected with the control line, a second first voltage line and a fourth node respectively, and is configured to write a voltage signal provided by the second first voltage line into the fourth node under control of a control signal provided by the control line; A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate. A positive projection of an active pattern of at least one transistor included in the fourth node control circuit on the substrate at least partially overlaps a positive projection of the first clock signal line on the substrate.

24. The display substrate of claim 21, wherein, The plurality of signal lines further include a control line; the first node control circuit is further electrically connected with a fourth node and a second first voltage line respectively, and is configured to control communication between the first node and the second first voltage line under control of an electric potential of the fourth node; A positive projection of an active pattern of at least one transistor included in the first node control circuit on the substrate at least partially overlaps a positive projection of the control line on the substrate.

25. The display substrate of claim 1, wherein, The driving circuit includes a first node electric potential maintaining circuit; the first node electric potential maintaining circuit is configured to maintain an electric potential of the first node; The first node electric potential maintaining circuit includes a second capacitor; a positive projection of a plate of the second capacitor on the substrate at least partially overlaps a positive projection of a fourth clock signal line on the substrate; A part of the plate of the second capacitor has a positive projection on the substrate, which is arranged between a positive projection of the first clock signal line on the substrate and a positive projection of the fourth clock signal line on the substrate.

26. The display substrate of claim 1, wherein, The driving circuit includes a third node control circuit and a fifth node control circuit; The third node control circuit is electrically connected with a first second voltage line, the third node and the fifth node respectively, and is configured to control an electric potential of the third node according to an electric potential of the fifth node under control of a voltage signal provided by the first second voltage line; The fifth node control circuit is electrically connected with a third clock signal line, the fourth node and the fifth node respectively, and is configured to control an electric potential of the fifth node according to a third clock signal provided by the third clock signal line under control of an electric potential of the fourth node; A positive projection of an active pattern of at least one transistor included in the third node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate; A positive projection of an active pattern of at least one transistor included in the fifth node control circuit on the substrate at least partially overlaps a positive projection of the third clock signal line on the substrate.

27. The display substrate of claim 1, wherein, The driving circuit further includes a fourth node control circuit and a seventh node control circuit; ​ The fourth node control circuit is electrically connected with the input end, the fourth clock signal line and the fourth node respectively, and is configured to write an input signal provided by the input end into the fourth node under control of a fourth clock signal provided by the fourth clock signal line; The seventh node control circuit is electrically connected with the first second voltage line, the fourth node and the seventh node respectively, and is configured to control a potential of the seventh node according to a potential of the fourth node under control of a voltage signal provided by the first second voltage line; The active pattern of at least one transistor included in the fourth node control circuit at least partially overlaps the active pattern of the second clock signal line on the substrate; The active pattern of at least one transistor included in the seventh node control circuit at least partially overlaps the active pattern of the second clock signal line on the substrate.

28. The display substrate of claim 1, wherein, The driving circuit includes a fifth node control circuit; the fifth node control circuit is electrically connected with the fifth node, the fourth clock signal line and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the fifth node under control of a fourth clock signal provided by the fourth clock signal line; The active pattern of at least one transistor included in the fifth node control circuit at least partially overlaps the active pattern of the second clock signal line on the substrate.

29. The display substrate of claim 1, wherein, The plurality of signal lines further include a control line; and the driving circuit includes a sixth node control circuit; The sixth node control circuit is electrically connected with the sixth node, the first first voltage line, the fifth node, the first clock signal line and the seventh node respectively, and is configured to write a first clock signal provided by the first clock signal line into the sixth node under control of a potential of the seventh node, and write a voltage signal provided by the first first voltage line into the sixth node under control of a potential of the fifth node; The active pattern of at least one transistor included in the sixth node control circuit at least partially overlaps the active pattern of the first clock signal line on the substrate; The active pattern of at least one transistor included in the sixth node control circuit at least partially overlaps the active pattern of the control line on the substrate. 30.The display substrate of claim 1, wherein, The plurality of signal lines further include a control line; and the driving circuit further includes a seventh node control circuit; the seventh node control circuit is electrically connected with the sixth node and the fifth node respectively, and is configured to control a potential of the seventh node according to a potential of the sixth node; The active pattern of a plate of a capacitor included in the seventh node control circuit at least partially overlaps the active pattern of the third clock signal line on the substrate; The active pattern of a plate of a capacitor included in the seventh node control circuit at least partially overlaps the active pattern of the second first voltage line on the substrate; The active pattern of a plate of a capacitor included in the seventh node control circuit at least partially overlaps the active pattern of the control line on the substrate; The active pattern of a plate of a capacitor included in the seventh node control circuit at least partially overlaps the active pattern of the first clock signal line on the substrate.

31. The display substrate of claim 2, wherein, The driving circuit comprises an output reset circuit; and the display substrate further comprises a second second voltage line; The output reset circuit is electrically connected with a seventh node, a driving output end and the second second voltage line respectively, and is configured to write a voltage signal provided by the second second voltage line into the driving output end under control of a potential of the seventh node; A normal projection of an active pattern of at least one transistor comprised in the driving output circuit on a substrate at least partially overlaps a normal projection of the fourth clock signal line on the substrate; A normal projection of an active pattern of at least one transistor comprised in the output reset circuit on the substrate at least partially overlaps a normal projection of the first first voltage line on the substrate; A normal projection of an active pattern of at least one transistor comprised in the output reset circuit on the substrate at least partially overlaps a normal projection of the fourth clock signal line on the substrate.

32. The display substrate of any one of claims 1-31, wherein, The driving circuit comprises an output reset circuit; The output reset circuit is electrically connected with a seventh node, a driving output end and the first second voltage line respectively, and is configured to write a voltage signal provided by the first second voltage line into the driving output end under control of a potential of the seventh node; The output reset circuit comprises a second transistor; A gate of the second transistor is electrically connected with a first conductive pattern, a first electrode of the second transistor is electrically connected with the first second voltage line, and a second electrode of the second transistor is electrically connected with the driving output end through a second conductive pattern; A normal projection of the first conductive pattern on the substrate at least partially overlaps a normal projection of the second conductive pattern on the substrate; The first conductive pattern and the second conductive pattern are arranged in different layers.

33. A display device comprising the display substrate according to any one of claims 1 to 32.

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