Audio artifact reduction in Universal Audio Jack (UAJ) interface circuitry

Abstract

Circuitry technology reduces or prevents auditory artifacts in Universal Audio Jack (UAJ) interface circuitry, improving the handling of device misconfigurations / misconnections. The interface includes at least one terminal for accepting an audio input signal or providing an audio line output signal coupled to an input or output of a first audio circuit. The first audio circuit operates from a low voltage domain and receives the audio input signal or provides the audio line output signal. A second circuit operates from a higher voltage domain, and a switching circuit couples at least one terminal to the second circuit. The output is slew rate controlled to control the output transition time, thereby avoiding auditory artifacts in the audio input signal or audio line output signal generated by the switching circuit connecting the second circuit to at least one terminal.

Description

Technical Field

[0001] The field of representative embodiments of this disclosure relates to processing audio signals in connection with a universal audio jack (UAJ), and more particularly to techniques for reducing auditory artifacts generated when the UAJ configuration on the interface side is incompatible with the connected device. Background Technology

[0002] Personal computer systems (including laptops) and personal devices (such as tablets and smartphones) typically include audio interfaces that have both input and output capabilities. In desktop computers, there is typically sufficient external panel space and available internal volume to accommodate multiple audio input and output connectors. In smaller devices, such as laptops, tablets, and smartphones, input and output functions are integrated into a single connector, which often has multiple functional modes. For example, the Universal Audio Jack (UAJ) found in many laptops can be used as a stereo line-level output jack, a stereo line-in jack, or a headphone jack for headphones with a microphone and headset speakers. Headphone configurations / modes typically have a common terminal, a pair of high-level audio output signals for the headset speakers, and a microphone input terminal that also carries a direct current (DC) voltage to supply operating voltage to the condenser microphone elements.

[0003] The internal management of the various signals supplied to and received from the UAJ is typically performed by device configuration software / firmware, which performs detection to determine if a device is connected, and if so, what type of device is connected. Manual configuration can also be performed and can override automatic configuration. In any case, whether during configuration or during user-made changes, audible artifacts such as pops and clicks can be generated on the UAJ terminal signals by connecting the audio interface circuitry path. This audio interface circuitry path causes voltage to be applied to the terminals that may be connected to output devices (such as home audio system speakers or professional sound generation equipment), and the typically transient applied voltage can generate pops / clicks and other audible artifacts. Such events produce unwanted sounds and, in some cases, can damage audio output devices, such as output transducers, like speakers.

[0004] Therefore, it would be advantageous to provide an audio interface circuit and its operation method that reduces or avoids the generation of popping / clicking sounds and other auditory artifacts. Summary of the Invention

[0005] In audio interface circuits and their operation methods, popping / clicking sounds and other auditory artifacts can be reduced or avoided.

[0006] An audio interface circuit includes at least one terminal for receiving an audio input signal or providing an audio line output signal, and a first audio circuit having an input or output coupled to the at least one terminal. The first audio circuit operates from a low voltage domain and receives the audio input signal as input or provides the audio line output signal as output. The audio interface circuit also includes a second circuit operating from a high voltage domain, the high voltage domain having a voltage level greater than the low voltage domain, and a switching circuit that couples the at least one terminal to the output of the second circuit in response to a control signal. The output of the second circuit is slew rate controlled to control the switching time of the output of the second circuit in response to the control signal, thereby avoiding auditory artifacts in the audio input signal or audio line output signal generated by the switching circuit connecting the second circuit to the at least one terminal.

[0007] The overview provided above is for illustrative purposes only and does not limit the scope of the claims. The following description illustrates exemplary embodiments according to this disclosure. Further embodiments and implementations will be apparent to those skilled in the art. Those skilled in the art will recognize that various equivalent techniques can be applied in place of or in combination with the embodiments discussed below, and all such equivalent techniques are covered by this disclosure. Attached Figure Description

[0008] Figure 1A This is a block diagram of an example system 10 according to an embodiment of the present disclosure.

[0009] Figure 1B This is a block diagram illustrating an example architecture 20 of the software and hardware components in system 10 according to embodiments of the present disclosure.

[0010] Figure 2 This is an illustration of an embodiment according to the present disclosure. Figure 1A and Figure 1B A block diagram showing the example details of audio interface 18.

[0011] Figure 3 This is a simplified schematic diagram illustrating an example audio interface circuit 40 according to an embodiment of the present disclosure, as can be seen in... Figure 1A , Figure 1B and Figure 2 Example audio interface circuit 40 implemented in audio interface 18.

[0012] Figure 4A The embodiments shown in this disclosure can be used for implementation. Figure 3 Example microphone bias circuit 47. Block diagram of microphone bias circuit 47.

[0013] Figure 4B This is an illustration of an embodiment according to the present disclosure. Figure 4A The signal waveform of an example signal within the microphone bias circuit 47 is shown in Figure 60.

[0014] Figure 5 The embodiments shown in this disclosure can be used in Figure 4A A schematic diagram of an example switch circuit 70 that implements switches S3 and S4 in the microphone bias circuit 47. Detailed Implementation

[0015] This disclosure covers circuits, integrated circuits, and methods of operation thereof for preventing or reducing auditory artifacts generated by audio interface circuits. Specifically, the audio interface circuit can supply and receive signals to and from a universal audio jack (UAJ) capable of receiving connections from various external audio transducers or other audio devices, such as headphones with or without microphones, stereo microphones, and line-in / out signals. The audio interface circuit includes at least one terminal for receiving an audio input signal or providing an audio line-out signal and a first audio circuit having an input or output coupled to the at least one terminal. The first audio circuit can operate from a low voltage domain and receive an audio input signal as input or provide an audio line-out signal as output. The audio interface circuit may also include a second circuit operating from a high voltage domain, the high voltage domain having a voltage level greater than that of the low voltage domain, and a switching circuit that couples the at least one terminal to the output of the second circuit in response to a control signal. The second circuit may be, for example, a microphone biasing circuit that provides an operating voltage to an external microphone connected to the at least one terminal. The output of the second circuit is controlled by the slew rate to control the switching time of the output of the second circuit in response to a control signal, thereby avoiding auditory artifacts in the audio input signal or audio line output signal generated by the switching circuit that connects the second circuit to at least one terminal.

[0016] Now for reference Figure 1AThis diagram illustrates a block diagram of an example system 10 according to an embodiment of the present disclosure. Example system 10 is an example of a computer system, which may be, for example, a laptop computer with a single UAJ for connecting to an audio device, although it will be understood that the techniques disclosed herein are applicable to other types of computing devices (such as desktop computers) and personal devices (such as smartphones, audio / video players / recorders, and tablets with audio connectivity). A central processing unit (CPU) 12 is coupled to a memory 14 that stores program instructions and data forming an operating system, application software, and other software modules supporting the execution of the operating system and application software. An input / output (I / O) subsystem 16 connects peripheral devices to the CPU 12 via one or more interface buses 17, and in example system 10, one of the peripheral devices is an audio interface 18 connected to the UAJJ1. In the example, an external audio device 5 is connected to the UAJJ1 via a plug 5 that may have two to four conductors.

[0017] Now for reference Figure 1B This diagram illustrates a block diagram of an example architecture 20 depicting software and hardware components in a system 10 according to an embodiment of the present disclosure. An operating system 22 provides resources to an application 23 executing within the system 10. The operating system 22 also manages a device input / output layer 24, which provides communication with various drivers provided for managing hardware devices. One of the drivers in the example architecture 20 is an audio device driver 26, which communicates with an audio interface 18 via an interface bus 17 through a hardware abstraction layer (HAL) 28 provided by the operating system. The audio interface 18, UAJ J1, and external audio devices (e.g., Figure 1AInteractions between the external audio device 5 and the external audio device 5 are typically managed by the audio device driver 26. These interactions may include determining the device type of the external audio device 5, configuring the connection to the external device 5, and receiving commands from the operating system 22 and / or application 23, which can directly control the configuration of the UAJ J1. During automatic device detection and configuration processes, during device driver initialization, or due to direct configuration commands received from the operating system 22 or application 23, the connection signal type may be changed, and in certain situations and operational phases, the signaling configuration of the UAJ J1 may not correctly match the signal configuration of the external audio device 5 connected to the UAJ J1. In particular, the conversion between the microphone bias voltage used to operate the condenser microphone element connected to the terminals of the UAJ J1 and the provisioning or receiving of other types of signals will generate pops or other auditory artifacts in the external audio device. For example, if the UAJ J1 is connected to an audio amplifier operating a speaker via the intended audio line output signal provided to the UAJ J1, but a microphone bias signal is instead sent, or even temporarily sent to those same terminals during auto-configuration, transients will be supplied to the connected audio amplifier and reproduced by the speaker, potentially causing damage or unwanted high-volume pops. In other examples, the UAJ J1 may be configured to provide headphone transducer or speaker output signals, but the UAJ J1 may alternatively be configured to accept audio input signals, in which case transients can also occur. Although Figure 1A Example System 10 and Figure 1B The hardware / software architecture 20 provides an example related to a typical laptop or desktop computer system, but such examples are not limiting, and the techniques disclosed herein can be used in simple systems such as single-threaded dedicated microcontroller systems without loss of generality, or in other architectures or system operation phases where the management of the audio interface 18 can be performed directly by firmware or other software or hardware components.

[0018] Now for reference Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1A and Figure 1BA block diagram illustrating example details of the audio interface 18. An encoder / decoder (CODEC) 42 receives and provides digital audio information from the interface bus 17. Audio output information is routed to digital-to-analog converters (DACs) 44A, 44B, and digital audio information is received from analog-to-digital converters (ADCs) 46A, 46B. A pair of line drivers DR1, DR2 provide line-level (e.g., 1Vp-p) output signals and / or transducer output signals to analog I / O circuitry 40, which includes switching and microphone amplification / biasing for microphones in externally connected devices. The analog I / O circuitry (details of which will be further described below) is used to manage the configuration of signals supplied to and / or received from external audio devices on UAJ J1. The example audio interface 18 also receives line-level inputs supplied to programmable gain amplifiers (PGAs) PGA1, PGA2 to handle a wide range of audio input voltages. The configuration control logic block 46 provides control information to PGAs PGA1, PGA2 and analog I / O circuit 40 to manage the configuration of audio interface 18.

[0019] Now for reference Figure 3 A simplified schematic diagram of an example audio interface circuit 40 according to an embodiment of the present disclosure is shown, as can be seen in... Figure 1A , Figure 1B and Figure 2 The audio interface 18 is implemented. Audio output block 43 includes line drivers DR1 and DR2 that receive audio output signals OUT1 and OUT2, and audio input block 44 includes PGAs PGA1 and PGA1 that provide audio input signals IN1 and IN2 as described above. Audio input block 44 is AC coupled to terminals of UAJ J1 via capacitors C1A-C1D and C2A-C2B, which provide signals to PGAs PGA1 and PGA2 respectively according to the states of switches S5-S8. Terminals of UAJ J1 are AC coupled to switches S5-S8 via capacitors C1A-C1D and C2A-C2B to configure the inputs of audio interface circuit 40 according to control signals received from configuration control logic block 46, as shown in Table I below. Audio output from audio interface circuit 40 is enabled or disabled according to the control signal output_disable, also provided by configuration control logic block 46. As described above, the sleeve terminal, first ring terminal r1, second ring terminal r2, and tip terminal of UAJ J1 are coupled to the audio input block 44 via capacitors C1A-C1D and C2A-C2B. The microphone bias circuit 47 is enabled by the microphone bias enable control signal bias enable and provides bias from the higher voltage domain V. HThe generated microphone bias voltage is selectively applied to one of the selected terminals Tip, r1, r2 or Sleeve of UAJ J1 according to the configuration selected in Table I below, where “X” indicates an “ignorant” state, which can assume a value of “0” or “1” without affecting the configuration or operation of the system.

[0020]

[0021] Table I

[0022] Headphones 1 and 2 are two different types of headphones, with their wiring configurations interchangeable with those of the return (GND) and microphone terminals. For Headphone 1, the polarity of the ADC receiving input from PGA1 is internally reversed. Changes to the switch control signals s1-s8 and the microphone bias enable control signal bias enable are managed by various software modules as described above and may cause pops or other artifacts depending on the type of device connected. The microphone bias circuit 47 is designed to reduce or avoid pops or other artifacts caused by the microphone bias applied to any of the selectable / deselectable terminals tip, r1, r2, and sleeve in Table I, because each of the terminals tip, r1, r2, and sleeve can carry a microphone signal and a microphone bias voltage present when the microphone input is selected and the microphone bias circuit 47 is enabled.

[0023] Now for reference Figure 4A This illustrates embodiments of the present disclosure that can be implemented. Figure 3 Example microphone bias circuit 47. Block diagram of microphone bias circuit 47. Voltage reference circuit 51 is selectively coupled by switch S10 to a filter formed by resistor R10 and capacitor C3, which controls the slew rate (rise time) of the voltage provided at the input of buffer amplifier B1, which provides a load-independent microphone bias voltage V. BIAS The slew rate. The output of the microphone bias circuit 47 is provided through one of switches S1, S2, S3, or S4, via one of the corresponding resistors R1, R2, R3, or R4, depending on the selected configuration as shown in Table I above. Switches S3 and S4 have special structures to prevent the generation of auditory artifacts, such as pops / clicks, when the stereo microphone configuration is selected, which could otherwise be presented to the audio amplification system with inputs connected to terminals Tip and r1 of UAJ J1. Refer below. Figure 5An example implementation of switches S3 and S4 is described, and current is supplied from the higher voltage domain V by preventing current from flowing from the microphone bias circuit 47 through terminals Tip and r1 of UAJ J1 when switches S3 and S4 are open (OFF). H The generated microphone bias signal V BIAS Isolation and protection, namely microphone bias voltage V BIAS The microphone bias output voltage V at the output of switch S3 DRV1 The microphone bias output voltage V at the output of switch S4 DRV2 Isolation. Switches S3 and S4 can have the same construction and can have an N-channel metal-oxide-semiconductor (NMOS) signal path 53A and a P-channel metal-oxide-semiconductor (PMOS) signal path 53B. This avoids the slew rate problem associated with using a single transistor to enable the microphone bias voltage, and this slew rate problem causes the microphone bias output voltage V to vary due to the operation of the switches themselves. DRV1 or V DRV2 The high slew rate in the circuit. Furthermore, the NMOS signal path 53A and PMOS signal path 53B are designed to prevent the microphone bias circuit output voltage V from being interrupted when the NMOS signal path 53A and PMOS signal path 53B are in the off state. BIAS The leakage is due to the voltage reference 51 and the buffer amplifier B1 being from the higher voltage domain V. H The other circuits in the audio interface circuit 40 operate from a lower voltage domain V. L The voltage regulator 54 provides the bias voltage V used in the operation and structure of the NMOS signal path 53A and the PMOS signal path 53B. D See below for reference. Figure 5 As stated above.

[0024] Now for reference Figure 4B The following illustrates embodiments according to the present disclosure. Figure 4A The example signal waveform within the microphone bias circuit 47 is shown in Figure 60. Waveform 58 shows the microphone bias output voltage V. DRV1 V DRV2 The overall output waveforms are shown in waveforms 56 and 57. Waveform 56 shows the overall output waveform when the NMOS signal path 53A is disabled, and waveform 57 shows the overall output waveform when the PMOS signal path 53B is disabled. Due to the turn-on threshold of the PMOS signal path 53B, a sudden rise 59 occurs in waveform 56 when an input signal 55A with a constant slew rate is supplied to the input of the PMOS signal path 53B. In the PMOS signal path 53B, the rise in waveform begins immediately, but due to the threshold voltage drop V across the switching device in the turn-on state... THNThe rise stops at time t1. Waveform 55B shows the input voltage waveform and is identical to waveform 55A. For readability, the N-channel output waveform 57, P-channel output waveform 56, and total output waveform 58 are shown below. Figure 4B The curve has shifted.

[0025] Now for reference Figure 5 This illustrates an embodiment of the invention that can be used according to the present disclosure. Figure 4A A schematic diagram of an example switching circuit 70 for the microphone bias circuit 47. The example switching circuit 70 is an implementation of switches S3 and S4 of Figure 4. A pair of transistors P1 and P2 provide a PMOS path 53B and a microphone bias V from the microphone bias circuit 47. BIAS Conducting current to provide the microphone bias voltage output voltage V to the terminal connected to the external microphone through resistors R1 and R2. DRIVE (For example, V) DRV1 V DRV2 As described above, transistor N1 is provided to clamp the intermediate node connecting the drain of transistor P1 and the source of transistor P2. Gate control voltages gc1 and gc2 are provided to control transistors P1, P2, and N1, while the gate control signal gc2 is in the 0V (on state) and higher voltage domains V. BIAS Switching between (off state) ensures that transistor P1 is completely turned off when switch circuit 70 is "on", and the gate control signal gc1 is at 0V (on state) and greater than or equal to the lower voltage domain supply voltage V. L The switching protection bias voltage VD is switched between the switching circuit and the protection bias voltage VD. The N-well of transistor P2 is connected to the protection bias voltage VD, which provides a lower voltage range voltage V that may transiently exist when transistor P1 is turned off when the switching circuit 70 is turned off. L Protection against any overvoltage. Transistors N2 and N3 provide the NMOS path 53A. The gate control signal gc3 switches between the protection bias voltage VD (on state) and 0V (off state). The gate control signal gc3 also controls transistor P3. When transistors N2 and N3 are turned off, transistor P3 clamps the intermediate node between transistors N2 and N3 to the protection bias voltage VD, preventing any transient of transistor N2 from pulling the intermediate node to a voltage higher than the protection bias voltage VD, i.e., towards the high voltage domain supply voltage V. H When transistor N2 is in the on state, it draws power from the supply voltage V in this voltage domain. HConducting current. Transistor P4 is operated by the gate control signal gc1, as described above, to pull the voltage at the gate of transistor N3 upwards towards the protection bias voltage VD. Resistor R11 is provided to prevent transistor N3 from turning on. Transistors N2 and N3 connect their deep N-wells 64A, 64B to the protection bias voltage VD and the surrounding substrates 62A, 62B to ground potential, such that the parasitic N-wells of the substrate diodes of transistors N2 and N3 remain reverse biased. Example voltages used for bias and supply voltage in example switching circuit 70 can be: higher voltage domain supply voltage V H =5.5V and protection bias voltage VD=3.0V, microphone bias output voltage V DRIVE The range is from 0V to 5.5V, and the supply voltage V in the lower voltage range is... L This can be, for example, within the range of 1V and 2V. Therefore, signals in the low voltage domain can vary from -1.4V to +1.4V without causing malfunctions.

[0026] In summary, this disclosure discloses and describes circuits and methods for preventing auditory artifacts generated by audio interface circuitry. The audio interface circuitry may include at least one terminal for receiving an audio input signal or providing an audio line output signal, and a first audio circuit having an input or output coupled to the at least one terminal. The first audio circuitry may operate from a low voltage domain and receive an audio input signal as input or provide an audio line output signal as output. The audio interface circuitry may also include a second circuitry operating from a high voltage domain, the high voltage domain having a voltage level greater than the low voltage domain, and a switching circuitry that couples the at least one terminal to the output of the second circuitry in response to a control signal. The second circuitry may have a slew rate-controlled output to control the switching time of the output of the second circuitry in response to a control signal, thereby avoiding auditory artifacts in the audio input signal or audio line output signal generated by the switching circuitry connecting the second circuitry to the at least one terminal.

[0027] In some example embodiments, at least one terminal has a selectable function among at least one audio line input or audio output function for providing an audio line output signal or receiving an audio input signal, and among a microphone bias output function. A first audio circuit may be an audio input or line output circuit coupled to at least one terminal for receiving an audio input signal or supplying an audio line output audio signal. A second circuit may be a microphone bias driver having an output that provides a microphone bias output level coupled to at least one terminal. The function of at least one terminal may be selectable among all of the audio line output function, the microphone bias output function, and the audio input function. A switching circuit may use a switch protection bias voltage greater than or equal to a power supply voltage in the low voltage domain to protect the switching circuit when the microphone bias driver is not coupled to at least one terminal. At least one terminal may be a Universal Audio Jack (UAJ) terminal, and the slew rate of the microphone bias driver output may be independent of the load presented to the microphone bias driver output. The microphone bias driver may include an output driver for generating the output of the microphone bias driver and a slew rate control circuit for receiving a reference input and providing an output signal for slew rate control to the input of the output driver.

[0028] In some example embodiments, the switching circuit can be protected by a switch protection bias voltage greater than or equal to the supply voltage of the low voltage domain. In some example embodiments, the audio output driver of the first audio circuit providing the audio line output signal can be designed to withstand voltage levels in the high voltage domain. In some example embodiments, the switching circuit can be designed to track the slew rate of the output of the second circuit.

[0029] While specific embodiments of the techniques disclosed herein have been shown and described in this disclosure, those skilled in the art will understand that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of this disclosure. For example, the techniques shown above can be applied to another type of audio interface circuit.

Claims

1. An audio interface circuit, comprising: At least one terminal is provided for receiving audio input signals or providing audio line output signals; A first audio circuit having an input or output coupled to the at least one terminal, wherein the first audio circuit operates from a low voltage domain and receives the audio input signal as an input or provides the audio line output signal as an output; A second circuit, operating from a high-voltage domain, wherein the high-voltage domain has a voltage level greater than that of the low-voltage domain; and A switching circuit that couples at least one terminal to the output of a second circuit in response to a control signal, wherein the output of the second circuit is slew rate controlled to control the switching time of the output of the second circuit in response to the control signal, thereby avoiding auditory artifacts generated in the audio input signal or the audio line output signal by the switching circuit that connects the second circuit to the at least one terminal.

2. The audio interface circuit according to claim 1, wherein, The at least one terminal has the ability to select between at least one of an audio line input or audio output function for providing an audio line output signal or receiving an audio input signal and between a microphone bias output function, wherein the first audio circuit is an audio input or line output circuit coupled to the at least one terminal for receiving the audio input signal or supplying the audio line output audio signal, wherein the second circuit is a microphone bias driver having an output for providing a microphone bias output level coupled to the at least one terminal.

3. The audio interface circuit according to claim 2, wherein, The function of the at least one terminal can be selected among all of the following: audio line output function, microphone bias output function, and audio input function.

4. The audio interface circuit according to claim 2, wherein, The switching circuit uses a switch protection bias voltage greater than or equal to the power supply voltage of the low voltage domain to protect the switching of the switching circuit when the microphone bias driver is not coupled to the at least one terminal.

5. The audio interface circuit according to claim 2, wherein, The at least one terminal implements a Universal Audio Jack (UAJ) terminal.

6. The audio interface circuit according to claim 2, wherein, The slew rate of the microphone bias driver output is independent of the load presented to the microphone bias driver output.

7. The audio interface circuit according to claim 6, wherein, The microphone bias driver includes: An output driver for generating the output of the microphone bias driver; and A slew rate control circuit is used to receive a reference input and provide a slew rate-controlled output signal to the input of the output driver.

8. The audio interface circuit according to claim 1, wherein, The switching circuit uses a switch protection bias voltage greater than or equal to the power supply voltage of the low voltage domain to protect the switch.

9. The audio interface circuit according to claim 1, wherein, The audio output driver of the first audio circuit that provides the audio line output signal is designed to withstand the voltage level of the high voltage domain.

10. The audio interface circuit according to claim 1, wherein, The switching circuit is designed to track the slew rate of the output of the second circuit.

11. A method for preventing audio interface circuits from generating auditory artifacts, comprising: Receive audio input signals from at least one terminal or provide audio line output signals to at least one terminal; A first audio circuit having an input or output coupled to at least one terminal operates from a low voltage domain; Receive the audio input signal as an input to the first audio circuit or provide the audio line output signal as an output from the first audio circuit; The second circuit is operated from a high voltage domain, wherein the high voltage domain has a voltage level greater than that of the low voltage domain; as well as The at least one terminal is selectively coupled to the output of the second circuit in response to a control signal using a switching circuit. as well as The slew rate of the output of the second circuit is controlled to control the switching time of the output of the second circuit in response to the control signal, thereby avoiding the generation of the auditory artifact by the switching circuit that connects the second circuit to the at least one terminal.

12. The method of claim 11, further comprising the function of selecting at least one terminal between at least one audio line input or audio output function for providing an audio line output signal or receiving an audio input signal and between a microphone bias output function, wherein, The first audio circuit is an audio input or line output circuit coupled to the at least one terminal for receiving the audio input signal or supplying the audio line output audio signal, wherein the second circuit is a microphone bias driver having an output that provides a microphone bias output level coupled to the at least one terminal.

13. The method according to claim 12, wherein, The function of the at least one terminal can be selected from all of the following: audio line output function, microphone bias output function, and audio input function.

14. The method of claim 12, further comprising protecting the switch circuit by applying a switch protection bias voltage greater than or equal to the power supply voltage of the low voltage domain to the switch when the microphone bias driver is not coupled to the at least one terminal.

15. The method according to claim 12, wherein, The at least one terminal implements a Universal Audio Jack (UAJ) terminal.

16. The method according to claim 12, wherein, The slew rate of the microphone bias driver output is independent of the load presented to the microphone bias driver output.

17. The method of claim 16, further comprising: The output of the microphone bias driver is generated from the output of the microphone bias driver; as well as A reference input is received at the slew rate control circuit of the microphone bias driver; as well as The slew rate control circuit provides a slew rate-controlled output signal to the input of the output driver.

18. The method of claim 11, further comprising protecting the switch of the switching circuit by applying a switch protection bias voltage greater than or equal to the power supply voltage of the low voltage domain to the switch.

19. The method according to claim 11, wherein, The audio output driver of the first audio circuit that provides the audio line output signal is designed to withstand the voltage level of the high voltage domain.

20. The method according to claim 11, wherein, The switching circuit is designed to track the slew rate of the output of the second circuit.

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