Signal driving circuit and slew rate enhancement method for photoelectric sensor readout system

Abstract

This invention relates to a signal driving circuit and slew rate enhancement method for a photoelectric sensor readout system, comprising: a signal detection and digitization module, which quantizes the input signal in a first timing stage; a digital storage and decoding module, coupled to the output of the signal detection and digitization module, which stores digital code values ​​and decodes the digital code values ​​into multiple control signals; a signal driving and sampling module, which receives the input signal at its input end and drives a sampling capacitor to sample in a second timing stage; and a slew rate enhancement execution module, whose control end is coupled to the output of the digital storage and decoding module and whose output end is coupled to the output node of the signal driving and sampling module, which, in response to the multiple control signals in the second timing stage, injects an auxiliary current corresponding to the digital code value into the output node; the first and second timing stages are two consecutive operating stages of the photoelectric sensor readout system. This invention eliminates the inherent delay between the detection and response stages in the slew rate enhancement mechanism.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a signal driving circuit and a method for enhancing the slew rate of a photoelectric sensor readout system. Background Technology

[0002] In solid-state image sensors and photoelectric detection systems, column-parallel readout architectures are widely used to achieve high frame rate imaging. In such architectures, the analog signal output from the front-end integrator needs to be buffered by a signal driver before being transmitted to an analog-to-digital converter (ADC) for sampling and quantization. The slew rate of the signal driver is a key parameter determining the charge build-up speed of the sampling capacitor, thus affecting the conversion accuracy of the ADC and the system power consumption. However, the traditional method of increasing the slew rate by increasing the static bias current of the operational amplifier leads to continuous static power loss, which is difficult to meet the application requirements of portable and low-power imaging devices. To balance the contradiction between high-speed build-up and low power consumption, slew rate boosting technology has been proposed. This type of technology typically uses an analog differentiator circuit or comparator array to detect the amplitude of the input signal jump in real time, and dynamically adjusts the injection amount of the tail current source or auxiliary current source through a feedback control loop based on the detection result, only instantaneously increasing the driving capability during large signal swings.

[0003] Traditional slew rate enhancement techniques utilize a feedback loop to respond to input voltage fluctuations and adjust the amount of auxiliary current injected into the output, such as... Figure 8 As shown, the specific working process can be described as follows: At the moment the main operational amplifier starts its integrating phase, due to the effect of charge sharing, the input voltage will undergo a reverse sudden change before it jumps in the correct direction. At the same time, this change will be coupled to the output terminal through the integrating capacitor. By detecting the direction of the jump of the input signal, current is selectively injected or extracted into the corresponding output terminal, so that the output signal can stabilize to the target point more quickly and start the exponential establishment process. However, the above-mentioned technical solutions have the following technical defects: First, the inherent response delay of the analog detection circuit and the establishment time of the feedback loop result in an unavoidable time difference between the signal detection stage and the current injection response stage. This delay causes the slew rate enhancement action to lag behind the signal transition, limiting the establishment speed in ultra-high-speed application scenarios. Second, the introduction of the detection circuit and feedback control loop from the main operational amplifier input to the output brings additional parasitic capacitance at the operational amplifier input and potential stability risks. The design of the loop compensation network restricts the operating bandwidth of the circuit and increases the system complexity. In addition, the existing solutions are difficult to accurately configure the auxiliary current according to the actual amplitude of the input signal, which easily leads to current overshoot or undershoot, resulting in a decrease in signal establishment accuracy. Finally, the complex control logic and continuous detection power consumption make it difficult to further optimize the circuit area and energy efficiency ratio. Summary of the Invention

[0004] Based on this, it is necessary to address the aforementioned technical problems by providing a signal driving circuit and slew rate enhancement method for a photoelectric sensor readout system that eliminates the inherent delay between the detection and response stages in the slew rate enhancement mechanism, avoids the stability risks introduced by complex feedback control loops, detects and quantizes the input signal at the end of the CTIA integral phase, enables the signal driver to respond quickly and accurately to changes in the amplitude of the input signal, and avoids the additional parasitic capacitance at the input terminal of the signal driver's operational amplifier introduced by the input signal detection module in traditional solutions, while also reducing circuit power consumption and area overhead.

[0005] The present invention provides a signal driving circuit for a photoelectric sensor readout system, comprising: The signal detection and digitization module is configured to quantize the input signal in the first timing stage to generate a digital code value; The digital storage and decoding module has its input end coupled to the output end of the signal detection and digitization module, and is configured to store the digital code value and decode the digital code value into multiple control signals. The signal driving and sampling module receives the input signal at its input terminal and is configured to drive the sampling capacitor to perform sampling in the second timing stage; The slew rate enhancement execution module has its control terminal coupled to the output terminal of the digital storage and decoding module and its output terminal coupled to the output node of the signal driving and sampling module. It is configured to respond to the plurality of control signals in the second timing phase and inject an auxiliary current corresponding to the digital code value into the output node to enhance the slew rate of the signal driving and sampling module. The first timing stage and the second timing stage are two consecutive working stages of the photoelectric sensor readout system.

[0006] In one embodiment, the signal detection and digitization module includes a 4-bit Flash ADC, which includes 15 parallel comparators, a resistor series voltage divider network, and a thermometer code to binary code encoder.

[0007] In one embodiment, the digital storage and decoding module includes a register array and a 4-to-16 decoder, the 4-to-16 decoder being used to convert a 4-bit digital code value into a 16-bit strobe control signal.

[0008] In one embodiment, the slew rate enhancement execution module includes an auxiliary current source array, which contains multiple independently selectable current sources with current values ​​configured according to binary weight ratios. The multiple control signals are used to select the corresponding independently selectable current sources to provide the auxiliary current in combination.

[0009] In one embodiment, the binary weight ratio is 1:2:4:8.

[0010] In one embodiment, the slew rate enhancement execution module is configured to inject the auxiliary current during a slew rate enhancement time in the second timing phase, so that the voltage of the output node is established to 95% of the target voltage; after the slew rate enhancement time ends, the signal driving and sampling module drives the sampling capacitor to complete the precise establishment in a closed-loop working mode.

[0011] The present invention also provides a method for enhancing the slew rate of a photoelectric sensor readout system, the method being executed based on a first timing phase and a second timing phase, comprising: In the first timing stage, the input signal is quantized to generate and store digital code values; In the second timing stage, the stored digital code value is decoded into multiple control signals; In response to the plurality of control signals, an auxiliary current corresponding to the digital code value is injected into the output node of the signal driver to improve the slew rate of the signal driver; The sampling capacitor is driven by the signal driver to perform sampling.

[0012] In one embodiment, the quantization of the input signal includes: The input signal is quantized in full parallel using a 4-bit Flash ADC.

[0013] In one embodiment, the injected auxiliary current corresponding to the digital code value includes: Multiple current source units in an auxiliary current source array are selected according to the digital code value, and the current values ​​of the multiple current source units are configured according to binary weight ratio.

[0014] In one embodiment, the injection of the auxiliary current lasts for a slew rate enhancement time, which is set to the time required for the voltage of the output node to build up to 95% of the target voltage; after the slew rate enhancement time ends, the signal driver drives the sampling capacitor in a closed-loop operating mode to complete the final build-up.

[0015] The signal driving circuit and slew rate enhancement method of the aforementioned photoelectric sensor readout system place signal detection, quantization, storage, and slew rate enhancement execution into two continuous and separate timing stages. In the first timing stage, the signal detection and digitization module completes the quantization and digitization of the input signal to generate a digital code value, which is then stored in the digital storage and decoding module. In the second timing stage, the digital storage and decoding module decodes the stored digital code value into multiple control signals. The slew rate enhancement execution module injects an auxiliary current corresponding to the digital code value into the output node of the signal driving and sampling module based on these control signals. This architecture utilizes the unique dual-line timing characteristics of the photoelectric sensor readout system to completely decouple the detection and response of the input signal amplitude in time. This ensures that the control signal of the auxiliary current is ready before the signal driver needs to establish a large slew rate voltage, thereby eliminating the time difference between the detection and response stages in traditional schemes and achieving a near-zero delay slew rate enhancement response. Meanwhile, since the amount of auxiliary current injected is directly determined by the digital code value quantized in the previous timing stage through decoding control, the entire enhancement process is an open-loop feedforward method, eliminating the need to rely on real-time feedback adjustment loops. This avoids the stability risks and complexities introduced by feedback loops. Furthermore, by precisely gating the binary-weighted auxiliary current source array using digitized code values, the injected auxiliary current can be proportionally matched to the expected change amplitude of the input signal, thereby preventing current overshoot or undershoot and improving the accuracy and controllability of voltage establishment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the signal driving circuit of a photoelectric sensor readout system according to one embodiment; Figure 2 The overall architecture diagram of the system-level slew rate improvement technology; Figure 3 This is a diagram of the quantizer structure for a 4-bit Flash ADC. Figure 4 A schematic diagram of the auxiliary current source array configured for binary weights; Figure 5 This is a schematic diagram of the working principle of the signal driving and sampling module; Figure 6 The diagram shows the operating phase and output voltage waveforms of the simulated front-end CTIA integrator; Figure 7 The timing diagram shows the operation of the signal driver and the slew rate enhancement module. Figure 8 This is a schematic diagram of a traditional slewing rate enhancement technology. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on the other component or there may be an intermediate component. When a component is considered to be "connected to" another component, it can be directly connected to the other component or there may be an intermediate component present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this specification are for illustrative purposes only and do not represent the only possible implementation.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0021] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature and the second feature are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0022] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0023] The following is combined with Figures 1-7 The present invention describes the signal driving circuit and slew rate enhancement method of the photoelectric sensor readout system.

[0024] like Figure 1 As shown, in one embodiment, a signal driving circuit for a photoelectric sensor readout system includes a signal detection and digitization module 110, a digital storage and decoding module 120, a signal driving and sampling module 130, and a slew rate enhancement execution module 140. The signal detection and digitization module 110 is configured to quantize the input signal in the first timing stage to generate a digital code value; the input terminal of the digital storage and decoding module 120 is coupled to the output terminal of the signal detection and digitization module 110 to store the digital code value and decode the digital code value into multiple control signals; the input terminal of the signal driving and sampling module 130 receives the input signal and is configured to drive the sampling capacitor to sample in the second timing stage; the control terminal of the slew rate enhancement execution module 140 is coupled to the output terminal of the digital storage and decoding module 120 and its output terminal is coupled to the output node of the signal driving and sampling module 130, and is configured to respond to multiple control signals in the second timing stage to inject an auxiliary current corresponding to the digital code value into the output node to improve the slew rate of the signal driving and sampling module 130, and the first timing stage and the second timing stage are two consecutive working stages of the photoelectric sensor readout system.

[0025] Reference Figure 2The system specifically includes a photoelectric sensor array, a CTIA capacitor transimpedance amplifier integrator (CTIA integrator for short), a signal detection and digitization module 110, a digital storage and decoding module 120, a slew rate enhancement execution module 140, and a signal driving and sampling module 130. The signal driving and sampling module 130 includes an operational amplifier as an input signal driver and an ADC sampling circuit containing a sampling capacitor. The output of the operational amplifier is coupled to the sampling capacitor to drive it to complete charge transfer. The output of the CTIA integrator is connected to the input of the signal detection and digitization module 110 and the input of the operational amplifier, respectively. In the first timing phase, i.e., the first line processing phase, the photocurrent generated by the photoelectric sensor is injected into the CTIA integrator for integration. At the end of the integration phase, the signal detection and digitization module 110 performs high-speed quantization on the integrator output voltage, converting it into a digital code value and storing it in the digital storage and decoding module 120. This phase completes the detection of the precise range of the input signal before the signal driving and sampling module 130 operates. In the second timing phase, i.e., the second line processing phase, the digital storage and decoding module 120 decodes the stored digital code value and generates a gating signal. This signal controls the auxiliary current source array and resistor topology network in the slew rate enhancement execution module 140 to replenish or extract charge to the sampling capacitor of the operational amplifier's output node, which is a capacitive sampling ADC. The charge amount reaches more than 95% of the input signal change. The input step amplitude is proportional to the tail current increment, as shown by the formula... Precise charge transfer control prevents overshoot. The slew rate enhancement execution module 140 further includes a resistor topology network containing multiple parallel resistors. One end of each parallel resistor is connected via a gating switch, and the other end is connected to a fixed potential, which may be the power supply potential or ground potential. The auxiliary current source array further includes one fixed-gating current source and four independently selectable current sources, forming a 5-current-source structure. The fixed-gating current source provides the basic bias current. This fully utilizes the dual-line timing characteristics of the photoelectric sensor readout chip, decoupling signal detection and slew rate enhancement in timing, achieving system-level slew rate improvement and significantly reducing static power consumption. See also Figure 6The photoelectric sensor readout system employs a line-by-line scanning method, with each line scan cycle including a CTIA reset phase and a CTIA integrating phase. During the CTIA integrating phase, the photocurrent generated by the photoelectric sensor is injected into the CTIA integrator for integration, and the output voltage changes linearly with time. At the end of the integrating phase (i.e., a specific moment before the end of the line cycle), the Flash ADC samples and quantizes the CTIA output voltage to generate a digital code value. Specifically, the Flash ADC performs its first sampling at the end of the first line integrating phase, its second sampling at the end of the second line integrating phase, and so on, with the Nth sampling performed at the end of the Nth line integrating phase. These sampling points are located at the end of each integrating phase and before the start of the reset phase, ensuring accurate detection and digitization of the input signal amplitude before the signal driver operates, providing control parameters for slew rate enhancement in the next line.

[0026] As an optional embodiment, the signal detection and digitization module 110 includes a 4-bit Flash ADC, which comprises 15 parallel comparators, a resistor series voltage divider network, and a thermometer code to binary code encoder. (See reference...) Figure 3 The 4-bit Flash ADC is from It consists of several parallel comparators, each comparator having one end connected to the input signal. The other end is connected to the corresponding reference voltage. ,exist and Between the reference voltages, a resistor series voltage divider generates the threshold levels for each quantization step. The comparator output is converted from the thermometer code to a binary code encoder to generate a 4-bit digital code value. The outputs of the 15 parallel comparators are thermometer codes. The encoder converts the output into a 4-bit binary number. The resistors are connected in series in the and Sixteen quantization steps are formed between them to achieve quantization of the input signal. The system employs 16-level partitioned detection; utilizing fully parallel processing capabilities, it completes 4-bit resolution signal comparison within one cycle, and performs high-speed quantization at the end of the first timing stage, providing zero-delay control preparation for slew rate enhancement in the second timing stage, thus eliminating the time difference between detection and response. REFP V REFN These represent the positive reference voltage terminal (Top Reference) and the negative reference voltage terminal (Bottom Reference) of the resistor series voltage divider network in the Flash ADC, respectively.

[0027] The slew rate enhancement execution module 140 includes an auxiliary current source array. The auxiliary current source array contains multiple independently selectable current sources with current values ​​configured according to a binary weight ratio. Multiple control signals are used to select the corresponding independently selectable current sources to provide the auxiliary current in combination. The binary weight ratio is 1:2:4:8; see reference. Figure 4 The auxiliary current source array includes four independently selectable current sources and one fixed-selection current source, with current values ​​set according to... The binary weight design uses four independently selectable current sources, with the last one... The fixed-selection current source employs a current mirror structure, with a PMOS current source providing charging current and an NMOS current source providing discharging current. Different combinations of current sources can be selected by controlling the CMOS switch array with a 16-bit gating signal, generating currents from... arrive There are 16 different auxiliary current levels. The corresponding current source units are selected to work in parallel, so that the auxiliary current is proportionally matched with the input step amplitude, preventing overshoot or undershoot and improving the settling accuracy.

[0028] The slew rate enhancement execution module 140 is configured to inject the auxiliary current during a slew rate enhancement period in the second timing phase, so that the voltage of the output node is built up to 95% of the target voltage. After the slew rate enhancement period ends, the signal driving and sampling module 130 drives the sampling capacitor in a closed-loop operating mode to complete the accurate establishment; refer to Figure 5 The differential circuit topology of the signal driving and sampling module 130 and the slew rate enhancement execution module 140, wherein the operational amplifier, which serves as the input signal driver, adopts a fully differential structure, and its positive input terminal is connected to a DC blocking capacitor C. DS Coupled to the VIP signal and selectively connected to the common-mode voltage VCM via a switch controlled by the reset signal RST, the negative input terminal is connected to another DC blocking capacitor C. DS Coupled to the VIN signal and selectively connected to the VCM via a switch controlled by RST, the positive output terminal VSTDP and the negative output terminal VSTDN form a differential output node and are respectively connected to the parasitic compensation capacitor C via switches controlled by the holding signal HD. P With C N The top plate and the bottom plate of the parasitic compensation capacitor are connected to RST or a fixed potential via a switch controlled by the HDd signal. In the auxiliary current source array included in the slew rate enhancement execution module 140, a PMOS current source is connected between the power supply and the VSTDP / VSTDN node and its gate switch is controlled by the slew rate enhancement enable signal EN_SR to provide charging auxiliary current. An NMOS current source is connected between the VSTDP / VSTDN node and ground and its gate switch is controlled by the slew rate enhancement enable inverted signal ENB_SR to provide discharging auxiliary current. The differential sampling capacitor C... SThe sampling capacitor is connected between VSTDP and the negative input terminal VIN- of the subsequent ADC, and between VSTDN and the positive input terminal VIN+ of the subsequent ADC, respectively. Its base plate is selectively connected to VCM via a switch. VIP and VIN represent the Positive and Negative terminals of the differential input signal, VSTDP and VSTDN represent the positive and negative output terminals of the operational amplifier, EN_SR and ENB_SR represent the slew rate enhancement enable signal and its inverted signal, respectively, and VCM represents the common-mode voltage providing the DC bias reference for the differential signal. During the slew rate enhancement phase, the auxiliary current source responds to the EN_SR or ENB_SR signal by directly injecting an auxiliary current proportional to the input step amplitude into the VSTDP and VSTDN nodes, bypassing the current limitation inside the operational amplifier. This allows the sampling capacitor to be rapidly charged or discharged to 95% of the target voltage during the slew rate enhancement time. Subsequently, after the slew rate enhancement time ends, the operational amplifier drives the sampling capacitor in closed-loop operation mode to complete the accurate establishment of the small signal. The signal driving and sampling module 130 includes an operational amplifier as an input signal driver and a sampling capacitor. The ADC sampling circuit uses an operational amplifier with a differential input and differential output structure. The positive input receives the VIP signal, the negative input receives the VIN signal, the positive output is VSTDP, and the negative output is VSTDN. The sampling capacitor... Differential sampling capacitors are connected to the positive and negative output terminals respectively. The output of the operational amplifier is coupled to the sampling capacitors to drive them to complete charge transfer. The slew rate enhancement execution module 140 controls the injection of auxiliary current through enable signals EN_SR and ENB_SR. EN_SR controls the activation of the charging current source, and ENB_SR controls the activation of the discharging current source. The auxiliary current is directly injected into the VSTDP and VSTDN nodes, i.e., the output nodes of the operational amplifier, bypassing the internal current limit of the operational amplifier. Slew rate enhancement time. It should be set to build up to 95% of the target voltage. The required time, follow ,in The change in the input signal. For the injection of auxiliary The auxiliary current value is reserved at 5% for precise tracking during the small signal setup phase. The maximum slew rate is determined based on the required accuracy. To achieve the fastest setup speed, the peak current of the auxiliary current source is... Need to meet ,in For sampling capacitor, The desired maximum slew rate. Small signal settling time. Depends on the closed-loop bandwidth when the operational amplifier is used as a signal driver ,satisfy ,in Given the number of time constants, establish a precision of 0.1%. Establish accuracy When it is 0.01% After the slew rate enhancement time ends, the auxiliary current is turned off, and the operational amplifier completes accurate signal tracking and establishment in closed-loop operation mode. Thus, the open-loop auxiliary current injection method avoids the stability risks caused by complex control loops, while taking into account both establishment speed and accuracy.

[0029] In addition, the present invention also provides a method for enhancing the slew rate of a photoelectric sensor readout system.

[0030] In one embodiment, the slew rate enhancement method of the photoelectric sensor readout system is executed based on a first timing phase and a second timing phase. In the first timing phase, the input signal is quantized to generate and store a digital code value. In the second timing phase, the stored digital code value is decoded into multiple control signals. In response to these control signals, an auxiliary current corresponding to the digital code value is injected into the output node of the signal driver to enhance the slew rate of the signal driver. The signal driver then drives a sampling capacitor for sampling. The first timing phase corresponds to the first processing phase of the photoelectric sensor readout system, where the photocurrent generated by the photoelectric sensor is injected into a CTIA integrator for integration. The CTIA integrator performs integration and conversion of the photocurrent. At the end of the integration phase, the Flash ADC performs high-speed quantization and stores the integrator output voltage. The second timing phase corresponds to the second processing phase of the system, where the code value in the digital register, after decoding, controls the slew rate enhancement circuit and the signal driver (operational amplifier), which, under the enhancement of the auxiliary current, drives the sampling capacitor, i.e., the capacitor-sampling ADC completes sampling. This method is applicable to multi-channel parallel processing architectures. Each channel independently executes alternating operations of the first and second timing stages. Slew rate enhancement is performed only at the beginning of the second timing stage, and the Flash ADC operates only at the end of the first timing stage. Through a dual-row timing architecture, the slew rate enhancement circuit is activated only when necessary, maintaining low power consumption during static operation, thus resolving the power consumption versus speed contradiction in traditional methods. See also Figure 7This demonstrates the detailed timing relationship between the signal driver and the slew rate enhancement module, showing the alternating execution of the first and second timing stages between two consecutive rows. Taking the N+1th row as an example, in the second timing stage within that row's cycle, the slew rate enhancement module starts synchronously with the sampling operation of the main ADC. Specifically, the slew rate enhancement enable signal EN_SR is aligned with the rising edge of the Phase1_ADC sampling stage control signal S1 and is activated simultaneously. The pulse width of the EN_SR signal is designed to be half the pulse width of the S1 signal. During the first half of the S1 cycle when EN_SR is active, an auxiliary current source injects an auxiliary current corresponding to the digital code value detected and stored in the Nth row (first timing stage) into the output node of the signal driver. This helps the operational amplifier output stage quickly charge the ADC sampling capacitor, efficiently establishing the voltage during the large signal slewing stage. During the second half of the S1 cycle after the EN_SR signal is deactivated, the auxiliary current injection stops, and the operational amplifier switches to closed-loop operating mode. Leveraging its own gain and bandwidth, it accurately establishes the small signal, thus ensuring the final accuracy of the sampled voltage. Meanwhile, during a specific period of scanning the (N+1)th row (typically at the end of the row cycle), the Flash ADC performs its (N+1)th sampling, quantizing the output voltage of the current row's CTIA integrator. This result is stored and used to control the slew rate enhancement during the (N+2)th row scan. This timing design achieves "zero-delay synchronization" between the detection and response phases: although the slew rate enhancement action (EN_SR) cannot start before the ADC sampling (S1), by utilizing the quantized result of the previous row (Nth row) to control the enhancement action of the current row (N+1), the inherent delay in the "detection-decision-response" path in traditional schemes is eliminated. This allows the slew rate enhancement mechanism to be synchronously activated at the very beginning of the sampling phase, thereby maximizing the setup speed.

[0031] Specifically, quantizing the input signal includes: performing fully parallel quantization of the input signal using a 4-bit Flash ADC; and employing a 4-bit Flash ADC architecture, by... It consists of several parallel comparators, each comparator having one end connected to the input signal. The other end is connected to the corresponding reference voltage. The reference voltage is formed by a series resistor connected in series. and The voltage is divided between these intervals, forming 16 quantization intervals. The comparator outputs a thermometer code. Converted to 4-bit binary code by the encoder The quantization process is completed within one clock cycle, ensuring no time difference between detection and response, thus achieving high-speed quantization and true early response.

[0032] The injection of auxiliary current corresponding to the digital code value includes: selecting multiple current source units in an auxiliary current source array according to the digital code value, with the current values ​​of the multiple current source units configured according to a binary weight ratio. Specifically, the binary weight ratio is 1:2:4:8, and the auxiliary current source array includes 4 independently selectable current sources and 1 fixed-selectable current source, with the current values ​​configured according to... The design uses a 16-bit gating signal generated after decoding of the digital code value. This signal controls a CMOS switch array to select the corresponding current source unit, thereby providing an auxiliary current that matches the change in the input signal. The auxiliary current is proportional to the input step amplitude, as shown by the formula... Confirmed, among which This is the proportionality coefficient. The input signal changes detected by the Flash ADC are used to prevent overshoot or undershoot, and the charge replenishment accuracy can reach over 95%, enabling precise and programmable control of the auxiliary current.

[0033] The auxiliary current injection lasts for a slew rate enhancement time, which is set to the time required for the output node voltage to build up to 95% of the target voltage. After the slew rate enhancement time ends, the signal driver drives the sampling capacitor in closed-loop operation mode to complete the final build-up. Slew rate enhancement time The calculation basis is ,in The target voltage change The capacitance value is the value of the sampling capacitor. Let be the value of the injected auxiliary current; assume the full-scale input of the ADC is . Sampling time is If the large signal establishment time is half of the quantization period, then the minimum slew rate requirement is: ,in For ADC full-scale input, Sampling time; setup time in the closed-loop operating mode. Depending on the closed-loop bandwidth of the operational amplifier when it is used as a signal driver, it satisfies ,in To establish error accuracy, when the accuracy is 0.1%, After the slew rate enhancement time ends, the operational amplifier completes precise signal tracking and establishment in closed-loop operation mode, realizing the separation design of fast establishment of large signals and precise establishment of small signals, simplifying the control logic and improving system stability.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A signal driving circuit for a photoelectric sensor readout system, characterized in that, include: The signal detection and digitization module is configured to quantize the input signal in the first timing stage to generate a digital code value; The digital storage and decoding module has its input end coupled to the output end of the signal detection and digitization module, and is configured to store the digital code value and decode the digital code value into multiple control signals. The signal driving and sampling module receives the input signal at its input terminal and is configured to drive the sampling capacitor to perform sampling in the second timing stage; The slew rate enhancement execution module has its control terminal coupled to the output terminal of the digital storage and decoding module and its output terminal coupled to the output node of the signal driving and sampling module. It is configured to respond to the plurality of control signals in the second timing phase and inject an auxiliary current corresponding to the digital code value into the output node to enhance the slew rate of the signal driving and sampling module. The first timing stage and the second timing stage are two consecutive working stages of the photoelectric sensor readout system.

2. The signal driving circuit of the photoelectric sensor readout system according to claim 1, characterized in that, The signal detection and digitization module includes a 4-bit Flash ADC, which comprises 15 parallel comparators, a resistor series voltage divider network, and a thermometer code to binary code encoder.

3. The signal driving circuit of the photoelectric sensor readout system according to claim 1, characterized in that, The digital storage and decoding module includes a register array and a 4-to-16 decoder, which is used to convert a 4-bit digital code value into a 16-bit strobe control signal.

4. The signal driving circuit of the photoelectric sensor readout system according to claim 1, characterized in that, The slew rate enhancement execution module includes an auxiliary current source array, which contains multiple independently selectable current sources with current values ​​configured according to binary weight ratios. The multiple control signals are used to select the corresponding independently selectable current sources to provide the auxiliary current in combination.

5. The signal driving circuit of the photoelectric sensor readout system according to claim 4, characterized in that, The binary weight ratio is 1:2:4:

8.

6. The signal driving circuit of the photoelectric sensor readout system according to claim 1, characterized in that, The slew rate enhancement execution module is configured to inject the auxiliary current during a slew rate enhancement time in the second timing phase, so that the voltage of the output node is established to 95% of the target voltage; after the slew rate enhancement time ends, the signal driving and sampling module drives the sampling capacitor to complete the accurate establishment in a closed-loop working mode.

7. A method for enhancing the slew rate of a photoelectric sensor readout system, characterized in that, The method is executed based on consecutive first and second time-series phases, including: In the first timing stage, the input signal is quantized to generate and store digital code values; In the second timing stage, the stored digital code value is decoded into multiple control signals; In response to the plurality of control signals, an auxiliary current corresponding to the digital code value is injected into the output node of the signal driver to improve the slew rate of the signal driver; The sampling capacitor is driven by the signal driver to perform sampling.

8. The signal driving circuit of the photoelectric sensor readout system according to claim 7, characterized in that, The quantization of the input signal includes: The input signal is quantized in full parallel using a 4-bit Flash ADC.

9. The signal driving circuit of the photoelectric sensor readout system according to claim 7, characterized in that, The injected auxiliary current corresponding to the digital code value includes: Multiple current source units in an auxiliary current source array are selected according to the digital code value, and the current values ​​of the multiple current source units are configured according to binary weight ratio.

10. The signal driving circuit of the photoelectric sensor readout system according to claim 7, characterized in that, The injection of the auxiliary current lasts for a slew rate enhancement time, which is set to be the time required for the voltage of the output node to build up to 95% of the target voltage. After the slew rate enhancement time ends, the signal driver drives the sampling capacitor in closed-loop operating mode to complete the final establishment.

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