Method of processing single crystal silicon ingots to improve laser scattering ring / nucleation patterns

Abstract

The present disclosure relates to methods of processing single crystal silicon ingots to improve laser scattering ring / nucleation patterns. The present disclosure discloses a method for reducing the size and density of defects in single crystal silicon wafers. The method involves subjecting a single crystal silicon ingot to annealing prior to wafering.

Description

[0001] Information related to divisional application This case is a divisional application of the invention patent application filed on December 10, 2018, with application number 201880076551.2 and invention title "Method for processing single-crystal silicon ingots to improve laser scattering ring / nucleus patterns". Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 608,624, filed December 21, 2017, the disclosure of which is incorporated herein by reference as if fully described herein. Technical Field

[0003] The field of the present invention generally relates to a method for processing a single-crystal silicon ingot to reduce the size and density of defects in a single-crystal silicon wafer cut from the processed ingot. Background Technology

[0004] Single-crystal materials are typically prepared using the Czochralski (“CZ”) method, which is the starting material for manufacturing many electronic components, such as semiconductor devices and solar cells. In simple terms, the Czochralski method involves melting a polycrystalline source material (such as polycrystalline silicon) in a crucible to form a silicon melt, and then pulling a single-crystal ingot from the melt.

[0005] Semiconductor wafers are typically made from single-crystal ingots (e.g., silicon ingots), which are processed to remove seed cones and end cones and then trimmed, optionally sheared and ground, to have one or more planes or notches to properly orient the wafer in subsequent processes. The ingot is then cut into individual wafers. While reference is made herein to semiconductor wafers made of silicon, other materials can be used to fabricate semiconductor wafers, such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of group III and V elements (e.g., gallium nitride or indium phosphide) or alloys of group II and VI components (e.g., cadmium sulfide or zinc oxide).

[0006] The ever-shrinking size of modern electronic devices imposes challenging constraints on the quality of silicon substrates, which is at least in part determined by the size and distribution of micro-defects grown therein. Most micro-defects formed in silicon crystals grown by the Chuklaski process are either inherent point defects of silicon (i.e., vacancies and self-filling interstitials) or aggregates of oxide deposits.

[0007] Attempting to produce substantially defect-free single-crystal silicon typically involves controlling the ratio of the crystal pull-out rate (v) to the magnitude (G) of the axial temperature gradient near the melt / crystal interface. For example, some known methods involve controlling the v / G ratio near a critical v / G value, in which vacancies and interstitial cells are incorporated into the grown crystal ingot at very low and relatively low concentrations, thus annihilating each other and therefore suppressing the possible formation of any micro-defects at lower temperatures. However, as described in U.S. Patent No. 8,673,248 to Kulkarni, controlling the v / G ratio near this critical v / G value can result in the formation of annular rings or “bands” with relatively large and / or concentrated condensed defects, extending radially inward from the transverse surface or circumferential edge of the silicon crystal ingot, referred to herein as “defect edge bands” or simply “defect bands.”

[0008] This defect band typically has a lower quality than other portions of the silicon ingot located radially inward from the defect band, and can significantly reduce the yield of the ingot. For example, increasingly stringent requirements for the wafer quality of memory devices have increased the required breakdown voltage for gate oxide integrity (GOI) testing, which is used to evaluate the quality of silicon or semiconductor wafers used in memory devices (e.g., SRAM, DRAM). Therefore, more GOI failures occur near or within the defect edge band of a substantially defect-free silicon wafer, thus reducing yield.

[0009] This background section is intended to introduce the reader to various aspects of the present invention that may be related to various aspects of the invention, which are described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of the various aspects of the invention. Therefore, it should be understood that these statements are intended to teach the reader and not to be taken as an endorsement of prior art. Summary of the Invention

[0010] In one aspect, the present invention relates to a method for processing a single-crystal silicon ingot, the method comprising: grinding the single-crystal silicon ingot, wherein the single-crystal silicon ingot includes a seed end, a tail end opposite to the seed end, and a body between the seed end and the tail end, wherein the body is ground to a constant diameter; annealing the ground single-crystal silicon ingot to a temperature and duration sufficient to reduce the size or number of localized laser scattering defects on wafers cut from the single-crystal silicon ingot; and cutting the annealed single-crystal silicon ingot into at least two single-crystal silicon wafers.

[0011] The present invention further relates to a method for processing a single-crystal silicon ingot, the method comprising: removing a seed cone and a tail cone from the single-crystal silicon ingot, wherein the single-crystal silicon ingot includes the seed cone, the tail cone opposite to the seed cone, and a body between the seed cone and the tail cone; shearing the body of the single-crystal silicon ingot such that the body of the single-crystal silicon ingot includes one or more single-crystal silicon segments, wherein the thickness of the segments is at least about 1 cm, at least about 10 cm, or at least about 20 cm; annealing one or more of the sheared single-crystal silicon segments to a temperature and duration sufficient to reduce the size or number of local laser scattering defects on a wafer cut from the single-crystal silicon segments; and cutting the annealed single-crystal silicon segments into at least two single-crystal silicon wafers.

[0012] Various improvements to the features mentioned above exist. Further features may also be incorporated into the above aspects. These improvements and additional features may exist individually or in any combination. For example, various features discussed below with respect to any of the illustrated embodiments may be incorporated individually or in any combination into any of the aspects described above. Attached Figure Description

[0014] Figure 1 This table depicts the reduction of LLS ring / nucleus pattern defects in single-crystal silicon fragments before and after annealing at two temperatures and two durations. Defects were measured under 37 nm and 47 nm test conditions. Detailed Implementation

[0015] The methods described herein facilitate the reduction of the size and concentration of defects formed in single-crystal ingots (e.g., single-crystal silicon ingots) grown using the Chuklaski method. Therefore, the methods of the present invention are sufficient to remove defect patterns that affect device yield. Wafers cut from ingots can have laser scattering (LLS) ring / nucleus patterns, the source of which has been considered as defects formed during crystal pulling or etch pits formed by polishing slicing processes. LLS ring / nucleus patterns can only be detected after the wafer has been cut and during LLS ring / nucleus pattern measurement (one of the final process steps in slicing technology). Conventionally, heat treatment is performed on the cut wafers to remove defects associated with LLS ring / nucleus patterns. According to the method of the present invention, the ingot in a rod state is annealed prior to wafer cutting. This annealing has several advantages, including reducing the size and density of defects constituting the LLS ring / nucleus pattern, time and cost savings compared to heat-treating individual wafers, reduced contamination due to heat treatment in the rod state, and uniformity resulting from heating the entire ingot or section of ingot rather than individual wafers.

[0016] The single-crystal silicon ingot used in the method of the present invention may have any length and diameter obtainable by the Chuklaski method. In some embodiments, the diameter of the ingot may be at least about 100 mm, at least about 200 mm, for example at least about 300 mm, at least about 400 mm, or even at least about 450 mm, for example between about 150 mm and about 450 mm. In some embodiments, the length of the ingot is at least 25 cm, for example at least about 50 cm, at least about 75 cm, at least about 100 cm, at least about 150 cm, or even at least about 200 cm, for example between about 100 cm and about 300 cm. In some embodiments, the mass of an ingot having these lengths and diameters may be at least about 15 kg or at least about 100 kg, for example at least about 200 kg, at least about 300 kg, at least about 400 kg, at least about 500 kg, at least about 600 kg, at least about 700 kg, or even at least about 800 kg, for example between about 15 kg and about 450 kg, for example between about 150 kg and about 450 kg. A single-crystal silicon ingot grown by the Chuklaski method includes a seed cone at a seed end and a tail cone at a tail end opposite the seed end. The ingot also includes a body portion between the seed end and the tail end. After ingot growth, the single-crystal silicon ingot may be cooled to a permissible disposal temperature. Although the method of the present invention can be applied to ingots in the form of grown material, generally, the seed cone and tail cone are removed from the ingot before the method of the present invention.

[0017] In some embodiments, a monocrystalline silicon ingot with the seed cone and tail cone removed may be sheared into one or more monocrystalline silicon segments. The monocrystalline silicon ingot may also be trimmed to have orientation planes or notches at peripheral portions to indicate crystal orientation. The thickness of any one of the one or more monocrystalline silicon segments may be at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 50 cm. Generally, the segment thickness is less than about 1 m, less than about 50 cm, less than about 40 cm, or less than 30 cm. In some embodiments, the segment thickness is between about 10 cm and about 30 cm.

[0018] In some embodiments, the ingot may be subjected to grinding sufficient to produce an ingot having a body having a constant diameter region. Grinding may occur over the entire monocrystalline silicon ingot (i.e., prior to shearing). The length of the uncuttered ingot may be at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 1 m, for example, between about 1 m and about 3 m. The weight of these ingots may be between about 15 kg and about 450 kg, for example, between about 150 kg and about 450 kg. Ingots having a diameter less than 150 mm or greater than 450 mm, or a loading size other than between about 15 kg and about 450 kg (e.g., between about 150 kg and about 450 kg), may also be grown using the systems and methods disclosed herein. Alternatively, the sheared segments may be ground into a constant diameter region. The thickness of any one of the one or more monocrystalline silicon segments may be at least about 1 cm, at least about 10 cm, at least about 20 cm, or at least about 50 cm. Generally, the fragment thickness is less than about 1 μm, less than about 50 cm, less than about 40 cm, or less than about 30 cm. In some embodiments, the fragment thickness is between about 10 cm and about 30 cm. A machine employing grinding wheels shapes the ingot to the precision required for wafer diameter control. Other grinding wheels are then used to carve feature notches or planes to define the proper orientation of the future wafer relative to a specific crystal axis. The diameter of the constant diameter region can be at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm, for example, between about 150 mm and about 450 mm.

[0019] During the growth process, the crucible slowly dissolves oxygen into the melt to incorporate it into the final crystal ingot. In some embodiments, the ingot or any single-crystal silicon wafer cut from it may include interstitial oxygen, the concentration of which is typically achievable using the Chuklaski method. In some embodiments, the ingot or any single-crystal silicon wafer cut from it includes oxygen at a concentration between about 4 PPMA (about 2 x 10⁻⁶ ppm). 17 atoms / cm 3 ) and approximately 18 PPMA (approximately 9x10 17 atoms / cm 3 In some embodiments, the semiconductor wafer includes oxygen at a concentration between approximately 4 PPMA (approximately 2 x 10⁻⁶ ppm). 17 atoms / cm 3 ) and approximately 45 PPMA (approximately 2.2 x 10⁻⁶) 18 atoms / cm 3 Between, for example, between approximately 10 PPMA (approximately 5 x 10) 17 atoms / cm 3 ) and approximately 35 PPMA (approximately 1.7 x 10⁻⁶) 18atoms / cm 3 Between 12 PPMA (approximately 6 x 10⁻⁶ ppm). Preferably, the ingot or any single-crystal silicon wafer cut from it contains oxygen with a concentration not exceeding about 12 PPMA (approximately 6 x 10⁻⁶ ppm). 17 atoms / cm 3 For example, less than about 10 PPMA (about 5 x 10⁻⁶ PPMA). 17 atoms / cm 3 Interstitial oxygen can be measured according to SEMI MF 1188-1105.

[0020] Typical carbon concentrations in ingots grown using the Chuklaski method can be less than approximately 1.0 x 10⁻⁶. 16 atoms / cm 3 For example, between approximately 2x10 15 atoms / cm 3 With approximately 1.0 x 10 16 atoms / cm 3 Between or between approximately 5x10 15 atoms / cm 3 With approximately 1.0 x 10 16 atoms / cm 3 between.

[0021] The intentional addition of dopants controls the resistivity distribution of the final crystal. Generally, the resistivity of an ingot or any monocrystalline silicon wafer cut from it is not limited. Instead, the resistivity of the ingot, segment, and wafer cut from it is determined by the end use of the wafer. An ingot, segment, or any monocrystalline silicon wafer cut from it can have any resistivity obtainable by the Chuklaski or floating zone method. Therefore, the resistivity of an ingot, segment, or any monocrystalline silicon wafer cut from it is based on the requirements of the end use / application of the structure of the invention. Thus, the resistivity can vary from milliohms or less to megaohms or greater. In some embodiments, an ingot or any monocrystalline silicon wafer cut from it includes p-type or n-type dopants. Suitable dopants include p-type dopants (e.g., boron, aluminum, gallium, and indium) and n-type dopants (e.g., phosphorus, arsenic, and antimony). The dopant concentration is selected based on the desired resistivity. In some embodiments, an ingot, segment, or any monocrystalline silicon wafer cut from it includes p-type dopants, such as boron. In some embodiments, any single-crystal silicon wafer, ingot, segment, or cut from it includes an n-type dopant, such as arsenic or phosphorus.

[0022] In some embodiments, an ingot, segment, or any single-crystal silicon wafer cut from it has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm, less than about 50 ohm-cm, less than about 1 ohm-cm, less than about 0.1 ohm-cm, or even less than about 0.01 ohm-cm. In some embodiments, an ingot, segment, or any single-crystal silicon wafer cut from it has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm or between about 1 ohm-cm and about 100 ohm-cm, for example, between about 0.01 ohm-cm and about 100 ohm-cm. The low resistivity wafer may include electroactive dopants, such as p-type dopants (e.g., boron, aluminum, gallium, and indium) and / or n-type dopants (e.g., phosphorus, arsenic, and antimony).

[0023] In some embodiments, the ingot, segment, or any single-crystal silicon wafer cut from it has a relatively high minimum bulk resistivity. The high resistivity ingot, segment, or wafer may include electroactive dopants, such as p-type dopants (e.g., boron, aluminum, gallium, and indium) and / or n-type dopants (e.g., phosphorus, arsenic, and antimony), which are typically present in very low concentrations. In some embodiments, any single-crystal silicon wafer, ingot, segment, or cut therefrom, has a minimum bulk resistivity of at least 100 Ohm-cm, at least about 500 Ohm-cm, at least about 1000 Ohm-cm, or even at least about 3000 Ohm-cm, for example, between 100 Ohm-cm and about 100,000 Ohm-cm, or between about 500 Ohm-cm and about 100,000 Ohm-cm, or between about 1000 Ohm-cm and about 100,000 Ohm-cm, or between about 500 Ohm-cm and about 10,000 Ohm-cm, or between about 750 Ohm-cm and about 10,000 Ohm-cm, between about 1000 Ohm-cm and about 10,000 Ohm-cm, between about 2000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm-cm. Between 10,000 Ohm-cm and approximately 3,000 Ohm-cm or between approximately 5,000 Ohm-cm.

[0024] Any monocrystalline silicon wafer, whether cast, segmented, or cut from it, may have any of the (100), (110), or (111) crystal orientations, and the choice of crystal orientation may be indicated by the end use of the structure.

[0025] The monocrystalline silicon ingot or its sheared fragment is annealed prior to wafer dicing. Annealing can occur on the ingot while the seed cone and end cone are still in place, thereby removing the seed cone and end cone, or a sheared fragment thereof, which can then be annealed. Annealing is performed at a temperature and duration sufficient to reduce defects found in LLS annular / nucleate patterns in wafers diced from annealed ingots or fragments. Advantageously, other defects may also be reduced. Annealing can occur in a furnace (e.g., a box furnace suitable for industrial or laboratory use). The annealing atmosphere is typically inert, i.e., non-hydrogenated and / or non-oxidizing. In some embodiments, the atmosphere may include argon, nitrogen, or a combination of argon and nitrogen. In some embodiments, the ambient atmosphere comprises argon. In some embodiments, the ambient atmosphere is essentially composed of high-purity argon, for example, at least about 99% by volume, at least about 99.9% by volume, at least about 99.99% by volume, or even at least about 99.999% by volume. In some embodiments, the ambient atmosphere comprises nitrogen. In some embodiments, the ambient atmosphere is essentially composed of high-purity nitrogen, for example, at least about 99% by volume, at least about 99.9% by volume, at least about 99.99% by volume, or even at least about 99.999% by volume. In some embodiments, the ambient atmosphere comprises a combination of argon and nitrogen, wherein the nitrogen content may vary between about 1% by volume and about 99% by volume, for example, between about 10% by volume and about 90% by volume, or between about 20% by volume and about 80% by volume, in equilibrium with argon. In some embodiments, the annealing temperature is at least about 600°C, for example, between about 600°C and about 1200°C, or between about 600°C and about 1000°C, or between about 600°C and about 900°C, or between about 700°C and about 900°C. In some embodiments, the monocrystalline silicon ingot or a fragment thereof is annealed for a duration of at least about 1 hour, for example, between about 1 hour and about 6 hours, for example, between about 1 hour and about 4 hours, or between about 1 hour and about 3 hours, or for a duration of about 2 hours.

[0026] After annealing and cooling to a temperature sufficient for handling, individual wafers are cut from the heat-treated ingot. Wafer shaping involves a series of precise mechanical and chemical process steps required to transform ingot fragments into functional wafers. During these steps, the wafer surface and dimensions are refined to rigorous detail. Each step is designed to conform the wafer to user specifications. The first of these critical steps is multi-wire sawing. The main state-of-the-art sawing technology is multi-wire sawing (MWS). Here, fine wires are arranged above a cylindrical roller, allowing hundreds of parallel segments to travel simultaneously through the ingot. As the saw moves slowly through the ingot as a whole, individual segments undergo translational motion to always keep the new wire in contact with silicon. The sawing effect is actually achieved by SiC or other abrasives running along the rotating wire. After MWS, the wafers are cleaned and consolidated into process batches and transported to the next operation. Lateral deflection of the wire saw can cause markings or “ripples” on the wafer surface, and wire-to-wire thickness variations result in wafer thickness variations of no more than a few micrometers. This exposes the wafers to complex polishing processes. At least two wafers are cut from an annealed ingot or segment. Each wafer includes: two principally parallel surfaces, one being the front surface of the monocrystalline silicon wafer and the other being the rear surface; a circumferential edge connecting the front and rear surfaces; a central plane between the front and rear surfaces and parallel to said surfaces; a central axis perpendicular to the central plane; and a blocky region between the front and rear surfaces. Each wafer has a thickness less than about 1500 micrometers, as measured between the front and rear surfaces and along the central axis. Typical segments (e.g., segments with lengths between about 10 cm and about 30 cm) can be cut into between about 2 wafers and about 400 wafers, for example, between about 2 wafers and about 300 wafers, or between about 10 wafers and about 300 wafers, or between about 50 wafers and about 300 wafers.

[0027] Pre-surface polishing is typically performed in a two-step process. A mechanical polishing step (thinning) produces flatness, followed by chemical etching to produce smoothness. After polishing, the wafer undergoes final cleaning. Thinning the wafer removes saw marks and surface defects from the front and back sides, thins the wafer to specifications, and relieves most of the stress that has accumulated in the wafer during the sawing process. The purpose of thinning includes removing subsurface damage in the cut wafer, thinning the wafer to the target thickness, and achieving high parallelism and flatness of the wafer surface. Both single-sided and double-sided thinning processes can be used to thin substrate wafers. In double-sided thinning (DSL), loose abrasive particles are suspended in a colloidal slurry to abrade the material on the wafer surface. The wafer is held in a gear carrier driven by planetary motion. After a batch of wafers is manually loaded into the holes of the carrier, the upper plate is forced downward by a specific pressure (or weight) (e.g., about 1 kg to about 30 kg or about 5 kg to about 20 kg, such as about 10 kg). The two plates begin to rotate in the same or opposite directions. During double-sided thinning, both sides of the wafer are thinned simultaneously. A gel-like slurry is continuously filled into the thinning machine, and a slurry film is typically present between the wafer and the two plates. As the abrasive grains slide or roll between the wafer surface and the two plates, the slurry removes material through the abrasive grains. Thinning can occur for at least 1 minute, at least 5 minutes, at least 10 minutes, at least 15 minutes, at least 20 minutes, or at least 25 minutes, for example, about 10 minutes. Thinning parameters, including thinning pressure, plate rotation speed, plate material, abrasive material and grain size, slurry concentration, slurry flow rate, and carrier design, can be based on conventional techniques. For example, the particle size in the thinning slurry can range from about 1 micrometer to about 250 micrometers, for example, between about 1 micrometer and about 50 micrometers, for example, between about 5 micrometers and about 20 micrometers. The rotation speed can range from about 10 rpm to about 150 rpm or from about 25 rpm to about 150 rpm, for example, about 50 rpm, about 75 rpm, or about 100 rpm. In some embodiments, the wafer may be contacted with an alumina (Al2O3) slurry. In some embodiments, the wafer may be contacted with a slurry comprising single-crystal diamond particles. In some embodiments, the wafer may be contacted with a slurry comprising boron carbide particles. In some embodiments, the wafer may be contacted with a slurry comprising silicon carbide particles.

[0028] Edge grinding is typically performed before or after thinning and is crucial for the structural integrity of the wafer. The edge grinding step is critical for the safety of the wafer edges. Single-crystal silicon is very fragile, and if the edges are not contoured or rounded, peeling can occur during processing. Edge peeling not only adversely affects individual wafers but can also contaminate processing equipment or nearby wafers, impacting other wafers being processed. The edges of 200 mm and 300 mm wafers are rounded, even in notched areas. This edge is ground with a diamond disc to remove damage and eliminate peripheral stress. Edge grinding adjusts the final diameter of the wafer (with an accuracy up to 0.02 mm).

[0029] After a final cleaning and polishing, the wafers are prepared for final inspection before delivery. Individual wafer planarity and surface grain are measured using specially designed inspection tools to ensure wafer quality. The method of this invention can reduce the defect characteristics of LLS annular / nucleus patterns. In some embodiments, the number of defects in LLS annular / nucleus patterns can be reduced by at least about 50%, for example, at least about 60%, at least about 70%, or even at least about 80%, using a 37 nm LLS size criterion.

[0030] Example 1.

[0031] A shear saw cuts the single-crystal silicon ingot grown using the Chuklaski method into fragments. This achieves the goal of Perfect Silicon. TM SunEdison Semiconductor Co., Ltd. grows silicon ingots under standard conditions. These standards include ingots free from agglomeration defects, DSOD (direct surface oxidation defects), COP (crystal-derived pits), D defects, and I defects. Oxygen concentration is less than 6.0 x 10⁻⁶. 17 atoms / cm 3 (Approximately 12 PPMA).

[0032] The sheared fragments can be ground into bodies with a constant diameter. Alternatively, the sheared fragments can be annealed prior to grinding. The fragments are loaded into a box furnace (TCM, STC80K-CT). In some cases, the fragments are annealed at 500°C for one hour in a nitrogen atmosphere. In some cases, the fragments are annealed at 900°C for two hours. The annealed fragments are then cut into individual wafers by a wire saw, and the LLS annular / nucleus defect pattern is analyzed.

[0033] The 37 nm (LLS lattice size) and 47 nm (LLS lattice size) LLS patterns were not removed during a heat treatment at 500 °C for 1 hour. See also Figure 1 The second and third rows. These rows depict wafer defect patterns based on the average number of wafers cut from the segment before annealing and the average number of wafers cut from 25 wafers after annealing. (Example) Figure 1 The results show that low-temperature, short-duration annealing did not significantly reduce defect density. LLS images of every 25 wafers stacked together were examined after polishing and cleaning steps, and each 25 images before and after the results were also sister cassettes, indicating that each cassette image was of the same image and quality before heat treatment. Higher-temperature, longer-duration annealing reduced the number of defects and caused pattern disappearance, and completely removed LLS annular / nucleate patterns under bar heat treatment conditions of 900°C for 2 hours. See also Figure 1 The fourth and fifth columns. For these wafers, based on the 37 nm LLS size guideline, the average number of LLS defects was reduced from 157 defects per wafer to 24 defects per wafer.

[0034] When describing elements of the invention or embodiments thereof, the articles “a,” “an,” “the,” and “said” are intended to indicate the presence of one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and indicate that additional elements may be present in addition to those listed.

[0035] Because various changes can be made to the above construction and methods without departing from the scope of the invention, all objectives contained in the above description and shown in the accompanying drawings should be interpreted as illustrative rather than restrictive.

Claims

1. A method for processing single-crystal silicon ingots, the method comprising: The single-crystal silicon ingot is ground, wherein the single-crystal silicon ingot includes a seed end, a tail end opposite to the seed end, and a body between the seed end and the tail end, wherein the body is ground to a constant diameter, wherein the diameter of the body of the single-crystal silicon ingot is at least about 150 mm, and the minimum thickness of the single-crystal silicon ingot is at least about 25 cm. The polished single-crystal silicon ingot is annealed at a temperature and for a duration sufficient to reduce the size or number of localized laser scattering defects on the wafer cut from the single-crystal silicon ingot, wherein the single-crystal silicon ingot is annealed at a temperature between about 600°C and about 900°C for a duration of at least about 1 hour, and further wherein the single-crystal silicon ingot is annealed in an atmosphere comprising argon, nitrogen, or a combination of argon and nitrogen, thereby reducing the number of defects in the laser scattering ring / nucleus pattern by at least 80% using the 37 nm LLS size criterion; and The annealed monocrystalline silicon ingot is cut into at least two monocrystalline silicon wafers.

2. The method of claim 1, wherein the single-crystal silicon ingot is grown by the Chuklaski process and the single-crystal silicon ingot is cooled prior to grinding, and further wherein the single-crystal silicon ingot comprises oxygen at a concentration between about 4 PPMA (about 2 x 10⁻⁶ ppm). 17 atoms / cm 3 ) and approximately 18 PPMA (approximately 9x10 17 atoms / cm 3 )between.

3. The method of claim 1, wherein the diameter of the body of the single-crystal silicon ingot is at least about 300 mm.

4. The method of claim 1, further comprising the step of shearing the single-crystal silicon ingot into one or more segments, wherein the thickness of the segments is at least about 1 cm.

5. The method of claim 1, further comprising the step of shearing the single-crystal silicon ingot into one or more segments, wherein the thickness of the segments is less than about 1 m.

6. The method of claim 1, further comprising the step of shearing the single-crystal silicon ingot into one or more segments, wherein the thickness of the segments is between about 10 cm and about 30 cm.

7. The method of claim 1, wherein each single-crystal silicon wafer cut from the annealed ingot comprises: Two main, generally parallel surfaces, one being the front surface of the monocrystalline silicon wafer and the other being the rear surface of the monocrystalline silicon wafer; a circumferential edge connecting the front and rear surfaces of the monocrystalline silicon wafer; a central plane between and parallel to the front and rear surfaces of the monocrystalline silicon wafer; a central axis perpendicular to the central plane; and a blocky region between the front and rear surfaces of the monocrystalline silicon wafer, wherein each wafer has a thickness less than approximately 1500 micrometers as measured between the front and rear surfaces of the monocrystalline silicon wafer and along the central axis.

8. The method of claim 1, wherein the annealed monocrystalline silicon ingot is cut into between about two monocrystalline silicon wafers and about 300 monocrystalline silicon wafers.

9. The method of claim 1, wherein the annealed single-crystal silicon ingot is cut into about 300 single-crystal silicon wafers.

10. The method of claim 1, wherein the single-crystal silicon ingot is annealed in an atmosphere comprising nitrogen.

11. The method of claim 1, wherein the single-crystal silicon ingot is annealed in an environment essentially composed of nitrogen.

12. The method of claim 1, wherein the single-crystal silicon ingot is annealed at a temperature between about 700°C and about 900°C.

13. The method of claim 1, wherein the monocrystalline silicon ingot is annealed for a duration between about 1 hour and about 4 hours.

14. The method of claim 1, wherein the monocrystalline silicon ingot is annealed for a duration of about 2 hours.

15. A method for processing single-crystal silicon ingots, the method comprising: Remove the seed cone and tail cone from the monocrystalline silicon ingot, wherein the monocrystalline silicon ingot includes the seed cone, the tail cone opposite the seed cone, and a body between the seed cone and the tail cone, wherein the diameter of the body of the monocrystalline silicon ingot is at least about 150 mm; The body of the monocrystalline silicon ingot is sheared such that the body of the monocrystalline silicon ingot comprises one or more monocrystalline silicon segments, wherein the thickness of the segments is at least about 1 cm, at least about 10 cm, or at least about 20 cm. Annealing one or more of the sheared single-crystal silicon segments at a temperature and duration sufficient to reduce the size or number of localized laser scattering defects on the wafer cut from the single-crystal silicon segments, wherein the one or more of the sheared single-crystal silicon segments are annealed at a temperature between about 600°C and about 900°C for a duration of at least about 1 hour, and further wherein the one or more of the sheared single-crystal silicon segments are annealed in an atmosphere comprising argon, nitrogen, or a combination of argon and nitrogen, thereby reducing the number of defects in the laser scattering annular / nucleate pattern by at least 80% using the 37 nm LLS size criterion; and The annealed single-crystal silicon fragment is cut into at least two single-crystal silicon wafers.

16. The method of claim 15, wherein the single-crystal silicon ingot is grown by the Chuklaski process, and wherein the single-crystal silicon ingot comprises oxygen at a concentration between about 4 PPMA (about 2 x 10⁻⁶ ppm). 17 atoms / cm 3 ) and approximately 18 PPMA (approximately 9x10 17 atoms / cm 3 )between.

17. The method of claim 15, further comprising grinding the body of the single-crystal silicon fragment, wherein the body is ground to a constant diameter of at least about 300 mm.

18. The method of claim 15, wherein the thickness of the single-crystal silicon segment is less than about 1 m.

19. The method of claim 15, wherein the thickness of the monocrystalline silicon segment is between about 10 cm and about 30 cm.

20. The method of claim 15, wherein each single-crystal silicon wafer diced from the annealed single-crystal silicon segment comprises: Two main, generally parallel surfaces, one being the front surface of the monocrystalline silicon wafer and the other being the rear surface of the monocrystalline silicon wafer; a circumferential edge connecting the front and rear surfaces of the monocrystalline silicon wafer; a central plane between and parallel to the front and rear surfaces of the monocrystalline silicon wafer; a central axis perpendicular to the central plane; and a blocky region between the front and rear surfaces of the monocrystalline silicon wafer, wherein each wafer has a thickness less than approximately 1500 micrometers as measured between the front and rear surfaces of the monocrystalline silicon wafer and along the central axis.

21. The method of claim 15, wherein the annealed single-crystal silicon fragment is cut into a range between about two single-crystal silicon wafers and about 300 single-crystal silicon wafers.

22. The method of claim 15, wherein the annealed single-crystal silicon fragment is diced into about 300 single-crystal silicon wafers.

23. The method of claim 15, wherein the single-crystal silicon fragment is annealed in an atmosphere comprising nitrogen.

24. The method of claim 15, wherein the single-crystal silicon fragment is annealed in an environment essentially composed of nitrogen.

25. The method of claim 15, wherein the single-crystal silicon fragment is annealed at a temperature between about 600°C and about 1000°C.

26. The method of claim 15, wherein the monocrystalline silicon fragment annealing lasts for a duration between about 1 hour and about 4 hours.

27. The method of claim 15, wherein the monocrystalline silicon fragment is annealed for a duration of about 2 hours.

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