A differential capacitive sensor signal detection device
By employing superposition amplification, capacitive coupling, and transformer coupling in a differential capacitive sensor to process the signals from the upper and lower plates of the intermediate capacitor, the problem of the reference signal and the measured signal being difficult to be in phase and frequency synchronization in phase-sensitive detection is solved, thus improving the accuracy of signal detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF EARTHQUAKE SCI CHINA EARTHQUAKE ADMINISTATION
- Filing Date
- 2026-04-02
- Publication Date
- 2026-06-05
AI Technical Summary
In differential capacitive sensors, it is difficult for the reference signal and the measured signal to be in phase and frequency in phase-sensitive detection, resulting in poor signal detection performance, especially in complex environments such as downhole drilling strain.
A differential capacitive sensor signal detection device is adopted. The signals of the upper and lower plates of the intermediate capacitor are amplified by superposition, coupled by capacitor and transformer, and then used as the measured signal. The square wave signal obtained by comparing the measured signal with the signals of the upper and lower plates of the intermediate capacitor through a comparison circuit is used as the reference signal to ensure the same frequency and phase characteristics of the signals.
It achieves the goal of ensuring that the reference signal and the measured signal are in phase and frequency in complex environments, thereby improving the accuracy and quality of signal detection.
Smart Images
Figure CN122149303A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of differential sensor signal detection technology, and particularly relates to a high-precision micro-displacement signal detection device for differential capacitive sensors. Background Technology
[0002] Differential capacitive micro-displacement sensors play a crucial role in high-precision measurements such as geophysical fields and seismic observations. They are commonly used in vertical pendulum / quartz horizontal pendulum inclinometers, borehole strain gauges, seismographs, and fused silica gravimeters. A differential capacitive sensor typically consists of three parallel metal plates. Depending on the instrument's mechanical structure, some instruments use the central plate as the moving plate and the two side plates as fixed plates (such as inclinometers and strain gauges), while others do the opposite (such as seismographs and fused silica gravimeters). In a differential capacitive sensor, changes in the position of the central or side plates will cause a change in the capacitance of the differential plate capacitor. A bridge circuit can be used to convert this change in capacitance into a voltage change. This voltage change, after phase-sensitive detection, amplification, and filtering, yields a voltage output signal proportional to the change in plate position. Based on this voltage output signal, the corresponding change in the measured physical quantity can be calculated.
[0003] In the micro-displacement signal detection circuit of a differential capacitive sensor, the phase-sensitive detector circuit, which is sensitive to the signal phase and frequency, plays a crucial role, and its performance directly determines the quality of the signal detection circuit. Phase-sensitive detectors are generally composed of analog switches and operational amplifiers, and they also require a local reference signal. To obtain good results, this local reference signal should be in phase and frequency with the measured signal. However, in reality, this requirement is often difficult to meet; there is always a certain phase jitter / phase shift between the local reference signal and the measured signal, affecting the signal detection effect and the instrument's observation quality. This problem is particularly serious in complex environments and long wiring applications such as downhole borehole strain. Summary of the Invention
[0004] The purpose of this invention is to provide a differential capacitive sensor signal detection device, which aims to solve the problem that it is difficult to ensure that the reference signal and the measured signal are in the same frequency and phase in phase-sensitive detection.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: A differential capacitive sensor signal detection device, the device comprising: a first metal plate and a second metal plate arranged in parallel and opposite to each other, wherein an intermediate capacitor is arranged in parallel between the first metal plate and the second metal plate; An upper capacitor is formed between the first metal plate and the upper plate of the intermediate capacitor; A lower capacitor is formed between the second metal plate and the lower electrode of the intermediate capacitor; The first metal plate and the second metal plate are connected to a sine wave signal source, so that the sine wave signals on the first metal plate and the second metal plate have equal amplitude, equal frequency, and opposite phase; An external capacitor is connected in parallel with the intermediate capacitor; The sum of the capacitances of the external capacitor and the intermediate capacitor is much greater than the capacitance values of the upper capacitor and the lower capacitor. The electrical signals output from the upper and lower plates of the intermediate capacitor are amplified by a superposition circuit and coupled by a first coupling circuit, and then connected to a phase-sensitive detector as the measured signal. The electrical signals output from the upper and lower plates of the intermediate capacitor are then connected to the phase-sensitive detector as reference signals after passing through a second coupling circuit and a comparison circuit. The phase-sensitive detector outputs a signal associated with the position of the intermediate capacitor.
[0006] Preferably, the superimposed amplifier circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a thirteenth resistor, a fifteenth resistor, a sixteenth resistor, a first capacitor, a fourth capacitor, an eighth capacitor, a first field-effect transistor, a second field-effect transistor, a first transistor, a second transistor, and a first integrated operational amplifier; The upper plate of the intermediate capacitor is connected to one end of the fourth resistor and the fifth resistor respectively, and the other end of the fourth resistor is connected to the gate of the second field-effect transistor. The lower stage board of the intermediate capacitor is connected to one end of the ninth resistor and the tenth resistor respectively, and the other end of the fifth resistor and the ninth resistor is grounded; the other end of the tenth resistor is connected to the gate of the first field-effect transistor. The drains of the first and second field-effect transistors are both connected to one end of the second resistor and one end of the fourth capacitor, and the other end of the second resistor is connected to the first positive power supply. The other end of the fourth capacitor is connected to one end of the first capacitor, one end of the first resistor, and the inverting input terminal of the first integrated operational amplifier, respectively. The other end of the first capacitor and the other end of the first resistor are connected to the output terminal of the first integrated operational amplifier. The positive power supply terminal of the first integrated operational amplifier is connected to the first positive power supply, the negative power supply terminal of the first integrated operational amplifier is connected to the negative power supply, and the non-inverting input terminal of the first integrated operational amplifier is grounded. The output terminal of the first integrated operational amplifier is also connected to the first coupling circuit and one end of the third resistor. The other end of the third resistor is connected to one end of the eighth capacitor and one end of the fifteenth resistor, and the other end of the fifteenth resistor is grounded. The other end of the eighth capacitor is connected to one end of the seventh resistor, one end of the eighth resistor, and the collector of the first transistor, respectively. The other end of the seventh resistor is connected to the source of the second field-effect transistor, and the other end of the eighth resistor is connected to the source of the first field-effect transistor. The base of the first transistor is connected to one end of the thirteenth resistor and the collector of the second transistor, respectively. The other end of the thirteenth resistor is grounded. The emitter of the first transistor is connected to the base of the second transistor and one end of the sixteenth resistor, respectively. The emitter of the second transistor and the other end of the sixteenth resistor are connected to the negative power supply.
[0007] Preferably, the first coupling circuit includes a second capacitor, a third capacitor, and a first transformer; The output terminal of the first integrated operational amplifier is also connected to one end of the second capacitor and one end of the third capacitor respectively; the other ends of the second capacitor and the third capacitor are connected to the upper end of the primary coil of the first transformer, the lower end of the primary coil of the first transformer is grounded; the middle tap of the secondary coil of the first transformer is grounded. The output signals from the upper and lower ends of the secondary coil of the first transformer are used as the measured signals and input to the phase-sensitive detector.
[0008] Preferably, the second coupling circuit includes a fifth capacitor, a sixth resistor, a fourteenth resistor, and a second transformer; The source of the first field-effect transistor is also connected to the upper end of the primary coil of the second transformer; The source of the second field-effect transistor is also connected to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the lower end of the primary coil of the second transformer. One end of the sixth resistor is connected to the second positive power supply, and the other end is connected to the middle tap of the secondary coil of the second transformer and one end of the fourteenth resistor. The other end of the fourteenth resistor is grounded. The upper and lower ends of the secondary coil of the second transformer are connected to the comparator circuit.
[0009] Preferably, the comparison circuit includes a comparator; The upper end of the secondary coil of the second transformer is connected to the inverting input or the non-inverting input of the comparator; the lower end of the secondary coil of the second transformer is connected to the non-inverting input or the inverting input of the comparator, and the square wave signal output by the output of the comparator is used as the reference signal input to the phase-sensitive detector. The positive power supply terminal of the comparator is connected to a second positive power supply, and the negative power supply terminal of the comparator is grounded.
[0010] Preferably, the phase-sensitive detector is also connected to a first amplifier circuit; The phase-sensitive detector includes a dual-channel first analog switch and a second analog switch; the first amplifier circuit includes a first amplifier unit and a second amplifier unit. The upper end of the secondary coil of the first transformer is connected to the S1 pin of the first analog switch and the S2 pin of the second analog switch, respectively. The lower end of the secondary coil of the first transformer is connected to the S2 pin of the first analog switch and the S1 pin of the second analog switch, respectively. The output of the comparator is connected to the IN1 and IN2 pins of the first analog switch, and the IN1 and IN2 pins of the second analog switch, respectively. The VDD pins of the first analog switch and the second analog switch are connected to the first positive power supply. The VSS pins of the first and second analog switches are connected to the negative power supply. The grounding pins of the first and second analog switches are grounded together; The NC pins of the first and second analog switches are left floating. The D1 and D2 pins of the first analog switch are connected to the first amplification unit; The D1 and D2 pins of the second analog switch are connected to the second amplification unit.
[0011] Preferably, the first amplification unit includes an eleventh resistor, a twelfth resistor, a seventh capacitor, and a second integrated operational amplifier; The D1 and D2 pins of the first analog switch are connected to one end of the eleventh resistor, and the other end of the eleventh resistor is connected to one end of the seventh capacitor, one end of the twelfth resistor, and the inverting input of the second integrated operational amplifier, respectively; the non-inverting input of the second integrated operational amplifier is grounded. The positive power supply terminal of the second integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the seventh capacitor, the other end of the twelfth resistor, and the output terminal of the second integrated operational amplifier are connected to the first output terminal.
[0012] Preferably, the second amplification unit includes a seventeenth resistor, an eighteenth resistor, a ninth capacitor, and a third integrated operational amplifier; The D1 and D2 pins of the second analog switch are connected to one end of the seventeenth resistor, and the other end of the seventeenth resistor is connected to one end of the ninth capacitor, one end of the eighteenth resistor, and the inverting input of the third integrated operational amplifier, respectively; the non-inverting input of the third integrated operational amplifier is grounded. The positive power supply terminal of the third integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the ninth capacitor, the other end of the eighteenth resistor, and the output terminal of the third integrated operational amplifier are connected to the second output terminal; The first output terminal and the second output terminal form a pair of differential signal output terminals.
[0013] Preferably, the phase-sensitive detector includes a third analog switch; the phase-sensitive detector is connected to a second amplification circuit, the second amplification circuit including a third amplification unit and an inverting amplification unit; The upper end of the secondary coil of the first transformer is connected to the S1 pin of the third analog switch; The lower end of the secondary coil of the first transformer is connected to the S2 pin of the third analog switch; The output of the comparator is connected to the IN1 and IN2 pins of the third analog switch, respectively. The VDD pin of the third analog switch is connected to the first positive power supply. The VSS pin of the third analog switch is connected to the negative power supply. The grounding pin of the third analog switch is grounded; The NC pin of the third analog switch is left floating; The D1 and D2 pins of the third analog switch are connected to the input terminals of the third amplification unit; The output terminal of the third amplification unit is connected to the input terminal of the inverting amplification unit; The output terminal of the third amplification unit is connected to the first output terminal.
[0014] Preferably, the inverting amplifier unit includes a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a tenth capacitor, and a fourth integrated operational amplifier; The third amplification unit has the same structure as the first amplification unit; The output terminal of the third amplification unit is connected to one end of the nineteenth resistor, and the other end of the nineteenth resistor is connected to one end of the tenth capacitor, one end of the twentieth resistor, and the inverting input terminal of the fourth integrated operational amplifier; the non-inverting input terminal of the fourth integrated operational amplifier is grounded. The positive power supply terminal of the fourth integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the tenth capacitor is connected to the output terminal of the fourth integrated operational amplifier; The output terminal of the fourth integrated operational amplifier is also connected to one end of the twenty-first resistor, and the other ends of the twenty and twenty-first resistors are connected to the second output terminal. The first output terminal and the second output terminal form a pair of differential signal output terminals.
[0015] The advantages of this invention are: The differential capacitive sensor signal detection device provided by this invention sends the signals from the upper and lower plates of the intermediate capacitor, after superposition amplification, capacitive coupling, and transformer coupling, to the phase-sensitive detector as the measured signal. The square wave signal obtained by comparing and calculating the signals from the upper and lower plates of the intermediate capacitor, after capacitor and transformer coupling, is sent to the phase-sensitive detector unit as the reference signal. Since both the measured signal and the reference signal originate from the upper and lower plates of the intermediate capacitor, this ensures that the two signals have excellent in-phase and frequency-synchronous characteristics. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the signal detection device for a differential capacitive sensor according to the present invention. Figure 2 This is a circuit structure diagram of a differential capacitive sensor signal detection device according to the present invention; Figure 3 This is a circuit diagram of another differential capacitive sensor signal detection device according to the present invention. Detailed Implementation
[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0018] See Figure 1 , Figure 1 This is a schematic diagram of the principle framework of a differential capacitive sensor signal detection device. Figure 1 As shown, the differential capacitive sensor signal detection device provided in this embodiment includes: a first metal plate and a second metal plate arranged parallel to each other and opposite to each other; an intermediate capacitor P2 is arranged parallel between the first metal plate and the second metal plate; an upper capacitor P1 is formed between the first metal plate and the upper plate of the intermediate capacitor; a lower capacitor P3 is formed between the intermediate capacitor and the lower plate of the second metal plate; a sine wave signal source is connected to the first metal plate and the second metal plate, so that the sine wave signals on the first metal plate and the second metal plate have equal amplitude, equal frequency, and opposite phase. An external capacitor C is connected in parallel between the upper and lower plates of the intermediate capacitor P2. in External capacitor C in The sum of the capacitances of the middle capacitor P2 and the upper capacitor P1 and the lower capacitor P3 is much greater than the capacitance values of the upper capacitor P1 and the lower capacitor P3.
[0019] The electrical signals output from the upper and lower plates of the intermediate capacitor P2 are amplified by a superposition circuit and coupled by a first coupling circuit, and then connected to a phase-sensitive detector as the measured signal. The electrical signals output from the upper and lower plates of the intermediate capacitor P2 are further amplified by a second coupling circuit and a comparator circuit, and then connected to the phase-sensitive detector as a reference signal. The output signal of the phase-sensitive detector is amplified to obtain a signal related to the position of the intermediate capacitor P2.
[0020] like Figure 1 As shown, the first metal plate, the second metal plate, and the intermediate capacitor P2 constitute a differential parallel plate capacitor. Depending on the sensor's mechanical structure design, the first and second metal plates on both sides can be used as fixed plates, and the intermediate capacitor P2 as a movable plate; alternatively, the intermediate capacitor P2 can be used as a fixed plate, and the first and second metal plates on both sides can be used as movable plates. The space between the upper and lower plates of the intermediate capacitor P2 is filled with an insulating material. The upper and lower plates of the intermediate capacitor P2, along with the insulating material, are arranged as a single unit, parallel to each other between the first and second metal plates. In other words, the first metal plate, the upper plate of the intermediate capacitor, the lower plate of the intermediate capacitor, and the second metal plate are all parallel to each other.
[0021] Assume the distance between the first metal plate and the upper plate of the intermediate capacitor P2 is d1, the distance between the upper and lower plates of the intermediate capacitor P2 is d2, and the distance between the lower plate of the intermediate capacitor P2 and the second metal plate is d3. Then the capacitance of the upper capacitor P1 is... Where ε is the dielectric constant of air, and S is the area of the metal plate. The capacitances of the middle capacitor P2 and the lower capacitor P3 are respectively... and ,here Let be the dielectric constant of the insulating material between the upper and lower plates of the intermediate capacitor P2. A wire is led out from each of the upper and lower plates of the intermediate capacitor P2 to introduce the signal into the subsequent detection circuit, and an external capacitor is connected between the two wires. The external capacitor It is connected in parallel with the intermediate capacitor P2. The capacitance of the two capacitors in parallel is .
[0022] A sinusoidal signal was applied to the first metal plate and the second metal plate. When the intermediate capacitor P2 is in the equilibrium position, the differential capacitive sensor outputs a voltage of... The output voltage is 0. When a change in the measured physical quantity causes the intermediate capacitor to deviate from its equilibrium position, the output voltage... The amplitude will increase accordingly, and its phase will correspond to the direction of deviation from the equilibrium state.
[0023] As described above, in this differential capacitive sensor, four parallel metal plates form three capacitors C connected in series. S C Z and C X And in C Z There is an external capacitor C connected at both ends. in Generally speaking, the capacitance of a parallel-plate capacitor is relatively small, in the tens of pF. And when connected in parallel with C... Z The capacitance at both ends is relatively large, making Much larger than C S and C XIn this way, the upper and lower plates of the intermediate capacitor P2 are nearly short-circuited, and the voltage difference is very small.
[0024] Then, the signals from the upper and lower plates of the intermediate capacitor P2 are amplified, capacitively coupled, and coupled by a transformer before being sent to the phase-sensitive detector. The square wave signal obtained by comparing and calculating the signals from the upper and lower plates of the intermediate capacitor P2, after being coupled by a capacitor and a transformer, is sent to the phase-sensitive detector unit as a reference signal. Since both the measured signal and the reference signal originate from the upper and lower plates of the intermediate capacitor P2, it is ensured that these two signals have excellent in-phase and frequency-synchronous characteristics.
[0025] The output of the phase-sensitive detector, after passing through an output amplification unit (which can be a proportional-integral amplifier or a low-pass filter plus proportional amplification), yields a differential output signal. The amplitude of this differential output voltage signal is proportional to the magnitude of the deviation of the intermediate capacitor P2 from its equilibrium position, while its phase is related to the direction of this deviation. Therefore, the position information of the intermediate capacitor P2 can be obtained from this differential output signal. Since the change in the position of the intermediate capacitor P2 is caused by the change in the measured physical quantity, the change information of the measured physical quantity can also be obtained.
[0026] See Figure 2 , Figure 2 This is a circuit diagram of a differential capacitive sensor signal detection device according to the present invention. Figure 2 As shown, the superimposed amplifier circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a thirteenth resistor R13, a fifteenth resistor R15, a sixteenth resistor R16, a first capacitor C1, a fourth capacitor C4, an eighth capacitor C8, a first field-effect transistor Q1, a second field-effect transistor Q2, a first transistor Q3, a second transistor Q4, and a first integrated operational amplifier U2.
[0027] The upper plate of the intermediate capacitor P2 is connected to one end of the fourth resistor R4 and the fifth resistor R5, respectively. The other end of the fourth resistor R4 is connected to the gate of the second field-effect transistor Q2. The lower plate of the intermediate capacitor P2 is connected to one end of the ninth resistor R9 and the tenth resistor R10, respectively. The other ends of the fifth resistor R5 and the ninth resistor R9 are grounded. The other end of the tenth resistor R10 is connected to the gate of the first field-effect transistor Q1. The drains of the first field-effect transistor Q1 and the second field-effect transistor Q2 are both connected to one end of the second resistor R2 and one end of the fourth capacitor. The other end of the second resistor R2 is connected to the first positive power supply. The other end of the fourth capacitor is connected to one end of the first capacitor C1, one end of the first resistor R1, and the inverting input of the first operational amplifier U2, respectively. The other ends of the first capacitor C1 and the first resistor R1 are connected to the output of the first operational amplifier U2. The positive power supply of the first operational amplifier U2 is connected to the first positive power supply, the negative power supply of the first operational amplifier U2 is connected to the negative power supply, and the non-inverting input of the first operational amplifier U2 is grounded.
[0028] The output of the first integrated operational amplifier U2 is also connected to the first coupling circuit and one end of the third resistor R3. The other end of the third resistor R3 is connected to one end of the eighth capacitor C8 and one end of the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded. The other end of the eighth capacitor C8 is connected to one end of the seventh resistor R7, one end of the eighth resistor R8, and the collector of the first transistor Q3. The other end of the seventh resistor R7 is connected to the source of the second field-effect transistor Q2, and the other end of the eighth resistor R8 is connected to the source of the first field-effect transistor Q1.
[0029] The base of the first transistor Q3 is connected to one end of the thirteenth resistor R13 and the collector of the second transistor Q4. The other end of the thirteenth resistor R13 is grounded. The emitter of the first transistor Q3 is connected to the base of the second transistor Q4 and one end of the sixteenth resistor R16. The emitter of the second transistor Q4 and the other end of the sixteenth resistor R16 are connected to the negative power supply.
[0030] The first coupling circuit includes a second capacitor C2, a third capacitor C3, and a first transformer T1. The output terminal of the first integrated operational amplifier U2 is also connected to one end of the second capacitor C2 and one end of the third capacitor C3, respectively. The other ends of the second capacitor C2 and the third capacitor C3 are connected to the upper end of the primary coil of the first transformer T1, and the lower end of the primary coil of the first transformer T1 is grounded; the middle tap of the secondary coil of the first transformer T1 is grounded. The output signals from the upper and lower ends of the secondary coil of the first transformer T1 are used as the measured signals input to a phase-sensitive detector.
[0031] The second coupling circuit includes a fifth capacitor C5, a sixth resistor R6, a fourteenth resistor R14, and a second transformer T2. The source of the first field-effect transistor Q1 is connected to the upper end of the primary coil of the second transformer T2; the source of the second field-effect transistor Q2 is connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is connected to the lower end of the primary coil of the second transformer T2.
[0032] One end of the sixth resistor R6 is connected to the second positive power supply, and the other end is connected to the center tap of the secondary coil of the second transformer T2 and one end of the fourteenth resistor R14. The other end of the fourteenth resistor R14 is grounded. In this embodiment, the voltage value of the center tap of the secondary coil of the second transformer T2 is half of the supply voltage of comparator U4, which is also half of the second positive power supply. This second positive power supply is related to the normal operating voltage of comparator U4. In this embodiment, the second positive power supply is 5V, but it can be 12VA, 10VA, or 15VA. Its specific voltage value can be adjusted according to the actual situation of the device, and there is no limitation on its specific voltage value.
[0033] The upper and lower ends of the secondary winding of the second transformer T2 are connected to a comparator circuit. The comparator circuit includes comparator U4. The upper end of the secondary winding of the second transformer T2 is connected to the inverting input (or non-inverting input) of comparator U4; the lower end of the secondary winding of the second transformer T2 is connected to the non-inverting input (or inverting input) of comparator U4. The square wave signal output from the output of comparator U4 is sent as a reference signal to the phase-sensitive detector. The positive power supply terminal of comparator U4 is connected to a second positive power supply, and the negative power supply terminal of comparator U4 is grounded.
[0034] The phase-sensitive detector includes a dual-channel first analog switch U1 and a second analog switch U3. The first amplifier circuit includes a first amplification unit and a second amplification unit. The upper end of the secondary coil of the first transformer T1 is connected to the S1 pin of the first analog switch U1 and the S2 pin of the second analog switch U3, respectively. The lower end of the secondary coil of the first transformer T1 is connected to the S2 pin of the first analog switch U1 and the S1 pin of the second analog switch U3, respectively. The output of the comparator U4 is connected to the IN1 and IN2 pins of the first analog switch U1, and the IN1 and IN2 pins of the second analog switch U3, respectively. The VDD pin of the first analog switch U1 and the second analog switch U3 are connected to a first positive power supply. The VSS pin of the first analog switch U1 and the second analog switch U3 are connected to a negative power supply. The ground pins of the first analog switch U1 and the second analog switch U3 are grounded. The NC pins of the first analog switch U1 and the second analog switch U3 are left floating. The D1 and D2 pins of the first analog switch U1 are connected to the first amplification unit. The D1 and D2 pins of the second analog switch U3 are connected to the second amplification unit.
[0035] The first amplification unit includes an eleventh resistor R11, a twelfth resistor R12, a seventh capacitor C7, and a second operational amplifier U5. The D1 and D2 pins of the first analog switch U1 are connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to one end of the seventh capacitor C7, one end of the twelfth resistor R12, and the inverting input of the second operational amplifier U5, respectively. The non-inverting input of the second operational amplifier U5 is grounded. The positive power supply terminal of the second operational amplifier U5 is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the seventh capacitor C7, the other end of the twelfth resistor R12, and the output terminal of the second operational amplifier U5 are connected to the first output terminal.
[0036] The second amplification unit includes a seventeenth resistor R17, an eighteenth resistor R18, a ninth capacitor C9, and a third operational amplifier U6. Pins D1 and D2 of the second analog switch U3 are connected to one end of the seventeenth resistor R17. The other end of the seventeenth resistor R17 is connected to one end of the ninth capacitor C9, one end of the eighteenth resistor R18, and the inverting input of the third operational amplifier U6, respectively. The non-inverting input of the third operational amplifier U6 is grounded. The positive power supply terminal of the third operational amplifier U6 is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the ninth capacitor C9, the other end of the eighteenth resistor R18, and the output terminal of the third operational amplifier U6 are connected to the second output terminal. The first and second output terminals form a pair of differential signal output terminals.
[0037] Please continue reading. Figure 2 SVin1+ and SVin1- originate from the upper and lower plates of the intermediate capacitor P2, respectively. As mentioned earlier, these two signals are very close in magnitude. These two signals are then fed to the gates of MOSFETs Q2 and Q1 via the fourth resistor R4 and the tenth resistor R10. The signals are amplified by superposition through MOSFETs Q2 and Q1. The drain currents of MOSFETs Q2 and Q1 are superimposed and coupled through the fourth capacitor C4, then fed to the first operational amplifier U2. The superimposed current flows through the first resistor R1 to obtain the output voltage of the first operational amplifier U2. The output of the first operational amplifier U2 is then fed back to the sources of MOSFETs Q2 and Q1 via the third resistor R3 and the fifteenth resistor R15. This forms a negative feedback superposition amplification. The second resistor R2, the fifth resistor R5, and the ninth resistor R9 provide the power supply (i.e., drain-source voltage and gate-source voltage) for the normal operation of the field-effect transistors Q2 and Q1. The first transistor Q3, the second transistor Q4, the thirteenth resistor R13, and the sixteenth resistor R16 form a constant current source (connected to the source of the field-effect transistors Q2 and Q1 through the seventh resistor R7 and the eighth resistor R8) to stabilize the operating point of the field-effect transistors.
[0038] The amplified output (i.e. the output of the first integrated operational amplifier U2) is coupled through the second capacitor C2 and the third capacitor C3 and sent to the primary of the first transformer T1. Equal and opposite signals will be formed at the upper and lower ends of the secondary winding of the first transformer T1. Because the midpoint of the secondary winding of the first transformer T1 is connected to ground, the signals at the upper and lower ends are symmetrical, that is, equal in magnitude and opposite in phase.
[0039] The signals SVin1+ and SVin1- from the upper and lower plates of the intermediate capacitor P2 are respectively supplied to the gates of field-effect transistors Q2 and Q1, and signals are taken from the sources of field-effect transistors Q2 and Q1, such as... Figure 2 As shown, the signal from the source of the field-effect transistor Q2 is connected to the lower end of the primary coil of the second transformer T2 via the fifth capacitor C5, and the signal from the source of the field-effect transistor Q1 is connected to the upper end of the primary coil of the second transformer T2. The signals from the upper and lower ends of the secondary coil of the second transformer T2 are converted into a square wave signal by the comparator U4.
[0040] In the first analog switch U1 and the second analog switch U3, IN1 (or IN2) determines whether switch 1 (i.e., D1 and S1) or switch 2 (i.e., D2 and S2) is connected or disconnected. Taking the ADG1223 analog switch as an example, IN1=IN2=0 indicates that switch 1 is disconnected and switch 2 is connected, while IN1=IN2=1 indicates that switch 1 is connected and switch 2 is disconnected.
[0041] The switching control signals for the first analog switch U1 and the second analog switch U3 are derived from the square wave signal output by comparator U4, serving as the reference signal. The signals to be measured by the first analog switch U1 and the second analog switch U3 originate from the upper and lower terminals of the secondary winding of the first transformer T1. Here, both the reference signal and the signal to be measured originate from SVin1+ and SVin1-, respectively. Because they share the same source, they maintain excellent in-phase and in-frequency characteristics. The first analog switch U1 and the second analog switch U3 implement differential phase-sensitive detection, which is amplified by the second integrated operational amplifier U5 and the fourth integrated operational amplifier U6 to obtain the final differential output signal.
[0042] See Figure 3 , Figure 3 This is another embodiment of a differential capacitive sensor signal detection device. The main difference between this embodiment and the previous one is that the phase-sensitive detector only includes a third analog switch U8. The phase-sensitive detector is connected to a second amplifier circuit, which includes a third amplification unit and an inverting amplification unit.
[0043] Specifically, the upper end of the secondary coil of the first transformer T1 is connected to the S1 pin of the third analog switch U8; the lower end of the secondary coil of the first transformer T1 is connected to the S2 pin of the third analog switch U8. The output of comparator U4 is connected to the IN1 and IN2 pins of the third analog switch U8, respectively. The VDD pin of the third analog switch U8 is connected to the first positive power supply; the VSS pin of the third analog switch U8 is connected to the negative power supply; the ground pin of the third analog switch U8 is grounded; the NC pin of the third analog switch U8 is left floating; the D1 and D2 pins of the third analog switch U8 are connected to the input of the third amplification unit. The output of the third amplification unit is connected to the input of the inverting amplification unit. The output of the third amplification unit is connected to the first output.
[0044] The structure of the third amplification unit is the same as that of the first amplification unit. It includes an eleventh resistor R11, a twelfth resistor R12, a seventh capacitor C7, and a second operational amplifier U5. Pins D1 and D2 of the third analog switch U8 are connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to one end of the seventh capacitor C7, one end of the twelfth resistor R12, and the inverting input of the second operational amplifier U5, respectively. The non-inverting input of the second operational amplifier U5 is grounded. The positive power supply terminal of the second operational amplifier U5 is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the seventh capacitor C7, the other end of the twelfth resistor R12, and the output terminal of the second operational amplifier U5 are connected to the first output terminal.
[0045] The inverting amplifier unit includes a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a tenth capacitor C10, and a fourth operational amplifier U7. The output of the first amplifier unit, which is also the output of the second operational amplifier U5, is connected to one end of the nineteenth resistor R19. The other end of the nineteenth resistor R19 is connected to one end of the tenth capacitor C10, one end of the twentieth resistor C20, and the inverting input of the fourth operational amplifier U7. The non-inverting input of the fourth operational amplifier U7 is grounded. The positive power supply terminal of the fourth operational amplifier U7 is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the tenth capacitor C10 is connected to the output of the fourth operational amplifier U7. The output of the fourth operational amplifier U7 is also connected to one end of the twenty-first resistor R21. The other ends of the twenty and twenty resistors R20 and R21 are connected to the second output terminal. The first and second output terminals form a pair of differential signal output terminals.
[0046] In this embodiment, only one third analog switch U8 is used to implement phase-sensitive detection. The signal to be tested / measured comes from the first transformer T1 (the signals output from the upper and lower ends of the secondary winding of T1 are equal in magnitude but opposite in phase), and the reference signal comes from the square wave signal output from the comparator U4. Because both come from the same source, they can maintain good in-phase and in-frequency characteristics.
[0047] The output of the third analog switch U8 is amplified by the third output amplifier unit to obtain the output signal SVout1+. This signal is then amplified by the inverting amplifier unit to obtain SVout1- (this signal is equal in magnitude but opposite in phase to SVout1+). Thus, SVout1+ and SVout1- form the final differential output signal.
[0048] The first positive power supply can be 12VA, 10VA, 15VA, etc., as long as it is within the normal operating range of the circuit. The negative power supply can be -12VA, -10VA, -15VA, etc., as long as it is within the normal operating range of the circuit. The specific voltage values are not limited.
[0049] The above description describes the preferred embodiments of the present invention and the technical principles applied thereto. For those skilled in the art, any obvious changes such as equivalent transformations or simple substitutions based on the technical solutions of the present invention, without departing from the spirit and scope of the present invention, shall fall within the protection scope of the present invention.
Claims
1. A differential capacitive sensor signal detection device, characterized in that, The device includes: a first metal plate and a second metal plate arranged in parallel and opposite to each other, with an intermediate capacitor arranged in parallel between the first metal plate and the second metal plate; An upper capacitor is formed between the first metal plate and the upper plate of the intermediate capacitor; A lower capacitor is formed between the second metal plate and the lower electrode of the intermediate capacitor; The first metal plate and the second metal plate are connected to a sine wave signal source, so that the sine wave signals on the first metal plate and the second metal plate have equal amplitude, equal frequency, and opposite phase; An external capacitor is connected in parallel with the intermediate capacitor; The sum of the capacitances of the external capacitor and the intermediate capacitor is much greater than the capacitance values of the upper capacitor and the lower capacitor. The electrical signals output from the upper and lower plates of the intermediate capacitor are amplified by a superposition circuit and coupled by a first coupling circuit, and then connected to a phase-sensitive detector as the measured signal. The electrical signals output from the upper and lower plates of the intermediate capacitor are then connected to the phase-sensitive detector as reference signals after passing through a second coupling circuit and a comparison circuit. The phase-sensitive detector outputs a signal associated with the position of the intermediate capacitor.
2. The differential capacitive sensor signal detection device as described in claim 1, characterized in that, The superimposed amplifier circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a thirteenth resistor, a fifteenth resistor, a sixteenth resistor, a first capacitor, a fourth capacitor, an eighth capacitor, a first field-effect transistor, a second field-effect transistor, a first transistor, a second transistor, and a first integrated operational amplifier; The upper plate of the intermediate capacitor is connected to one end of the fourth resistor and the fifth resistor respectively, and the other end of the fourth resistor is connected to the gate of the second field-effect transistor. The lower stage board of the intermediate capacitor is connected to one end of the ninth resistor and the tenth resistor respectively, and the other end of the fifth resistor and the ninth resistor is grounded; the other end of the tenth resistor is connected to the gate of the first field-effect transistor. The drains of the first and second field-effect transistors are both connected to one end of the second resistor and one end of the fourth capacitor, and the other end of the second resistor is connected to the first positive power supply. The other end of the fourth capacitor is connected to one end of the first capacitor, one end of the first resistor, and the inverting input terminal of the first integrated operational amplifier, respectively. The other end of the first capacitor and the other end of the first resistor are connected to the output terminal of the first integrated operational amplifier. The positive power supply terminal of the first integrated operational amplifier is connected to the first positive power supply, the negative power supply terminal of the first integrated operational amplifier is connected to the negative power supply, and the non-inverting input terminal of the first integrated operational amplifier is grounded. The output terminal of the first integrated operational amplifier is also connected to the first coupling circuit and one end of the third resistor. The other end of the third resistor is connected to one end of the eighth capacitor and one end of the fifteenth resistor, and the other end of the fifteenth resistor is grounded. The other end of the eighth capacitor is connected to one end of the seventh resistor, one end of the eighth resistor, and the collector of the first transistor, respectively. The other end of the seventh resistor is connected to the source of the second field-effect transistor, and the other end of the eighth resistor is connected to the source of the first field-effect transistor. The base of the first transistor is connected to one end of the thirteenth resistor and the collector of the second transistor, respectively. The other end of the thirteenth resistor is grounded. The emitter of the first transistor is connected to the base of the second transistor and one end of the sixteenth resistor, respectively. The emitter of the second transistor and the other end of the sixteenth resistor are connected to the negative power supply.
3. The differential capacitive sensor signal detection device as described in claim 2, characterized in that, The first coupling circuit includes a second capacitor, a third capacitor, and a first transformer; The output terminal of the first integrated operational amplifier is also connected to one end of the second capacitor and one end of the third capacitor respectively; the other ends of the second capacitor and the third capacitor are connected to the upper end of the primary coil of the first transformer, the lower end of the primary coil of the first transformer is grounded; the middle tap of the secondary coil of the first transformer is grounded. The output signals from the upper and lower ends of the secondary coil of the first transformer are used as the measured signals and input to the phase-sensitive detector.
4. The differential capacitive sensor signal detection device as described in claim 3, characterized in that, The second coupling circuit includes a fifth capacitor, a sixth resistor, a fourteenth resistor, and a second transformer; The source of the first field-effect transistor is also connected to the upper end of the primary coil of the second transformer; The source of the second field-effect transistor is also connected to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the lower end of the primary coil of the second transformer. One end of the sixth resistor is connected to the second positive power supply, and the other end is connected to the middle tap of the secondary coil of the second transformer and one end of the fourteenth resistor. The other end of the fourteenth resistor is grounded. The upper and lower ends of the secondary coil of the second transformer are connected to the comparator circuit.
5. The differential capacitive sensor signal detection device as described in claim 4, characterized in that, The comparison circuit includes a comparator; The upper end of the secondary coil of the second transformer is connected to the inverting input or the non-inverting input of the comparator; the lower end of the secondary coil of the second transformer is connected to the non-inverting input or the inverting input of the comparator, and the square wave signal output by the output of the comparator is used as the reference signal input to the phase-sensitive detector. The positive power supply terminal of the comparator is connected to a second positive power supply, and the negative power supply terminal of the comparator is grounded.
6. The differential capacitive sensor signal detection device as described in claim 5, characterized in that, The phase-sensitive detector is also connected to a first amplifier circuit; The phase-sensitive detector includes a dual-channel first analog switch and a second analog switch; the first amplifier circuit includes a first amplifier unit and a second amplifier unit. The upper end of the secondary coil of the first transformer is connected to the S1 pin of the first analog switch and the S2 pin of the second analog switch, respectively. The lower end of the secondary coil of the first transformer is connected to the S2 pin of the first analog switch and the S1 pin of the second analog switch, respectively. The output of the comparator is connected to the IN1 and IN2 pins of the first analog switch, and the IN1 and IN2 pins of the second analog switch, respectively. The VDD pins of the first analog switch and the second analog switch are connected to the first positive power supply. The VSS pins of the first and second analog switches are connected to the negative power supply. The grounding pins of the first and second analog switches are grounded together; The NC pins of the first and second analog switches are left floating. The D1 and D2 pins of the first analog switch are connected to the first amplification unit; The D1 and D2 pins of the second analog switch are connected to the second amplification unit.
7. The differential capacitive sensor signal detection device as described in claim 6, characterized in that, The first amplification unit includes an eleventh resistor, a twelfth resistor, a seventh capacitor, and a second integrated operational amplifier; The D1 and D2 pins of the first analog switch are connected to one end of the eleventh resistor, and the other end of the eleventh resistor is connected to one end of the seventh capacitor, one end of the twelfth resistor, and the inverting input of the second integrated operational amplifier, respectively; the non-inverting input of the second integrated operational amplifier is grounded. The positive power supply terminal of the second integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the seventh capacitor, the other end of the twelfth resistor, and the output terminal of the second integrated operational amplifier are connected to the first output terminal.
8. The differential capacitive sensor signal detection device as described in claim 7, characterized in that, The second amplification unit includes a seventeenth resistor, an eighteenth resistor, a ninth capacitor, and a third integrated operational amplifier; The D1 and D2 pins of the second analog switch are connected to one end of the seventeenth resistor, and the other end of the seventeenth resistor is connected to one end of the ninth capacitor, one end of the eighteenth resistor, and the inverting input of the third integrated operational amplifier, respectively; the non-inverting input of the third integrated operational amplifier is grounded. The positive power supply terminal of the third integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the ninth capacitor, the other end of the eighteenth resistor, and the output terminal of the third integrated operational amplifier are connected to the second output terminal; The first output terminal and the second output terminal form a pair of differential signal output terminals.
9. The differential capacitive sensor signal detection device as described in claim 5, characterized in that, The phase-sensitive detector includes a third analog switch; the phase-sensitive detector is connected to a second amplifier circuit, which includes a third amplifier unit and an inverting amplifier unit. The upper end of the secondary coil of the first transformer is connected to the S1 pin of the third analog switch; The lower end of the secondary coil of the first transformer is connected to the S2 pin of the third analog switch; The output of the comparator is connected to the IN1 and IN2 pins of the third analog switch, respectively. The VDD pin of the third analog switch is connected to the first positive power supply. The VSS pin of the third analog switch is connected to the negative power supply. The grounding pin of the third analog switch is grounded; The NC pin of the third analog switch is left floating; The D1 and D2 pins of the third analog switch are connected to the input terminals of the third amplification unit; The output terminal of the third amplification unit is connected to the input terminal of the inverting amplification unit; The output terminal of the third amplification unit is connected to the first output terminal.
10. The differential capacitive sensor signal detection device as described in claim 9, characterized in that, The inverting amplifier unit includes a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a tenth capacitor, and a fourth integrated operational amplifier; The third amplification unit has the same structure as the first amplification unit; The output terminal of the third amplification unit is connected to one end of the nineteenth resistor, and the other end of the nineteenth resistor is connected to one end of the tenth capacitor, one end of the twentieth resistor, and the inverting input terminal of the fourth integrated operational amplifier; the non-inverting input terminal of the fourth integrated operational amplifier is grounded. The positive power supply terminal of the fourth integrated operational amplifier is connected to the first positive power supply, and the negative power supply terminal is connected to the negative power supply. The other end of the tenth capacitor is connected to the output terminal of the fourth integrated operational amplifier; The output terminal of the fourth integrated operational amplifier is also connected to one end of the twenty-first resistor, and the other ends of the twenty and twenty-first resistors are connected to the second output terminal. The first output terminal and the second output terminal form a pair of differential signal output terminals.