Optical device and electronic device comprising the same

Abstract

Disclosed are an optical device including: a light source providing light; a plurality of first nanostructures collimating the light from the light source and converting a light path of the light from the light source; a light guide totally reflecting the light incident thereon from the plurality of first nanostructures so that the light travels from one end thereof to the other end; a spatial light modulator modulating a phase of the light incident thereon from the light guide and outputting the light having the phase thus modulated; and a plurality of second nanostructures collimating the light incident thereon from the light guide and converting a light path of the light incident thereon to provide the light incident thereon to the spatial light modulator, and an electronic device including the same.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 727,645, filed December 3, 2024, and U.S. Application No. 19 / 202,265, filed May 8, 2025, and all rights derived therefrom thereof, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to optical devices and electronic devices including such optical devices. Background Technology

[0003] With the development of the information society, various types of display devices have been developed to display information. For example, augmented reality (AR) devices are display devices that overlay virtual images onto real images seen through the user's eyes. As another example, stereoscopic image display devices are display devices that separately display left-eye and right-eye images to allow viewers to perceive a three-dimensional effect based on binocular parallax. Summary of the Invention

[0004] In augmented reality devices or stereoscopic image display devices, lasers with easily manipulated wavefronts can be primarily used as light sources. However, since lasers have poor color reproduction and generate noise due to constructive interference (such as speckle), it may be desirable for display devices to have improved color reproduction and reduced noise.

[0005] The disclosed embodiments provide an optical device with improved color reproduction and noise reduction.

[0006] The disclosed embodiments also provide an electronic device including an optical device with improved color reproduction and noise reduction.

[0007] According to one or more disclosed embodiments, the optical device includes: a light source for providing light; a plurality of first nanostructures for collimating light from the light source and converting the optical path of the light from the light source; a light guide for total internal reflection of light incident thereon from the plurality of first nanostructures such that the light incident thereon travels from one end to the other; a spatial light modulator for modulating the phase of light incident thereon from the light guide and outputting light having the thus modulated phase; and a plurality of second nanostructures for collimating light incident thereon from the light guide and converting the optical path of the light incident thereon to provide the light incident thereon to the spatial light modulator.

[0008] In the embodiments, the plurality of first nanostructures may have a first width, a first height, and a first spacing.

[0009] In the embodiments, the plurality of second nanostructures may have a second width, a second height, and a second spacing.

[0010] In an embodiment, the length of the second region in which a plurality of second nanostructures are arranged can be greater than the length of the first region in which a plurality of first nanostructures are arranged in the first direction.

[0011] In an embodiment, the length of the second region in which a plurality of second nanostructures are arranged in the second direction orthogonal to the first direction may be the same as the length of the first region in which a plurality of first nanostructures are arranged in the second direction.

[0012] In one embodiment, the light source may be an organic light-emitting diode on silicon (OLEDoS) display device including an organic light-emitting layer disposed on a first semiconductor substrate.

[0013] In an embodiment, the light source may include: a first light source providing first light of a first color; a second light source providing second light of a second color; and a third light source providing third light of a third color.

[0014] In an embodiment, each of the first light source, the second light source, and the third light source may be an OLEDoS display device including an organic light-emitting layer disposed on a first semiconductor substrate.

[0015] In an embodiment, the plurality of first nanostructures may include: a plurality of first sub-nanostructures superimposed on a first light source, wherein the plurality of first sub-nanostructures collimate first light emitted from the first light source and convert the optical path of the first light emitted from the first light source; a plurality of second sub-nanostructures superimposed on a second light source, wherein the plurality of second sub-nanostructures collimate second light emitted from the second light source and convert the optical path of the second light emitted from the second light source; and a plurality of third sub-nanostructures superimposed on a third light source, wherein the plurality of third sub-nanostructures collimate third light emitted from the third light source and convert the optical path of the third light emitted from the third light source.

[0016] In the embodiments, the plurality of first sub-nanostructures and the plurality of second sub-nanostructures may be different from each other.

[0017] In an embodiment, the plurality of third sub-nanostructures may differ from the plurality of first sub-nanostructures and the plurality of second sub-nanostructures.

[0018] In one embodiment, the spatial light modulator may be a liquid crystal on silicon (LCoS) display device including a liquid crystal layer disposed on a second semiconductor substrate.

[0019] In an embodiment, the spatial light modulator may include: a first spatial light modulator for modulating the phase of a first light; a second spatial light modulator for modulating the phase of a second light; and a third spatial light modulator for modulating the phase of a third light.

[0020] In an embodiment, each of the first spatial light modulator, the second spatial light modulator, and the third spatial light modulator may be an LCoS display device including a liquid crystal layer disposed on a second semiconductor substrate.

[0021] In an embodiment, the plurality of second nanostructures may include: a plurality of fourth sub-nanostructures stacked with a first spatial light modulator, wherein the plurality of fourth sub-nanostructures collimate first light incident on them from the light guide portion and convert the optical path of the first light to provide the first light incident on them to the first spatial light modulator; a plurality of fifth sub-nanostructures stacked with a second spatial light modulator, wherein the plurality of fifth sub-nanostructures collimate second light incident on them from the light guide portion and convert the optical path of the second light incident on them to provide the second light incident on them to the second spatial light modulator; and a plurality of sixth sub-nanostructures stacked with a third spatial light modulator, wherein the plurality of sixth sub-nanostructures collimate third light incident on them from the light guide portion and convert the optical path of the third light incident on them to provide the third light incident on them to the third spatial light modulator.

[0022] In the embodiments, the plurality of fourth sub-nanostructures and the plurality of fifth sub-nanostructures may be different from each other.

[0023] In the embodiments, the plurality of sixth sub-nanostructures may be different from the plurality of fourth sub-nanostructures and the plurality of fifth sub-nanostructures.

[0024] In one embodiment, the light guide may extend in a first direction, the light source may be arranged adjacent to one side of the light guide in the first direction, and the spatial light modulator may be arranged adjacent to the other side of the light guide in the first direction.

[0025] In an embodiment, the light guide may include: a first extension portion extending in a first direction; a second extension portion extending upward in a third direction intersecting the first direction; and a reflector disposed in the region where one side of the first extension portion and one side of the second extension portion intersect.

[0026] According to one or more disclosed embodiments, an electronic device includes: a lens; and an optical device that provides an image to a user's monocular eye via the lens. In such an embodiment, the optical device includes: a light source that provides light; a plurality of first nanostructures that collimate the light from the light source and convert the optical path of the light from the light source; a light guide that causes total internal reflection of light incident thereon from the plurality of first nanostructures such that the light incident thereon travels from one end to the other; a spatial light modulator that modulates the phase of the light incident thereon from the light guide and outputs light having the thus modulated phase; and a plurality of second nanostructures that collimate the light incident thereon from the light guide and convert the optical path of the light incident thereon to provide the light incident thereon to the spatial light modulator.

[0027] Optical devices and electronic devices including such optical devices, according to some disclosed embodiments, can improve color reproduction and light efficiency by using OLEDoS display devices or LEDoS display devices instead of conventional lasers as light sources, while preventing noise caused by constructive interference.

[0028] In some embodiments, multiple OLEDoS display devices or multiple LEDoS display devices, each emitting one of the first to third lights, can be used as multiple light sources, and multiple first to multiple third sub-nanostructures can be provided for each of the multiple light sources. In such embodiments, color difference can be effectively prevented by refracting light through the formation of multiple first to multiple third sub-nanostructures, while taking into account the color difference that light may focus at different locations according to color during the refraction process.

[0029] In some embodiments, multiple spatial light modulators and multiple fourth to multiple sixth sub-nanostructures may be provided for each of the first to third light beams. In such embodiments, the focal point of each of the first to third light beams can be formed independently, thereby effectively preventing chromatic aberration.

[0030] However, the effects of the embodiments are not limited to those described herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon reference to the claims. Attached Figure Description

[0031] The above and other features of the disclosed embodiments will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 This is a perspective view of an electronic device including a display device according to some disclosed embodiments; Figure 2 It is used to describe Figure 1 A plan view of the display device and the light guide section; Figure 3 It is used to describe Figure 2 Front views of multiple first nanostructures; Figure 4 It is used to describe Figure 2 Front views of multiple second nanostructures; Figure 5 It is used to describe Figure 1 A plan view of the display device and the light guide section; Figure 6 It is used to describe Figure 1 A plan view of the display device and the light guide section; Figure 7 It is used to describe Figure 1A plan view of the display device and the light guide section; Figure 8 It is used to describe Figure 1 A plan view of the display device and the light guide section; Figure 9 It is used to describe Figure 1 An exploded perspective view of the display device; Figure 10 It is used to describe Figure 9 A block diagram of the display panel; Figure 11 yes Figure 10 The equivalent circuit diagram of the first sub-pixel; Figure 12 It is used to describe Figure 9 A floor plan of the display panel; Figure 13 It is used to describe Figure 12 A floor plan of the display area; Figure 14 It is used to describe Figure 12 A floor plan of the display area; Figure 15 This is an example of a display panel shown along... Figure 13 A sectional view taken by line I1-I1'; Figure 16 This is an example of another embodiment of the display panel shown along... Figure 13 A sectional view taken from line I1-I1'. Detailed Implementation

[0032] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the invention are illustrated. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0033] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0034] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or an intermediary layer may be present. Conversely, when an element is referred to as being "directly on" another element, no intermediary element is present.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms containing “at least one.” Thus, an element mentioned in the claims and subsequently referenced as “the” element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” “At least one of A and B” or “at least one selected from A and B” means “A and / or B.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” or “including” and / or variations thereof are used in this specification, it indicates the presence of the stated features, areas, integrals, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0036] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used here to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to also include different orientations of the device. For example, if the device in one of the drawings is flipped, the element described as being “below” the other elements will subsequently be oriented “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can include both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, the element described as being “below” or “under” the other elements will subsequently be positioned “above” the other elements. Thus, the terms “below” or “under” can include both “above” and “below” orientations.

[0037] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and the disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0039] The embodiments are described herein with reference to schematic cross-sectional views as idealized embodiments. Thus, variations in the illustrated shapes will be anticipated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but will include, for example, deviations in shape caused by manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the presented claims.

[0040] In the following description, the disclosed embodiments will be illustrated with reference to the accompanying drawings.

[0041] Figure 1 This is a perspective view of an electronic device including a display device according to some disclosed embodiments.

[0042] Reference Figure 1 The electronic device 1000, which includes a display device according to some embodiments, may be an eyeglass-type display device in which the display device housing 1200 is implemented in a lightweight and small size. Embodiments of the electronic device 1000 including the display device may include a display device 10, a spatial light modulator (SLM), a plurality of first nanostructures (ICP), a plurality of second nanostructures (OCP), a light guide (WG), a left eye lens 1010, a right eye lens 1020, a support frame 1030, eyeglass frame temples 1040 and 1050, and the display device housing 1200.

[0043] The display device housing 1200 can accommodate an optical device, which includes a display device 10, a spatial light modulator (SLM), a plurality of first nanostructures (ICPs), a plurality of second nanostructures (OCPs), and a light guide WG. An image displayed on the display device 10 can have a path converted by the plurality of first nanostructures (ICPs) and incident on the light guide WG. An image passing through the light guide WG can have a path converted by the plurality of second nanostructures (OCPs) and incident on the spatial light modulator (SLM). The image whose phase is modulated in the spatial light modulator (SLM) can be provided to the user's right eye through the right eye lens 1020. Therefore, the user can view an augmented reality image combining a virtual image displayed on the display device 10 and a real image viewed through the right eye lens 1020 through their right eye.

[0044] Figure 1 An embodiment is shown where the display device housing 1200 is located on one side of the support frame 1030, but the embodiment is not limited thereto. In another embodiment, for example, the display device housing 1200 may be located on the other side of the support frame 1030, and in such an embodiment, the image of the display device 10 can be provided to the user's left eye. Alternatively, the display device housing 1200 may be located on both one side and the other side of the support frame 1030. In such an embodiment, the user can view the image displayed on the display device 10 through both the user's left and right eyes.

[0045] Figure 1 An embodiment of a head-mounted device, including an electronic device 1000 in the form of glasses, is shown, but the embodiment is not limited thereto. In the embodiment, for example, the electronic device 1000 including the display device may have various forms, such as being secured to a user's head via a headband.

[0046] Figure 2 It is used to describe Figure 1 A plan view of the display device and the light guide section.

[0047] Reference Figure 2 In an embodiment, the light guide portion WG may extend in the first direction DR1. The light guide portion WG may include a material (such as glass or plastic) that allows light to pass through. The light guide portion WG may include a material with a high refractive index. In an embodiment, for example, the refractive index of the light guide portion WG may be about 2.0 or greater and about 4.1 or less.

[0048] Multiple first nanostructure ICPs can be located on one side of the light guide portion WG. Each of the multiple first nanostructure ICPs can have a size similar to the wavelength of light emitted from the display device 10. In an embodiment, the multiple first nanostructure ICPs can have a first width, a first height, and a first spacing (or interval). In an embodiment, for example, the first height of the multiple first nanostructure ICPs can be about 600 nanometers (nm), and the first spacing of the multiple first nanostructure ICPs can be about 330 nm. The phase delay of the light emitted from the display device 10 can be adjusted according to the first width of the multiple first nanostructure ICPs. In other words, the angle of refraction of the light emitted from the display device 10 by the multiple first nanostructure ICPs can depend on the first width of the multiple first nanostructure ICPs. In an embodiment, for example, each of the multiple first nanostructure ICPs can have a cylindrical shape, but the embodiment is not limited to this.

[0049] The plurality of first nanostructure ICPs may include materials that allow light to pass through. In embodiments, for example, the plurality of first nanostructure ICPs may include at least one selected from silicon oxide-based materials, silicon nitride-based materials, and titanium oxide-based materials.

[0050] The display device 10 can be positioned adjacent to one side of the light guide portion WG. The display device 10 can be stacked with a plurality of first nanostructures ICP on the second direction DR2.

[0051] The display device 10 can be a light source that provides light. The display device 10 can provide or emit light in the second direction DR2.

[0052] In one embodiment, for example, the display device 10 may be an organic light-emitting diode on silicon (OLEDoS) display device including an organic light-emitting layer disposed on a semiconductor substrate. In another embodiment, for example, the display device 10 may be a light-emitting diode on silicon (LED) (LEDoS) display device including an LED disposed on a semiconductor substrate, but the embodiments are not limited thereto.

[0053] Multiple second nanostructure OCPs can be located on the other side of the light guide portion WG. Each of the multiple second nanostructure OCPs can have a size similar to the wavelength of light emitted from the display device 10. In an embodiment, the multiple second nanostructure OCPs can have a second width, a second height, and a second spacing (or interval). In an embodiment, for example, the second width of the multiple second nanostructure OCPs can be about 260 nm, the second height of the multiple second nanostructure OCPs can be about 600 nm, and the second spacing of the multiple second nanostructure OCPs can be about 396 nm. In an embodiment, for example, each of the multiple second nanostructure OCPs can have a rectangular hexahedral shape, but the embodiment is not limited to this.

[0054] The plurality of second nanostructure OCPs may include materials that allow light to pass through. In embodiments, for example, the plurality of second nanostructure OCPs may include at least one selected from silicon oxide-based materials, silicon nitride-based materials, and titanium oxide-based materials.

[0055] The spatial light modulator (SLM) can be positioned adjacent to the other side of the light guide section (WG). The SLM can be stacked with multiple second nanostructures (OCP) on the second direction (DR2).

[0056] A spatial light modulator (SLM) can modulate the phase or amplitude of light. An SLM can be a reflective spatial light modulator that modulates the phase or amplitude of incident light and reflects incident light having the modulated phase or amplitude. In embodiments, for example, the SLM can be a liquid crystal on silicon (LCoS) display device including a liquid crystal layer disposed on a semiconductor substrate, but embodiments are not limited thereto.

[0057] Light emitted from the display device 10 can travel to a plurality of first nanostructure ICPs. The light can be collimated as it passes through the plurality of first nanostructure ICPs. Furthermore, the light can have a converted optical path as it passes through the plurality of first nanostructure ICPs. In an embodiment, for example, the light can travel in a second direction DR2 and then be refracted as it passes through the plurality of first nanostructure ICPs to travel in a direction intersecting the first direction DR1 and the second direction DR2. In this case, the light can be incident on the light guide WG at an angle equal to or greater than the critical angle at which total internal reflection occurs within the light guide WG.

[0058] Light that is totally internally reflected inside the light guide WG can pass through multiple second nanostructures OCP and exit the light guide WG to travel to the spatial light modulator SLM. The light can be phase-modulated in the SLM. Alternatively, light can be reflected from the SLM. The reflected light can be refracted as it passes through the multiple second nanostructures OCP and travels to the focal point FP.

[0059] Figure 3 It is used to describe Figure 2 Front views of multiple first nanostructures.

[0060] Reference Figure 3 In one embodiment, multiple first nanostructures ICP can be arranged in the first region A1.

[0061] Multiple first nanostructure ICPs can be uniformly or non-uniformly arranged in the first region A1. In an embodiment, for example, the first width, first height, and first spacing of the multiple first nanostructure ICPs located at the periphery of the first region A1 can be different from the first width, first height, and first spacing of the multiple first nanostructure ICPs located at the center of the first region A1.

[0062] The planar shape of the first region A1 can correspond to the planar shape of the display area of ​​the display device 10. In an embodiment, for example, if the planar shape of the display area of ​​the display device 10 is circular, the planar shape of the first region A1 can also be formed as circular. Figure 3 An embodiment is shown in which the planar shape of the first region A1 is a square. In this embodiment, for example, the length a1 of the first region A1 in the first direction DR1 may be equal to the length b1 of the first region A1 in the third direction DR3.

[0063] Figure 4 It is used to describe Figure 2 A front view of multiple second nanostructures.

[0064] Reference Figure 4 In one embodiment, multiple second nanostructures OCP can be arranged in the second region A2.

[0065] Multiple second nanostructures OCP can be uniformly or non-uniformly arranged in the second region A2. In an embodiment, for example, the second width, second height, and second spacing of the multiple second nanostructures OCP located at the periphery of the second region A2 can be different from the second width, second height, and second spacing of the multiple second nanostructures OCP located at the center of the second region A2.

[0066] The planar shape of the second region A2 may differ from that of the first region A1. In an embodiment, the planar shape of the second region A2 may be a rectangle in which the length a2 of the second region A2 in the first direction DR1 is greater than the length b2 of the second region A2 in the third direction DR3. This is because the light path is modified when light passes through the first region A1. Therefore, the length a2 of the second region A2 in the first direction DR1 may be greater than the length a1 of the first region A1 in the first direction DR1. The length b2 of the second region A2 in the third direction DR3 may be equal to the length b1 of the first region A1 in the third direction DR3.

[0067] Figure 5 It is used to describe Figure 1 A plan view of the display device and light guide section. Any repetitive detailed descriptions of elements that are the same as or similar to those described above will be omitted or simplified, and the differences will be described primarily.

[0068] Reference Figure 5 The optical device according to some disclosed embodiments may include a first display device 10_R, a second display device 10_G, a third display device 10_B, a plurality of first sub-nanostructures ICP_R, a plurality of second sub-nanostructures ICP_G, and a plurality of third sub-nanostructures ICP_B.

[0069] In an embodiment, such as Figure 2 As shown, display device 10 can be a single display device that emits all of the first light, the second light, and the third light. In another embodiment, as... Figure 5 As shown, the display device 10 may include a first display device 10_R that emits a first light, a second display device 10_G that emits a second light, and a third display device 10_B that emits a third light. In an embodiment, for example, the first light may be red light, the second light may be green light, and the third light may be blue light. The first display device 10_R, the second display device 10_G, and the third display device 10_B may all be OLEDoS display devices or LEDoS display devices.

[0070] In an embodiment, such as Figure 5 As shown, the first display device 10_R and the second display device 10_G are adjacent to each other in the first direction DR1, and the second display device 10_G and the third display device 10_B are adjacent to each other in the first direction DR1, but the embodiment is not limited to this. In another embodiment, for example, the first display device 10_R and the second display device 10_G may be adjacent to each other in the third direction DR3, and the second display device 10_G and the third display device 10_B may be adjacent to each other in the third direction DR3. In this embodiment, the first display device 10_R may be arranged adjacent to the third display device 10_B, and the third display device 10_B may be arranged adjacent to the second display device 10_G.

[0071] In an embodiment, such as Figure 5 As shown, the plurality of first nanostructures ICP may include a plurality of first sub-nanostructures ICP_R, a plurality of second sub-nanostructures ICP_G, and a plurality of third sub-nanostructures ICP_B.

[0072] Multiple first sub-nanostructures ICP_R can be stacked with the first display device 10_R in the second direction DR2. The multiple first sub-nanostructures ICP_R can collimate and convert the optical path of the first light emitted from the first display device 10_R. The multiple first sub-nanostructures ICP_R can have a first sub-width, a first sub-height, and a first sub-pitch.

[0073] Multiple second sub-nanostructures ICP_G can be stacked with the second display device 10_G in the second direction DR2. The multiple second sub-nanostructures ICP_G can collimate and convert the optical path of the second light emitted from the second display device 10_G. The multiple second sub-nanostructures ICP_G can have a second sub-width, a second sub-height, and a second sub-spacing.

[0074] Multiple third sub-nanostructures ICP_B can be stacked with the third display device 10_B in the second direction DR2. The multiple third sub-nanostructures ICP_B can collimate and convert the optical path of the third light emitted from the third display device 10_B. The multiple third sub-nanostructures ICP_B can have a third sub-width, a third sub-height, and a third sub-spacing.

[0075] The first sub-nanostructure ICP_R, the second sub-nanostructure ICP_G, and the third sub-nanostructure ICP_B can be different from each other. In embodiments, for example, the first sub-width, the second sub-width, and the third sub-width can be different from each other, or the first sub-height, the second sub-height, and the third sub-height can be different from each other, or the first sub-spacing, the second sub-spacing, and the third sub-spacing can be different from each other.

[0076] By providing a first display device 10_R, a second display device 10_G, and a third display device 10_B, as well as a first sub-nanostructure ICP_R, a second sub-nanostructure ICP_G, and a third sub-nanostructure ICP_B for each of the first to third light rays, the embodiment can effectively prevent color differences in light focusing at different positions according to color during the refraction process. Therefore, in such an embodiment, light of different colors can be focused at accurate positions, thereby providing the user with a clearer image.

[0077] Figure 6 It is used to describe Figure 1 A plan view of the display device and light guide section. Any repetitive detailed descriptions of elements that are the same as or similar to those described above will be omitted or simplified, and the differences will be described primarily.

[0078] Reference Figure 6 The optical device according to some of the disclosed embodiments may include a first spatial light modulator SLM_R, a second spatial light modulator SLM_G, a third spatial light modulator SLM_B, a plurality of fourth sub-nanostructures OCP_R, a plurality of fifth sub-nanostructures OCP_G, and a plurality of sixth sub-nanostructures OCP_B.

[0079] In an embodiment, such as Figure 2 As shown, the spatial light modulator (SLM) can be a spatial light modulator that modulates the phases of the first, second, and third lights. In another embodiment, as... Figure 6As shown, the spatial light modulator (SLM) may include a first spatial light modulator (SLM_R) that modulates the phase of a first light, a second spatial light modulator (SLM_G) that modulates the phase of a second light, and a third spatial light modulator (SLM_B) that modulates the phase of a third light. The first spatial light modulator (SLM_R), the second spatial light modulator (SLM_G), and the third spatial light modulator (SLM_B) may all be LCoS display devices.

[0080] In an embodiment, such as Figure 6 As shown, the multiple second nanostructures OCP may include multiple fourth sub-nanostructures OCP_R, multiple fifth sub-nanostructures OCP_G, and multiple sixth sub-nanostructures OCP_B.

[0081] Multiple fourth sub-nanostructures OCP_R can be stacked with a first spatial light modulator SLM_R in the second direction DR2. These multiple fourth sub-nanostructures OCP_R can collimate the first light that is totally internally reflected by the light guide WG and change its optical path to guide the reflected light to the first spatial light modulator SLM_R. The multiple fourth sub-nanostructures OCP_R can have a fourth sub-width, a fourth sub-height, and a fourth sub-spacing.

[0082] Multiple fifth sub-nanostructures OCP_G can be stacked with a second spatial light modulator SLM_G in the second direction DR2. These multiple fifth sub-nanostructures OCP_G can collimate the second light that is totally internally reflected by the light guide WG and change its optical path to guide the reflected light to the second spatial light modulator SLM_G. The multiple fifth sub-nanostructures OCP_G can have a fifth sub-width, a fifth sub-height, and a fifth sub-spacing.

[0083] Multiple sixth-sub nanostructures OCP_B can be stacked with a third spatial light modulator SLM_B in the second direction DR2. These multiple sixth-sub nanostructures OCP_B can collimate the third light that is totally internally reflected by the light guide WG and change its optical path to guide the reflected light to the third spatial light modulator SLM_B. The multiple sixth-sub nanostructures OCP_B can have a sixth-sub width, a sixth-sub height, and a sixth-sub spacing.

[0084] The fourth sub-nanostructure OCP_R, the fifth sub-nanostructure OCP_G, and the sixth sub-nanostructure OCP_B can be different from each other. In embodiments, for example, the fourth sub-width, the fifth sub-width, and the sixth sub-width can be different from each other, or the fourth sub-height, the fifth sub-height, and the sixth sub-height can be different from each other, or the fourth sub-spacing, the fifth sub-spacing, and the sixth sub-spacing can be different from each other.

[0085] By providing first to third spatial light modulators (SLM_R, SLM_G, and SLM_B) and fourth to sixth sub-nanostructures (OCP_R, OCP_G, and OCP_B) for each of the first to third light beams, the embodiment can perform phase modulation of light by taking into account the chromatic aberration of light focusing at different positions during refraction. Therefore, in such an embodiment, light of different colors can be focused at precise locations, thereby providing the user with a clearer image.

[0086] Figure 7 It is used to describe Figure 1 A plan view of the display device and light guide section. Any repetitive detailed descriptions of elements that are the same as or similar to those described above will be omitted or simplified, and the differences will be described primarily.

[0087] Reference Figure 7 The optical device according to some disclosed embodiments may include a first display device 10_R, a second display device 10_G, a third display device 10_B, a plurality of first sub-nanostructures ICP_R, a plurality of second sub-nanostructures ICP_G, a plurality of third sub-nanostructures ICP_B, a plurality of fourth sub-nanostructures OCP_R, a plurality of fifth sub-nanostructures OCP_G, a plurality of sixth sub-nanostructures OCP_B, a first spatial light modulator SLM_R, a second spatial light modulator SLM_G, and a third spatial light modulator SLM_B.

[0088] In an embodiment, such as Figure 7 As shown, the spatial light modulator (SLM) may include a first spatial light modulator (SLM_R) that modulates the phase of a first light, a second spatial light modulator (SLM_G) that modulates the phase of a second light, and a third spatial light modulator (SLM_B) that modulates the phase of a third light. The first spatial light modulator (SLM_R), the second spatial light modulator (SLM_G), and the third spatial light modulator (SLM_B) may all be LCoS display devices.

[0089] In such an embodiment, the plurality of second nanostructures OCP may include a plurality of fourth sub-nanostructures OCP_R, a plurality of fifth sub-nanostructures OCP_G, and a plurality of sixth sub-nanostructures OCP_B.

[0090] Figure 7 The first to third display devices 10_R, 10_G and 10_B, a plurality of first to third sub-nanostructures ICP_R, ICP_G and ICP_B, a first spatial light modulator to a third spatial light modulator SLM_R, SLM_G and SLM_B, and a plurality of fourth to sixth sub-nanostructures OCP_R, OCP_G and OCP_B can be respectively referenced above. Figure 5 and Figure 6The first to third display devices 10_R, 10_G and 10_B, the plurality of first to third sub-nanostructures ICP_R, ICP_G and ICP_B, the first to third spatial light modulators SLM_R, SLM_G and SLM_B, and the plurality of fourth to sixth sub-nanostructures OCP_R, OCP_G and OCP_B described are substantially the same.

[0091] Figure 8 It is used to describe Figure 1 A plan view of the display device and light guide section. Any repetitive detailed descriptions of elements that are the same as or similar to those described above will be omitted or simplified, and the differences will be described primarily.

[0092] Figure 8 The display device 10, multiple first nanostructure ICPs, multiple second nanostructure OCPs, and spatial light modulator SLM can be referenced above. Figure 2 The described display device 10, multiple first nanostructure ICPs, multiple second nanostructure OCPs, and spatial light modulator SLM are substantially the same.

[0093] Reference Figure 8 In an embodiment, the light guide portion WG may include a first extension portion WG_1 extending in the first direction DR1, a second extension portion WG_2 extending in the second direction DR2, and a reflector RE.

[0094] The first extension portion WG_1 can extend along the first direction DR1. Multiple second nanostructures OCP can be located on one side of the first extension portion WG_1 along the first direction DR1. A spatial light modulator SLM can be arranged adjacent to that side of the first extension portion WG_1. The multiple second nanostructures OCP and the spatial light modulator SLM can be stacked along the second direction DR2. The multiple second nanostructures OCP and the spatial light modulator SLM can be arranged adjacent to each other along the second direction DR2.

[0095] The second extension portion WG_2 can extend along the second direction DR2. Multiple first nanostructure ICPs can be located on one side of the second extension portion WG_2 in the direction opposite to the second direction DR2. The display device 10 can be arranged adjacent to one side of the second extension portion WG_2. Multiple first nanostructure ICPs and the display device 10 can be stacked along the first direction DR1. Multiple first nanostructure ICPs and the display device 10 can be arranged adjacent to each other along the first direction DR1.

[0096] The reflector RE can be arranged in the area where the first extension WG_1 and the second extension WG_2 intersect. The reflector RE can switch or change the direction of light travel by reflecting light traveling within the light guide WG. In an embodiment, for example, light guided in the second direction DR2 inside the light guide WG can be reflected by the reflector RE and travel in the first direction DR1.

[0097] In such an embodiment, since the light guide WG has a reflector RE, the length of the light guide WG in one direction can be reduced. Therefore, miniaturization of the light guide WG becomes possible, thereby reducing the size of the optical device and improving usability.

[0098] Figure 9 It is used to describe Figure 1 An exploded perspective view of the display device. Figure 10 It is used to describe Figure 9 A block diagram of the display panel.

[0099] Reference Figure 9 and Figure 10 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment can be applied to the display unit of a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Optionally, the display device 10 according to the embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for implementing virtual and augmented reality.

[0100] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0101] The display panel 100 can be formed into a planar shape similar to a quadrilateral. In an embodiment, for example, the display panel 100 can have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a predetermined curvature, or it can be formed at a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral, and can be formed into a shape similar to other polygons, circles, or ellipses. The planar shape of the display device 10 can correspond to the planar shape of the display panel 100, but the disclosed embodiments are not limited thereto.

[0102] The display panel 100 includes multiple pixels (PX), multiple scan lines (SL), multiple light emission control lines (EL), multiple data lines (DL), a scan driver 610, a light emission driver 620, and a data driver 700. For example... Figure 10 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0103] Multiple pixels (PX) can be arranged in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix on the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) can extend on the first direction (DR1) and can be arranged on the second direction (DR2). Multiple data lines (DL) can extend on the second direction (DR2) and can be arranged on the first direction (DR1).

[0104] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emission control lines EL include multiple first emission control lines ECL1 and multiple second emission control lines ECL2.

[0105] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. In an embodiment, the plurality of sub-pixels SP1, SP2, and SP3 may include, for example: Figure 11 The multiple pixel transistors shown can be formed by semiconductor processes and can be located on a semiconductor substrate ( Figure 15 On the SSUB in the image. In embodiments, for example, the multiple pixel transistors of multiple sub-pixels SP1, SP2 and SP3 may include or be formed of complementary metal-oxide-semiconductor (CMOS), but the disclosed embodiments are not limited thereto.

[0106] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and can emit light corresponding to the data voltage from the light-emitting element.

[0107] The scan driver 610, the light-emitting driver 620, and the data driver 700 can be arranged in the non-display area NDA.

[0108] The scan driver 610 includes multiple scan transistors, and the light-emitting driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and can be formed on a semiconductor substrate (…). Figure 15 The SSUB in the diagram. In embodiments, for example, the plurality of scanning transistors and the plurality of light-emitting transistors may include or be formed of CMOS, but the disclosed embodiments are not limited thereto.

[0109] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0110] The light-emitting driver 620 includes a first light-emitting control driver 621 and a second light-emitting control driver 622. Each of the first light-emitting control driver 621 and the second light-emitting control driver 622 can receive a light-emitting timing control signal ECS from the timing control circuit 400. The first light-emitting control driver 621 can generate a first light-emitting control signal based on the light-emitting timing control signal ECS and sequentially output the first light-emitting control signal to the first light-emitting control line ECL1. The second light-emitting control driver 622 can generate a second light-emitting control signal based on the light-emitting timing control signal ECS and sequentially output the second light-emitting control signal to the second light-emitting control line ECL2.

[0111] The data driver 700 may include multiple data transistors, and the multiple data transistors can be formed by semiconductor processes and can be formed on a semiconductor substrate (…). Figure 15 On the SSUB in the diagram. In embodiments, for example, the plurality of data transistors may include or be formed of CMOS, but the disclosed embodiments are not limited thereto.

[0112] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the converted analog data voltage to the data line DL. In such an embodiment, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0113] The heat dissipation layer 200 may be stacked on the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100 (e.g., its rear surface). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer (such as silver (Ag), copper (Cu), or aluminum (Al)) or a graphite layer with high thermal conductivity.

[0114] The circuit board 300 can be electrically connected to the first pad (also referred to as a "soldering pad") portion of the display panel 100 using a conductive adhesive such as an anisotropic conductive film. Figure 12 Multiple first pads of PDA1 in the middle ( Figure 12 (PD1 in the example). The circuit board 300 may be a flexible printed circuit board or flexible film comprising or made of flexible materials. Figure 9 An embodiment with the circuit board 300 in an unfolded state is shown, but the circuit board 300 can be bent. In the bent state, one end of the circuit board 300 can be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion of the display panel 100 using a conductive adhesive material. Figure 12 Multiple first pads of PDA1 in the middle ( Figure 12 (PD1 in the circuit board 300). One end of the circuit board 300 can be the end opposite to the other end of the circuit board 300.

[0115] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the light emission timing control signal ECS to the light emission driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0116] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. In an embodiment, for example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply the generated driving voltages to the display panel 100. (See below for further details.) Figure 11 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0117] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In an embodiment, the scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Additionally, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0118] Optionally, similar to the scan driver 610, the light-emitting driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be arranged in the non-display area NDA of the display panel 100. In such an embodiment, the timing control circuit 400 may include a plurality of timing transistors, and each of the power supply circuits 500 may include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors may be formed by semiconductor processes and may be formed on a semiconductor substrate (…). Figure 15 On the SSUB in the data driver 700. In embodiments, for example, the multiple timing transistors and multiple power transistors may include or be formed of CMOS, but the disclosed embodiments are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 may be arranged on the data driver 700 and the first pad portion ( Figure 12 Between PDA1 in the middle.

[0119] Figure 11 yes Figure 10 The equivalent circuit diagram of the first sub-pixel.

[0120] Reference Figure 11In this embodiment, the first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line ECL1, the second emission control line ECL2, and the data line DL. Additionally, the first sub-pixel SP1 can be connected to the first driving voltage line VSL, which is subject to a first driving voltage VSS corresponding to a low potential voltage; the second driving voltage line VDL, which is subject to a second driving voltage VDD corresponding to a high potential voltage; and the third driving voltage line VIL, which is subject to a third driving voltage VINT corresponding to an initialization voltage.

[0121] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0122] The light-emitting element LE emits light according to the driving current (Ids) flowing through the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current (Ids). The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the disclosed embodiments are not limited thereto. In embodiments, for example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In such embodiments, the light-emitting element LE can be a miniature light-emitting diode.

[0123] The first transistor T1 can be a drive transistor that controls the source-drain current (Ids) (hereinafter referred to as the "drive current") flowing between the source and drain electrodes based on the voltage applied to the gate electrode.

[0124] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL, and connects one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0125] The third transistor T3 can be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal controlling the scan line GCL, and connects the first node N1 to the second node N2. Therefore, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0126] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light-emitting control signal of the first light-emitting control line ECL1, and connects the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL, and connects the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0127] The sixth transistor T6 can be arranged between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second light emission control signal of the second light emission control line ECL2, and connects the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1.

[0128] A first capacitor CP1 is formed or connected between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed or connected between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0129] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In an embodiment, for example, each of the first transistors T1 to the sixth transistor T6 can be a p-type MOSFET, but the disclosed embodiments are not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an n-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be p-type MOSFETs, and the remaining transistors can be n-type MOSFETs.

[0130] Figure 11 An embodiment of the first sub-pixel SP1 including six transistors T1 to T6 and two capacitors CP1 and CP2 is shown. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this embodiment. Figure 11 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 11 The quantities shown.

[0131] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be compared with the reference. Figure 11The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, any repetitive detailed descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are omitted in the disclosure.

[0132] Figure 12 It is used to describe Figure 9 A floor plan of the display panel.

[0133] Reference Figure 12 The display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, a light-emitting driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0134] The scan driver 610 may be located on a first side of the display area DAA, and the light-emitting driver 620 may be located on a second side of the display area DAA. In an embodiment, for example, the scan driver 610 may be located on one side of the display area DAA in a first direction DR1, and the light-emitting driver 620 may be located on the other side of the display area DAA in the first direction DR1. However, the disclosed embodiments are not limited thereto, and both the scan driver 610 and the light-emitting driver 620 may be located on either the first or second side of the display area DAA.

[0135] The first pad portion PDA1 may include a plurality of first pads PD1 attached to the circuit board 300 by a conductive adhesive. The first pad portion PDA1 may be located on the third side of the display area DAA. In an embodiment, for example, the first pad portion PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be located on the outer side of the data driver 700 in the second direction DR2.

[0136] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the test pads used to test whether the display panel 100 is operating correctly. During the testing process, the multiple second pads PD2 may be connected to a fixture or probe pins or to a test circuit board. The test circuit board may be a rigid printed circuit board comprising or made of rigid materials or a flexible printed circuit board comprising or made of flexible materials.

[0137] The second pad portion PDA2 can be located on the fourth side of the display area DAA. In an embodiment, for example, the second pad portion PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can also be located on the outer side of the second distribution circuit 720 in the second direction DR2.

[0138] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. In an embodiment, for example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 may be located on the third side of the display area DAA of the display panel 100. In an embodiment, for example, the first distribution circuit 710 may be located on one side of the display area DAA in the second direction DR2.

[0139] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the light-emitting driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be components used to test the operation of each pixel PX of the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. In an embodiment, for example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0140] The cathode connection portion CCA can be the display element layer ( Figure 15 The second electrode of EML (in the middle) Figure 15 The cathode connection (CAT) is connected to the region of the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA can be arranged outside at least one side of the display area DAA. In an embodiment, for example, the cathode connection portion CCA can be arranged outside at least one side selected from the left, right, upper, and lower sides of the display area DAA. Optionally, as Figure 12 As shown, the cathode connection portion CCA can be arranged around the display area DAA to minimize the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0141] Figure 13 It is used to describe Figure 12 A floor plan of the display area. Figure 14 It is used to describe Figure 12 A floor plan of the display area.

[0142] Reference Figure 13 and Figure 14 Each of the multiple pixels PX includes a first light-emitting region EA1 as the light-emitting region of the first sub-pixel SP1, a second light-emitting region EA2 as the light-emitting region of the second sub-pixel SP2, and a third light-emitting region EA3 as the light-emitting region of the third sub-pixel SP3.

[0143] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can have the following characteristics: Figure 13 and Figure 14 The planar shapes shown are quadrilateral or hexagonal, but the disclosed embodiments are not limited thereto. The first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may have planar shapes such as polygons, circles, ellipses, or irregular shapes other than quadrilaterals or hexagons.

[0144] In an embodiment, such as Figure 13 As shown, in each of the plurality of pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent to each other in the first direction DR1. Additionally, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent to each other in the first direction DR1. Furthermore, the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent to each other in the second direction DR2. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be different.

[0145] Optionally, such as Figure 14 As shown, the light-emitting regions EA1, EA2, EA3, and EA4 can have a hexagonal planar shape. In such an embodiment, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent to each other in the first direction DR1, and the second light-emitting region EA2 and the fourth light-emitting region EA4 can be adjacent to each other in the second direction DR2. Furthermore, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent to each other in the first oblique direction DD1, and the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1, which is the direction between the first direction DR1 and the second direction DR2, can indicate a direction inclined at approximately 45 degrees compared to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 can be a direction perpendicular to the first oblique direction DD1.

[0146] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be blue light, the second light can be green light, and the third light can be red light. In an embodiment, for example, the blue band can represent the main peak wavelength of the light being in the band from about 370 nm to about 460 nm, the green band can represent the main peak wavelength of the light being in the band from about 480 nm to about 560 nm, and the red band can represent the main peak wavelength of the light being in the band from about 600 nm to about 750 nm.

[0147] Each of the multiple pixels PX can include, for example Figure 13 The three luminescent regions EA1, EA2, and EA3 shown may include, for example, Figure 14 The four light-emitting regions EA1, EA2, EA3, and EA4 are shown. In such an embodiment, the fourth light-emitting region EA4, which is the light-emitting region of the fourth sub-pixel SP4, can emit the same second light as the second light-emitting region EA2, but the disclosed embodiments are not limited thereto.

[0148] The light-emitting areas of multiple pixels PX can be arranged in a stripe structure where the light-emitting areas are arranged in the first direction DR1, wherein the light-emitting areas EA1, EA2, EA3 and EA4 are as follows: Figure 14 The PenTile arranged in a diamond shape is shown. ® The structure or the hexagonal structure in which the light-emitting area is arranged in a hexagonal shape.

[0149] Figure 15 This is an example of a display panel shown along... Figure 13 A sectional view taken from line I1-I1'.

[0150] Reference Figure 15 The embodiment of the display panel 100 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0151] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference... Figure 11 The first transistor T1 to the sixth transistor T6 are described.

[0152] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity described above. In an embodiment, for example, if the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. In another embodiment, if the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0153] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0154] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be located on the side surface of the gate electrode GE. The side insulating film (SINS) can be located on the lower insulating film (BINS).

[0155] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can be stacked with the gate electrode GE on the third direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0156] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA can be increased by using the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, which can increase the length of the channel region CH of each pixel transistor PTR.

[0157] The first semiconductor insulating film SINS1 can be located on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1.

[0158] Multiple contact terminals (CTEs) may be located on a second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) may be connected to at least one selected from the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) through a hole defined or formed through the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) may comprise an alloy of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or formed from an alloy of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0159] The third semiconductor insulating film SINS3 can be located on the side surface of each of the plurality of contact terminals CTEs. The upper surface of each of the plurality of contact terminals CTEs can be exposed and not covered by the third semiconductor insulating film SINS3.

[0160] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 may include silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon carbonitride (SiCN) or silicon oxide (SiO) x Inorganic membrane formation, but the disclosed embodiments are not limited thereto.

[0161] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In embodiments, the thin-film transistor can be located on either a glass substrate or a polymer resin substrate. The glass substrate can be a rigid, non-bending substrate, while the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0162] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9 disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0163] The first insulating films INS1 to the eighth insulating films INS8 are used to insulate the first conductive layers ML1 to the eighth conductive layers ML8. The first conductive layers ML1 to the eighth conductive layers ML8 are used to achieve this by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP. Figure 11 The circuit of the first sub-pixel SP1 shown.

[0164] In one embodiment, for example, only the first transistor T1 to the sixth transistor T6 are formed on the semiconductor backplane SBP, and the first transistor T1 to the sixth transistor T6 are connected to the first capacitor CP1 and the second capacitor CP2 through the first conductive layer ML1 to the eighth conductive layer ML8. Additionally, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE are also connected through the first conductive layer ML1 to the eighth conductive layer ML8.

[0165] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise or be formed of substantially the same material as each other. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of these materials, or an alloy formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first vias VA1 to VA8 may comprise or be formed of substantially the same material as each other. The first insulating films INS1 to INS8 may comprise silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x Inorganic membrane formation, but the disclosed embodiments are not limited thereto.

[0166] The ninth insulating film INS9 can be located on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 may include silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x Inorganic membrane formation, but the disclosed embodiments are not limited thereto.

[0167] Each of the ninth vias VA9 can be connected to the eighth conductive layer ML8 exposed by penetrating the ninth insulating film INS9. The ninth via VA9 can comprise at least one or an alloy selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or can be formed from at least one or an alloy selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0168] The display element layer (EML) can be located on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth insulating film (INS10) and an eleventh insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0169] The reflective electrode RL can be located on the ninth insulating film INS9. The reflective electrode RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4. In an embodiment, for example, as shown... Figure 15 As shown, the reflective electrode RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0170] The first reflective electrode RL1 can be located on the ninth insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be located on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be located on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be located on its corresponding third reflective electrode RL3.

[0171] Since the second reflective electrode RL2 can be an electrode that substantially reflects light from the light-emitting element, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0172] The first reflective electrode RL1 may comprise an alloy selected from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be formed from an alloy selected from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In embodiments, for example, the first reflective electrode RL1 may comprise titanium nitride (TiN), the second reflective electrode RL2 may comprise aluminum (Al), the third reflective electrode RL3 may comprise titanium nitride (TiN), and the fourth reflective electrode RL4 may comprise titanium (Ti).

[0173] The tenth insulating film INS10 can be located on the ninth insulating film INS9. The tenth insulating film INS10 can be arranged between adjacent reflective electrodes RL. The tenth insulating film INS10 can be a film used to flatten the height difference caused by the reflective electrodes RL. The eleventh insulating film INS11 can be located on the tenth insulating film INS10 and the reflective electrodes RL.

[0174] The tenth insulating film INS10 and the eleventh insulating film INS11 may include silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x Inorganic membrane formation, but the disclosed embodiments are not limited thereto.

[0175] The eleventh insulating film INS11 can be an optical auxiliary layer used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixels SP1, SP2, and SP3. The thickness of the eleventh insulating film INS11 in the first sub-pixels SP1, SP2, and SP3 can be different. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixels SP1, SP2, and SP3, the thickness of the eleventh insulating film INS11 can be set in each of the first sub-pixels SP1, SP2, and SP3.

[0176] In an embodiment, for example, such as Figure 15 As shown, the thickness of the eleventh insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0177] Each of the tenth vias VA10 can be connected to a reflective electrode RL exposed through the eleventh insulating film INS11. The tenth via VA10 can comprise at least one or an alloy selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or can be formed from at least one or an alloy selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0178] The first electrode AND of each of the light-emitting elements LE can be located on the eleventh insulating film INS11 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy including any of them, or can be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy including any of them. In an embodiment, for example, the first electrode AND of each light-emitting element LE can include titanium nitride (TiN) or be formed of titanium nitride (TiN).

[0179] A pixel-defining film (PDL) may be located on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL may cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL may separate a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be a region in which a light-emitting element LE, including the first electrode AND, a light-emitting stack IL, and a second electrode CAT, is arranged.

[0180] The first light-emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light-emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light-emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0181] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be located on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be located on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be located on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may comprise silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x The inorganic film is formed. Optionally, the first pixel defining film PDL1 and the third pixel defining film PDL3 include silicon nitride (SiN). x Inorganic films of the series or made of silicon nitride (SiN) x The inorganic film formation of the series, wherein the second pixel defining film PDL2 may include silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x The inorganic film is formed. The thickness of the first pixel-defined film PDL1, the thickness of the second pixel-defined film PDL2, and the thickness of the third pixel-defined film PDL3 can each be about 500 angstroms (Å).

[0182] In this embodiment, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with a stepped height difference to prevent the first encapsulating inorganic film TFE1 from breaking due to step coverage. Step coverage refers to the ratio of the degree to which the film is applied to the inclined portion to the degree to which the film is applied to the flat portion. When the step coverage is low, the possibility of the film breaking at the inclined portion may increase.

[0183] Each of the plurality of trench TRCs may pass through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In each of the plurality of trench TRCs, at least a portion of the eleventh insulating film INS11 may have a recessed shape.

[0184] At least one trench TRC can be arranged between adjacent sub-pixels SP1, SP2, and SP3. In an embodiment, as shown... Figure 15 As shown, two trench TRCs are arranged between adjacent sub-pixels SP1, SP2 and SP3, but the disclosed embodiments are not limited thereto.

[0185] The light-emitting stack IL may include multiple stacked layers IL1, IL2, and IL3. In an embodiment, as shown... Figure 15 As shown, the light-emitting stack IL has a three-tiered structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but the disclosed embodiments are not limited thereto. In embodiments, for example, as... Figure 16 As shown, the light-emitting stack IL can have a dual-tandem structure comprising two stacked layers.

[0186] In an embodiment where the light-emitting stack IL has a three-tiered structure, the light-emitting stack IL may have a tiered structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. In an embodiment, for example, the light-emitting stack IL may include a first stacked layer IL1 emitting light of a first color, a second stacked layer IL2 emitting light of a second color, and a third stacked layer IL3 emitting light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0187] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting third light, and a third electron transport layer are sequentially stacked.

[0188] A first charge-generating layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an n-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a p-type charge-generating layer that supplies holes to the second stacked layer IL2. The n-type charge-generating layer may include a dopant of a metallic material.

[0189] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an n-type charge generation layer that supplies electrons to the second stacked layer IL2 and a p-type charge generation layer that supplies holes to the third stacked layer IL3.

[0190] A first stacked layer IL1 may be located on the first electrode AND and the pixel defining film PDL, and in each of the trench TRCs, the residual film RIL located on the bottom surface of the trench TRC may be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be located on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space may be arranged in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 may be located on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected by the trench TRC and may be arranged to cover the second stacked layer IL2 in each of the trench TRCs.

[0191] In an embodiment where the light-emitting stack IL has a three-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. Alternatively, in a dual-series structure, each of the plurality of trench TRCs can be a structure for disconnecting the charge generation layer and the lower stacked layer disposed between the lower and upper stacked layers.

[0192] In an embodiment, the height of each of the plurality of trench TRCs may be greater than the height of the pixel defining film PDL to stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. The height of each of the plurality of trench TRCs represents the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL indicates the length of the pixel defining film PDL in the third direction DR3. In an embodiment, other structures may exist instead of trench TRCs to disconnect the hole transport layer and charge generation layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In an embodiment, for example, a separator wall having an inverted conical shape may be located on the pixel defining film PDL instead of a trench TRC.

[0193] In an embodiment, such as Figure 15As shown, the light-emitting stack IL is arranged in all of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3; however, the disclosed embodiments are not limited thereto. In embodiments, for example, the first stack layer IL1 may be arranged in the first light-emitting region EA1 instead of the light-emitting stack IL, and may not be arranged in the second light-emitting region EA2 and the third light-emitting region EA3. Additionally, the second stack layer IL2 may be arranged in the second light-emitting region EA2, and may not be arranged in the first light-emitting region EA1 and the third light-emitting region EA3. Furthermore, the third stack layer IL3 may be arranged in the third light-emitting region EA3, and may not be arranged in the first light-emitting region EA1 and the second light-emitting region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be omitted.

[0194] The second electrode CAT can be located on the light-emitting stack IL. The second electrode CAT can be located on the third stack layer IL3 in each of the plurality of trench TRCs. The second electrode CAT can include a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag), or formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In embodiments where the second electrode CAT includes or is formed of a semi-transmissive conductive material, luminous efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 by using microcavities.

[0195] The encapsulation layer TFE can be located on the display element layer EML. The encapsulation layer TFE may include one or more inorganic films TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be located on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be located on the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be formed in which silicon nitride (SiN) is present. x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium dioxide (TiO) x ) layer and alumina (AlO) x A layer of one or more inorganic membranes stacked alternately.

[0196] Additionally, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign matter such as dust. In an embodiment, for example, at least one organic film TFE2 of the encapsulation layer TFE may be disposed between a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE3. The at least one organic film TFE2 of the encapsulation layer TFE may be a monomer. Optionally, the at least one organic film TFE2 of the encapsulation layer TFE may be an organic film comprising acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, or made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0197] The adhesive layer (ADL) can be a layer used to adhere the encapsulation layer (TFE) and the optical layer (OPL). The adhesive layer (ADL) can be a double-sided adhesive. Alternatively, the adhesive layer (ADL) can be a transparent adhesive or a transparent adhesive resin.

[0198] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the adhesive layer ADL.

[0199] A first color filter CF1 can be superimposed on a first emitting region EA1 of a first sub-pixel SP1. The first color filter CF1 can transmit light of a first color (that is, light in the blue band). The blue band can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emitting region EA1.

[0200] The second color filter CF2 can be superimposed on the second emitting region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (that is, light in the green band). The green band can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of a second color emitted from the second emitting region EA2.

[0201] The third color filter CF3 can be superimposed on the third emitting region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color (that is, light in the red band). The red band can be from approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emitting region EA3.

[0202] Each of the plurality of lenses LNS may be located on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light directed to the front of the display device 10. Each of the plurality of lenses LNS may have a profile shape that convexes in the upward direction.

[0203] The filler layer (FIL) can be located on multiple lenses (LNS). The filler layer (FIL) can have a predetermined refractive index such that light travels in the third direction (DR3) at the interface between the multiple lenses (LNS) and the filler layer (FIL). Alternatively, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, or made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0204] The cover layer CVL can be located on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin substrate. In embodiments where the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the filler layer FIL. In such embodiments, the filler layer FIL can be used to adhere the cover layer CVL. In embodiments where the cover layer CVL is a glass substrate, the cover layer CVL can be used as an encapsulation substrate. In embodiments where the cover layer CVL is a polymer resin substrate, the cover layer CVL can be applied directly to the filler layer FIL.

[0205] The polarizer POL can be located on one surface of the CVL cover layer. The polarizer POL can be a structure used to prevent visibility degradation due to reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. In embodiments, for example, the phase retardation film can be a λ / 4 (quarter-wave) plate, but the disclosed embodiments are not limited thereto. In embodiments, the polarizer POL can also be omitted if visibility degradation due to reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0206] Figure 16 This is an example of another embodiment of the display panel shown along... Figure 13 A sectional view taken from line I1-I1'.

[0207] Figure 16 Implementation examples and Figure 15The embodiments are essentially the same, except that: the first electrode AND of each of the light-emitting elements LE is electrically connected by contact with the side surface of the connection electrode ANC connected to the eighth conductive layer ML8, and the trench TRC is omitted; instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. In the following text, [the following will be omitted or simplified]. Figure 16 The embodiments and Figure 15 The embodiments are described in detail without any repetition of elements that are the same or similar to those in the embodiments.

[0208] Reference Figure 16 In this embodiment, multiple connection electrodes ANC may be located on the first portion AA1 of the ninth insulating film INS9. Each of the multiple connection electrodes ANC may be located on its corresponding first portion AA1 of the ninth insulating film INS9. The multiple connection electrodes ANC may comprise an alloy or transparent conductive oxide containing at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be formed of an alloy or transparent conductive oxide containing at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the multiple connection electrodes ANC may comprise titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the disclosed embodiments are not limited thereto.

[0209] Multiple reflective electrodes RL can be located on multiple connecting electrodes ANC, respectively. Each of the multiple reflective electrodes RL can be located on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or can be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In an embodiment, for example, each of the multiple reflective electrodes RL can include aluminum (Al) with high reflectivity.

[0210] Multiple optical auxiliary films (OALs) can be respectively located on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be located on its corresponding reflective electrode (RL). The multiple optical auxiliary films (OALs) may include silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) xInorganic membrane formation, but the disclosed embodiments are not limited thereto.

[0211] The stepped layer STPL can be located on the reflective electrode RL in each of the first luminescent region EA1 and the third luminescent region EA3, and the optical auxiliary film OAL can be located on the stepped layer STPL. In the second luminescent region EA2, only the optical auxiliary film OAL can be located on the reflective electrode RL. The thickness of the optical auxiliary film OAL in the first luminescent region EA1, the second luminescent region EA2, and the third luminescent region EA3 can be substantially the same.

[0212] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first light-emitting region EA1 and the third light-emitting region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second light-emitting region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be set by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0213] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0214] The first electrode AND of each of the light-emitting elements LE can be located on its corresponding optical auxiliary film OAL. Since the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each of the light-emitting elements LE can be located on the upper and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Therefore, the first electrode AND of each of the light-emitting elements LE can be electrically connected by contact with the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to the case where the first electrode AND of each of the light-emitting elements LE is connected to the exposed reflective electrode RL through a through-hole defined or formed by the optical auxiliary film OAL, masking processes can be reduced, thus reducing manufacturing costs and improving manufacturing efficiency.

[0215] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connection electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0216] The ninth insulating film INS9 may include a first portion AA1 superimposed on the third-direction DR3 with the connecting electrode ANC and a second portion AA2 not superimposed on the third-direction DR3 with the connecting electrode ANC. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth insulating film INS9 may be substantially the same as each other.

[0217] Optionally, the thickness of the first portion AA1 of the ninth insulating film INS9 may be greater than the thickness of the second portion AA2. In such an embodiment, the side surface of the first portion AA1 of the ninth insulating film INS9 may be exposed, and the first electrode AND of each light-emitting element LE may be located on the exposed side surface of the first portion AA1 of the ninth insulating film INS9.

[0218] The first electrode AND of each of the light-emitting elements LE may comprise an alloy or transparent conductive oxide selected from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or may be formed from an alloy or transparent conductive oxide selected from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first electrode AND of each of the light-emitting elements LE may comprise titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the disclosed embodiments are not limited thereto.

[0219] The pixel-defining film (PDL) can be located on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3.

[0220] The pixel-limiting film (PDL) may include a first pixel-limiting film (PDL1), a second pixel-limiting film (PDL2), a third pixel-limiting film (PDL3), and a fourth pixel-limiting film (PDL4).

[0221] The first pixel defining film PDL1 may be located on the first electrode AND of each of the light-emitting elements LE. Specifically, the first pixel defining film PDL1 may cover a portion of the upper surface of the first electrode AND located on the optical auxiliary film OAL. Additionally, the first pixel defining film PDL1 may cover the first electrode AND located on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 may be located on the upper surface of the second portion AA2 of the ninth insulating film INS9.

[0222] The planarization film PNS is a film used to planarize the steps (or step structures) caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0223] The planarization film PNS can be located on the first pixel defining film PDL1, which covers the side surface of the first electrode AND located on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can be located on the first pixel defining film PDL1, which is positioned on the second part AA2 of the ninth insulating film INS9.

[0224] The planarization film PNS can be disposed between adjacent connecting electrodes ANC along the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL along the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL along the first direction DR1 or the second direction DR2.

[0225] Although the step layer STPL is absent in the second light-emitting region EA2, it is present in each of the first light-emitting region EA1 and the third light-emitting region EA3. As a result, the overall height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second light-emitting region EA2 can be less than the overall height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in each of the first light-emitting region EA1 and the third light-emitting region EA3. Therefore, the planarization film PNS can cover the upper surface of the first pixel defining film PDL1 located on the upper surface of the first electrode AND disposed in the second light-emitting region EA2.

[0226] In an embodiment, the upper surface of the planarization film PNS can be flatly connected to the upper surface of the first pixel defining film PDL1 disposed in the first light-emitting region EA1 and the third light-emitting region EA3. That is, the planarization film PNS may not cover the upper surface of the first pixel defining film PDL1 located on the upper surface of the first electrode AND disposed in each of the first light-emitting region EA1 and the third light-emitting region EA3.

[0227] The second pixel defining film PDL2 can be located on the first pixel defining film PDL1 and the planarization film PNS, the third pixel defining film PDL3 can be located on the second pixel defining film PDL2, and the fourth pixel defining film PDL4 can be located on the third pixel defining film PDL3. The first pixel defining film PDL1 and the third pixel defining film PDL3 include silicon nitride (SiN). x Inorganic films or films containing silicon nitride (SiN) xThe inorganic film is formed, and the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS may include silicon oxide (SiO2). x Inorganic membranes or membranes containing silicon dioxide (SiO2) x The inorganic film is formed. Since the first pixel defining film PDL1 comprises or is formed of a material different from the planarization film PNS, the first pixel defining film PDL1 can be used as a stop in the process of chemical polishing and mechanical polishing of the planarization film PNS.

[0228] The planarization film PNS and the second pixel defining film PDL2 include silicon oxide (SiO2). x The same inorganic film or composed of silicon oxide (SiO) x In embodiments where the same inorganic film is formed, the planarization film PNS and the second pixel defining film PDL2 can be formed as a single film.

[0229] Since the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the lower surface of the fourth pixel defining film PDL4 can be exposed without being covered by the third pixel defining film PDL3. That is, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have a cross-sectional structure in the shape of an eaves or a mushroom.

[0230] The light-emitting stack IL can be located on the first electrode AND and the pixel defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different lights. In an embodiment where the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light in a wavelength range including one of a first light, a second light, and a third light, and the remaining one can emit light in a wavelength range including the other two light wavelengths. In an embodiment, for example, the first stacked layer IL1 can emit light including the wavelength range of the first light and the wavelength range of the third light, and the second stacked layer IL2 can emit light including the wavelength range of the second light. Here, the first light can be blue light, the second light can be green light, and the third light can be red light.

[0231] A charge-generating layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge-generating layer may include an n-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a p-type charge-generating layer that supplies holes to the second stacked layer IL2. The n-type charge-generating layer may include a dopant of a metallic material.

[0232] In embodiments where the first stacked layer IL1 is not formed on the exposed lower surface of the fourth pixel defining film PDL4 that is not covered by the third pixel defining film PDL3, the first stacked layer IL1 can be disconnected by a roof-shaped or mushroom-shaped cross-sectional structure formed by the third pixel defining film PDL3 and the fourth pixel defining film PDL4. In such embodiments, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be disconnected. In embodiments, such as Figure 16 As shown, the second stacked layer IL2 can be connected without being disconnected, but the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be effectively prevented from flowing between the adjacent light-emitting regions EA1, EA2, and EA3 through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer. Therefore, the light-emitting stacks IL in the adjacent light-emitting regions EA1, EA2, and EA3 can be effectively prevented from being affected by current and from emitting light other than the initially intended light.

[0233] Figure 16 An embodiment of a light-emitting stack IL having a dual-tandem structure wherein the light-emitting stack IL comprises two stacked layers IL1 and IL2 is shown, but the disclosed embodiments are not limited thereto. In the embodiments, for example, as Figure 15 As shown, the light-emitting stack IL can have a triple-tandem structure comprising three stacked layers. In such an embodiment, by adjusting the height of the third pixel defining film PDL3, the charge-generating layers between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3, can be designed to be disconnected. Optionally, as... Figure 15 As shown, a trench TRC can be added that defines or forms through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In such an embodiment, the trench TRC can extend through at least a portion of the ninth insulating film INS9, but the disclosed embodiments are not limited thereto.

[0234] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0235] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. An optical device, the optical device comprising: A light source provides light; Multiple first nanostructures collimate the light from the light source and convert the optical path of the light from the light source; A light guide portion that allows light incident on the light guide portion from the plurality of first nanostructures to be totally internalized in such a way that the light on the light guide portion travels from one end of the light guide portion to the other end. A spatial light modulator modulates the phase of light incident on the spatial light modulator from the light guide and outputs light having the phase modulated thereon. as well as Multiple second nanostructures collimate the light incident from the light guide onto the multiple second nanostructures and convert the optical path of the light incident onto the multiple second nanostructures to provide the light incident onto the multiple second nanostructures to the spatial light modulator.

2. The optical device according to claim 1, wherein, The plurality of first nanostructures have a first width, a first height, and a first spacing.

3. The optical device according to claim 1, wherein, The plurality of second nanostructures have a second width, a second height, and a second spacing.

4. The optical device according to claim 1, wherein, The length of the second region where the plurality of second nanostructures are arranged is greater in the first direction than the length of the first region where the plurality of first nanostructures are arranged in the first direction.

5. The optical device according to claim 4, wherein, The length of the second region in which the plurality of second nanostructures are arranged in the second direction orthogonal to the first direction is the same as the length of the first region in which the plurality of first nanostructures are arranged in the second direction.

6. The optical device according to claim 1, wherein, The light source is an organic light-emitting diode (OLED) display device comprising an organic light-emitting layer disposed on a first semiconductor substrate.

7. The optical device according to claim 1, wherein, The light source includes: The first light source provides the first light of the first color; A second light source provides a second light of a second color; and A third light source, providing a third color of light.

8. The optical device according to claim 7, wherein, Each of the first light source, the second light source, and the third light source is a silicon-based organic light-emitting diode display device including an organic light-emitting layer disposed on a first semiconductor substrate.

9. The optical device according to claim 7, wherein, The plurality of first nanostructures include: Multiple first sub-nanostructures are stacked with the first light source, wherein the multiple first sub-nanostructures collimate the first light emitted from the first light source and convert the optical path of the first light emitted from the first light source; A plurality of second sub-nanostructures are stacked with the second light source, wherein the plurality of second sub-nanostructures collimate the second light emitted from the second light source and convert the optical path of the second light emitted from the second light source; and Multiple third sub-nanostructures are stacked with the third light source, wherein the multiple third sub-nanostructures collimate the third light emitted from the third light source and convert the optical path of the third light emitted from the third light source.

10. The optical device according to claim 9, wherein, The plurality of first sub-nanostructures and the plurality of second sub-nanostructures are different from each other.

11. The optical device according to claim 10, wherein, The plurality of third sub-nanostructures are different from the plurality of first sub-nanostructures and the plurality of second sub-nanostructures.

12. The optical device according to claim 1, wherein, The spatial light modulator is a liquid crystal on silicon display device including a liquid crystal layer disposed on a second semiconductor substrate.

13. The optical device according to claim 1, wherein, The spatial light modulator includes: The first spatial light modulator modulates the phase of the first light; A second spatial light modulator modulates the phase of a second light; and A third-space light modulator modulates the phase of a third light source.

14. The optical device according to claim 13, wherein, Each of the first spatial light modulator, the second spatial light modulator, and the third spatial light modulator is a liquid crystal on silicon display device including a liquid crystal layer disposed on a second semiconductor substrate.

15. The optical device according to claim 13, wherein, The plurality of second nanostructures include: Multiple fourth sub-nanostructures are stacked with the first spatial light modulator, wherein the multiple fourth sub-nanostructures collimate the first light incident from the light guide portion onto the multiple fourth sub-nanostructures and convert the optical path of the first light incident onto the multiple fourth sub-nanostructures to provide the first light incident onto the multiple fourth sub-nanostructures to the first spatial light modulator. A plurality of fifth sub-nanostructures are stacked with the second spatial light modulator, wherein the plurality of fifth sub-nanostructures collimate the second light incident from the light guide onto the plurality of fifth sub-nanostructures and convert the optical path of the second light incident onto the plurality of fifth sub-nanostructures to provide the second light incident onto the plurality of fifth sub-nanostructures to the second spatial light modulator; and Multiple sixth sub-nanostructures are stacked with the third spatial light modulator, wherein the multiple sixth sub-nanostructures collimate the third light incident on the multiple sixth sub-nanostructures from the light guide portion and convert the optical path of the third light incident on the multiple sixth sub-nanostructures to provide the third light incident on the multiple sixth sub-nanostructures to the third spatial light modulator.

16. The optical device according to claim 15, wherein, The plurality of fourth sub-nanostructures and the plurality of fifth sub-nanostructures are different from each other.

17. The optical device according to claim 16, wherein, The plurality of sixth sub-nanostructures are different from the plurality of fourth sub-nanostructures and the plurality of fifth sub-nanostructures.

18. The optical device according to claim 1, wherein, The light guide extends in the first direction. The light source is arranged adjacent to one side of the light guide in the first direction, and The spatial light modulator is arranged adjacent to the other side of the light guide in the first direction.

19. The optical device according to claim 1, wherein, The light guide portion includes: The first extension extends in the first direction; The second extension extends upward at a third point intersecting the first direction; and A reflector is arranged in the area where one side of the first extension and one side of the second extension meet.

20. An electronic device, the electronic device comprising: lens; as well as An optical device that displays an image to a user's single eye through the lens. The optical device includes: A light source provides light; Multiple first nanostructures collimate the light from the light source and convert the optical path of the light from the light source; A light guide portion that allows light incident on the light guide portion from the plurality of first nanostructures to be totally internalized such that the light incident on the light guide portion travels from one end of the light guide portion to the other end; A spatial light modulator that modulates the phase of light incident on the spatial light modulator from the light guide and outputs light having the thus modulated phase; and Multiple second nanostructures collimate the light incident from the light guide onto the multiple second nanostructures and convert the optical path of the light incident onto the multiple second nanostructures to provide the light from the multiple second nanostructures to the spatial light modulator.

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