A digital low-dropout regulator circuit, module with load transient compensation

Abstract

The application discloses a kind of load instant compensation digital low-dropout regulator circuit, module, it is related to digital low-dropout regulator technical field.The application is additionally equipped with the load instant compensation circuit built with all transistor at the output of digital low-dropout regulator, it is coupled by coupling capacitor department coupling real-time change of digital low-dropout regulator output voltage, and by instant adjustment to the control voltage of voltage-controlled current source through voltage dividing resistance department, to control the current flowing through voltage-controlled current source with opposite change trend, and by the replication function of current mirror, current replication is carried out and is returned to digital low-dropout regulator output, to relieve digital low-dropout regulator output voltage change, instant compensation to digital low-dropout regulator output is realized, no longer rely on clock signal frequency, significantly improve transient response effect, can optimize circuit ripple when load is stable simultaneously, avoid the problem that circuit area is large under the influence of load capacitance.

Description

Technical Field

[0001] This invention relates to the field of digital low dropout voltage regulator technology, and more specifically, to: 1. a digital low dropout voltage regulator circuit based on real-time load compensation using a current mirror; 2. a digital low dropout voltage regulator module based on real-time load compensation using a current mirror. Background Technology

[0002] Digital low-dropout regulators (DLDOs) have become a core solution for on-chip power supplies in SoCs due to their strong process compatibility and high integrability. However, inherent defects in the current DLDO architecture regarding transient response, load adaptability, and compensation mechanisms severely limit its application in high-precision scenarios. 1. Traditional DLDOs rely on digital control loops to regulate the output voltage, and their response speed is directly limited by the control clock frequency. When the load current (generally equivalent to the current flowing through the load current source I...)... L When a sudden change occurs (such as a jump from 1μA to 10mA), the digital control loop needs at least one clock cycle to start adjustment, resulting in a significant undershoot of the output voltage.

[0003] 2. While the circuit ripple of traditional DLDOs is acceptable under stable load conditions, there is still room for optimization.

[0004] 3. The digital control loop of a traditional DLDO uses a variable load capacitor C. L The capacitance value is used to compensate for sudden changes in load current. This method is highly dependent on the load capacitance, which can easily lead to an excessively large circuit area due to the influence of the load capacitance—that is, in order to suppress a significant undershoot in the output voltage, C needs to be increased. L The capacitance value leads to a significant increase in circuit area. Summary of the Invention

[0005] Therefore, it is necessary to provide a digital low-dropout regulator circuit and module with real-time load compensation to address the problems of transient response being limited by clock frequency, circuit ripple still being optimizable when the load is stable, and circuit area being too large due to the influence of load capacitance in traditional digital low-dropout regulators.

[0006] This invention is achieved using the following technical solution: In a first aspect, the present invention provides a digital low-dropout regulator circuit with real-time load compensation, comprising: a regulator main circuit and a real-time load compensation circuit.

[0007] The main circuit of the voltage regulator has an output port Vout. The load real-time compensation circuit is connected to Vout and is entirely built using transistors.

[0008] The load real-time compensation circuit includes: a coupling capacitor section, a voltage divider resistor section, a voltage-controlled current source, and a current mirror section. The coupling capacitor section couples the voltage to Vout. The voltage divider resistor section divides the voltage output from the coupling capacitor section. The voltage-controlled current source controls the current flowing through it with an opposite trend based on the voltage divider signal from the voltage divider resistor section. The current mirror replicates the current flowing through the voltage-controlled current source and returns it to Vout.

[0009] This type of digital low-dropout regulator circuit with instant load compensation is implemented according to the method or process of an embodiment of this disclosure.

[0010] In a second aspect, the present invention discloses a digital low-dropout regulator module with real-time load compensation, which adopts the digital low-dropout regulator circuit layout with real-time load compensation as disclosed in the first aspect.

[0011] This type of digital low-dropout regulator module with instant load compensation is implemented according to the method or process of embodiments of this disclosure.

[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention adds a real-time load compensation circuit to the output terminal of a digital low-dropout regulator. This circuit couples the real-time changes in the output voltage of the digital low-dropout regulator through a coupling capacitor and adjusts the control voltage of the voltage-controlled current source in real time through a voltage divider resistor. This, in turn, controls the current flowing through the voltage-controlled current source with an opposite trend. Furthermore, the current is replicated using a current mirror and returned to the output terminal of the digital low-dropout regulator, thus mitigating voltage changes at the output terminal. This achieves real-time compensation for the output of the digital low-dropout regulator, eliminating reliance on clock signal frequency and significantly improving transient response. Simultaneously, it optimizes the circuit ripple of the digital low-dropout regulator when the load is stable.

[0013] 2. The instant load compensation circuit of this invention is entirely constructed using transistors, avoiding the introduction of components that would result in excessively large circuit areas and preventing the circuit area from becoming too large due to the influence of load capacitance. The instant load compensation circuit of this invention can be constructed with as few as 7 PMOS transistors, minimizing the circuit area required. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1A circuit diagram of a digital low-dropout regulator circuit with real-time load compensation provided in Embodiment 1 of the present invention; Figure 2 for Figure 1 Circuit diagram of the main circuit of the medium voltage regulator; Figure 3 Simulation results provided for Embodiment 2 of the present invention Figure 1 ; Figure 4 Simulation results provided for Embodiment 2 of the present invention Figure 2 . Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] Example 1 See Figure 1 This demonstrates the digital low-dropout regulator circuit with real-time load compensation provided in Embodiment 1, which mainly consists of two parts: 1. The main circuit of the voltage regulator can be a traditional DLDO mentioned in the background art—for example, using... Figure 2 The circuit design can be either this type or other DLDO designs. However, it should be noted that regardless of the design used, the main circuit of the regulator always has an output port Vout, and its function is the same—to stabilize Vout to make it close to the reference voltage VREF.

[0020] So, with Figure 2For example, the main circuit of a voltage regulator can be designed to include: a comparator, a bidirectional shift register, a switch array, and an external load.

[0021] The comparator's positive input is connected to VREF, its negative input is connected to Vout, and its output is connected to the input of the bidirectional shift register. That is, the comparator compares VREF and Vout: if Vout < VREF, the comparator outputs a high level (i.e., "1"); if Vout > VREF, the comparator outputs a low level (i.e., "0").

[0022] The comparator and bidirectional shift register control terminals are both connected to the clock signal CLK. That is, the comparator and bidirectional shift register share the same clock control. The bidirectional shift register outputs a parallel signal that matches the switch array based on the comparator's comparison result.

[0023] An external load is connected to Vout. As mentioned in the background section, the external load can generally be equivalent to: one load capacitor C. L 1 load current source I L C L The upper electrode is connected to Vout, and the lower electrode is connected to ground VSS; L The input terminal is connected to Vout, and the output terminal is connected to ground VSS.

[0024] A switch array is connected between the control terminal of the bidirectional shift register and Vout, and is used to periodically control the number of switches on as the external load changes under CLK control, thereby providing feedback adjustment to Vout. Generally, the switch array is constructed based on PMOS transistors. In this embodiment 1, the switch array is designed to include: 16 PMOS transistors Q1~Q 16 Q i The gate of the PMOS transistor is connected to the i-th output of the bidirectional shift register, the source is connected to the power supply VDD, and the drain is connected to Vout; i∈[1,16]. That is, the 16 PMOS transistors are located on the 16 connectable branches from VDD to Vout—each PMOS transistor acts as a 1-bit switch, controlling the conduction or cutoff of the corresponding branch.

[0025] As mentioned in the background section, the principle by which the main circuit of the voltage regulator described above regulates the output voltage (i.e., the voltage of Vout) is as follows: Under the control of CLK, the comparator reflects the change of Vout relative to VREF in the bidirectional shift register to control the shift direction of the digital code in the bidirectional shift register, and changes Q1~Q through the parallel signal output by the bidirectional shift register. 16The number of PMOS transistors turned on (only one PMOS transistor is controlled in a single control cycle: if Vout < VREF, one PMOS transistor is turned on; if Vout > VREF, one PMOS transistor is turned off) is modulated to gradually bring Vout closer to VREF.

[0026] 2. The load real-time compensation circuit is connected to Vout and is entirely constructed using transistors.

[0027] Unlike the main circuit of a voltage regulator, which relies on CLK to control and compensate for Vout, the load real-time compensation circuit is an instantaneous compensation mechanism that no longer depends on the clock signal frequency, which can significantly improve the transient response.

[0028] See Figure 1 The load real-time compensation circuit can be divided into the following components according to its function: coupling capacitor section, voltage divider resistor section, voltage-controlled current source section, and current mirror section.

[0029] ① The coupling capacitor couples the voltage of Vout.

[0030] In this embodiment 1, the coupling capacitor section can be designed to include: one PMOS transistor M1, which is used as a capacitor.

[0031] like Figure 1 As shown, the gate of M1 serves as the input terminal of the coupling capacitor section and is connected to Vout; the source of M1 is connected to the drain of M1 and serves as the output terminal of the coupling capacitor section.

[0032] ② The voltage divider resistors divide the voltage output from the coupling capacitor section.

[0033] Specifically, the voltage divider resistor section includes at least three PMOS transistors, which are connected in series as diode resistors between the output terminal of the coupling capacitor section and ground VSS, and are used to control the voltage divider signal to the voltage-controlled current source.

[0034] In this embodiment 1, the voltage divider resistor section can be designed to include: 3 PMOS transistors M2~M4, which are connected in series as diode resistors to divide the voltage.

[0035] like Figure 1 As shown, the source of M2 serves as the input terminal of the voltage divider resistor section and is connected to the output terminal of the coupling capacitor section; the gate of M2 is connected to the drain of M2 and to the source of M3; the gate of M3 is connected to the drain of M3 and the source of M4; the gate of M4 is connected to the drain of M4 and ground VSS.

[0036] In other words, M2, M3, and M4, connected in series as described above, act as resistors and form a voltage divider network from the voltage output from the coupling capacitor section to VSS.

[0037] Of course, several PMOS transistors (also connected in series as diode resistors) can be added between M2 and the output terminal of the coupling capacitor to adjust the voltage division range of M4.

[0038] ③ The voltage-controlled current source controls the current flowing through it with an opposite trend based on the voltage divider signal from the voltage divider resistor section.

[0039] In this embodiment 1, the voltage-controlled current source can be designed to include: one PMOS transistor M5.

[0040] like Figure 1 As shown, the gate of M5 serves as the control terminal of the voltage-controlled current source and is connected to the output terminal of the voltage divider resistor section; the source of M5 serves as the input terminal of the voltage-controlled current source; and the drain of M5 is connected to ground VSS and serves as the output terminal of the voltage-controlled current source.

[0041] In other words, the gate voltage of M5 is actually the voltage that M4 receives. When the gate voltage of M5 increases, the current flowing through M5 decreases; when the gate voltage of M5 decreases, the current flowing through M5 increases.

[0042] ④ The current mirror copies the current flowing through the voltage-controlled current source and returns it to Vout.

[0043] In this embodiment 1, the current mirror section can be designed to include: two PMOS transistors M6~M7.

[0044] like Figure 1 As shown, the gate of M6 is connected to the drain of M6 and to the input terminal of the voltage-controlled current source; the sources of M6 and M7 are connected to VDD; the gate of M7 is connected to the gate of M6, and the drain is connected to Vout.

[0045] M6 forms one branch of the current mirror, and M7 forms another branch of the current mirror. The current in the branch where M6 is located changes synchronously with the current flowing through M5. The current mirror replicates the current in the branch where M6 is located to the branch where M7 is located, and then applies it to Vout.

[0046] In summary, the load instant compensation circuit can be constructed with as few as 7 PMOS transistors, which can minimize the circuit area occupied.

[0047] The principle of adjusting the output voltage (i.e., the voltage of Vout) based on the above-described load instant compensation circuit is as follows: When the load current suddenly increases (corresponding to the load switching to a heavy load), C LInsufficient charge in the capacitor causes a drop in the voltage of Vout. The voltage of Vout is coupled to the voltage divider resistor through the coupling capacitor, which reduces the voltage divider signal. The voltage-controlled current source increases the current flowing through it due to the reduced voltage divider signal, which in turn increases the current flowing through one of the branches of the current mirror. This increased current is then replicated to Vout to mitigate the voltage drop caused by load changes. The process is reversed when the load current suddenly decreases, and will not be described further.

[0048] As can be seen from the above principles, the load instantaneous compensation circuit has significant immediacy in adjusting the voltage Vout. Moreover, even when the load is stable, the load instantaneous compensation circuit can optimize circuit ripple to a certain extent.

[0049] This embodiment 1 also discloses a digital low-dropout regulator module with real-time load compensation, which adopts the layout of the digital low-dropout regulator circuit with real-time load compensation disclosed in embodiment 1. The modular packaging makes it easier to promote and apply the aforementioned circuit.

[0050] Of course, the above-mentioned digital low-dropout regulator circuit with real-time load compensation can also be designed as a chip—if designed as a chip, the corresponding terminals can be designed as pins.

[0051] Example 2 To demonstrate the effectiveness and superiority of the load-instantaneous compensation digital low-dropout regulator circuit proposed in Example 1, this Example 2 constructs a load-instantaneous compensation digital low-dropout regulator circuit based on Example 1 (using... Figure 1 , Figure 2 The specific circuit design shown was used for simulation experiments, and compared with the traditional DLDO (using...) Figure 2 (Specific circuit design).

[0052] 1. The variation of the compensation current (i.e., the current flowing through M7) in the digital low-dropout regulator circuit with instant load compensation was investigated. See the results below. Figure 3 .

[0053] As Vout changes over time, the gate voltage of M5 also changes, generating a compensation current through the current mirror to suppress sudden load changes. For example... Figure 3 As shown, around 315µs, the load current suddenly increases, and the switching array cannot immediately provide enough current, resulting in a current supply of Vout being less than demand. L Rapid discharge causes a voltage drop in Vout, and the load compensation circuit compensates immediately by increasing the load compensation current to suppress voltage changes.

[0054] 2. The voltage ripple variation of a digital low-dropout regulator circuit with real-time load compensation and a traditional DLDO was investigated. See the results below. Figure 4 .

[0055] like Figure 4 As shown, for the 280us~310us range, the load did not change abruptly and was in a light load stage: the voltage ripple generated by the digital low dropout regulator circuit with instant load compensation (approximately 32mV) was reduced by 15.01mV and optimized by approximately 34.6% compared to the voltage ripple of the traditional DLDO (approximately 47mV).

[0056] Around 315µs, the load changed abruptly, and both circuits experienced voltage undershoot. However, the undershoot of the digital low dropout regulator circuit with instant load compensation was reduced by 22.5mV and optimized by about 13.7% compared to the traditional DLDO.

[0057] For the 335us~360us range, when the load does not change abruptly and is in a heavy load phase: the voltage ripple generated by the digital low dropout regulator circuit with instant load compensation (approximately 3.5mV) is reduced by 0.51mV and optimized by approximately 8.4% compared to the voltage ripple of a traditional DLDO (approximately 4mV).

[0058] In other words, using a load instant compensation circuit can achieve a low metastable voltage ripple and a low voltage undershoot during load switching, effectively improving the stability and reliability of the entire circuit.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A digital low-dropout regulator circuit with instant load compensation, comprising: The main circuit of the voltage regulator, which has an output port Vout, is characterized in that it further includes: a load real-time compensation circuit connected to Vout and constructed entirely of transistors, comprising: The coupling capacitor section couples the voltage of Vout. The voltage divider resistor section divides the voltage output from the coupling capacitor section; A voltage-controlled current source, which controls the current flowing through it based on the voltage divider signal from the voltage divider resistor section changing in opposite directions; and The current mirror replicates the current flowing through the voltage-controlled current source and returns it to Vout.

2. The digital low-dropout regulator circuit with real-time load compensation according to claim 1, characterized in that, The coupling capacitor section includes: one PMOS transistor M1, which acts as a capacitor; The gate of M1 serves as the input terminal of the coupling capacitor section and is connected to Vout; The source of M1 is connected to the drain of M1 and serves as the output terminal of the coupling capacitor section.

3. The digital low-dropout regulator circuit with real-time load compensation according to claim 1, characterized in that, The voltage divider resistor section includes at least three PMOS transistors connected in series as diode resistors between the output terminal of the coupling capacitor section and ground VSS, which are used to control the voltage divider signal to the voltage-controlled current source.

4. The digital low-dropout regulator circuit with real-time load compensation according to claim 3, characterized in that, The voltage divider resistor section includes: 3 PMOS transistors M2~M4; The source of M2 serves as the input terminal of the voltage divider resistor section and is connected to the output terminal of the coupling capacitor section. The gate of M2 is connected to the drain of M2 and to the source of M3; The gate of M3 is connected to the drain of M3 and the source of M4, and serves as the output terminal of the voltage divider resistor section. The gate of M4 is connected to the drain of M4 and ground VSS.

5. The digital low-dropout regulator circuit with instant load compensation according to claim 1, characterized in that, The voltage-controlled current source includes: one PMOS transistor M5; The gate of M5 serves as the control terminal of the voltage-controlled current source and is connected to the output terminal of the voltage divider resistor section; The source of M5 serves as the input terminal of the voltage-controlled current source; The drain of M5 is connected to ground VSS and serves as the output terminal of the voltage-controlled current source.

6. The digital low-dropout regulator circuit with instant load compensation according to claim 1, characterized in that, The current mirror section includes: two PMOS transistors M6 and M7; The gate of M6 is connected to the drain of M6 and is connected to the input terminal of the voltage-controlled current source; The source terminals of M6 and M7 are connected to VDD; The gate of M7 is connected to the gate of M6, and the drain is connected to Vout.

7. The digital low-dropout regulator circuit with instant load compensation according to any one of claims 1-6, characterized in that, The main circuit of the voltage regulator includes: a comparator, a bidirectional shift register, a switch array, and an external load; The positive input of the comparator is connected to the reference voltage VREF, the negative input is connected to Vout, and the output is connected to the input of the bidirectional shift register; the control terminals of both the comparator and the bidirectional shift register are connected to the clock signal CLK. The external load is connected to Vout; the switch array is connected between the control terminal of the bidirectional shift register and Vout, and is used to periodically control the number of switches to be turned on as the external load changes under the control of CLK, so as to make feedback adjustments to Vout.

8. The digital low-dropout regulator circuit with instant load compensation according to claim 7, characterized in that, The external load includes: 1 load capacitor C L 1 load current source I L C L The upper electrode is connected to Vout, and the lower electrode is connected to ground VSS; L The input terminal is connected to Vout, and the output terminal is connected to ground VSS.

9. The digital low-dropout regulator circuit with instant load compensation according to claim 7, characterized in that, The switch array includes: 16 PMOS transistors Q1~Q 16 Q i The gate is connected to the i-th output of the bidirectional shift register, the source is connected to the power supply VDD, and the drain is connected to Vout; i∈[1,16].

10. A digital low-dropout voltage regulator module with real-time load compensation, characterized in that, It adopts the layout of a digital low-dropout regulator circuit with real-time load compensation as described in any one of claims 1-9.

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