A bandgap reference circuit applied to high-precision ADC

Abstract

The application discloses a band gap reference circuit applied to a high-precision ADC and relates to the field of analog integrated circuit design.The high-order temperature nonlinearity (curvature error of first-order compensation) problem is solved, the temperature stability is improved through the design of a high-order segmented temperature compensation circuit unit, the shortcomings of traditional first-order compensation are optimized through the segmented compensation circuit, and the error caused by high-order temperature nonlinearity is reduced.The power supply rejection ratio (PSRR) and noise resistance are improved.The Cascode compensation margin compensation mode is adopted in the operational amplifier circuit module, the influence of power voltage fluctuation is suppressed, high output impedance is provided through self-biasing common-source common-gate current mirror, power noise coupling is reduced, and the PSRR is improved.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design, and more specifically to a bandgap reference circuit for use in high-precision ADCs. Background Technology

[0002] The bandgap reference circuit is a core module in analog integrated circuits. Its function is to generate a stable DC voltage that is nearly unaffected by temperature and supply voltage. This reference voltage is widely used in analog-to-digital converters (ADCs), digital-to-analog converters (DACs), voltage regulators, and various precision analog systems, providing them with a high-precision reference. Furthermore, it can provide stable bias current to other analog circuit modules through voltage-to-current conversion. Its performance directly determines the accuracy and reliability of the entire system. Negative temperature coefficient voltage (CTAT) and positive temperature coefficient voltage (PTAT) refer to voltages with negative and positive temperature coefficients, respectively. In traditional bandgap reference circuits, the base-emitter voltage VBE of a transistor exhibits a negative temperature coefficient characteristic, while the voltage difference ΔVBE between two different transistors exhibits a positive temperature coefficient characteristic. By weighted superposition of these two voltage sources with opposite temperature coefficients, a stable reference voltage signal can be obtained. However, existing bandgap reference circuits still have the following technical limitations: (1) Process deviation: Deviations in the process parameters of resistors and bipolar junction transistors (BJTs) can cause drift in output voltage and temperature coefficient. Such problems usually need to be compensated by adjustment techniques, but this increases the complexity and cost of the circuit. (2) Temperature nonlinearity: Higher-order temperature nonlinearity of VBE (such as curvature error) cannot be completely eliminated by traditional first-order temperature compensation methods. Higher-order compensation or nonlinear correction techniques are required to solve this problem. (3) Power supply rejection ratio (PSRR) limitation: In low-voltage or high-noise environments, fluctuations in power supply voltage will be coupled to the output through MOSFETs or resistors. Special PSRR enhancement circuits are usually required to improve anti-interference performance. (4) Low-voltage adaptation challenge: With the continuous reduction of power supply voltage in modern nanotechnology, traditional bandgap structures are difficult to apply directly. Special low-voltage architectures (such as segmented curvature compensation or self-biased structures) are required to achieve compatibility. Summary of the Invention

[0003] This invention utilizes negative temperature coefficient (CTAT) current and positive temperature coefficient (PTAT) current to design a high-order temperature compensation circuit, which participates in compensating the temperature curve of the reference voltage and reducing the temperature drift of the reference. This invention solves the technical defects of traditional bandgap reference circuits through the collaborative design of the bandgap reference core circuit unit, LDO circuit unit, and high-order segmented temperature compensation circuit unit, specifically as follows: (1) Solving the problem of high-order temperature nonlinearity (curvature error of first-order compensation), this invention improves temperature stability through the design of high-order segmented temperature compensation circuit unit. (2) Improving power supply rejection ratio (PSRR) and noise immunity, this invention reduces power supply noise coupling and improves PSRR through Cascode-compensated op-amp margin compensation method and current mirror isolation.

[0004] This invention provides a bandgap reference circuit for high-precision ADCs, the bandgap reference circuit comprising: a bandgap reference core circuit unit, an LDO circuit module, and a startup circuit module; The core circuit unit of the bandgap reference includes: a clamping operational amplifier feedback network, a positive and negative temperature coefficient voltage generation circuit, a current mirror circuit, and a segmented compensation circuit; the two input terminals of the clamping operational amplifier feedback network are connected to the clamping voltage VA and clamping voltage VB output by the positive and negative temperature coefficient voltage generation network, and the clamping operational amplifier feedback network generates a zero temperature coefficient reference voltage VREF and inputs the reference voltage VREF to the input terminal of the positive and negative temperature coefficient voltage generation network; The LDO circuit module clamps the output node bias voltage VS1 to its two input terminals through a current negative feedback op-amp circuit and generates a reference current IREF. The reference current IREF is mirrored and copied by a self-biased low-voltage cascode current mirror to provide the bias current required by the nonlinear compensation module. The startup circuit module provides a temporary bias current or voltage to enable the bandgap reference voltage source to start working from the degenerate bias point and gradually stabilize. Once the bandgap reference voltage source starts working normally, its output voltage will gradually replace the temporary bias provided by the startup circuit, thereby ensuring the stability and reliability of the entire circuit system.

[0005] Preferably, the emitter junction area ratio of transistors Q1 and Q3 to that of transistors Q2 and Q4 is 1:8.

[0006] Preferably, the clamping operational amplifier feedback circuit includes: amplifier A1, NMOS transistor M16, and resistor array; the positive terminal clamping voltage VA of amplifier A1 is connected to the second terminal of resistor R1 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M1, the negative terminal clamping voltage VB of amplifier A1 is connected to the second terminal of resistor R2 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M2, the output terminal P0 of amplifier A1 is connected to the gate of NMOS transistor M16, the drain of NMOS transistor M16 is connected to the power supply voltage, and the source of NMOS transistor M6 is connected to the first terminal of the resistor array and the base of transistors Q3 and Q4 in the positive and negative temperature coefficient voltage generation circuit, and serves as the output of the bandgap reference.

[0007] Preferably, the positive and negative temperature coefficient voltage generating circuit includes: resistors R1, R2, R4, R6, and R7; PMOS transistors M1 and M2; and transistors Q1, Q2, Q3, and Q4. The first terminal of resistor R1 is connected to the power supply voltage, and the second terminal of R1 is connected to the drain of PMOS transistor M1, serving as an output terminal to output a clamping voltage VA. The first terminal of resistor R2 is connected to the power supply voltage, and the second terminal of R2 is connected to the drain of PMOS transistor M2, serving as an output terminal to output a clamping voltage VB. The gate and source of PMOS transistor M1 are connected, and the source is connected to the collector of transistor Q3. The gate and source of PMOS transistor M2 are connected... The sources of transistors are connected to the collector of transistor Q4, and the base of transistor Q3 is connected to the base of transistor Q4 and connected to the output of the clamping operational amplifier feedback circuit. The collector of transistor Q1 is connected to the emitter of transistor Q3 and the base of transistor Q1. The collector of transistor Q2 is connected to the emitter of transistor Q4 and the base of transistor Q2. The first end of resistor R4 is connected to the emitter of transistor Q2, and the second end of resistor R4 is connected to the emitter of transistor Q1 and the first end of resistor R6, serving as the output terminal to output voltage Vptat. The second end of resistor R6 is connected to the first end of resistor R7 and the output terminal of the compensation circuit.

[0008] Preferably, the current mirror circuit includes: resistors R3 and R5, a PMOS transistor M3, NMOS transistors M4, M5, M6, M7, and M17, and a transistor Q5; the first terminal of resistor R3 is connected to the power supply voltage, the second terminal of R3 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M3 is connected to the source of PMOS transistor M2, the source of PMOS transistor M3 is connected to the collector of transistor Q5, the base of transistor Q5 is floating, the emitter of transistor Q5 is connected to the first terminal of resistor R5, the gate of NMOS transistor M4, and the gate of NMOS transistor M5, and the second terminal of resistor R5 is connected to the NMOS transistor M17. The drain of S-MOSFET M4, the gate of NMOS transistor M6, the gate of NMOS transistor M7, and the gate of NMOS transistor M are connected. The source of NMOS transistor R4 is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is grounded. The drain of NMOS transistor M5 is connected to the output of PMOS transistor M8 and LDO circuit as the input of compensation circuit. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7. The source of NMOS transistor M7 is grounded. The drain of NMOS transistor M17 is connected to the source of NMOS transistor M13 as the input of compensation circuit. The source of NMOS transistor M17 is grounded.

[0009] Preferably, the compensation circuit includes: PMOS transistors M8, M9, M10, and M11, and NMOS transistors M12, M13, M14, and M15; the drain of PMOS transistor M8 is connected to the output port of the LDO circuit unit, the drain of NMOS transistor M5 in the current mirror circuit, and the drain of PMOS transistor M10; the gate of PMOS transistor M8 is connected to the input voltage VREF2; the gate of PMOS transistor M9 is connected to the reference ground REFGND; the source of PMOS transistor M9 is grounded; the gate of PMOS transistor M10 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit; the source of PMOS transistor M10 is connected to the drain of PMOS transistor M11; the source of PMOS transistor M11 is an output terminal of the compensation circuit; and the drain of NMOS transistor M12 is connected to the power supply voltage. The gate of NMOS transistor M12 is connected to the input voltage Vint2.5. The source of NMOS transistor M12 is connected to the drain of NMOS transistor M13. The gate of NMOS transistor M13 is connected to the input voltage VREF1. The source of NMOS transistor M13 is connected to the source of NMOS transistor M15 and the drain of NMOS transistor M17. The gate of NMOS transistor M15 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit. The drain of NMOS transistor M15 is connected to the source of NMOS transistor M14. The gate of NMOS transistor M14 is connected to the input voltage Vint2.5. The drain of NMOS transistor M14 is another output terminal of the compensation circuit. The two output terminals of the compensation circuit are connected to the second terminal of resistor R6 and the first terminal of resistor R7 after current merging to output the compensation current.

[0010] Preferably, the LDO circuit includes: PMOS transistors M18, M19, M20, M21, M26, and M27; NMOS transistors M23, M24, M25, and M28; capacitor C1; and resistors R8 and R9. The drain of PMOS transistor M18 is connected to the bandgap reference voltage VS1, and the gate of PMOS transistor M18 is connected to the drain of PMOS transistor M18 and PMOS transistor M19. The gate and input port NIBI of the PMOS transistor M19 are connected. The drain of the PMOS transistor M19 is connected to VS1. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20, the drain of the PMOS transistor M21, and the drain of the PMOS transistor M22. The gate of the PMOS transistor M20 is connected to its drain and is also connected to VS1. The gate of the PMOS transistor M21 is connected to the input VL. The gate of the NMOS transistor M23 is connected to the drain of the NMOS transistor M23, the source of the PMOS transistor M21, the gate of the NMOS transistor M24, and the drain of the NMOS transistor M25. The source of the NMOS transistor M23 is connected to the reference ground. The gate of the PMOS transistor M22 is connected to the first terminal of the resistor R8 and the source of the NMOS transistor M28. The source of the PMOS transistor M22 is connected to... The first terminal of capacitor C1 is connected to the gate of NMOS transistor M28 and the drain of NMOS transistor M24. The source of NMOS transistor M24 is connected to the reference ground. The gate and source of NMOS transistor M25 are connected and connected to the reference ground. The second terminal of capacitor C1 is connected to the reference ground. The drain of PMOS transistor M26 is connected to VS1. The gate of PMOS transistor M26 is connected to the source of PMOS transistor M26, the gate of PMOS transistor M27 and the drain of NMOS transistor M28. The drain of PMOS transistor M27 is connected to VS1. The source of PMOS transistor M27 is connected to port RB0 as the LDO circuit output reference current. The second terminal of resistor R8 is connected to the first terminal of resistor R9. The second terminal of resistor R9 is connected to the reference ground.

[0011] Preferably, the operational amplifier A1 circuit includes: resistors R10, R11, R12, and R13; transistors Q5 and Q6; NMOS transistors M29, M31, M35, M36, M37, M42, M44, M45, M46, M47, M48, M49, M52, M53, M54, and M55; PMOS transistors M30, M32, M33, M34, M38, M39, M40, M41, M43, M50, and M51; and capacitor C2; the first terminal of resistor R10 is connected to the power supply voltage, and the second terminal of resistor R10 is connected to resistor R11. The first terminal of the resistor R11 is connected to the collector of transistor Q5. The base of transistor Q5 is connected to the input voltage VM. Transistor Q6 is connected to the input voltage VP. The emitters of transistors Q5 and Q6 are connected and connected to the drain of NMOS transistor M29 and the source of NMOS transistor M30. The gate of NMOS transistor M29 is connected to the input clamping voltage VA. The gate of NMOS transistor M30 is connected to the input VA. The source of NMOS transistor M29 and the drain of NMOS transistor M30 are connected and connected to the drain of NMOS transistor M31 and NMOS transistor M32. The source of the NMOS transistor M31 is connected to the source of the amplifier, which serves as the output voltage P0. The gate of the NMOS transistor M31 is connected to the input clamping voltage VB, and the source of M31 is connected to the reference ground. The gate of the NMOS transistor M32 is connected to the reference ground, and the drain of the NMOS transistor M32 is connected to the reference ground. The drain of the PMOS transistor M33 is connected to the power supply voltage. The gate of the PMOS transistor M33 is connected to the gates of PMOS transistors M41, M34, and M42. The source of the PMOS transistor M33 is connected to the drain of the PMOS transistor M34. The source of the PMOS transistor M34 is connected to the drain of the NMOS transistor M35. The gate of the NMOS transistor M35 is connected to VA. The source of the NMOS transistor M35 is connected to the drains of the NMOS transistors M36 and M37. The gate of the NMOS transistor M36 is connected to the source of the amplifier, which serves as the output voltage P0 of the amplifier. VB is connected. The source of NMOS transistor M36 is connected to reference ground. The gate and drain of NMOS transistor M37 are connected to reference ground. The drain and gate of PMOS transistor M39 are connected to the power supply voltage. The source of PMOS transistor M39 is connected to the gate of PMOS transistor M38, the gate of PMOS transistor M40, and the source of PMOS transistor M41. The drain of PMOS transistor M38 is connected to the power supply voltage. The source of PMOS transistor M38 is connected to the drain of PMOS transistor M41. The drain of PMOS transistor M40 is connected to the power supply voltage. The source of PMOS transistor M40 is connected to the drain of PMOS transistor M42 and connected to the first terminal of capacitor C2. The sources of PMOS transistors M42 and M41 are respectively connected to the drain and source of PMOS transistor M43. The gate of PMOS transistor M43 is connected to input VINT1.The gate of NMOS transistor M44 is connected to the collector of transistor Q6. The source of NMOS transistor M44 is connected to the sources of PMOS transistors M43 and M41. The gate of NMOS transistor M45 is connected to the collector of transistor Q5. The source of NMOS transistor M45 is connected to the drain of PMOS transistors M43 and M42. The drain of NMOS transistor M44 is connected to the drain of NMOS transistor M45 and also connected to the drains of NMOS transistors M46, M48, and M49, and connected to the output port P1. The gate of NMOS transistor M46 is connected to VA. The source of NMOS transistor M46 is connected to the drain of NMOS transistor M47. The gate of NMOS transistor M47 is connected to VB. The source of NMOS transistor M47 is connected to reference ground. NMOS transistor M48... The gate and source of the NMOS transistor M49 are connected to the reference ground. The gate and source of the PMOS transistor M50 are connected to the power supply voltage. The source of the PMOS transistor M50 is connected to the gate of the PMOS transistor M51, the drain of the PMOS transistor M42, the drain of the PMOS transistor M43, and the source of the NMOS transistor M45. The drain of the PMOS transistor M51 is connected to the power supply voltage. The source of the PMOS transistor M51 is connected to the second terminal of capacitor C2 and the drain of the NMOS transistor M52. The source of NMOS transistor M53 is connected to the output port as output V0. The gate of NMOS transistor M52 is connected to VA. The gate of NMOS transistor M53 is also connected to VA. The source of NMOS transistor M52 and the drain of NMOS transistor M53 are connected and then connected to the drains of NMOS transistors M54 and M55. The gate of NMOS transistor M54 is connected to VB. The source of NMOS transistor M54 is connected to reference ground. The gate and source of NMOS transistor M55 are both connected to reference ground.

[0012] Preferably, the startup circuit includes: NMOS transistors M56, M57, M58, M59, M60, M61, M62, M63, and M64; the drain of NMOS transistor M56 is connected to the input power supply, the gate of NMOS transistor M56 is connected to the gate of NMOS transistor M60, the source of NMOS transistor M56 is connected to the source of NMOS transistor M16 in the bandgap reference core circuit, the drain of NMOS transistor M57 is connected to the power supply voltage, and the source of NMOS transistor M57 is connected to NMOS transistor M58. The drains of NMOS transistors M57, M58, M59, and M60 are connected. The source of NMOS transistor M60 is connected to the drain of NMOS transistor M61 and the gate of NMOS transistor M62. The gate and drain of NMOS transistor M61 are connected. The source and gate of NMOS transistor M62 are connected and connected to the source of NMOS transistor M61 and the drain of NMOS transistor M63. The gate and drain of NMOS transistor M63 are connected. The source of NMOS transistor M63 is connected to the drain of NMOS transistor M64. The gate and drain of NMOS transistor M64 are connected. The source of NMOS transistor M64 is grounded.

[0013] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention solves the problem of high-order temperature nonlinearity (curvature error of first-order compensation). This invention improves temperature stability by designing a high-order piecewise temperature compensation circuit unit, and optimizes the shortcomings of traditional first-order compensation by segmented compensation circuit, thereby reducing the error caused by high-order temperature nonlinearity.

[0014] 2. This invention improves power supply rejection ratio (PSRR) and noise immunity: The operational amplifier circuit module of this invention adopts a Cascode compensation margin method to suppress the influence of power supply voltage fluctuations; the self-biased cascode current mirror provides high output impedance, reduces power supply noise coupling, and improves PSRR. Attached Figure Description

[0015] Figure 1 This is the core circuit diagram of the bandgap reference of the present invention.

[0016] Figure 2 This is the circuit diagram for an LDO.

[0017] Figure 3 This is the circuit diagram for amplifier A1.

[0018] Figure 4 This is the circuit diagram for startup. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0020] like Figures 1-4 As shown, an embodiment of the present invention specifically provides a bandgap reference circuit, including: The core circuit unit of the bandgap reference includes: a clamping operational amplifier feedback network, a positive and negative temperature coefficient voltage generation network, a current mirror circuit, and a segmented compensation circuit; the two input terminals of the clamping operational amplifier feedback network are connected to the clamping voltage VA and clamping voltage VB output by the positive and negative temperature coefficient voltage generation network, and the clamping operational amplifier feedback network generates a zero temperature coefficient reference voltage VREF and inputs the reference voltage VREF to the input terminal of the positive and negative temperature coefficient voltage generation network; The LDO circuit module clamps the output node bias voltage VS1 to its two input terminals through a current negative feedback op-amp circuit and generates a reference current IREF. The reference current IREF is mirrored and copied by a self-biased low-voltage cascode current mirror to provide the bias current required by the nonlinear compensation module.

[0021] The positive and negative temperature coefficient voltage generating circuit includes: resistors R1, R2, R4, R6, and R7; PMOS transistors M1 and M2; and transistors Q1, Q2, Q3, and Q4. The first terminal of resistor R1 is connected to the power supply voltage, and the second terminal of R1 is connected to the drain of PMOS transistor M1, serving as the output terminal to output the clamping voltage VA. The first terminal of resistor R2 is connected to the power supply voltage, and the second terminal of R2 is connected to the drain of PMOS transistor M2, serving as the output terminal to output the clamping voltage VB. The gate and source of PMOS transistor M1 are connected, and the source is connected to the collector of transistor Q3. The gate and source of PMOS transistor M2 are connected... The source of transistor Q1 is connected to the collector of transistor Q4. The base of transistor Q3 is connected to the base of transistor Q4 and is also connected to the output of the clamping operational amplifier feedback circuit. The collector of transistor Q1 is connected to the emitter of transistor Q3 and the base of transistor Q1. The collector of transistor Q2 is connected to the emitter of transistor Q4 and the base of transistor Q2. The first end of resistor R4 is connected to the emitter of transistor Q2. The second end of resistor R4 is connected to the emitter of transistor Q1 and the first end of resistor R6, serving as the output terminal to output voltage Vptat. The second end of resistor R6 is connected to the first end of resistor R7 and the output terminal of the compensation circuit. The emitter junction area ratio of transistors Q1, Q3 and Q2, Q4 is 1:8.

[0022] The current mirror circuit includes: resistors R3 and R5, a PMOS transistor M3, NMOS transistors M4, M5, M6, M7, and M17, and a transistor Q5. The first terminal of resistor R3 is connected to the power supply voltage, and the second terminal of R3 is connected to the drain of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the source of PMOS transistor M2. The source of PMOS transistor M3 is connected to the collector of transistor Q5. The base of transistor Q5 is left floating. The emitter of transistor Q5 is connected to the first terminal of resistor R5, the gate of NMOS transistor M4, and the gate of NMOS transistor M5. The second terminal of resistor R5 is connected to the NMOS transistor... The drain of transistor M4, the gate of NMOS transistor M6, the gate of NMOS transistor M7, and the gate of NMOS transistor M are connected. The source of NMOS transistor R4 is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is grounded. The drain of NMOS transistor M5 is connected to the output of PMOS transistor M8 and LDO circuit as the input of compensation circuit. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7. The source of NMOS transistor M7 is grounded. The drain of NMOS transistor M17 is connected to the source of NMOS transistor M13 as the input of compensation circuit. The source of NMOS transistor M17 is grounded.

[0023] The compensation circuit includes: PMOS transistors M8, M9, M10, and M11; and NMOS transistors M12, M13, M14, and M15. The drain of PMOS transistor M8 is connected to the output port of the LDO circuit unit, the drain of NMOS transistor M5 in the current mirror circuit, and the drain of PMOS transistor M10. The gate of PMOS transistor M8 is connected to the input voltage VREF2. The gate of PMOS transistor M9 is connected to the reference ground REFGND, and the source of PMOS transistor M9 is grounded. The gate of PMOS transistor M10 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit. The source of PMOS transistor M10 is connected to PMOS transistor M11. The source of PMOS transistor M11 is connected to the output terminal of the compensation circuit. The drain of NMOS transistor M12... The gate of NMOS transistor M12 is connected to the input voltage Vint2.5, the source of NMOS transistor M12 is connected to the drain of NMOS transistor M13, the gate of NMOS transistor M13 is connected to the input voltage VREF1, the source of NMOS transistor M13 is connected to the source of NMOS transistor M15, the gate of NMOS transistor M15 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit, the drain of NMOS transistor M15 is connected to the source of NMOS transistor M14, the gate of NMOS transistor M14 is connected to the input voltage Vint2.5, and the drain of NMOS transistor M14 is connected to the output terminal of the compensation circuit. The output terminal of the compensation circuit is connected to the second terminal of resistor R6 and the first terminal of resistor R7 to output compensation current.

[0024] The compensation circuit module mirrors the PTAT current on M4 and M5 using NMOS transistors M6 and M7, and uses the output voltage VS1 of the bandgap reference circuit as the input to the LDO circuit. The LDO circuit can generate a temperature-independent ZTAT current. NMOS transistor M17 mirrors the PTAT current on M4 and M5. When the temperature changes, the Vptat voltage output by the positive and negative temperature coefficient voltage generation circuit changes accordingly. Vptat is input to the gates of NMOS transistors M10 and M15 to control the switching degree of the CTAT and PTAT compensation circuits, thereby controlling the CTAT and PTAT compensation currents. Different compensation currents are generated in different temperature regions, and the generated compensation currents are fed back to the positive and negative temperature coefficient voltage generation circuits to complete the piecewise nonlinear compensation.

[0025] The clamping operational amplifier feedback circuit includes: amplifier A1, NMOS transistor M16, and resistor array; the positive terminal clamping voltage VA of amplifier A1 is connected to the second terminal of resistor R1 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M1, the negative terminal clamping voltage VB of amplifier A1 is connected to the second terminal of resistor R2 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M2, the output terminal P0 of amplifier A1 is connected to the gate of NMOS transistor M16, the drain of NMOS transistor M16 is connected to the power supply voltage, and the source of NMOS transistor M6 is connected to the first terminal of the resistor array and the base of transistors Q3 and Q4 in the positive and negative temperature coefficient voltage generation circuit, and serves as the output of the bandgap reference.

[0026] The core circuit module of this bandgap reference uses an operational amplifier to clamp the clamping voltages VA and VB to the same voltage. ,in These are the voltage differences between the base (B) and emitter (E) of transistors Q1, Q2, Q3, and Q4, respectively. Since the thermal voltage VT is positively correlated with temperature, and n is the area ratio of transistors Q1, Q3 and Q2, Q4, an IPTAT positive temperature coefficient current can be obtained from this network. By adjusting the value of 2*lnn(R6+R7) / R2, a temperature-independent reference voltage can be obtained.

[0027] The LDO circuit includes: PMOS transistors M18, M19, M20, M21, M26, and M27; NMOS transistors M23, M24, M25, and M28; capacitor C1; and resistors R8 and R9. The drain of PMOS transistor M18 is connected to the bandgap reference voltage VS1, and the gate of PMOS transistor M18 is connected to the drain of PMOS transistor M18 and the gate of PMOS transistor M19. The gate and input port NIBI of the PMOS transistor M19 are connected. The drain of the PMOS transistor M19 is connected to VS1. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20, the drain of the PMOS transistor M21, and the drain of the PMOS transistor M22. The gate of the PMOS transistor M20 is connected to its drain and is also connected to VS1. The gate of the PMOS transistor M21 is connected to the input VL. The gate of the NMOS transistor M23 is connected to the drain of the NMOS transistor M23, the source of the PMOS transistor M21, the gate of the NMOS transistor M24, and the drain of the NMOS transistor M25. The source of the NMOS transistor M23 is connected to the reference ground. The gate of the PMOS transistor M22 is connected to the first terminal of the resistor R8 and the source of the NMOS transistor M28. The source of transistor M22 is connected to the first terminal of capacitor C1, the gate of NMOS transistor M28, and the drain of NMOS transistor M24. The source of NMOS transistor M24 is connected to reference ground. The gate and source of NMOS transistor M25 are connected and also connected to reference ground. The second terminal of capacitor C1 is connected to reference ground. The drain of PMOS transistor M26 is connected to VS1. The gate of PMOS transistor M26 is connected to the source of PMOS transistor M26, the gate of PMOS transistor M27, and the drain of NMOS transistor M28. The drain of PMOS transistor M27 is connected to VS1. The source of PMOS transistor M27 is connected to port RB0 as the LDO circuit output reference current. The second terminal of resistor R8 is connected to the first terminal of resistor R9. The second terminal of resistor R9 is connected to reference ground.

[0028] The operational amplifier A1 circuit includes: resistors R10, R11, R12, and R13; transistors Q5 and Q6; NMOS transistors M29, M31, M35, M36, M37, M42, M44, M45, M46, M47, M48, M49, M52, M53, M54, and M55; PMOS transistors M30, M32, M33, M34, M38, M39, M40, M41, M43, M50, and M51; and capacitor C2. The first terminal of resistor R10 is connected to the power supply voltage, and the second terminal of resistor R10 is connected to the second terminal of resistor R11. At one end, the second end of resistor R11 is connected to the collector of transistor Q5. The base of transistor Q5 is connected to the input voltage VM. Transistor Q6 is connected to the input voltage VP. The emitters of transistors Q5 and Q6 are connected and connected to the drain of NMOS transistor M29 and the source of NMOS transistor M30. The gate of NMOS transistor M29 is connected to the input clamping voltage VA. The gate of NMOS transistor M30 is connected to the input VA. The source of NMOS transistor M29 and the drain of NMOS transistor M30 are connected and connected to the drain of NMOS transistor M31 and NMOS transistor M32. The source of the NMOS transistor M31 is connected to the source of the amplifier, which serves as the output voltage P0. The gate of the NMOS transistor M31 is connected to the input clamping voltage VB, and the source of M31 is connected to the reference ground. The gate of the NMOS transistor M32 is connected to the reference ground, and the drain of the NMOS transistor M32 is connected to the reference ground. The drain of the PMOS transistor M33 is connected to the power supply voltage. The gate of the PMOS transistor M33 is connected to the gates of PMOS transistors M41, M34, and M42. The source of the PMOS transistor M33 is connected to the drain of the PMOS transistor M34. The source of the PMOS transistor M34 is connected to the drain of the NMOS transistor M35. The gate of the NMOS transistor M35 is connected to VA. The source of the NMOS transistor M35 is connected to the drains of the NMOS transistors M36 and M37. The gate of the NMOS transistor M36 is connected to the source of the amplifier, which serves as the output voltage P0 of the amplifier. VB is connected. The source of NMOS transistor M36 is connected to reference ground. The gate and drain of NMOS transistor M37 are connected to reference ground. The drain and gate of PMOS transistor M39 are connected to the power supply voltage. The source of PMOS transistor M39 is connected to the gate of PMOS transistor M38, the gate of PMOS transistor M40, and the source of PMOS transistor M41. The drain of PMOS transistor M38 is connected to the power supply voltage. The source of PMOS transistor M38 is connected to the drain of PMOS transistor M41. The drain of PMOS transistor M40 is connected to the power supply voltage. The source of PMOS transistor M40 is connected to the source of PMOS transistor M42 and connected to the first terminal of capacitor C2. The drain of PMOS transistor M42 and the source of PMOS transistor M41 are respectively connected to the drain and source of PMOS transistor M43. The gate of PMOS transistor M43 is connected to input VINT1.The gate of NMOS transistor M44 is connected to the collector of transistor Q6. The source of NMOS transistor M44 is connected to the sources of PMOS transistors M43 and M41. The gate of NMOS transistor M45 is connected to the collector of transistor Q5. The source of NMOS transistor M45 is connected to the drain of PMOS transistors M43 and M42. The drain of NMOS transistor M44 is connected to the drain of NMOS transistor M45 and also connected to the drains of NMOS transistors M46, M48, and M49, and connected to the output port P1. The gate of NMOS transistor M46 is connected to VA. The source of NMOS transistor M46 is connected to the drain of NMOS transistor M47. The gate of NMOS transistor M47 is connected to VB. The source of NMOS transistor M47 is connected to reference ground. NMOS transistor M48... The gate and source of the NMOS transistor M49 are connected to the reference ground. The gate and source of the PMOS transistor M50 are connected to the power supply voltage. The source of the PMOS transistor M50 is connected to the gate of the PMOS transistor M51, the drain of the PMOS transistor M42, the drain of the PMOS transistor M43, and the source of the NMOS transistor M45. The drain of the PMOS transistor M51 is connected to the power supply voltage. The source of the PMOS transistor M51 is connected to the second terminal of capacitor C2 and the drain of the NMOS transistor M52. The source of NMOS transistor M53 is connected to the output port as output V0. The gate of NMOS transistor M52 is connected to VA. The gate of NMOS transistor M53 is also connected to VA. The source of NMOS transistor M52 and the drain of NMOS transistor M53 are connected and then connected to the drains of NMOS transistors M54 and M55. The gate of NMOS transistor M54 is connected to VB. The source of NMOS transistor M54 is connected to reference ground. The gate and source of NMOS transistor M55 are both connected to reference ground.

[0029] The startup circuit includes: NMOS transistors M56, M57, M58, M59, M60, M61, M62, M63, and M64. The drain of NMOS transistor M56 is connected to the input power supply; the gate of NMOS transistor M56 is connected to the gate of NMOS transistor M60; the source of NMOS transistor M56 is connected to the source of NMOS transistor M16 in the bandgap reference core circuit; the drain of NMOS transistor M57 is connected to the power supply voltage; the source of NMOS transistor M57 is connected to the drain of NMOS transistor M58; and the source of NMOS transistor M58 is connected to the drain of NMOS transistor M59. The source of NMOS transistor M59 is connected to the drain of M59. The gates of NMOS transistors M57, M58, M59, and M60 are connected. The source of NMOS transistor M60 is connected to the drain of NMOS transistor M61 and the gate of NMOS transistor M62. The gate of NMOS transistor M61 is connected to its drain. The source of NMOS transistor M62 is connected to its gate and connected to the source of NMOS transistor M61 and the drain of NMOS transistor M63. The gate of NMOS transistor M63 is connected to its drain. The source of NMOS transistor M63 is connected to the drain of NMOS transistor M64. The gate of NMOS transistor M64 is connected to its drain. The source of NMOS transistor M64 is grounded.

[0030] When the power is on, the NMOS transistors M57-M60 are stacked in series as a protection circuit, and the source-drain connection of NMOS transistor M62 acts as a capacitor. When the power supply increases, a voltage difference appears across M62. At this time, NMOS transistors M63 and M64 conduct to generate current, which is reflected through NMOS transistor M61 to NMOS transistor M56 and input to the resistor array of the bandgap reference to generate voltage, so that the core circuit of the bandgap reference is freed from the degenerate bias point. When the bandgap reference circuit is working normally, the source voltage of NMOS transistor M56 rises, causing Vgs of M56 to drop below the threshold Vt, M56 is turned off, and the startup circuit is shut down.

[0031] It employs a two-segment high-order coefficient compensation, and the core architecture uses an adjustable high-order compensation coefficient circuit generated by the PTAT voltage to address... The two temperature ranges, where positive and negative temperature coefficients are dominant respectively, are adjusted separately. The auxiliary circuit includes front-end calibration designs such as voltage divider resistor trimming, output resistor trimming, and trimming coefficient trimming.

[0032] Under military temperature conditions (-55℃ - 125℃), the typical temperature drift coefficient is 5ppm / ℃, and the maximum temperature drift under extreme conditions is less than 20ppm / ℃. The output low temperature drift voltage is 2.048V (the actual voltage drift after adjustment is less than 5mV), the typical linear sensitivity is 0.08% / V, the typical actual integral noise root mean square value is about 8uV in the frequency range of 0.1 - 10Hz, and the typical current loss is 346uA.

[0033] Table 1. Performance comparison of this invention with other bandgap reference circuits

[0034] Table 1 compares the performance of this invention with three published bandgap reference circuits, including Product 1 [Analog Devices. Precision Low Drift 2.048 V / 2.500 V SOT-23 Voltage Reference. ADR380 / ADR381 Datasheet, [Online]. Available: www.analog.com.], Product 2 [Analog Devices. Precision Micropower, Low Dropout Voltage References. REF19x Series Datasheet, [Online]. Available: www.analog.com.], and Product 3 [AnalogDevices. Micropower, Low Noise Precision Voltage References with Shutdown. ADR390 / ADR391 / ADR392 / ADR395 Datasheet, [Online]. Available: www.analog.com.]. The comparison table shows that this invention exhibits excellent performance.

Claims

1. A bandgap reference circuit for use in a high-precision ADC, the bandgap reference circuit comprising: Bandgap reference core circuit unit, LDO circuit module, startup circuit module; The core circuit unit of the bandgap reference includes: a clamping operational amplifier feedback network, a positive and negative temperature coefficient voltage generation circuit, a current mirror circuit, and a segmented compensation circuit; the two input terminals of the clamping operational amplifier feedback network are connected to the clamping voltage VA and clamping voltage VB output by the positive and negative temperature coefficient voltage generation network, and the clamping operational amplifier feedback network generates a zero temperature coefficient reference voltage VREF and inputs the reference voltage VREF to the input terminal of the positive and negative temperature coefficient voltage generation network; The LDO circuit module clamps the output node bias voltage VS1 to its two input terminals through a current negative feedback op-amp circuit and generates a reference current IREF. The reference current IREF is mirrored and copied by a self-biased low-voltage cascode current mirror to provide the bias current required by the nonlinear compensation module. The startup circuit module provides a temporary bias current or voltage to enable the bandgap reference voltage source to start working from the degenerate bias point and gradually stabilize. Once the bandgap reference voltage source starts working normally, its output voltage will gradually replace the temporary bias provided by the startup circuit, thereby ensuring the stability and reliability of the entire circuit system.

2. The bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The clamping operational amplifier feedback circuit includes: amplifier A1, NMOS transistor M16, and resistor array; the positive terminal clamping voltage VA of amplifier A1 is connected to the second terminal of resistor R1 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M1, the negative terminal clamping voltage VB of amplifier A1 is connected to the second terminal of resistor R2 in the positive and negative temperature coefficient voltage generation circuit and the drain of PMOS transistor M2, the output terminal P0 of amplifier A1 is connected to the gate of NMOS transistor M16, the drain of NMOS transistor M16 is connected to the power supply voltage, and the source of NMOS transistor M6 is connected to the first terminal of the resistor array and the base of transistors Q3 and Q4 in the positive and negative temperature coefficient voltage generation circuit, and serves as the output of the bandgap reference.

3. The bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The positive and negative temperature coefficient voltage generating circuit includes: resistors R1, R2, R4, R6, and R7; PMOS transistors M1 and M2; and transistors Q1, Q2, Q3, and Q4. The first terminal of resistor R1 is connected to the power supply voltage, and the second terminal of R1 is connected to the drain of PMOS transistor M1, serving as the output terminal to output the clamping voltage VA. The first terminal of resistor R2 is connected to the power supply voltage, and the second terminal of R2 is connected to the drain of PMOS transistor M2, serving as the output terminal to output the clamping voltage VB. The gate and source of PMOS transistor M1 are connected, and the source is connected to the collector of transistor Q3. The gate and source of PMOS transistor M2 are connected... The source of transistor Q1 is connected to the collector of transistor Q4. The base of transistor Q3 is connected to the base of transistor Q4 and is connected to the output of the clamping operational amplifier feedback circuit. The collector of transistor Q1 is connected to the emitter of transistor Q3 and the base of transistor Q1. The collector of transistor Q2 is connected to the emitter of transistor Q4 and the base of transistor Q2. The first end of resistor R4 is connected to the emitter of transistor Q2. The second end of resistor R4 is connected to the emitter of transistor Q1 and the first end of resistor R6, serving as the output terminal to output voltage Vptat. The second end of resistor R6 is connected to the first end of resistor R7 and the output terminal of the compensation circuit.

4. The bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The current mirror circuit includes: resistors R3 and R5, PMOS transistor M3, NMOS transistors M4, M5, M6, M7, and M17, and transistor Q5. The first terminal of resistor R3 is connected to the power supply voltage, and the second terminal of R3 is connected to the drain of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the source of PMOS transistor M2. The source of PMOS transistor M3 is connected to the collector of transistor Q5. The base of transistor Q5 is left floating. The emitter of transistor Q5 is connected to the first terminal of resistor R5, the gate of NMOS transistor M4, and the gate of NMOS transistor M5. The second terminal of resistor R5 is connected to the NMOS transistor M17. The drain of M4, the gate of NMOS transistor M6, the gate of NMOS transistor M7, and the gate of NMOS transistor M are connected. The source of NMOS transistor R4 is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is grounded. The drain of NMOS transistor M5 is connected to the output of PMOS transistor M8 and LDO circuit as the input of compensation circuit. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7. The source of NMOS transistor M7 is grounded. The drain of NMOS transistor M17 is connected to the source of NMOS transistor M13 as the input of compensation circuit. The source of NMOS transistor M17 is grounded.

5. The bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The compensation circuit includes: PMOS transistors M8, M9, M10, and M11; and NMOS transistors M12, M13, M14, and M15. The drain of PMOS transistor M8 is connected to the output port of the LDO circuit unit, the drain of NMOS transistor M5 in the current mirror circuit, and the drain of PMOS transistor M10. The gate of PMOS transistor M8 is connected to the input voltage VREF2. The gate of PMOS transistor M9 is connected to the reference ground REFGND, and the source of PMOS transistor M9 is grounded. The gate of PMOS transistor M10 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit. The source of PMOS transistor M10 is connected to the drain of PMOS transistor M11. The source of PMOS transistor M11 is an output terminal of the compensation circuit. The drain of NMOS transistor M12 is connected to the power supply voltage. The gate of MOSFET M12 is connected to the input voltage Vint2.

5. The source of NMOS transistor M12 is connected to the drain of NMOS transistor M13. The gate of NMOS transistor M13 is connected to the input voltage VREF1. The source of NMOS transistor M13 is connected to the source of NMOS transistor M15 and the drain of NMOS transistor M17. The gate of NMOS transistor M15 is connected to the output voltage Vptat of the positive and negative temperature coefficient voltage generation circuit. The drain of NMOS transistor M15 is connected to the source of NMOS transistor M14. The gate of NMOS transistor M14 is connected to the input voltage Vint2.

5. The drain of NMOS transistor M14 is another output terminal of the compensation circuit. The two output terminals of the compensation circuit are connected to the second terminal of resistor R6 and the first terminal of resistor R7 after current merging to output the compensation current.

6. A bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The LDO circuit includes: PMOS transistors M18, M19, M20, M21, M26, and M27; NMOS transistors M23, M24, M25, and M28; capacitor C1; and resistors R8 and R9. The drain of PMOS transistor M18 is connected to the bandgap reference voltage VS1, and the gate of PMOS transistor M18 is connected to the drain of PMOS transistor M18 and the gate of PMOS transistor M19. The gate and input port NIBI of the PMOS transistor M19 are connected. The drain of the PMOS transistor M19 is connected to VS1. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20, the drain of the PMOS transistor M21, and the drain of the PMOS transistor M22. The gate of the PMOS transistor M20 is connected to its drain and is also connected to VS1. The gate of the PMOS transistor M21 is connected to the input VL. The gate of the NMOS transistor M23 is connected to the drain of the NMOS transistor M23, the source of the PMOS transistor M21, the gate of the NMOS transistor M24, and the drain of the NMOS transistor M25. The source of the NMOS transistor M23 is connected to the reference ground. The gate of the PMOS transistor M22 is connected to the first terminal of the resistor R8 and the source of the NMOS transistor M28. The source of the PMOS transistor M22 is connected to... The first terminal of capacitor C1 is connected to the gate of NMOS transistor M28 and the drain of NMOS transistor M24. The source of NMOS transistor M24 is connected to the reference ground. The gate and source of NMOS transistor M25 are connected and connected to the reference ground. The second terminal of capacitor C1 is connected to the reference ground. The drain of PMOS transistor M26 is connected to VS1. The gate of PMOS transistor M26 is connected to the source of PMOS transistor M26, the gate of PMOS transistor M27 and the drain of NMOS transistor M28. The drain of PMOS transistor M27 is connected to VS1. The source of PMOS transistor M27 is connected to port RB0 as the LDO circuit output reference current. The second terminal of resistor R8 is connected to the first terminal of resistor R9. The second terminal of resistor R9 is connected to the reference ground.

7. A bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The operational amplifier A1 circuit includes: resistors R10, R11, R12, and R13; transistors Q5 and Q6; NMOS transistors M29, M31, M35, M36, M37, M42, M44, M45, M46, M47, M48, M49, M52, M53, M54, and M55; PMOS transistors M30, M32, M33, M34, M38, M39, M40, M41, M43, M50, and M51; and capacitor C2. The first terminal of resistor R10 is connected to the power supply voltage, and the second terminal of resistor R10 is connected to the second terminal of resistor R11. At one end, the second end of resistor R11 is connected to the collector of transistor Q5. The base of transistor Q5 is connected to the input voltage VM. Transistor Q6 is connected to the input voltage VP. The emitters of transistors Q5 and Q6 are connected and connected to the drain of NMOS transistor M29 and the source of NMOS transistor M30. The gate of NMOS transistor M29 is connected to the input clamping voltage VA. The gate of NMOS transistor M30 is connected to the input VA. The source of NMOS transistor M29 and the drain of NMOS transistor M30 are connected and connected to the drain of NMOS transistor M31 and NMOS transistor M32. The source of the NMOS transistor M31 is connected to the source of the amplifier, which serves as the output voltage P0. The gate of the NMOS transistor M31 is connected to the input clamping voltage VB, and the source of M31 is connected to the reference ground. The gate of the NMOS transistor M32 is connected to the reference ground, and the drain of the NMOS transistor M32 is connected to the reference ground. The drain of the PMOS transistor M33 is connected to the power supply voltage. The gate of the PMOS transistor M33 is connected to the gates of PMOS transistors M41, M34, and M42. The source of the PMOS transistor M33 is connected to the drain of the PMOS transistor M34. The source of the PMOS transistor M34 is connected to the drain of the NMOS transistor M35. The gate of the NMOS transistor M35 is connected to VA. The source of the NMOS transistor M35 is connected to the drains of the NMOS transistors M36 and M37. The gate of the NMOS transistor M36 is connected to the source of the amplifier, which serves as the output voltage P0 of the amplifier. VB is connected. The source of NMOS transistor M36 is connected to reference ground. The gate and drain of NMOS transistor M37 are connected to reference ground. The drain and gate of PMOS transistor M39 are connected to the power supply voltage. The source of PMOS transistor M39 is connected to the gate of PMOS transistor M38, the gate of PMOS transistor M40, and the source of PMOS transistor M41. The drain of PMOS transistor M38 is connected to the power supply voltage. The source of PMOS transistor M38 is connected to the drain of PMOS transistor M41. The drain of PMOS transistor M40 is connected to the power supply voltage. The source of PMOS transistor M40 is connected to the drain of PMOS transistor M42 and connected to the first terminal of capacitor C2. The sources of PMOS transistors M42 and M41 are respectively connected to the drain and source of PMOS transistor M43. The gate of PMOS transistor M43 is connected to input VINT1.The gate of NMOS transistor M44 is connected to the collector of transistor Q6. The source of NMOS transistor M44 is connected to the sources of PMOS transistors M43 and M41. The gate of NMOS transistor M45 is connected to the collector of transistor Q5. The source of NMOS transistor M45 is connected to the drain of PMOS transistors M43 and M42. The drain of NMOS transistor M44 is connected to the drain of NMOS transistor M45 and also connected to the drains of NMOS transistors M46, M48, and M49, and connected to the output port P1. The gate of NMOS transistor M46 is connected to VA. The source of NMOS transistor M46 is connected to the drain of NMOS transistor M47. The gate of NMOS transistor M47 is connected to VB. The source of NMOS transistor M47 is connected to reference ground. NMOS transistor M48... The gate and source of the NMOS transistor M49 are connected to the reference ground. The gate and source of the PMOS transistor M50 are connected to the power supply voltage. The source of the PMOS transistor M50 is connected to the gate of the PMOS transistor M51, the drain of the PMOS transistor M42, the drain of the PMOS transistor M43, and the source of the NMOS transistor M45. The drain of the PMOS transistor M51 is connected to the power supply voltage. The source of the PMOS transistor M51 is connected to the second terminal of capacitor C2 and the drain of the NMOS transistor M52. The source of NMOS transistor M53 is connected to the output port as output V0. The gate of NMOS transistor M52 is connected to VA. The gate of NMOS transistor M53 is also connected to VA. The source of NMOS transistor M52 and the drain of NMOS transistor M53 are connected and then connected to the drains of NMOS transistors M54 and M55. The gate of NMOS transistor M54 is connected to VB. The source of NMOS transistor M54 is connected to reference ground. The gate and source of NMOS transistor M55 are both connected to reference ground.

8. A bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The startup circuit includes: NMOS transistors M56, M57, M58, M59, M60, M61, M62, M63, and M64. The drain of NMOS transistor M56 is connected to the input power supply, the gate of NMOS transistor M56 is connected to the gate of NMOS transistor M60, and the source of NMOS transistor M56 is connected to the source of NMOS transistor M16 in the bandgap reference core circuit. The drain of NMOS transistor M57 is connected to the power supply voltage, and the source of NMOS transistor M57 is connected to NMOS transistor M58. The drains of NMOS transistors M57, M58, M59, and M60 are connected. The source of NMOS transistor M60 is connected to the drain of NMOS transistor M61 and the gate of NMOS transistor M62. The gate and drain of NMOS transistor M61 are connected. The source and gate of NMOS transistor M62 are connected and connected to the source of NMOS transistor M61 and the drain of NMOS transistor M63. The gate and drain of NMOS transistor M63 are connected. The source of NMOS transistor M63 is connected to the drain of NMOS transistor M64. The gate and drain of NMOS transistor M64 are connected. The source of NMOS transistor M64 is grounded.

9. A bandgap reference circuit for a high-precision ADC as described in claim 1, characterized in that, The emitter junction area ratio of transistors Q1 and Q3 to that of transistors Q2 and Q4 is 1:8.

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