System and method for mitigating clock signal drift

Abstract

A system comprising: processing circuitry; and a memory storing instructions that, based on execution by the processing circuitry, cause the processing circuitry to perform the following operations: determine a first value of a signal at a first clock edge of a clock signal; determine a second value of the signal at a second clock edge of the clock signal; generate an output value based on a calculation of at least the first value and the second value; determine a state of the clock signal based on a comparison between the output value and a reference value; and adjust the clock signal based on the state.

Description

Technical Field

[0001] One or more aspects of embodiments of the present disclosure relate to electronic circuits, and more specifically to systems and methods for mitigating clock signal drift in electronic circuits. Background Technology

[0002] Digital circuits are commonly found in devices such as microprocessors, memory systems, and communication interfaces. They are used to process, store, and transmit digital data, enabling complex functions such as computation, information storage, and signal processing. Digital circuits can utilize a clock signal calibrated to the data signal to provide a timing reference, which is used to coordinate and / or synchronize the operation of various components in the circuit. The effects of voltage and temperature variations in the circuit can cause the clock signal to drift and become out of phase with the data signal during operation.

[0003] The information disclosed in this background section is only intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0004] According to some embodiments of this disclosure, a method is provided, comprising: determining a first value of a signal at a first clock edge of a clock signal; determining a second value of the signal at a second clock edge of the clock signal; generating an output value based on calculations of at least the first value and the second value; determining a state of the clock signal based on a comparison between the output value and a reference value; and adjusting the clock signal based on the state.

[0005] In some embodiments, determining the state includes identifying the clock signal as leading relative to the signal, and wherein the adjustment of the clock signal includes increasing the delay of the clock signal.

[0006] In some embodiments, determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

[0007] In some embodiments, the calculation includes at least one of the sum of the first value and the second value, the average, or the mode.

[0008] In some embodiments, the sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, and wherein the reference value is based on the number of values ​​among the plurality of values.

[0009] In some embodiments, the reference value is based on the quantity of the value divided by 2.

[0010] In some embodiments, the clock signal includes a number of K phases, and the method further includes: determining one or more values ​​of the signal obtained at one or more Kth clock edges; determining one or more values ​​of the signal obtained at one or more (K+M)th clock edges, wherein M is equal to or greater than 1 and less than K; determining a first sum of the one or more values ​​of the signal obtained at the one or more Kth clock edges; determining a second sum of the one or more values ​​of the signal obtained at the one or more (K+M)th clock edges; comparing the first sum with the reference value; comparing the second sum with the reference value; determining a first state based on the comparison between the first sum and the reference value; determining a second state based on the comparison between the second sum and the reference value; and determining the state of the clock signal based at least in part on the first state and the second state.

[0011] In some embodiments, the first state is one of leading, lagging, or aligned relative to the signal, and the second state is one of leading, lagging, or aligned relative to the signal, and the method further includes determining the state of the clock signal as leading relative to the signal based on the majority of at least the first state and the second state being leading relative to the signal.

[0012] In some embodiments, the first state is one of leading, lagging, or aligning with the signal, and the second state is one of leading, lagging, or aligning with the signal, and the method further includes determining the state of the clock signal as lagging with respect to the signal based on at least the majority of the first and second states being lagging with respect to the signal.

[0013] In some embodiments, the reference value is calculated based on an assumption of jitter in the clock signal.

[0014] According to some embodiments of this disclosure, a system is provided, including: a processing circuit; and a memory storing instructions, the instructions being executed by the processing circuit to cause the processing circuit to perform: determining a first value of a signal at a first clock edge of a clock signal; determining a second value of the signal at a second clock edge of the clock signal; generating an output value based on calculations of at least the first value and the second value; determining a state of the clock signal based on a comparison between the output value and the reference value; and adjusting the clock signal based on the state.

[0015] In some embodiments, determining the state includes identifying the clock signal as leading relative to the signal, and wherein the adjustment of the clock signal includes increasing the delay of the clock signal.

[0016] In some embodiments, determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

[0017] In some embodiments, the calculation includes at least one of the sum of the first value and the second value, the average, or the mode.

[0018] In some embodiments, the sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, and wherein the reference value is based on the number of values ​​among the plurality of values.

[0019] In some embodiments, the reference value is based on the quantity of the value divided by 2.

[0020] In some embodiments, the clock signal includes a number of K phases, and the instructions, based on the processing circuitry, further cause the processing circuitry to perform: determining one or more values ​​of the signal acquired at one or more Kth clock edges; determining one or more values ​​of the signal acquired at one or more (K+M)th clock edges, wherein M is equal to or greater than 1 and less than K; determining a first sum of the one or more values ​​of the signal acquired at the one or more Kth clock edges; determining a second sum of the one or more values ​​of the signal acquired at the one or more (K+M)th clock edges; comparing the first sum with the reference value; comparing the second sum with the reference value; determining a first state based on the comparison between the first sum and the reference value; determining a second state based on the comparison between the second sum and the reference value; and determining the state of the clock signal based at least in part on the first state and the second state.

[0021] In some embodiments, the first state is one of leading, lagging, or aligned relative to the signal, and the second state is one of leading, lagging, or aligned relative to the signal, and the instruction is based on the processing circuitry further performing the following: determining the state of the clock signal as leading relative to the signal based on the majority of at least the first and second states being leading relative to the signal.

[0022] In some embodiments, the first state is one of leading, lagging, or aligned relative to the signal, and the second state is one of leading, lagging, or aligned relative to the signal, and the instruction is based on the processing circuitry further executing: determining the state of the clock signal as lagging relative to the signal based on at least the majority of the first and second states being lagging relative to the signal.

[0023] In some embodiments, the reference value is calculated based on an assumption of jitter in the clock signal.

[0024] These and other features, aspects, and advantages of embodiments of this disclosure will be more fully understood when considered in relation to the following detailed description, the appended claims, and the accompanying drawings. Of course, the actual scope of the invention is defined by the appended claims. Attached Figure Description

[0025] The following figures illustrate non-limiting and non-exhaustive embodiments of this example, wherein, unless otherwise stated, the same reference numerals refer to the same parts in the various views.

[0026] Figure 1 A block diagram of an electronic device according to one or more embodiments is depicted.

[0027] Figure 2 Depicting according to one or more embodiments Figure 1 A block diagram of the components of an electronic device.

[0028] Figure 3 A timing diagram of a clock signal in the presence of jitter is depicted according to one or more embodiments.

[0029] Figure 4 A timing diagram associated with a clock signal in half-rate mode, according to one or more embodiments, is depicted, the clock signal exhibiting a phase shift ahead of a tracking signal.

[0030] Figure 5 A timing diagram associated with a clock signal in half-rate mode, according to one or more embodiments, is depicted, the clock signal exhibiting a hysteresis phase shift relative to a tracking signal.

[0031] Figure 6 A schematic representation of an example trace according to one or more embodiments is depicted, wherein the trace signal value is sampled at the corresponding clock edge.

[0032] Figure 7 A table is depicted showing the expected sum of tracking signal values ​​for determining the state of a clock signal when the clock signal is in half-rate mode, according to one or more embodiments.

[0033] Figure 8 A timing diagram associated with a clock signal in a quarter-rate mode, according to one or more embodiments, is depicted, the clock signal exhibiting a phase shift ahead of a tracking signal.

[0034] Figure 9 A timing diagram associated with a clock signal in a quarter-rate mode, according to one or more embodiments, is depicted, the clock signal exhibiting a hysteresis phase shift relative to a tracking signal.

[0035] Figure 10 A schematic representation of an example trace according to one or more embodiments is depicted, wherein the trace signal value is sampled at the corresponding clock edge.

[0036] Figure 11 A table is depicted showing the expected sum of tracking signal values ​​for determining the state of a clock signal when the clock signal is in quarter-rate mode, according to one or more embodiments.

[0037] Figure 12 A flowchart is depicted for a process for detecting and mitigating clock signal drift according to one or more embodiments.

[0038] Figure 13 A flowchart is provided illustrating a process for detecting and mitigating clock signal drift in a multi-phase clock signal according to one or more embodiments.

[0039] Figure 14 A flowchart is depicted illustrating a process for detecting and mitigating clock signal drift in a four-phase clock signal in half-rate mode, according to one or more embodiments.

[0040] Figure 15 A flowchart is depicted illustrating a process for detecting and mitigating clock signal drift in a four-phase clock signal in a quarter-rate mode, according to one or more embodiments. Detailed Implementation

[0041] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, wherein the same reference numerals throughout denote the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are unnecessary for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description may not be repeated. Furthermore, in the drawings, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified for clarity.

[0042] Embodiments of this disclosure are described below with reference to block diagrams and flowcharts. Therefore, it should be understood that each block of the block diagrams and flowcharts can be implemented as a computer program product, a complete hardware embodiment, a combination of hardware and computer program products, and / or an apparatus, system, computing device, computing entity, etc., which execute instructions, operations, steps, and interchangeable similar terms (e.g., operable instructions, instructions for execution, program code, etc.) on a computer-readable storage medium. For example, code retrieval, loading, and execution can be performed sequentially, such that one instruction is retrieved, loaded, and executed at a time. In some example embodiments, retrieval, loading, and / or execution can be performed in parallel, such that multiple instructions are retrieved, loaded, and / or executed together. Therefore, such embodiments can produce machines specifically configured to perform the steps or operations specified in the block diagrams and flowcharts. Thus, the block diagrams and flowcharts support various combinations of embodiments for performing specified instructions, operations, or steps.

[0043] Furthermore, the features of the embodiments of this disclosure may be combined in part or in whole with one or more other features, and may operate in various ways, and the embodiments may be implemented independently of one or more other embodiments, or in combination with one or more other embodiments.

[0044] Clock signals are used in electronic circuits to provide a timing reference for coordinating and / or synchronizing the operation of various components within the circuit. Clock signals can be initially calibrated to be synchronized with data signals. However, during operation, clock signals may drift out of phase with data signals due to variations in the supply voltage (102) and temperature within the circuit, as well as other changes. For example, the data signal path and the clock signal path may be on different power supplies and thus experience different voltage-dependent characteristics, such as propagation delay, timing variations, and sensitivity to noise. Temperature variations across circuits and / or components can affect the behavior of semiconductor materials and cause changes in speed, thereby affecting timing.

[0045] Electronic circuits can also be susceptible to jitter, which can introduce unpredictable variations in signal timing. Besides phase shift, clock signals can also be affected by jitter. In some cases, the presence of jitter can obscure the observation of phase shift, thus complicating the accurate detection and compensation of phase drift.

[0046] Embodiments of this disclosure relate to systems, methods, and techniques for detecting and compensating for clock signal drift in the presence of potential jitter. The circuitry may include a data signal, a tracking signal, and a clock signal. The clock signal and tracking signal may be generated from the same clock source and initially calibrated to synchronize with the data signal. In some embodiments, the tracking signal path and the data signal path may share the same power supply and be relatively close to each other on the circuitry. Thus, when compared to circuitry where the tracking signal path and the data signal path have different power supplies and / or are relatively far apart, it can be assumed that the tracking signal and data signal remain synchronized, or are relatively closer to each other for synchronization. The tracking signal can be used as a representation of the timing of the data signal. The phase shift of the clock signal relative to the data signal can be determined by determining the phase shift between the clock signal and the tracking signal.

[0047] In some embodiments, the value of the tracking signal (e.g., 0 or 1) at the clock edge of the clock signal is used to determine the clock signal state. The clock signal state can indicate whether the clock signal leads, lags, or is aligned with the tracking signal. For example, for one or more samples, the tracking signal may have a first value at a first clock edge, a second value at a second clock edge, and so on.

[0048] In some embodiments, a sum of one or more tracking signal values ​​is determined and compared to a reference value to determine the clock signal state. The reference value may be based on the number of sampled tracking signal values ​​included in the sum. In an example where each sampled tracking signal value can be 0 or 1, the reference value may be the number of samples in the sum divided by two. In some embodiments, the sum of tracking signal values ​​equal to the reference value is used as an indicator that the clock signal can be aligned with the tracking signal. In some embodiments, the sum of tracking signal values ​​greater than the reference value is used as an indicator that the clock signal may be lagging, and the sum of tracking signal values ​​less than the reference value is used as an indicator that the clock signal may be leading. In some embodiments, the sum of tracking signal values ​​greater than the reference value is used as an indicator that the clock signal may be leading, and the sum of tracking signal values ​​less than the reference value is used as an indicator that the clock signal may be lagging.

[0049] In some embodiments, the clock signal is a multi-phase clock signal that generates multiple clock signals with different phase offsets (e.g., a 90° or 180° phase difference). The multiple clock signals can be used to determine whether the overall clock signal is ahead, behind, or aligned with the tracking signal. The value of the tracking signal at the corresponding clock edge of the multiple clock signals can be used to determine the clock signal state (e.g., whether the clock signal is ahead, behind, or aligned with the tracking signal). Individual clock signals of the multi-phase clock signal can have ahead, behind, or aligned states.

[0050] In some embodiments, the overall determination of the clock signal state is based on a majority poll of two or more (e.g., all) individual clock signals. For example, if a majority of the multiphase clock signals exhibit a leading state, the clock signal can be determined to be leading. If there is no majority (e.g., an equal number of clock signals have leading and lagging states), the clock signal can be determined to be overall aligned.

[0051] The clock signal can be adjusted based on whether it is determined to lead or lag the tracking signal. For example, if the clock signal leads the tracking signal, the clock signal delay can be increased, and if the clock signal lags the tracking signal, the clock signal delay can be decreased. In some examples, the clock signal delay can be adjusted by a preset unit amount. Continuous feedback and adjustment of the clock signal can occur during runtime, at a preset frequency, or based on one or more triggers or conditions.

[0052] Figure 1 A block diagram is depicted of an electronic device 100 with clock signal shift mitigation according to one or more embodiments. The electronic device 100 may include one or more power supplies 102, one or more data inputs 104, a clock source 106, and one or more electronic components 108. The one or more electronic components 108 may include one or more dies, integrated circuits, printed circuit boards, individual circuit components, and other forms of circuitry.

[0053] In some embodiments, one or more power sources (also referred to as voltage sources) 102 provide a power supply voltage or a positive voltage rail in the electronic circuitry of the electronic device 100. One or more power sources 102 may power one or more of the clock source 106 and / or electronic components 108. For example, one or more power sources 102 may supply power for controlling logic gates, enabling transistor switches, signal amplification, etc. In some embodiments, different voltage sources 102 may power different components of the electronic components 108.

[0054] One or more data inputs 104 may receive one or more data signals generated at electronic device 100 or received from another device. Clock source 106 may include a crystal oscillator, clock generator IC, phase-locked loop (PLL), external clock source from communication interface, on-chip RC oscillator, or internal processor / FPGA clock generator, etc.

[0055] Figure 2 Depicting according to one or more embodiments Figure 1 A block diagram of an example of electronic component 108. In some embodiments, electronic component 108 includes a first die (DIE0) 202 and a second die (DIE1) 204 connected via one or more interconnects 220. In some embodiments, the first die 202 serves as a transmitter-side die, and the second die 204 serves as a receiver-side die. The first die 202 may include a digital block 206, which includes a transmit side of an active signal (Tx VALID) 208, a data signal (Tx DATA) 210, a clock tracking signal (Tx TRACK, also referred to as a tracking signal) 212, and a clock signal (Tx CK) 214. In some embodiments, the active signal 208, the data signal 210, the tracking signal 212, and the clock signal 214 are fed into a corresponding serializer 216 and a corresponding driver 218, and transmitted to the second die 204 via a corresponding interconnect 220.

[0056] In some embodiments, the first die 202 includes a phase-locked loop (PLL) 232, a phase interpolator 230, a frequency divider (DIV) 234, and a first clock signal delay controller (delay controller 1) 228. The PLL 232 can receive a reference signal from the clock source 106 and generate an output clock signal whose phase can be fixed relative to the phase of the reference signal. The PLL 232 can continuously or periodically (e.g., on a regular or irregular basis) adjust the phase of the generated clock signal to match the reference clock signal.

[0057] In some embodiments, the phase interpolator 230 generates multiple clock phases based on a clock signal generated by the PLL 232. The phase interpolator 230 can generate multi-phase clock signals offset by a specified amount (e.g., 90°, 180°). For example, the phase interpolator 230 can generate four equally spaced clock phases (also referred to as a four-phase clock signal) from a clock signal generated by the PLL 232. The four-phase clock signal can also be understood as having four separate clock signals offset by equally spaced clock phases.

[0058] In some embodiments, the frequency divider 234 reduces the frequency of the clock signal by a certain factor. This frequency reduction can be used to create a slower clock signal for a subsystem or to provide the clock signal required for timing-critical tasks at different stages of the circuit. In some embodiments, the first clock delay controller 228 is used to adjust the timing of the clock signal by introducing a delay or delay unit. Adjusting the timing of the clock signal can help establish or maintain synchronization between the clock signal 214 and the data signal 210. In some embodiments, the tracking signal 212 is a copy of the clock signal 214 and is also synchronized with the data signal 210.

[0059] In some embodiments, the second die 204 may receive one or more of a valid signal 208, a data signal 210, a tracking signal 212, and a clock signal 214. The second die 204 may feed the received signals 208-214 to corresponding analog front-end (AFE) amplifiers 222. In some embodiments, the valid signal 208, data signal 210, and tracking signal 212 are fed to corresponding deserializers 224 and received at the digital block 226 of the second die 204. Figure 2 In the embodiment depicted, the data signal received at the digital block 226 of the second die 204 is represented as data signal (RxDATA) 246, the tracking signal received at the digital block 226 of the second die 204 is represented as tracking signal (Rx TRACK) 244, and the clock signal received at the digital block 226 of the second die 204 is represented as clock signal 242.

[0060] In some embodiments, the AFE amplifier 222 and deserializer 224 for the valid signal, data signal, and track signal share a voltage source (not shown). In some embodiments, the paths of the track signal 244 and data signal 246 may also be relatively closer to each other than the path of the clock signal 242. The track signal 244 and data signal 246 may be assumed to be synchronized, or relatively closer to synchronized than the clock signal 242 and data signal 246. In some embodiments, the track signal 244 may be used as a representation of the timing of the data signal 246. In some cases, although the clock signal 214 and track signal 212 may be generated from the same source and both are initially calibrated to be synchronized with the data signal 210 at the first die 202, the clock signal 242 may lose synchronization relative to the data signal 246 when it reaches the digital block 226 of the second die 204. The phase shift of the clock signal 242 relative to the data signal 246 can be determined by identifying the phase shift between the clock signal 242 and the track signal 244.

[0061] In some embodiments, the second die 204 includes a tracking controller 236 configured to receive a tracking signal 244 and a clock signal 242 as inputs at the second die 204, and to determine a command (hereinafter referred to as a delay control command) for delaying or advancing the clock signal 242 at the second die 204. In some embodiments, the second die 204 may include a phase generator or a delay controller 238 configured to receive the delay control command from the tracking controller 236 and adjust the clock signal 242 accordingly. For example, if the tracking controller 236 determines that the clock signal 242 is ahead of the tracking signal 244, the delay controller 238 may delay the clock signal 242 by an amount, such as one or more unit intervals. If the tracking controller 236 determines that the clock signal 242 is behind the tracking signal 244, the delay controller 238 may advance the clock signal 242 by an amount. Continuous or periodic feedback and adjustment of the clock signal 242 may occur during runtime, at a preset frequency, or based on one or more triggers or conditions.

[0062] In some embodiments, the tracking controller 236 includes one or more settings and / or parameters for determining the state of a clock signal and / or controlling the delay controller 238. In some embodiments, an enable signal fed to the tracking controller 236 allows the tracking controller 236 to be turned on or off. One or more parameters of the tracking controller 236 may include the number of samples (N) of the tracking signal acquired and utilized in determining the delay control command (also referred to as the tracking duration). In some embodiments, the tracking controller 236 may receive such settings or parameters, such as the enable signal and the tracking duration, from the processor 248.

[0063] Figure 3A timing diagram of a clock signal 242 in the presence of jitter is depicted according to one or more embodiments. The phase shift of the clock signal 242 relative to the data signal 246 can be determined by determining the phase shift between the clock signal 242 and the tracking signal 244. In some embodiments, a sampled value 302 (e.g., 0 or 1) of the tracking signal 244 at a clock edge 304 of the clock signal 242 is used to determine the clock signal state. The clock signal state can indicate whether the clock signal 242 is leading, lagging, or aligned with the tracking signal 244. For example, at clock edge 304, the sampled value 302 of the tracking signal 244 is 0. Clock edge 304 also occurs at the expected time 308. However, in the presence of jitter, the clock edge may occur unexpectedly earlier or later than the expected time 310 anywhere within a representative clock edge window 306. Window 306 is provided for illustrative purposes and may not exist for discrete time windows where jitter may occur. Jitter can also occur unpredictably at any clock edge, which may cause the sampled value 302 of the tracking signal 244 at the clock edge to be an inaccurate representation of the phase shift of the clock signal 242.

[0064] Figure 4 A timing diagram 400, according to one or more embodiments, is depicted in half-rate (HR) mode associated with clock signal 242, exhibiting a lead phase shift relative to tracking signal 244, and Figure 5 A timing diagram 500 associated with clock signal 242 in half-rate mode according to one or more embodiments is depicted, exhibiting a hysteresis phase shift relative to tracking signal 244. In some embodiments, the tracking signal may be sampled at one or more clock edges 410 of clock signal 242, and the sum of the sampled values ​​302 of the tracking signal may be used as an indicator of the state of clock signal 242 (e.g., whether clock signal 242 is leading, lagging, or aligned with tracking signal 244). For example, clock edge 410a leads tracking signal edge 244a, and the sampled value 302 of tracking signal 244 at clock edge 410a is low and has a value of 0. Similarly, the sampled value 302 of tracking signal 244 at clock edge 410c is 0. The tracking signal 244 at clock edges 410b and 410d is high and has a value of 1.

[0065] In some embodiments, the sum of the sampled values ​​302 of the tracking signal can be compared with a reference value to determine whether the state of the clock signal 242 is leading, lagging, or aligned. In some embodiments, the sampled values ​​302 of the tracking signal can be associated with one or more groups (also referred to as tracking).

[0066] Figure 6Schematic representations of example traces 502, 504, 506, and 508 are depicted, where the trace signal is sampled at the corresponding clock edge (also called a bit). Figure 6 In the example, the tracking signal is sampled at four clock edges, although the embodiment is not limited thereto. For example, the first track 502 may include sampled values ​​302 of the tracking signal at the first, fifth, ninth, and thirteenth clock edges (or Bit [0], Bit [4], Bit [8], Bit

[12] ) of the clock signal 242. The second track 504 may include sampled values ​​302 of the tracking signal at the second, sixth, tenth, and fourteenth clock edges (or Bit [1], Bit [5], Bit [9], Bit

[13] ) of the clock signal 242. The third track 506 may include sampled values ​​302 of the tracking signal at the third, seventh, eleventh, and fifteenth clock edges (or Bit [2], Bit [6], Bit

[10] , Bit

[14] ) of the clock signal 242. The fourth track 508 may include sampled values ​​302 of the track signal at the fourth, eighth, twelfth, and sixteenth clock edges (or Bit [3], Bit [7], Bit

[11] , Bit

[15] ) of the clock signal 242. In some embodiments, there may be fewer or more than four tracks and fewer or more than four samples for each track.

[0067] The sum of sampled values ​​302 of the tracking signals of a single track (e.g., 502, 504, 506, 508) acquired at the clock edge can be used to determine the state of the clock signal, such as the clock edge sampled by a single track indicating a leading, lagging, or aligned clock signal state relative to the tracking signal 244. The state of the clock signal provided by a single track can be determined by comparing the sum of the sampled values ​​302 of the tracking signals with a reference value.

[0068] Figure 7 Depicting Figure 6A table of expected sums 514-520 of the track signal values ​​identified in tracking 502-508 is used to determine a first clock signal state 522a-522c (collectively referred to as 522) when the clock signal does not encounter jitter, and to determine a second clock signal state 524a-524c (collectively referred to as 524) when the clock signal experiences jitter. In some embodiments, clock signal states 522 and 524 are calculated based on the sum of the sampled values ​​302 of the corresponding track signals. In some embodiments, the reference value used to compare with the sum of track values ​​to determine the state of the clock signal is based on the number (N) of samples (track signal values) included in the sum. The number of samples included in the sum is based on the tracking duration, which may be set, for example, by the processor 248 and provided as an input parameter to the tracking controller 236. Figure 5 In the example, where there are four samples in a single track (e.g., 502, 504, 506, 508), the value of N is four.

[0069] Taking tracking 502 and tracking 506 as examples, assuming that when tracking 502 is sampled at Bit [0], Bit [4], Bit [8], and Bit

[12] , and when tracking 506 is sampled at Bit [2], Bit [6], Bit

[10] , and Bit

[14] , the tracking signal will have a value of 1. Then, when the clock signal lags without any jitter, the sum of the tracking values ​​514 and 518 equals the reference value (N). For tracking 504 and 508, when the clock signal leads without any jitter, the sum of the tracking values ​​516 and 520 equals the reference value (N).

[0070] In some embodiments, the sum of the corresponding tracking values ​​of N / 2 can be used as an indication of clock signal alignment relative to the tracking signal in the presence of potential jitter. For example, when the clock signal is aligned with the tracking signal but jitter occurs, the sampled tracking signal can randomly take values ​​of 0 or 1. The average of the possible tracking values ​​at the corresponding clock edges is calculated for N samples, thereby producing a reference value of N / 2 in the presence of potential jitter.

[0071] In some embodiments, in the presence of potential jitter, the sum of the first tracking values ​​514 being less than the calculated average reference value (N / 2) can be used as an indication that the clock signal is ahead of the tracking signal. In some embodiments, in the presence of potential jitter, the sum of the first tracking values ​​514 being greater than the calculated average reference value (N / 2) can be used as an indication that the clock signal is behind the tracking signal.

[0072] In some embodiments, in the presence of potential jitter, the sum of the second tracking values ​​516 being greater than the calculated average reference value (N / 2) can be used as an indication that the clock signal is ahead of the tracking signal. In some embodiments, in the presence of potential jitter, the sum of the second tracking values ​​516 being less than the calculated average reference value (N / 2) can be used as an indication that the clock signal is behind the tracking signal.

[0073] In some embodiments, in the presence of potential jitter, the sum of the third tracking values ​​518 being less than the calculated average reference value (N / 2) can be used as an indication that the clock signal is ahead of the tracking signal. In some embodiments, in the presence of potential jitter, the sum of the third tracking values ​​518 being greater than the calculated average reference value (N / 2) can be used as an indication that the clock signal is behind the tracking signal.

[0074] In some embodiments, in the presence of potential jitter, the sum of the fourth tracking values ​​520 being greater than the calculated average reference value (N / 2) can be used as an indication that the clock signal is ahead of the tracking signal. In some embodiments, in the presence of potential jitter, the sum of the fourth tracking values ​​520 being less than the calculated average reference value (N / 2) can be used as an indication that the clock signal is behind the tracking signal.

[0075] exist Figure 6 In the example, there are four samples in a single track (e.g., 502, 504, 506, 508). Therefore, in the presence of potential jitter, the reference value is N / 2 = 2. In some embodiments, the reference value can be specified based on a different function. In some embodiments, the reference value is specified based on a value associated with the alignment state, and whether the tracking is ahead or behind is based on whether the sum is greater than or less than the value associated with the alignment state.

[0076] In some embodiments, the overall determination of the clock signal state is based on a majority polling of two or more (e.g., all) of individual tracks (e.g., 502, 504, 506, 508). For example, if a majority of individual tracks (e.g., 502, 504, 506, 508) indicates a leading state, the clock signal can be determined to be leading. If no majority exists (e.g., an equal number of individual tracks indicate both leading and lagging states), then the clock signal 242 can be determined to be overall aligned.

[0077] The clock signal 242 can be adjusted based on whether it is determined to lead or lag the tracking signal 244. For example, if the clock signal 242 leads the tracking signal 244, the tracking controller 236 can send a command to the delay controller 238 to add an additional delay to the clock signal 242. If the clock signal 242 lags the tracking signal 244, the tracking controller 236 can send a command to the delay controller 238 to advance the clock signal 242. The clock signal 242 can be delayed or advanced by one or more predetermined unit intervals or a customized amount.

[0078] refer to Figure 4 and Figure 5 In some embodiments, clock signal 242 is a four-phase clock signal and includes a first-phase clock signal 402, a second-phase clock signal 404, a third-phase clock signal 406, and a fourth-phase clock signal 408. The second-phase clock signal 404 can be offset by 90° from the first-phase clock signal 402. The third-phase clock signal 406 can be offset by 180° from the first-phase clock signal 402. The fourth-phase clock signal 408 can be offset by 270° from the first-phase clock signal 402. The four tracks 502, 504, 506, and 508 can be based on these four clock signals. In some embodiments, the first clock edge of the first-phase clock signal 402 can correspond to the first clock edge of clock signal 242, the first clock edge of the second-phase clock signal 404 can correspond to the second clock edge of clock signal 242, the first clock edge of the third-phase clock signal 406 can correspond to the third clock edge of clock signal 242, and the first clock edge of the fourth-phase clock signal 408 can correspond to the fourth clock edge of clock signal 242.

[0079] Figure 8 A timing diagram 800 is depicted in quarter-rate mode (QR) associated with clock signal 242 according to one or more embodiments, exhibiting a phase shift ahead of tracking signal 244. Figure 9 A timing diagram 900, depicting a clock signal 242 in a quarter-rate mode according to one or more embodiments, is shown, exhibiting a hysteresis phase shift relative to a tracking signal 244. In the quarter-rate mode, the clock signal 242 and the tracking signal 244 have half the rate or frequency of the data signal digit 246. Figure 10 A schematic representation of four examples of tracking 502, 504, 506, and 508 is depicted, where the tracking signal is sampled at the corresponding clock edge (also called a bit).

[0080] Figure 11 Depicting in Figure 10The table of expected sums 514-520 of the tracking signal values ​​identified in tracking 502-508 is used to determine a first clock signal state 522a-522c (collectively referred to as 522) when the clock signal is in quarter-rate mode, provided that the clock signal does not encounter jitter, and a second clock signal state 524a-524c (collectively referred to as 524) when the clock signal experiences jitter. In some embodiments, this technique is similar to that described above. Figure 7 The described technique involves a clock signal in half-rate mode. However, in some embodiments, in quarter-rate mode, the lead state 522b and lag state 522c of a jitter-free second track 504 may be indistinguishable based on the sum 516 of the track signal values. In some embodiments, in quarter-rate mode, the lead state 522b and lag state 522c of a jitter-free fourth track 508 may be indistinguishable based on the sum 520 of the track signal values. In some embodiments, these values ​​are not used to evaluate the clock signal state when the clock signal is in quarter-rate mode.

[0081] Figure 12 A flowchart is depicted for a process 1200 for detecting and mitigating clock signal shift according to one or more embodiments. Process 1200 begins, and at operation 1202, the tracking controller 236 determines a first value of a signal (e.g., tracking signal 244) at a first clock edge of clock signal 242. At operation 1204, the tracking controller 236 determines a second value of the signal (e.g., tracking signal 244) at a second clock edge of clock signal 242.

[0082] At operation 1206, the tracking controller 236 generates an output value based on calculations of at least the first and second values. In some embodiments, the output value is the sum of the first and second values. In some embodiments, the output value is the average of the first and second values. In some embodiments, the output value is the mode of the first and second values.

[0083] At operation 1208, the tracking controller 236 determines the state of the clock signal based on a comparison between the output value and a reference value. The reference value may be based on the number of sampled tracking signal values ​​included in the output value. In an example where each sampled tracking signal value can be 0 or 1, the reference value may be the number of samples in the output value divided by two. In some embodiments, the output value of the tracking signal value equal to the reference value is used as an indicator that the clock signal can be aligned with the tracking signal. In some embodiments, the output value of the tracking signal value greater than the reference value is used as an indicator that the clock signal may be lagging, and the output value of the tracking signal value less than the reference value is used as an indicator that the clock signal may be leading. In some embodiments, the output value of the tracking signal value greater than the reference value is used as an indicator that the clock signal may be leading, and the output value of the tracking signal value less than the reference value is used as an indicator that the clock signal may be lagging.

[0084] At operation 1210, the tracking controller 236 can adjust the clock signal based on a defined state. For example, the tracking controller 236 can send a command to the delay controller 238 to delay the clock signal based on a state where the clock signal leads the tracking signal. The tracking controller 236 can also send a command to the delay controller 238 to advance the clock signal based on a state where the clock signal lags the tracking signal.

[0085] Figure 13 A flowchart is depicted for a process 1300 for detecting and mitigating clock signal drift of a multi-phase clock signal according to one or more embodiments.

[0086] Process 1300 begins, and at operation 1302, the tracking controller 236 can determine one or more values ​​of a signal (e.g., a tracking signal) acquired at one or more Kth clock edges of a clock signal having K phases. At operation 1304, the tracking controller 236 can determine one or more values ​​of a signal acquired at one or more K+Mth clock edges, where M is equal to or greater than 1 and less than K.

[0087] At operation 1306, the tracking controller 236 can determine a first sum of one or more values ​​of the signal acquired at one or more K-th clock edges. At operation 1308, the tracking controller 236 can determine a second sum of one or more values ​​of the signal acquired at one or more K+M-th clock edges.

[0088] At operation 1310, the tracking controller 236 can compare the first sum with a reference value. At operation 1312, the tracking controller 236 can compare the second sum with a reference value.

[0089] At operation 1314, the tracking controller 236 can determine a first state based on a comparison between a first sum and a reference value. The first state can be that the first sum indicates that the clock signal is ahead, behind, or aligned with the tracking signal. At operation 1316, the tracking controller 236 can determine a second state based on a comparison between a second sum and a reference value. The second state can be that the second sum indicates that the clock signal is ahead, behind, or aligned with the tracking signal.

[0090] At operation 1318, the tracking controller 236 can determine the state of the clock signal based at least on the first state and the second state. In some embodiments, the state of the clock signal can be that the clock signal is ahead of the tracking signal based on at least a majority of the first and second states. In some embodiments, the state of the clock signal can be that the clock signal is lagging behind the tracking signal based on at least a majority of the first and second states. Otherwise (e.g., if no majority exists), the state of the clock signal can be that the clock signal is aligned with the tracking signal.

[0091] At operation 1320, the tracking controller 236 can adjust the clock signal based on the state. For example, the tracking controller 236 can send a command to the delay controller 238 to delay the clock signal based on a state where the clock signal leads the tracking signal. The tracking controller 236 can also send a command to the delay controller 238 to advance the clock signal based on a state where the clock signal lags the tracking signal.

[0092] Figure 14 A flowchart depicts a process 1400 for detecting and mitigating clock signal drift in a four-phase clock signal in half-rate mode, according to one or more embodiments. Process 1400 begins, and at operation 1402, the tracking controller 236 determines a first sum of N values ​​of the tracking signal acquired at N clock edges of a first clock signal of the four-phase clock signal. In some embodiments, a hysteresis counter is set to zero, and a lead counter is set to zero. At operation 1404, the tracking controller 236 determines whether the first sum is greater than or equal to a reference value N / 2. If the first sum is greater than or equal to the reference value N / 2, process 1400 proceeds to operation 1406. If the first sum is not greater than or equal to N / 2, process 1400 proceeds to operation 1408. At operation 1406, the hysteresis counter is incremented by 1. At operation 1408, the lead counter is incremented by 1.

[0093] At operation 1410, the tracking controller 236 determines a second sum of the N values ​​of the tracking signal acquired at the N clock edges of the second clock signal of the four-phase clock signal. At operation 1412, the tracking controller 236 determines whether the second sum is greater than or equal to a reference value N / 2. If the second sum is greater than or equal to the reference value N / 2, process 1400 proceeds to operation 1416. If the second sum is not greater than or equal to N / 2, process 1400 proceeds to operation 1414. At operation 1414, the hysteresis counter is incremented by 1. At operation 1416, the lead counter is incremented by 1.

[0094] At operation 1418, the tracking controller 236 determines a third sum of the N values ​​of the tracking signal acquired at the N clock edges of the third clock signal of the four-phase clock signal. At operation 1420, the tracking controller 236 determines whether the third sum is greater than or equal to a reference value N / 2. If the third sum is greater than or equal to the reference value N / 2, process 1400 proceeds to operation 1422. If the third sum is not greater than or equal to N / 2, process 1400 proceeds to operation 1424. At operation 1422, the hysteresis counter is incremented by 1. At operation 1424, the lead counter is incremented by 1.

[0095] At operation 1426, the tracking controller 236 determines the fourth sum of the N values ​​of the tracking signal acquired at the N clock edges of the fourth clock signal of the four-phase clock signal. At operation 1428, the tracking controller 236 determines whether the fourth sum is greater than a reference value N / 2. If the fourth sum is greater than or equal to the reference value N / 2, process 1400 proceeds to operation 1432. If the fourth sum is not greater than or equal to N / 2, process 1400 proceeds to operation 1430. At operation 1430, the hysteresis counter is incremented by 1. At operation 1432, the lead counter is incremented by 1.

[0096] In some embodiments, at operation 1434, the tracking controller 236 determines whether the lead counter is greater than 2. If the lead counter is greater than 2, process 1400 proceeds to operation 1436, and the tracking controller 236 delays the clock signal 242. If the lead counter is not greater than 2, process 1400 proceeds to operation 1438, where the tracking controller 236 determines whether the lag counter is greater than 2. If the lag counter is greater than 2, process 1400 proceeds to operation 1440, and the tracking controller 236 advances the clock signal 242. If the lag counter is not greater than 2, process 1400 ends.

[0097] Figure 15 A flowchart depicts a process 1500 for detecting and mitigating clock signal drift in a four-phase clock signal in a quarter-rate mode, according to one or more embodiments. Figure 7As shown, in quarter-rate mode, there is no difference between the sum of the second tracking values ​​(516) for the leading and lagging states, and there is also no difference between the sum of the fourth tracking values ​​(520) for the leading and lagging states. These values ​​are not considered when evaluating the overall state of the clock signal.

[0098] Process 1500 begins, and at operation 1502, the tracking controller 236 determines a first sum of N values ​​of the tracking signal acquired at the N clock edges of the first clock signal of the four-phase clock signal. In some embodiments, the hysteresis counter is set to zero, and the lead counter is set to zero. At operation 1504, the tracking controller 236 determines whether the first sum is greater than or equal to a reference value N / 2. If the first sum is greater than or equal to the reference value N / 2, process 1500 proceeds to operation 1506. If the first sum is not greater than or equal to N / 2, process 1500 proceeds to operation 1508. At operation 1506, the hysteresis counter is incremented by 1. At operation 1508, the lead counter is incremented by 1.

[0099] At operation 1510, the tracking controller 236 determines a third sum of the N values ​​of the tracking signal acquired at the N clock edges of the third clock signal of the four-phase clock signal. At operation 1512, the tracking controller 236 determines whether the third sum is greater than or equal to the reference value N / 2. If the third sum is greater than or equal to the reference value N / 2, process 1500 proceeds to operation 1516. If the third sum is not greater than or equal to N / 2, process 1500 proceeds to operation 1514. At operation 1514, the hysteresis counter is incremented by 1. At operation 1516, the lead counter is incremented by 1.

[0100] In some embodiments, at operation 1518, the tracking controller 236 determines whether a lead counter is greater than 1. If the lead counter is greater than 1, process 1500 proceeds to operation 1520, and the tracking controller 236 delays the clock signal 242. If the lead counter is not greater than 1, process 1500 proceeds to operation 1522, where the tracking controller 236 determines whether a lag counter is greater than 1. If the lag counter is greater than 1, process 1500 proceeds to operation 1524, and the tracking controller 236 advances the clock signal 242. If the lag counter is not greater than 1, process 1500 terminates.

[0101] Embodiments of this disclosure improve the function of electronic systems, at least by enabling more accurate detection and compensation of phase drift in clock signals within circuitry in the presence of jitter. Without the technology of this disclosure, jitter may obscure the presence of phase drift or incorrectly indicate it. The technology of this disclosure makes the observation of phase drift more robust relative to the presence of jitter in the clock signal.

[0102] One or more embodiments of this disclosure can be implemented in one or more processors. The term processor can refer to one or more processors and / or one or more processing cores. One or more processors can be hosted in a single device or distributed across multiple devices (e.g., on a cloud system). Processors can include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable gate arrays (FPGAs). In a processor, as used herein, each function is performed by hardware configured (i.e., hardwired) to perform that function, or by more general-purpose hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium (e.g., memory). Processors can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processors can include other processing circuitry; for example, processing circuitry can include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

[0103] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of the inventive concept, the first element, component, region, layer, or portion discussed herein may be referred to as the second element, component, region, layer, or portion.

[0104] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. Furthermore, unless explicitly stated otherwise, the embodiments described herein are not mutually exclusive. Aspects of the embodiments described herein can be combined in several implementations.

[0105] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, intended to explain the inherent biases of measured or calculated values ​​that can be recognized by one of ordinary skill in the art.

[0106] As used herein, the singular forms “a” and “an” are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when following a list of elements, rather than a single element in that list. Furthermore, when describing embodiments of the inventive concept, the use of “may” means “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” can be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0107] Although exemplary embodiments of systems and methods for mitigating clock signal shifts have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it is to be understood that systems and methods for mitigating clock signal shifts constructed in accordance with the principles of this disclosure may be implemented in ways other than those specifically described herein. This disclosure is also defined in the following claims and their equivalents.

[0108] Systems and methods for mitigating clock signal drift may include one or more combinations of the features set forth in the following statements.

[0109] Statement 1: A method comprising: determining a first value of a signal at a first clock edge of the clock signal; determining a second value of the signal at a second clock edge of the clock signal; generating an output value based on a calculation of at least the first value and the second value; determining a state of the clock signal based on a comparison between the output value and the reference value; and adjusting the clock signal based on the state.

[0110] Statement 2: In the method of Statement 1, determining the state includes identifying the clock signal as leading relative to the signal, and adjusting the clock signal includes increasing the delay of the clock signal.

[0111] Statement 3: In the method according to any one of Statement 1 or 2, wherein determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

[0112] Statement 4: In any of the methods in statements 1-3, the calculation includes at least one of the sum, average, or mode of the first and second values.

[0113] Statement 5: In any of the methods in statements 1-4, the sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, and the reference value is based on the number of values ​​among the plurality of values.

[0114] Statement 6: In any of the methods in statements 1-5, the reference value is based on the quantity of the value divided by 2.

[0115] Statement 7: In the method according to any one of Statements 1-6, wherein the clock signal comprises a number K phases, and the method further comprises: determining one or more values ​​of the signal obtained at one or more Kth clock edges; determining one or more values ​​of the signal obtained at one or more (K+M)th clock edges, wherein M is equal to or greater than 1 and less than K; determining a first sum of the one or more values ​​of the signal obtained at the one or more Kth clock edges; determining a second sum of the one or more values ​​of the signal obtained at the one or more (K+M)th clock edges; comparing the first sum with the reference value; comparing the second sum with the reference value; determining a first state based on the comparison between the first sum and the reference value; determining a second state based on the comparison between the second sum and the reference value; and determining the state of the clock signal based at least in part on the first state and the second state.

[0116] Statement 8: In any of the methods in Statements 1-7, wherein the first state is one of leading, lagging, or aligned relative to the signal, and wherein the second state is one of leading, lagging, or aligned relative to the signal, and wherein the method further comprises: determining the state of the clock signal as leading relative to the signal based on the majority of at least the first state and the second state being leading relative to the signal.

[0117] Statement 9: In any of the methods in Statements 1-8, wherein the first state is one of leading, lagging, or aligned relative to the signal, and wherein the second state is one of leading, lagging, or aligned relative to the signal, and wherein the method further comprises: determining the state of the clock signal as lagging relative to the signal based on at least the majority of the first and second states being lagging relative to the signal.

[0118] Statement 10: In any of the methods in Statements 1-9, the reference value is calculated based on an assumption of jitter in the clock signal.

[0119] Statement 11: A system comprising:

[0120] A processing circuit; and a memory storing instructions, the instructions being executed by the processing circuit to: determine a first value of a signal at a first clock edge of a clock signal; determine a second value of the signal at a second clock edge of the clock signal; generate an output value based on calculations of at least the first and second values; determine a state of the clock signal based on a comparison between the output value and a reference value; and adjust the clock signal based on the state.

[0121] Statement 12: In the system according to Statement 11, wherein determining the state includes identifying the clock signal as leading relative to the signal, and wherein the adjustment of the clock signal includes increasing the delay of the clock signal.

[0122] Statement 13: In the system according to Statement 11 or 12, wherein determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

[0123] Statement 14: In the system according to any one of statements 11-13, wherein the calculation includes at least one of the sum, average or mode of the first value and the second value.

[0124] Statement 15: In any of the statements 11-14, the sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, and the reference value is based on the number of values ​​among the plurality of values.

[0125] Statement 16: In any of the statements 11-15, the reference value is based on the quantity of the value divided by 2.

[0126] Statement 17: In a system of any one of Statements 11-16, wherein the clock signal comprises a number of K phases, and the instruction, based on execution by the processing circuitry, further causes the processing circuitry to perform: determining one or more values ​​of the signal acquired at one or more K-th clock edges; determining one or more values ​​of the signal acquired at one or more K+M-th clock edges, wherein M is equal to or greater than 1 and less than K; determining a first sum of the one or more values ​​of the signal acquired at the one or more K-th clock edges; determining a second sum of the one or more values ​​of the signal acquired at the one or more K+M-th clock edges; comparing the first sum with the reference value; comparing the second sum with the reference value; determining a first state based on the comparison between the first sum and the reference value; determining a second state based on the comparison between the second sum and the reference value; and determining the state of the clock signal based at least in part on the first state and the second state.

[0127] Statement 18: In a system of any of Statements 11-17, wherein the first state is one of leading, lagging, or aligned relative to the signal, and wherein the second state is one of leading, lagging, or aligned relative to the signal, and wherein the instruction, based on being run by the processing circuitry, further causes the processing circuitry to perform: determining the state of the clock signal as leading relative to the signal based on at least the majority of the first and second states being leading relative to the signal.

[0128] Statement 19: In a system of any one of Statements 11-18, wherein the first state is one of leading, lagging, or aligned relative to the signal, and wherein the second state is one of leading, lagging, or aligned relative to the signal, and wherein the instruction, based on being run by the processing circuitry, further causes the processing circuitry to perform: determining the state of the clock signal as lagging relative to the signal based on at least the majority of the first and second states being lagging relative to the signal.

[0129] Statement 20: In any of the statements 11-19, the reference value is calculated based on the assumption of jitter in the clock signal.

Claims

1. A method for mitigating clock signal drift, comprising: Determine the first value of the signal at the first clock edge of the clock signal; Determine the second value of the signal at the second clock edge of the clock signal; An output value is generated based on calculations of at least the first and second values; The state of the clock signal is determined based on the comparison between the output value and the reference value; and The clock signal is adjusted based on the state.

2. The method according to claim 1, wherein, Determining the state includes identifying the clock signal as leading relative to the signal, and wherein the adjustment of the clock signal includes increasing the delay of the clock signal.

3. The method according to claim 1, wherein, Determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

4. The method according to claim 1, wherein, The calculation includes at least one of the sum of the first value and the second value, the average value, or the mode.

5. The method according to claim 4, wherein, The sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, wherein the reference value is based on the number of values ​​among the plurality of values.

6. The method according to claim 5, wherein, The reference value is based on the quantity of the value divided by 2.

7. The method according to claim 1, wherein, The clock signal includes K phases, and the method further includes: Determine one or more values ​​of the signal obtained at one or more Kth clock edges; Determine one or more values ​​of the signal obtained at one or more clock edges of the K+Mth digit, wherein M is equal to or greater than 1 and less than K; Determine a first sum of the one or more values ​​of the signal obtained at the one or more Kth clock edges; Determine a second sum of the one or more values ​​of the signal obtained at the one or more K+M-th clock edges; Compare the first sum with the reference value; Compare the second sum with the reference value; Based on the comparison between the first sum and the reference value, a first state is determined; Based on the comparison between the second sum and the reference value, a second state is determined; and The state of the clock signal is determined at least in part based on the first state and the second state.

8. The method according to claim 7, wherein, The first state is one of leading, lagging, or aligning relative to the signal, and the second state is one of leading, lagging, or aligning relative to the signal, and the method further includes: The state of the clock signal is determined to be ahead of the signal based on the majority of at least the first state and the second state being ahead of the signal.

9. The method according to claim 7, wherein, The first state is one of leading, lagging, or aligning relative to the signal, and the second state is one of leading, lagging, or aligning relative to the signal, and the method further includes: The state of the clock signal is determined to be lagging relative to the signal based on at least most of the first and second states being lagging relative to the signal.

10. The method according to claim 1, wherein, The reference value is calculated based on the assumption of jitter in the clock signal.

11. A system for mitigating clock signal drift, comprising: Processing circuitry; and A memory storing instructions, which are based on the processing circuitry executing the following: Determine the first value of the signal at the first clock edge of the clock signal; Determine the second value of the signal at the second clock edge of the clock signal; An output value is generated based on calculations of at least the first and second values; The state of the clock signal is determined based on the comparison between the output value and the reference value; and The clock signal is adjusted based on the state.

12. The system according to claim 11, wherein, Determining the state includes identifying the clock signal as leading relative to the signal, and wherein the adjustment of the clock signal includes increasing the delay of the clock signal.

13. The system according to claim 11, wherein, Determining the state includes identifying the clock signal as lagging relative to the signal, and wherein the adjustment of the clock signal includes advancing the clock signal.

14. The system according to claim 11, wherein, The calculation includes at least one of the sum of the first value and the second value, the average value, or the mode.

15. The system according to claim 14, wherein, The sum is based on a plurality of values ​​obtained at a plurality of clock edges, the plurality of values ​​including the first value and the second value, wherein the reference value is based on the number of values ​​among the plurality of values.

16. The system according to claim 15, wherein, The reference value is based on the quantity of the value divided by 2.

17. The system according to claim 11, wherein, The clock signal includes K phases, and the instructions are based on the processing circuitry further executing the following: Determine one or more values ​​of the signal obtained at one or more Kth clock edges; Determine one or more values ​​of the signal obtained at one or more clock edges of the K+Mth digit, wherein M is equal to or greater than 1 and less than K; Determine a first sum of the one or more values ​​of the signal obtained at the one or more Kth clock edges; Determine a second sum of the one or more values ​​of the signal obtained at the one or more K+M-th clock edges; Compare the first sum with the reference value; Compare the second sum with the reference value; Based on the comparison between the first sum and the reference value, a first state is determined; Based on the comparison between the second sum and the reference value, a second state is determined; and The state of the clock signal is determined at least in part based on the first state and the second state.

18. The system according to claim 17, wherein, The first state is one of leading, lagging, or aligning relative to the signal, and wherein the second state is one of leading, lagging, or aligning relative to the signal, and The instructions are based on the processing circuit's execution, which further causes the processing circuit to carry out the following: The state of the clock signal is determined to be ahead of the signal based on the majority of at least the first state and the second state being ahead of the signal.

19. The system according to claim 17, wherein, The first state is one of leading, lagging, or aligning relative to the signal, and wherein the second state is one of leading, lagging, or aligning relative to the signal, and The instructions are based on the processing circuit's execution, which further causes the processing circuit to carry out the following: The state of the clock signal is determined to be lagging relative to the signal based on at least most of the first and second states being lagging relative to the signal.

20. The system according to claim 11, wherein, The reference value is calculated based on the assumption of jitter in the clock signal.

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