Controller performing permanent data erasing operation and method of operation thereof

Abstract

A semiconductor device, a controller, and an operating method thereof are disclosed. In an embodiment, a controller includes an internal command generator configured to generate rewrite operation setting information to perform a rewrite operation on a data storage area corresponding to a data permanent erase request in response to the data permanent erase request, a rewrite data generator configured to generate a plurality of cell addresses corresponding to the data storage area based on the rewrite operation setting information, and generate a plurality of pieces of rewrite data to be respectively written to the data storage area corresponding to the plurality of cell addresses, and a storage area controller configured to control the data storage area to store the plurality of pieces of rewrite data corresponding to the plurality of cell addresses, respectively.

Description

Cross-reference to related applications

[0001] This patent document claims priority and benefit to Korean Patent Application No. 10-2024-0178595, filed on December 4, 2024, the entire disclosure of which is incorporated herein by reference as part of the disclosure of this patent document. Technical Field

[0002] Various embodiments of the disclosed technology generally relate to a semiconductor device, a controller, a permanent data erasure operation, and a method of operating the controller. Background Technology

[0003] A storage device is a component that stores data under the control of a host device, such as a computer, smartphone, tablet, or other electronic device. A storage device may include a memory device for storing data and a controller for controlling that memory device. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to a controller designed to reduce the time required for permanent data erasure operations and a method of operating the controller.

[0005] In embodiments of the disclosed technology, a controller may include: an internal command generator configured to generate rewrite operation setting information in response to a data permanent erasure request to perform a rewrite operation on a data storage area corresponding to the data permanent erasure request; a rewrite data generator communicating with the internal command generator and configured to generate multiple cell addresses corresponding to the data storage area based on the rewrite operation setting information, and to generate multiple rewrite data entries to be written to the data storage areas corresponding to the multiple cell addresses respectively; and a storage area controller communicating with the rewrite data generator and configured to control the data storage area to store the multiple rewrite data entries corresponding to the multiple cell addresses respectively.

[0006] In embodiments of the disclosed technology, a method of operating a controller may include: receiving a data permanent erasure request from an external device to delete data stored in a data storage area; setting range information of the data storage area corresponding to the data permanent erasure request and a data pattern to be written to the data storage area; generating an encrypted data pattern by encrypting the data pattern based on the range information; and performing a permanent data erasure operation corresponding to the data permanent erasure request based on the encrypted data pattern.

[0007] In embodiments of the disclosed technology, a storage device may include: a memory device including a plurality of namespaces; a host interface communicating with the memory device and configured to generate rewrite operation setting information for each of the plurality of namespaces in response to a data permanent erase request; and a processor communicating with the host interface and configured to: receive the rewrite operation setting information for each of the plurality of namespaces from the host interface; generate rewrite data to be written to each of the plurality of namespaces based on the rewrite operation setting information for each of the plurality of namespaces; and write the rewrite data into each of the plurality of namespaces of the memory device. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a storage device based on an embodiment of the disclosed technology.

[0009] Figure 2 This is a diagram illustrating an example of performing a permanent data erasure operation based on an embodiment of the disclosed technology.

[0010] Figure 3 This is a diagram illustrating an example of generating rewritten data based on an embodiment of the disclosed technology.

[0011] Figure 4 This is a diagram illustrating another example of generating rewritten data based on an embodiment of the disclosed technology.

[0012] Figure 5 This is a diagram illustrating another example of generating rewritten data based on an embodiment of the disclosed technology.

[0013] Figure 6 This is a diagram illustrating a method of operating a controller based on an embodiment of the disclosed technology.

[0014] Figure 7 This is a diagram illustrating a controller based on an embodiment of the disclosed technology. Detailed Implementation

[0015] The specific structural and functional features of the disclosed technology are disclosed in the context of the following embodiments. However, embodiments of the disclosed technology may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0016] The storage device can perform a sanitize operation upon request from the host device. The sanitize operation permanently deletes data by removing user data from a target area of ​​the storage device and rewriting that data using a predetermined data pattern (e.g., writing the predetermined data pattern to the target area). Through the sanitize operation, the storage device can prevent access to previously stored user data.

[0017] During the cleanup operation, the data patterns used can be encrypted and stored using predetermined encryption techniques. In this case, the time required for the cleanup operation may be increased due to repeated requests for encryption of the data patterns and repeated responses to those requests. The disclosed techniques can be implemented in some embodiments to reduce the time required for the cleanup operation.

[0018] Figure 1 This is a diagram illustrating a storage device 50 based on an embodiment of the disclosed technology. In some embodiments, the term "storage device" is used to refer to a data storage device.

[0019] Reference Figure 1 The storage device 50 may include a memory device 100 and a controller 200, with the controller 200 controlling the memory device 100. The storage device 50 may store data under the control of a host device 300 (or in response to a request from the host device 300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet computer, in-vehicle infotainment system, etc.

[0020] In some implementations, depending on the communication method with host device 300, storage device 50 can be configured as one of various types of storage devices. These types may include solid-state drives (SSDs), multimedia cards in the form of multimedia cards (MMC), embedded MMC (eMMC), size-reduced MMC (RS-MMC), and micro MMC, secure digital cards in the form of secure digital cards (SD), mini SD, and micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-e) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0021] The storage device 50 can be manufactured in various package types such as: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0022] The memory device 100 can store data. The memory device 100 can operate in response to control signals from the controller 200. The memory device 100 may include multiple memory blocks for storing data. Each memory block may include multiple memory cells. Each of the multiple memory cells may be configured as a multi-level cell (MLC) for storing two bits of data, a three-level cell (TLC) for storing three bits of data, a four-level cell (QLC) for storing four bits of data, or a similar configuration.

[0023] In this embodiment, the memory device 100 may be a non-volatile memory device, which retains data even when no power is supplied. For ease of description, it is assumed that the memory device 100 is a NAND flash memory device.

[0024] In this embodiment, the memory device 100 may receive commands and addresses from the controller 200. The memory device 100 may perform operations specified by the commands on the region indicated by the address. For example, the memory device 100 may perform write operations (or programming operations), read operations, and erase operations.

[0025] In embodiments, memory device 100 may include multiple namespaces NS1 to NSn. A namespace may refer to a region within the memory space of memory device 100 that is partitioned or divided based on logical block address (LBA). In some embodiments, the terms "logical block address (LBA)" and "logical address" may be used interchangeably. For example, if the total address range of the memory space of memory device 100 is from logical address 1 to logical address 1000 and is divided into two namespaces (e.g., namespace 0 and namespace 1), then namespace 0 may be the region corresponding to logical addresses 1 to 500, and namespace 1 may be the region corresponding to logical addresses 501 to 1000. In some embodiments, the term "namespace" may be used to indicate a logical partition or a number of memories formatted as logical blocks, allowing the creation of multiple virtual drives on a single data storage device.

[0026] The controller 200 can control the overall operation of the storage device 50.

[0027] When power is applied to storage device 50, controller 200 can run firmware. For example, firmware (FW) may include host interface layer (HIL) 211 for controlling communication with host device 300, flash translation layer (FTL) 231 for controlling communication between host device 300 and memory device 100, and flash interface layer (FIL) for controlling communication with memory device 100.

[0028] In an embodiment, the controller 200 may receive data and a logical block address from the host device 300, and convert the logical block address into a physical block address PBA, which represents the address of each memory cell in the memory device 100 containing the data to be stored. In some embodiments, the terms "physical block address PBA" and "physical address" may be used interchangeably.

[0029] In this embodiment, the controller 200 may provide the memory device 100 with commands, addresses or data corresponding to the operation upon request from the host device 300, so as to perform programming operations, reading operations, erasing operations, etc.

[0030] In an embodiment, when the controller 200 receives a write command and multiple data entries from the host device 300, the controller 200 generates at least one dataset based on the logical addresses of the multiple data entries. The metadata included in the dataset may include namespace identification information, and the multiple data entries included in the dataset will be stored in that namespace. The controller 200 may control the memory device 100 to program or write each dataset to each namespace based on the metadata included in the dataset.

[0031] In this embodiment, the controller 200 can independently generate commands, addresses, and data without a request from the host device 300, and transmit the generated commands, addresses, and data to the memory device 100. For example, the controller 200 can provide commands, addresses, and data to the memory device 100 to perform programming and reading operations involving internal operations such as wear leveling, read-and-reclaim, and garbage collection.

[0032] In an embodiment, controller 200 may include an internal command generator 210, a rewrite data generator 220, and a storage area controller 230. The rewrite data generator 220 and storage area controller 230 may be implemented using hardware, software, or a combination thereof. The hardware may include one or more processors, memories, interfaces, or other components that perform the specified operations, and the software may include commands, code, or other instructions that perform the specified operations.

[0033] In this embodiment, the internal command generator 210 can control the communication between the host device 300 and the controller 200. For example, the internal command generator 210 can drive HIL 211.

[0034] In this embodiment, the controller 200 may receive requests from the host device 300 instructing various operations via an internal command generator 210. Furthermore, the controller 200 may transmit responses to the requests to the host device 300 via the internal command generator 210.

[0035] In an embodiment, the internal command generator 210 may receive a data permanent erase request from the host device 300. The data permanent erase request may represent a request for a cleanup operation in the memory device 100. The cleanup operation may be a permanent data erase operation for deleting data stored in a data storage area of ​​the memory device 100 as requested by the host device 300, and storing the rewritten data in the requested data storage area. In other words, the cleanup operation may include an erase operation for deleting data stored in the data storage area, and a write operation for storing the rewritten data. The rewritten data may be written to the data storage area based on the permanent data erase operation.

[0036] In this embodiment, the data storage area can be a region for storing data, such as a page, storage block, plane, die, namespace, etc., which includes multiple memory units.

[0037] In some embodiments, a data permanent erasure request may include identification information of the data storage area in the memory device 100 for which a permanent data erasure operation corresponding to the data permanent erasure request is to be performed, the address of the data storage area, the data pattern to be written to the data storage area, the data pattern reversal operation condition information, and the number of iterations of the permanent data erasure operation. In some embodiments, the term "data pattern reversal operation condition information" refers to the condition information used to perform a data pattern reversal operation.

[0038] The data pattern inversion operation can refer to the operation of inverting the bits included in the data pattern. For example, the data pattern inversion operation can include inverting the bit value "1" to the bit value "0" and inverting the bit value "0" to the bit value "1".

[0039] In an embodiment, the internal command generator 210 may generate rewrite operation setting information in response to a data permanent erasure request provided by the host device 300, so as to perform a rewrite operation on the data storage area in the memory device 100 corresponding to the data permanent erasure request. For example, the rewrite operation setting information may include at least one of the following: identification information of the data storage area in the memory device 100 to which the permanent data erasure operation is to be performed, the address of the data storage area, the data mode to be written to the data storage area, the data mode reversal operation condition information, the number of iterations of the permanent data erasure operation, etc.

[0040] In an embodiment, the rewrite operation settings information may include various types of information for generating rewrite data to be written to the data storage area.

[0041] In an embodiment, the rewrite data generator 220 may include a resource manager 221 and an encryption engine 222. The resource manager 221 may be a component that manages resources such as write buffers and read buffers for performing write operations, read operations, erase operations, permanent data erase operations, and other operations. The encryption engine 222 may be a component that encrypts data to be written to the memory device 100 based on various encryption technologies. The resource manager 221 and the encryption engine 222 may be implemented using hardware, software, or a combination thereof. The hardware includes one or more processors, memories, interfaces, or other components that perform the specified operations, and the software includes commands, code, or other instructions that perform the specified operations.

[0042] In an embodiment, the rewrite data generator 220 can generate multiple cell addresses corresponding to data storage areas in the memory device 100 based on rewrite operation setting information, and generate multiple rewrite data entries to be written to the multiple cell addresses respectively. The cell address can be an address representing a data storage area such as a page, memory block, plane, die, or namespace, or an address representing a direct memory access (DMA) unit and other data memory units. For example, the rewrite data generator 220 can determine a data pattern based on the rewrite operation setting information and perform an encryption operation on the determined data pattern to generate multiple rewrite data entries. In some embodiments, the rewrite data generator 220 can determine whether to perform a data pattern inversion operation before the encryption operation.

[0043] In this embodiment, the storage area controller 230 can control the memory device 100.

[0044] In an embodiment, the storage region controller 230 may control a permanent data erasure operation on a data storage region in the memory device 100 in response to a request from the rewrite data generator 220. For example, the storage region controller 230 may control the data storage region to store multiple rewrite data entries corresponding to multiple cell addresses. The storage region controller 230 may drive the FTL 231. The storage region controller 230 may translate logical addresses of the host device 300 into physical addresses and generate commands corresponding to requests from the host device 300. The storage region controller 230 may provide commands and addresses or data to the memory device 100, or receive data read from the memory device 100.

[0045] The host device 300 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0046] Figure 2 This is a diagram illustrating an example of performing a permanent data erasure operation based on an embodiment of the disclosed technology.

[0047] Reference Figure 2 The internal command generator 210 can request the rewrite data generator 220 to generate rewrite data OWDATA and provide rewrite operation setting information OWSET_INFO.

[0048] The rewrite data generator 220 can receive the rewrite operation setting information OWSET_INFO from the internal command generator 210.

[0049] In this embodiment, the rewrite data generator 220 may store rewrite operation setting information OWSET_INFO. For example, the rewrite data generator 220 may store information such as: DPATT_INFO information about the data mode of the data storage area to be written, identification information of the data storage area indicating the permanent data erasure operation to be performed, RANGE_INFO information about the cleanup range of the address of the data storage area, INV_INFO information about the data mode reversal operation conditions, and the number of iterations of the permanent data erasure operation.

[0050] In this embodiment, the data pattern, the inversion operation condition information INV_INFO, and the number of iterations for the permanent data erase operation can vary depending on the data storage area. For example, a permanent data erase operation can be performed on each of the multiple namespaces NS1 to NSn based on different data patterns. Furthermore, a permanent data erase operation can be performed on each of the multiple namespaces NS1 to NSn based on different inversion operation condition information INV_INFO. In some implementations, a permanent data erase operation can be performed on each of the multiple namespaces NS1 to NSn based on different number of iterations.

[0051] In this embodiment, the identification information of multiple namespaces NS1 to NSn can be different from each other.

[0052] Additionally, the rewrite data generator 220 can store information EC_INFO related to the encryption operation. EC_INFO may include the encryption technology and the size of the data used to perform the encryption operation.

[0053] In an embodiment, the rewrite data generator 220 can generate rewrite data OWDATA based on information about the data pattern DPATT_INFO, cleanup range information RANGE_INFO, data pattern inversion operation condition information INV_INFO, and information related to encryption operations EC_INFO.

[0054] In one embodiment, the storage area controller 230 can receive rewritten data OWDATA and the logical address LBA of the data storage area from the rewritten data generator 220, and can control the data storage area to store the rewritten data OWDATA in the data storage area indicated by the logical address LBA.

[0055] For example, the storage area controller 230 can translate a logical address LBA into a physical address PBA mapped to that logical address LBA. The storage area controller 230 can generate a command CMD indicating a permanent data erase operation and provide the generated command CMD, rewritten data OWDATA, and physical address PBA to the memory device 100. The command CMD can instruct (1) an erase operation to erase data in the data storage area, and (2) a write operation to store the rewritten data OWDATA in the data storage area from which the data was erased, in response to the command CMD indicating the permanent data erase operation.

[0056] The memory device 100 can perform a permanent data erasure operation on the data storage area indicated by the physical address PBA based on the command CMD and rewrite data OWDATA provided from the memory area controller 230.

[0057] Figure 3 This is a diagram illustrating an example of generating OWDATA rewritten data based on an embodiment of the disclosed technology. Specifically, Figure 3 This illustrates an example where one or more logical storage blocks LB1 to LBn within the i-th namespace NSi, from namespaces NS1 to NSn, are the target data storage areas for a permanent data erasure operation. However, compared to... Figure 3 Unlike the example shown, the target data storage area can include all logical storage blocks within a single namespace, or multiple logical storage blocks within multiple namespaces.

[0058] Reference Figure 3The i-th namespace NSi can include multiple logical memory blocks LB1 to LBn. The multiple logical memory blocks LB1 to LBn can be arranged using consecutive logical addresses.

[0059] In an embodiment, the logical address of the data storage area may include the starting address SLBA of the data storage area and the number of logical storage blocks NLB. For example, the cleanup range information RANGE_INFO stored in the rewrite data generator 220 may include the identification information of the i-th namespace NSi, the starting address SLBA indicating the first logical storage block LB1, and the number of logical storage blocks NLB indicating the n logical storage blocks starting from the starting address SLBA.

[0060] In this embodiment, the rewrite data generator 220 can generate rewrite data OWDATA by encrypting the data pattern DPATT. For example, the rewrite data generator 220 can encrypt the data pattern DPATT corresponding to the i-th namespace NSi to generate rewrite data OWDATA to be written to multiple logical storage blocks LB1 to LBn.

[0061] In an embodiment, the rewrite data generator 220 can use at least one of the identification information of the data storage area or the logical address of the data storage area as seed data to encrypt the data pattern DPATT. For example, the rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA indicating the first logical storage block LB1 as seed data to encrypt the data pattern DPATT corresponding to the i-th namespace NSi.

[0062] Under the control of the storage area controller 230, the rewritten data OWDATA can be written to physical storage blocks corresponding to multiple logical storage blocks LB1 to LBn, such as storage blocks in the memory device 100.

[0063] Figure 4 This is a diagram illustrating another example of generating rewritten data based on an embodiment of the disclosed technology.

[0064] Reference Figure 4 The rewrite data generator 220 can encrypt each preset size data pattern DPATT.

[0065] In this embodiment, the rewrite data generator 220 can check a preset size from the information EC_INFO related to the encryption operation. The preset size can be the size of a data storage area such as a page, block, plane, die, etc., or it can represent the size of a direct memory access (DMA) cell.

[0066] For example, assuming the DMA unit size corresponds to the logical memory block size, and the rewrite data generator 220 encrypts the data pattern DPATT for each DMA unit size. Specifically, the rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA1 of the first logical memory block LB1 as seed data to encrypt the data pattern DPATT, generating the first rewrite data OWDATA1 to be written to the first logical memory block LB1. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA2 of the second logical memory block LB2 as seed data to encrypt the data pattern DPATT, generating the second rewrite data OWDATA2 to be written to the second logical memory block LB2. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA3 of the third logical memory block LB3 as seed data to encrypt the data pattern DPATT, generating the third rewrite data OWDATA3 to be written to the third logical memory block LB3. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBAn of the n-th logical storage block LBn as seed data to encrypt the data pattern DPATT to generate the n-th rewrite data OWDATAn to be written to the n-th logical storage block LBn.

[0067] Figure 5 This is a diagram illustrating another example of generating rewritten data based on an embodiment of the disclosed technology.

[0068] Reference Figure 5 The rewrite data generator 220 can determine whether to invert the data pattern DPATT based on inversion operation condition information. When the inversion operation condition information is met, the rewrite data generator 220 can invert the data pattern DPATT; conversely, when the inversion operation condition information is not met, the data pattern DPATT can be used without inverting it. The inversion operation condition information can be determined by conditions such as the number of iterations of the permanent data erasure operation and the preset size of the data storage area.

[0069] In an embodiment, the rewrite data generator 220 can be determined based on the number of iterations of the permanent data erase operation. For example, when the permanent data erase operation is repeatedly executed based on the number of iterations, the rewrite data generator 220 can alternate between using the data mode DPATT and the inverted data mode INV_DPATT, and can use the data mode DPATT to generate rewrite data OWDATA1 to OWDATAn during the last permanent data erase operation. As another example, the rewrite data generator 220 can use the data mode DPATT to generate rewrite data OWDATA1 to OWDATAn during an odd number of permanent data erase operations, and use the inverted data mode INV_DPATT to generate rewrite data OWDATA1' to OWDATAn' during an even number of permanent data erase operations.

[0070] In this embodiment, the rewrite data generator 220 can alternately use the data mode DPATT and the inverted data mode INV_DPATT for each preset size data storage area. For example, assuming that the data mode DPATT and the inverted data mode INV_DPATT are used alternately for each logical storage block, the data mode of the first logical storage block LB1 can be used as is, while the data mode of the second logical storage block LB2 can be inverted.

[0071] In the example above, the data pattern DPATT is reversed based on the number of iterations of the permanent data erasure operation and the preset size of the data storage area. However, the disclosed technique is not limited to this, and the rewrite data generator 220 can reverse the data pattern DPATT based on various conditions.

[0072] In an embodiment, the rewrite data generator 220 can invert the data pattern DPATT based on the inversion operation condition information, and then encrypt the inverted data pattern INV_DPATT to generate rewrite data OWDATA1' to OWDATAn'.

[0073] In the example of encrypting the inverted data pattern INV_DPATT for each logical storage block, the rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA1 of the first logical storage block LB1 as seed data to encrypt the inverted data pattern INV_DPATT to generate the first rewritten data OWDATA1' to be written to the first logical storage block LB1. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA2 of the second logical storage block LB2 as seed data to encrypt the inverted data pattern INV_DPATT to generate the second rewritten data OWDATA2' to be written to the second logical storage block LB2. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBA3 of the third logical storage block LB3 as seed data to encrypt the inverted data pattern INV_DPATT to generate the third rewritten data OWDATA3' to be written to the third logical storage block LB3. The rewrite data generator 220 can use the identification information of the i-th namespace NSi and the starting address SLBAn of the n-th logical storage block LBn as seed data to encrypt the inverted data pattern INV_DPATT to generate the n-th rewrite data OWDATAn' to be written to the n-th logical storage block LBn.

[0074] Methods and references for generating the first rewritten data OWDATA1 to the nth rewritten data OWDATAn Figure 4 The methods of description are the same; therefore, detailed descriptions will be omitted.

[0075] Figure 6 This is a diagram illustrating a method of operating a controller 200 based on an embodiment of the disclosed technology.

[0076] Figure 6 The method shown can be derived from Figure 1 The controller 200 shown is executed.

[0077] Reference Figure 6 In S601, the controller 200 can receive a data permanent erase request from an external device. The external device can be... Figure 1 The main unit 300.

[0078] In S603, controller 200 can set the range information of the data storage area corresponding to the data permanent erasure request and the data mode of the data storage area to be written.

[0079] For example, controller 200 can use range information as seed data to encrypt data patterns.

[0080] In S605, controller 200 can set the reverse operation condition information of the data mode.

[0081] In some implementations, controller 200 may determine whether to invert the data pattern based on inversion operation condition information.

[0082] For example, in S607, controller 200 can determine whether the conditions for reversing operation are met.

[0083] Based on the determination result of S607, when the inversion operation condition information is met, in step S609, the controller 200 can invert the data mode.

[0084] In S611, controller 200 can encrypt the inverted data pattern based on range information.

[0085] Conversely, based on the determination result of S607, when the inversion operation condition information is not met, in step S613, the controller 200 can encrypt the data pattern based on the range information.

[0086] In S615, controller 200 can control permanent data erasure operations corresponding to data permanent erasure requests based on encrypted data modes.

[0087] Figure 7 This is a diagram illustrating a controller based on an embodiment of the disclosed technology.

[0088] Figure 7 The controller 1000 shown can represent Figure 1 The controller 200 shown.

[0089] Reference Figure 7 The controller 1000 may include a processor 1010, a memory 1020, an error correction circuit 1030, a host interface 1040, a memory interface 1050, and a communication bus 1060. The processor 1010, memory 1020, error correction circuit 1030, host interface 1040, and memory interface 1050 of the controller 1000 can communicate with each other via the communication bus 1060.

[0090] Figure 7 The host interface 1040 shown provides an interface to the host device 300, carries communication between the controller 1000 and the host device 300, and may include... Figure 1 The internal command generator 210 is shown.

[0091] The processor 1010 can run firmware, code, or one or more commands that include various types of information required for the operation of the controller 1000. In an embodiment, Figure 1The rewrite data generator 220 and the storage area controller 230 can be implemented as one or more components included in the processor 1010.

[0092] The memory 1020 can be used as a buffer memory, cache memory, operational memory or other types of memory.

[0093] In some implementations, memory 1020 may store firmware, code, and one or more commands that include various types of information required for the operation of controller 1000.

[0094] Error correction circuit 1030 can perform error correction when data is stored in or read from memory device 100. For example, error correction circuit 1030 can perform error correction code (ECC) encoding based on the data to be written to memory device 100. The encoded data can then be transmitted to memory device 100. Error correction circuit 1030 can also perform ECC decoding on data received from memory device 100.

[0095] The controller 1000 can communicate with external devices (e.g., host device 300, application processor, etc.) via host interface 1040.

[0096] In one embodiment, the host interface 1040 can receive requests from an external device instructing internal operations on multiple data storage areas, and can generate rewrite operation configuration information for each of the multiple data storage areas based on the requests. For example, the multiple data storage areas may represent multiple namespaces. The request may specifically instruct a permanent data erasure operation.

[0097] In this embodiment, the rewrite operation settings can be different for each of the multiple namespaces.

[0098] In this embodiment, the processor 1010 may determine whether to invert the data pattern to be written to each of the multiple namespaces based on the data pattern inversion operation condition information. The processor 1010 may encrypt the data pattern to be written to each of the multiple namespaces or the inverted data pattern based on the identification information of each of the multiple namespaces and the logical address of each of the multiple namespaces to generate rewritten data.

[0099] The controller 1000 can communicate with the memory device 100 via the memory interface 1050. The controller 1000 can transmit commands, addresses, control signals, etc. to the memory device 100 via the memory interface 1050, and can also receive data from the memory device 100.

[0100] The processor 1010 can transmit a command indicating a permanent data erasure operation, the logical address of each of the multiple namespaces, and the rewrite data to the memory device 100 via the memory interface 1050.

[0101] In some embodiments of the disclosed technology, a controller capable of reducing the time required for permanent data erasure operations and a method for operating the controller are provided.

[0102] The above-disclosed embodiments and implementation schemes are merely examples, and various improvements and changes can be made to the disclosed embodiments and implementation schemes, as well as other embodiments and implementation schemes, based on the content described and illustrated in this patent document.

Claims

1. A controller for controlling a memory device storing data, comprising: An internal command generator generates rewrite operation setting information in response to a data permanent erase request, in order to perform a rewrite operation on the data storage area in the memory device corresponding to the data permanent erase request; The rewrite data generator communicates with the internal command generator and, based on the rewrite operation setting information, generates multiple unit addresses corresponding to the data storage area, and generates multiple rewrite data entries to be written to the data storage areas corresponding to the multiple unit addresses respectively. as well as A storage area controller communicates with the rewrite data generator and controls the data storage area in the memory device to store the multiple rewrite data corresponding to the multiple cell addresses, respectively.

2. The controller according to claim 1, wherein, The rewrite operation setting information includes at least one of the following: identification information of the data storage area in the memory device, logical address of the data storage area, information about the data pattern to be written to the data storage area, or inversion operation condition information for performing an inversion operation on the data pattern.

3. The controller according to claim 2, wherein, The rewrite data generator generates the multiple rewrite data by encrypting the data pattern.

4. The controller according to claim 3, wherein, The rewrite data generator encrypts a data pattern of a preset size.

5. The controller according to claim 3, wherein, The rewrite data generator encrypts the data pattern by using at least one of the identification information of the data storage area or the logical address of the data storage area as seed data.

6. The controller according to claim 2, wherein, The rewrite data generator determines whether to reverse the data pattern based on the inversion operation condition information.

7. The controller according to claim 6, wherein, When the rewritten data generator reverses the data pattern based on the inversion operation condition information, the rewritten data generator encrypts the inverted data pattern to generate the multiple rewritten data.

8. The controller according to claim 1, wherein, The data storage area corresponds to one of a plurality of namespaces.

9. A method of operating a controller, the controller controlling a memory device storing data, the method comprising: The controller receives a data permanent erase request from an external device to delete data stored in the data storage area of ​​the memory device; Set the range information of the data storage area corresponding to the data permanent erasure request and the data mode to be written to the data storage area; An encrypted data pattern is generated by encrypting the data pattern based on the range information; as well as Perform a permanent data erasure operation corresponding to the data permanent erasure request based on the encrypted data mode.

10. The method according to claim 9, wherein, Performing the permanent data erasure operation corresponding to the data permanent erasure request includes: Delete the data stored in the data storage area; and The encrypted data pattern is stored in the data storage area where the data has been deleted.

11. The method according to claim 9, wherein, Encrypting the data pattern includes using the range information as seed data to encrypt the data pattern.

12. The method according to claim 9, wherein, Encrypting the data pattern includes encrypting a data pattern of a preset size.

13. The method of claim 9, further comprising: Before encrypting the data pattern Set the inversion operation condition information for performing the inversion operation on the data pattern; as well as Based on the inversion operation condition information, it is determined whether to invert the data pattern.

14. The method according to claim 13, wherein, Encrypting the data pattern includes reversing the data pattern based on the reversal operation condition information and encrypting the reversed data pattern.

15. A storage device, comprising: A memory device, including multiple namespaces associated with local address information; A host interface that communicates with a host device to enable the host device to access the memory device, and the host interface that, in response to a data permanent erase request from the host device, generates rewrite operation setting information for each of the plurality of namespaces; as well as The processor communicates with the host interface and: receives rewrite operation setting information for each of the plurality of namespaces from the host interface; generates rewrite data to be written to each of the plurality of namespaces based on the rewrite operation setting information for each of the plurality of namespaces; and writes the rewrite data into each of the plurality of namespaces of the memory device.

16. The storage device according to claim 15, wherein, The rewrite operation settings are different for each of the multiple namespaces.

17. The storage device according to claim 15, wherein, The rewrite operation settings information includes at least one of the following: identification information of each of the plurality of namespaces, logical address of each of the plurality of namespaces, information about the data pattern to be written to each of the plurality of namespaces, and inversion operation condition information for performing an inversion operation on the data pattern.

18. The storage device according to claim 17, wherein, The processor: based on the inversion operation condition information of the data pattern, determines whether to invert the data pattern to be written to each of the plurality of namespaces; and based on the identification information of each of the plurality of namespaces and the logical address of each of the plurality of namespaces, encrypts the data pattern to be written to each of the plurality of namespaces or the inverted data pattern to generate the rewritten data.

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