Data copying method and related apparatus

Abstract

Embodiments of the present application provide a data copying method and related device to solve the problem of long data copying path and low copying efficiency. The method comprises: a first copying unit acquires a first message, the first message being used to indicate copying first data at a first address in a first memory bank to a second address in the first memory bank; and according to the first message, the first copying unit copies the first data in the first memory bank to the second address.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data copying method and related apparatus. Background Technology

[0002] Data copying is an essential step in the central processing unit (CPU)'s data processing. However, as the amount of data copied increases, the efficiency of using the CPU for data copying cannot meet the growing demands. Therefore, the industry has begun to adopt hardware offloading to complete data copying tasks, freeing up CPU computing power.

[0003] Existing technologies solve the problem of offloading data copying tasks from the CPU to the accelerator for execution. However, when the accelerator executes the data copying task, it needs to read the data into the accelerator based on the source address and then write the data to the destination address. This results in a long data path and low data copying efficiency. Summary of the Invention

[0004] This application provides a data copying method and related equipment to solve the problems of long data copying paths and low data copying efficiency.

[0005] Firstly, this application provides a data copying method. The method is applied to a first copying unit, which is located in a first memory module. The method includes: the first copying unit acquiring a first message, the first message instructing that first data at a first address in the first memory module be copied to a second address in the first memory module; and, according to the first message, the first copying unit copying the first data from the first memory module to the second address. When the source address and destination address of the first data are on the same memory module, local copying is performed through the copying unit in that memory module. The data does not need to be read from the memory module into the accelerator / CPU first, and then written from the accelerator / CPU back to the memory module, thus shortening the data copying path and improving copying efficiency.

[0006] In one possible implementation, the first data is a portion of the target data, which is interleaved across M memory modules. The target data comprises K data sub-blocks, and each of the M memory modules stores at least one data sub-block. The first data comprises N data sub-blocks from the K data sub-blocks, and the first memory module is one of the M memory modules. K and M are integers greater than or equal to 2, and N is an integer greater than or equal to 1. When the target data is interleaved across multiple memory modules, the distributed copy unit can complete the copying of data sub-blocks locally, thereby reducing the number of times the target data is transmitted through the communication bus, reducing the occupation of the communication bus, and shortening the data copying path, thus improving data copying efficiency.

[0007] In one possible implementation, the method further includes: a first copy unit acquiring a second message, the second message instructing that second data at a third address in a first memory module be copied to a fourth address in a second memory module, the second data comprising at least one data sub-block, and the second memory module being one of M memory modules; according to the second message, the first copy unit sending the fourth address and the second data to the second memory module. Thus, the second copy unit in the second memory module can write the second data to the fourth address. For data sub-blocks copied across memory modules, the data copy can also be completed in a single transmission, reducing the occupancy of the communication bus and improving copy efficiency.

[0008] In one possible implementation, the length of each of the N data sub-blocks is the interleaving granularity of the memory interleaving. The first message also includes data length indication information, which indicates the length of the first data. The data length indication information is the product of N and the interleaving granularity, or the data length indication information is N, where N is an integer greater than or equal to 1. Therefore, when multiple data sub-blocks have source addresses belonging to the same memory module and destination addresses belonging to the same memory module, they can be merged into a single message for data copy indication, reducing the number of messages and improving data copy efficiency.

[0009] In one possible implementation, according to the first message, the first copy unit copies the first data from the first memory module to the second address, including: determining whether the second address is within the first address range, where the first address range is the address range defined by the length of the first data; if the second address is within the first address range, then copying the first data from the first address range to the second address range in descending order, where the second address range is the address range defined by the length of the first data; if the second address is not within the first address range, then copying the first data from the first address range to the second address range in ascending order. This ensures that the data is copied completely and accurately.

[0010] In one possible implementation, the first message further includes overlap indication information, which is used to indicate whether the second address is within the first address range. Determining whether there is an overlap between the first address range and the second address range in the first memory module according to the first message includes: determining whether the second address is within the first address range according to the overlap indication information.

[0011] In one possible implementation, determining whether the second address is within the range of the first address based on the first message includes: determining the range of the first address based on the first address and data length information; and determining whether the second address is within the range of the first address.

[0012] In one possible implementation, the first memory module further includes a first memory module controller, and the first copy unit is disposed in the first memory module controller.

[0013] The second aspect provides a data copying method. This method is applied to a computing unit. The method includes: determining, based on the source address of the target data, the destination address of the target data, the length of the target data, and a memory interleaving algorithm, first distribution information and second distribution information of K data sub-blocks of the target data across M memory modules. The first distribution information includes the memory module to which each data sub-block in the K data sub-blocks at the source address belongs, and the second distribution information includes the memory module to which each data sub-block in the K data sub-blocks at the destination address belongs, where K is an integer greater than or equal to 2, and M is an integer greater than or equal to 2; determining, based on the first and second distribution information, whether the source address and destination address of each data sub-block belong to the same memory module; if the source address and destination address of the first data in the first memory module of the M memory modules belong to the same memory module, then sending a first message to the first memory module. The first data includes N data sub-blocks out of the K data sub-blocks, and the first message is used to instruct that the first data be copied from the first address to the second address in the first memory module, where the first address is the source address of the first data, the second address is the destination address of the first data, and N is an integer greater than or equal to 1.

[0014] In one possible implementation, if the destination address of the second data in the first memory module out of M memory modules belongs to the second memory module, then a second message is sent to the first memory module. The second data includes at least one of the K data sub-blocks. The first data is different from the second data. The second message is used to instruct that the second data be copied from a third address in the first memory module to a fourth address in the second memory module. The third address is the source address of the second data, and the fourth address is the destination address of the second data. The second message may include the third address, the fourth address, and data length indication information of the second data, etc.

[0015] In one possible implementation, a first address range is determined based on the length of the first address and the first data; then, it is determined whether the second address is within the first address range to obtain overlap indication information. The overlap indication information is used to indicate whether the second address is within the first address range. The first address range is the address range defined by the length of the first address and the second data.

[0016] A third aspect provides a data copying method. This method is applied to a second copying unit in a second memory module. The second copying unit acquires second data and a fourth address from a first memory module; the second copying unit writes the second data to the fourth address. The second data is a portion of target data, which is stored interleaved across M memory modules. The target data includes K data sub-blocks, and each of the M memory modules stores at least one of the data sub-blocks. The first data includes at least one of the K data sub-blocks. The second memory module is one of the M memory modules, where K and M are integers greater than or equal to 2.

[0017] Fourthly, this application provides a data copying device. The device is applied to a first copying unit, which is disposed in a first memory module. The device includes an acquisition module for acquiring a first message, the first message indicating that first data at a first address in the first memory module be copied to a second address in the first memory module. The copying module is used to copy the first data from the first memory module to the second address according to the first message.

[0018] In one possible implementation, the first data is a portion of the target data, which is interleaved across M memory modules. The target data comprises K data sub-blocks, and each of the M memory modules stores at least one data sub-block. The first data comprises N data sub-blocks from the K data sub-blocks, and the first memory module is one of the M memory modules. K and M are integers greater than or equal to 2, and N is an integer greater than or equal to 1. When the target data is interleaved across multiple memory modules, the distributed copy unit can complete the copying of data sub-blocks locally, thereby reducing the number of times the target data is transmitted through the communication bus, reducing the occupation of the communication bus, and shortening the data copying path, thus improving data copying efficiency.

[0019] In one possible implementation, the acquisition module is further configured to acquire a second message, which instructs that second data at a third address in the first memory module be copied to a fourth address in the second memory module. The second data includes at least one data sub-block, and the second memory module is one of M memory modules. The copy module is configured to send the second data to the second memory module by the first copy unit according to the second message.

[0020] In one possible implementation, the length of each of the N data sub-blocks is the interleaving granularity of the memory interleaving. The first message also includes data length indication information, which indicates the length of the first data. The data length indication information is the product of N and the interleaving granularity, or the data length indication information is N, where N is an integer greater than or equal to 1. Therefore, when multiple data sub-blocks have source addresses belonging to the same memory module and destination addresses belonging to the same memory module, they can be merged into a single message for data copy indication, reducing the number of messages and improving data copy efficiency.

[0021] In one possible implementation, the copy unit is configured to determine whether the second address is within the first address range based on the first message, wherein the first address range is an address range defined by the length of the first address and the first data; the copy unit is configured to copy the first data in the first address range to the second address range in descending order when the second address is within the first address range, wherein the second address range is an address range defined by the length of the second address and the first data; and the copy unit is configured to copy the first data in the first address range to the second address range in ascending order when the second address is not within the first address range.

[0022] In one possible implementation, the first message further includes overlap indication information, which is used to indicate whether the second address is within the range of the first address. The copying unit is used to determine whether the second address is within the range of the first address based on the overlap indication information.

[0023] In one possible implementation, the copy unit is used to determine the first address range based on the first address and data length information; and to determine whether the second address is within the first address range.

[0024] In one possible implementation, the first memory module further includes a first memory module controller, and the first copy unit is disposed in the first memory module controller.

[0025] The fifth aspect provides a data copying device. This device is applied to a computing unit. The device includes: a processing module, configured to determine, based on the source address of the target data, the destination address of the target data, the length of the target data, and a memory interleaving algorithm, a first distribution information and a second distribution information of K data sub-blocks of the target data in M ​​memory modules, wherein the first distribution information includes the memory module to which each data sub-block in the K data sub-blocks in the source address belongs, and the second distribution information includes the memory module to which each data sub-block in the K data sub-blocks in the destination address belongs, where K is an integer greater than or equal to 2, and M is an integer greater than or equal to 2; a processing module, configured to determine, based on the first distribution information and the second distribution information, whether the source address and destination address of each data sub-block belong to the same memory module; and a transceiver module, configured to send a first message to the first memory module when the source address and destination address of the first data in the first memory module belong to the same memory module, wherein the first data includes N data sub-blocks in the K data sub-blocks, and the first message is used to instruct the first data to be copied from a first address to a second address in the first memory module, where the first address is the source address of the first data, the second address is the destination address of the first data, and N is an integer greater than or equal to 1.

[0026] In one possible implementation, the transceiver module is used to send a second message to the first memory module when the destination address of the second data in the first memory module out of M memory modules belongs to the second memory module. The second data includes at least one of K data sub-blocks, and the first data is different from the second data. The second message is used to instruct the copying of the second data from a third address in the first memory module to a fourth address in the second memory module, where the third address is the source address of the second data and the fourth address is the destination address of the second data.

[0027] In one possible implementation, the processing module is used to determine a first address range based on the length of the first address and the first data; the processing module is used to determine whether the second address is within the first address range to obtain overlap indication information. The overlap indication information is used to indicate whether the second address is within the first address range. The first address range is the address range defined by the length of the first address and the second data.

[0028] A sixth aspect provides a data copying device. This device is applied to a second copying unit in a second memory module. The device includes: an acquisition module for acquiring a data copying request from a first copying unit of a first memory module, the data copying request instructing the second copying unit to send second data to the first copying unit, the data copying request including a third address of the second data and data length indication information of the second data, the third address belonging to the second memory module; a reading module for the second copying unit to read the second data from the third address according to the data copying request; and a transceiver module for the second copying unit to send the second data to the first copying unit.

[0029] A seventh aspect provides a data copying device, including a processor and an interface circuit. The interface circuit is configured to receive signals from other devices outside the data copying device and transmit them to the processor, or to send signals from the processor to other devices outside the data copying device. The processor implements any one of the first to third aspects, and any possible implementation thereof, through logic circuits or executable code instructions. The data copying device can be a copying unit, a memory controller, or a memory module.

[0030] Eighthly, a computer-readable storage medium is provided that stores a computer program or instructions which, when executed by a processor, implement the methods of any one of the first to third aspects and any possible implementation thereof.

[0031] Ninthly, a computer program product storing instructions is provided, which, when executed by a processor, implements any one of the first to third aspects and any possible implementation thereof.

[0032] In a tenth aspect, a chip is provided, comprising a processor and potentially a memory, for implementing the methods of any one of the first to third aspects, and any possible implementation thereof. The chip system may be composed of a chip or may include chips and other discrete devices.

[0033] Eleventhly, a communication system is provided, the system comprising means for implementing the method provided in the first aspect, means for implementing the method provided in the second aspect, and means for implementing the method provided in the third aspect. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a data copying system;

[0035] Figure 2 A schematic diagram of a data copying system provided in this application;

[0036] Figure 3 A schematic diagram of a message format provided in this application;

[0037] Figure 4 A schematic diagram illustrating a data copying scenario provided in this application;

[0038] Figure 5 A schematic diagram illustrating another data copying scenario provided in this application;

[0039] Figure 6 A flowchart illustrating a data copying method provided in this application;

[0040] Figure 7 A flowchart illustrating another data copying method provided in this application.

[0041] Figure 8 A schematic diagram of a data copying device provided in this application;

[0042] Figure 9 A schematic diagram of another data copying device provided in this application;

[0043] Figure 10 A schematic diagram of another data copying device provided in this application. Detailed Implementation

[0044] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0045] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. "A plurality of" means two or more.

[0046] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0047] Memory is a type of storage device and one of the most important components of a computer. It acts as a bridge between the central processing unit (CPU) and other devices, primarily used for temporary data storage and working in conjunction with the CPU to coordinate its processing speed, thereby improving overall system performance. Memory can also be called main memory or internal memory.

[0048] Memory typically uses a memory module structure. Based on the packaging and pin configuration, memory modules can be divided into single in-line memory modules (SIMM) and dual in-line memory modules (DIMM). One memory module can be inserted into a single slot on the motherboard. A memory module is made up of multiple identical memory chips mounted on the same printed circuit board (PCB). Memory chips, commonly known as memory chips, are the basic units that make up a memory module.

[0049] Based on their working principles, memory is mainly divided into read-only memory (ROM) and random access memory (RAM). ROM can only read data and cannot write data arbitrarily. It has the advantage that data remains unchanged after power failure and is generally used to store unchangeable data, such as in the Basic Input Output System (BIOS). The contents stored in RAM can be accessed randomly through instructions. Data in RAM is lost when power is off, so it can only be stored during system startup. The term "memory" usually refers to RAM.

[0050] Based on their structure and operating principles, RAM can be divided into static RAM and dynamic RAM. Currently, the most commonly used memory in the industry is synchronous dynamic random access memory (SDRAM). Synchronous means that the memory requires a synchronized clock; internal command transmission and data transfer are based on this clock. Dynamic means that the memory array needs constant refreshing to ensure data is not lost. Random means that data is not stored linearly sequentially, but rather read and written freely at specified addresses. To improve the speed of SDRAM, the industry can also use double data rate SDRAM (DDR SDRAM). This doubles the speed of SDRAM without increasing the clock frequency, and has twice the transfer rate and memory bandwidth of SDRAM. DDR SDRAM can also be called memory modules, memory modules, or simply memory.

[0051] A memory controller (MC) can also be installed on the motherboard. For example, the memory controller can be located within the CPU, or it can be located within the memory itself. When the CPU accesses memory, the memory controller controls the CPU's access to memory. The channel between the memory controller and the memory is called a memory channel. Alternatively, a memory channel can be understood as a memory controller and the corresponding memory medium. To improve the CPU's data processing speed, two or more memory controllers can be installed on the motherboard, each controlling a portion of the memory. In this scenario, the motherboard includes two or more memory channels, which are generally identical and independent. Dual-channel memory essentially means that the CPU has two completely independent memory controllers. One memory channel can correspond to one or more memory module slots. When there are two or more memory controllers on the motherboard, each memory controller controls a portion of the memory system, and each memory channel has an equal memory capacity.

[0052] To improve system performance, memory interleaving technology can be used to evenly interleave accesses across all memory channels. The interleaving method can be configured by the system administrator, and can be performed between multiple memory channels connected to a single processor, or between multiple memory channels across multiple processors.

[0053] Generally, due to spatial locality in software programs, the addresses accessed by a software program within a short period of time may be concentrated in a small range. When accesses are concentrated in a certain address range, if accesses are distinguished only by the high-order address bits, it may lead to accesses being concentrated on a single memory channel, while other memory channels remain idle. To fully utilize the system's memory bandwidth and ensure bandwidth balance across memory channels, thereby improving the utilization rate of DDR SDRAM, DDR SDRAM access operations need to be interleaved. Address interleaving is typically used to evenly distribute the address space to be accessed across all memory channels (usually using low-order interleaving), utilizing all memory channels to process the accessed addresses.

[0054] When each memory channel in a memory system has the same memory capacity, all memory channels can use the same interleaving window and interleaving algorithm. For example, when there are two memory channels in a memory system, an average interleaving method can be used to interleave the addresses in the memory system onto the two memory channels. For example, odd-numbered addresses are interleaved onto the first memory channel, and even-numbered addresses are interleaved onto the second memory channel.

[0055] To improve the efficiency of the entire computer system, data copying tasks can be offloaded from the CPU to the accelerator. However, when the accelerator performs data copying tasks, it needs to read the data into the accelerator based on the source address and then write the data to the destination address. The data path is relatively long, which has a significant impact on data copying performance and bus bandwidth.

[0056] For example, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a data copying system. Figure 1 The data copying system shown includes a CPU, a copying unit, an accelerator, at least two memory modules (e.g., DDR1, DDR2, etc.) and a communication bus. The communication bus connects the CPU, the copying unit, the accelerator, and the at least two memory modules, and is used for communication between the CPU, the copying unit, the accelerator, and the at least two memory modules.

[0057] The accelerator is used to issue data copy commands to the copy unit. The copy unit is used to execute the data copy task according to the data copy commands.

[0058] A memory module includes a memory module controller, which manages and schedules read and write requests for its associated memory modules. For example, DDR1 may include a DDR controller (DDRC)1, and DDR2 may include DDRC2. The memory module controller needs to handle a large number of read and write requests from copy units and map the logical addresses in the read and write requests to the physical addresses of the memory modules.

[0059] The process of copying data in the copy unit is as follows: first, the data is read from a certain DDR into the copy unit according to the source address, and then the data is written to the destination address of a certain DDR. The data path is relatively long, which has a significant impact on the data copying performance and bus bandwidth.

[0060] For example: We need to copy 192 bytes of data from source address 0x00 to destination address 0x100.

[0061] If the interleaving granularity of the address in DDRC is 64B, the address distribution of 192B data in DDR1 and DDR2 is as follows: DDRC1 includes addresses 0x00, 0x80, 0x100, and 0x180; DDRC2 includes addresses 0x40, 0xC0, 0x140, and 0x1C0.

[0062] When the copy unit copies 192 bytes of data from source address 0x00 to destination address 0x100, it needs to perform three copy operations, each copying 64 bytes of data: 0x000->0x100, 0x40->0x140, and 0x80->0x180. The process is as follows: Figure 1 As shown.

[0063] It can be observed that addresses 0x40 and 0x140 belong to the same DDRC. When the copy unit performs the copy task, it still needs to read the data from address 0x40 into the accelerator (copy unit), and then the accelerator (copy unit) writes the data into address 0x140, which brings a long data path delay and has a significant impact on bus bandwidth.

[0064] like Figure 2 As shown, Figure 2 This is a schematic diagram of a data copying system provided in this application. In this embodiment, the data copying system includes a CPU, an accelerator, a communication bus, at least one computing unit, and M memory modules. M is an integer greater than or equal to 2. At least one computing unit is connected to at least one memory module via the communication bus. The CPU is connected to one computing unit, and / or, the accelerator is connected to one computing unit. It should be noted that this application does not limit the number of computing units or the devices connected to them. Figure 2 The diagram shows two computing units, one connected to the accelerator and the other connected to the CPU. This should not be construed as limiting the scope of this application. The computing unit can be hardware independent of the accelerator and CPU. The computing unit and the accelerator can be integrated or separate, or it can be a software functional module within the accelerator / CPU. Figure 2 Two memory modules are shown, but the number of memory modules can be more, and there is no limit here.

[0065] In this embodiment, the data copy system employs memory interleaving technology. This technology evenly interleaves data access across all memory channels of the system, essentially splitting the data into multiple sub-blocks and storing them across M memory modules. The number of data sub-blocks is determined by the data size and the interleaving granularity. The distribution of these sub-blocks across the M memory modules is then determined using the memory interleaving algorithm, specifying the memory module and storage address for each sub-block. The memory module corresponding to a data sub-block is the one storing that sub-block. The interleaving granularity is the size of the data sub-block.

[0066] To improve data copying efficiency, this embodiment employs distributed copying units, placing these units close to the memory modules to reduce the length of the data copying path and minimize the overhead on the communication bus. For example, each memory module can include a copying unit, meaning the copying execution end is located within the memory module. When the source and destination addresses of a data sub-block belong to the same memory module, data copying can be completed within the memory module using the copying unit within the memory module. This results in a short copying path and eliminates the need for data transmission via the communication bus.

[0067] The memory module includes a memory controller (such as DDRC). In one possible implementation, the copy unit can be located within the DDRC. In another possible implementation, the copy unit can also be a hardware unit independent of the DDRC; this is not a limitation.

[0068] In this embodiment, the CPU / accelerator issues a data copy instruction, which may include the source address and destination address of the target data, as well as the length of the target data. The data copy instruction instructs the target data to be copied from the source address to the destination address.

[0069] The computing unit, connected to the CPU / accelerator, calculates the distribution of target data across M memory modules based on data copy instructions. Assume the target data comprises K data sub-blocks, where K is an integer greater than or equal to 2. The computing unit determines the first and second distribution information of the K data sub-blocks using a memory interleaving algorithm, based on the interleaving granularity, the size (i.e., length) of the target data, the source address, and the destination address. The first distribution information includes the memory module to which each of the K data sub-blocks at the source address belongs, and the second distribution information includes the memory module to which each of the K data sub-blocks at the destination address belongs.

[0070] Furthermore, based on the first distribution information and the second distribution information, the computing unit can determine whether each data sub-block is copied across memory modules, that is, whether the source address and destination address of each data sub-block belong to the same memory module. For data sub-blocks that are not copied across memory modules, i.e., data sub-blocks whose source address and destination address belong to the same memory module, it can be determined that the copying unit in the memory module to which it belongs will perform the copying. For data sub-blocks that are copied across memory modules, i.e., data sub-blocks whose source address and destination address belong to different memory modules, it can be determined that the copying unit in the memory module to which the source address belongs will perform the copying. Of course, for data sub-blocks that are copied across memory modules, it can also be determined that the copying unit in the memory module to which the destination address belongs will perform the copying. This embodiment uses the example of cross-memory module copying by the copying unit in the memory module to which the source address belongs as an example for explanation.

[0071] The computing unit can further send messages to the memory module to instruct the copying unit in the memory module to copy data sub-blocks. In one possible implementation, the computing unit can send one message to the corresponding memory module for each data sub-block. In another possible implementation, if at least two data sub-blocks have source addresses belonging to the same memory module and destination addresses belonging to the same memory module, the computing unit can instruct the copying of these at least two data sub-blocks using the same message.

[0072] like Figure 3 As shown, Figure 3 This is a schematic diagram of a message format provided in this application. In this embodiment, the message sent by the computing unit to the memory module may include the source address, destination address, and data length indication information of the data to be copied (at least one data sub-block). Thus, the copying unit in the memory module can read the data to be copied according to the source address and data length information, and write the data to the destination address. Since the length of each data sub-block is at the interleaving granularity, in one possible implementation, the data length indication information in the message can be the product of the number of data sub-blocks to be copied and the interleaving granularity. In another possible implementation, the data length indication information in the message can be the number of data sub-blocks to be copied, in which case the copying unit obtains the length of the data to be copied based on the number of data sub-blocks to be copied and the interleaving granularity. Optionally, the message may also include the interleaving granularity, so that the copying unit can determine the address distribution in the M memory modules according to the interleaving granularity and the memory interleaving algorithm, and can also determine the length of the data to be copied according to the interleaving granularity and the number of data sub-blocks to be copied. Of course, the interleaving granularity can be configured in the copying unit and does not need to be carried through the message. The copy unit in the memory module that receives the message can determine whether the data to be copied indicated by the message is to be copied across memory modules, and if the data to be copied is to be copied across memory modules, the memory module to which the destination address belongs, based on the destination address in the message and the address distribution of the M memory modules.

[0073] Taking the first memory module out of M memory modules as an example, if the computing unit determines that the first data in the first memory module will not be copied across memory modules, the computing unit sends a first message to the first memory module. The first message includes a first address and a second address, used to indicate that the first data will be copied from the first address to the second address. The first address is the source address of the first data, and the second address is the destination address of the first data. It should be noted that the first address and the second address are the least significant bits of the first data. The first data includes N data sub-blocks out of K data sub-blocks. N is an integer greater than or equal to 1. The first message also includes data length indication information for the first data, which can be N*interleaving granularity or N. Thus, after receiving the first message, the first copying unit in the first memory module reads the first data from the corresponding position in the first memory module according to the first address and the data length indication information in the first message. The first copying unit also determines whether the second address belongs to the first memory module based on the destination address. If the second address belongs to the first memory module, the first copying unit writes the first data to the address range corresponding to the second address, completing the internal copy of the first data in the first memory module.

[0074] If the computing unit determines that the second data in the second memory module is copied across memory modules, and the destination address of the second data belongs to the second memory module, then the computing unit sends a second message to the first memory module. The second message includes a third address and a fourth address, used to instruct that the second data at the third address in the first memory module be copied to the fourth address in the second memory module. The third address is the source address of the second data, and the fourth address is the destination address of the second data. It should be noted that the third and fourth addresses are the least significant bits of the second data. The second data includes at least one of N data sub-blocks, for example, the second data includes S data sub-blocks. S is an integer greater than or equal to 1. The second message also includes data length indication information for the second data, which can be S*interleaving granularity or simply S. Therefore, after receiving the second message, the first copying unit in the first memory module reads the second data from the corresponding position in the first memory module according to the third address and the data length indication information in the second message. The first copying unit also determines whether the fourth address belongs to the second memory module based on the destination address and sends the second data and the fourth address to the second memory module. The second copy unit in the second memory module obtains the second data and the fourth address, and writes the second data into the address range corresponding to the fourth address, completing the cross-memory module copy of the second data. Therefore, the data to be copied can be transferred only once on the bus to complete the cross-memory module copy, reducing the data copy's occupancy on the communication bus and improving data copy efficiency.

[0075] When the source and destination addresses of the data to be copied belong to the same memory module, the copy unit needs to determine whether the destination address is within the address range corresponding to the source address. This determines whether to copy the data in descending or ascending order to ensure the data is completely copied to the destination address. Copying in descending order means writing data from the most significant byte to the least significant byte. Copying in ascending order means writing data from the least significant byte to the most significant byte.

[0076] For example, when the first copy unit copies the first data, it can determine whether the second address is within the first address range based on the first message. That is, the second address is greater than the first address and less than the first address plus the length of the first data. Here, the first address range is the range corresponding to the source address of the first data, i.e., the address range corresponding to the storage control where the first data is stored before copying. The first address range is the address range defined by the first address and the length of the first data. If the second address is within the first address range, the first copy unit copies the first data to the second address range in descending order of address. If the second address is not within the first address range, the first copy unit copies the first data to the second address range in ascending order of address. The second address range is the address range corresponding to the destination address of the first data, i.e., the address range corresponding to the storage control where the first data is stored after copying. The second address range is the address range defined by the second address and the length of the first data.

[0077] There are several methods for the first copy unit to determine whether the second address is within the first address range. In one possible implementation, the first message includes overlap indication information, which indicates whether the second address is within the first address range. For example, the overlap indication information in the first message may occupy one bit; when the value of this bit is 0, it indicates that the second address is within the first address range, and when the value of this bit is 1, it indicates that the second address is not within the first address range. Alternatively, when the value of this bit is 0, it indicates that the second address is not within the first address range, and when the value of this bit is 1, it indicates that the second address is within the first address range. Of course, the overlap indication information in the first message may occupy more bits; this is not limited here. Thus, the first copy unit can determine whether the second address is within the first address range based on the overlap indication information in the first message. In this case, the calculation unit determines the first address range based on the first address and the length of the first data, and determines whether the second address is within the first address range to determine the overlap indication information in the first message.

[0078] In another possible implementation, the first message may not include overlap indication information. Instead, the first copy unit determines whether the second address is within the range of the first address based on the first address, the second address, and the data length indication information in the first message. The first copy unit can obtain the length of the first data based on the data length indication information. The first copy unit determines the range of the first address based on the first address and the length of the first data, and then determines whether the second address is within the range of the first address.

[0079] In this embodiment, a distributed copy unit is employed, with copy units set up within each memory module, allowing the copy units to perform data copying locally. For data sub-blocks whose source and destination addresses belong to the same memory module, the copy unit within that memory module can complete the data copying within the memory module itself, eliminating the need for data transmission via the communication bus. This reduces the data copying path and improves data copying efficiency. For data sub-blocks copied across memory modules, the data copying can also be completed in a single transmission, reducing the occupancy of the communication bus and improving copying efficiency. Furthermore, for data copies that do not cross memory modules (i.e., data copies within the same memory module), the copy unit determines whether to use descending or ascending address order for data copying based on whether the address ranges corresponding to the source and destination addresses of the data overlap. This ensures that the data is completely copied to the destination address, guaranteeing data accuracy and integrity.

[0080] To make this solution easier to understand, examples are provided below.

[0081] Taking a data copy system including computing units, DDR1, and DDR2 as an example. DDR1 includes DDRC1, which includes data copy unit 1. DDR2 includes DDRC2, which includes copy unit 2. Assuming the address interleaving granularity in DDRC is 64B, the address distribution is as follows: DDRC1 includes addresses 0x00, 0x80, 0x100, and 0x180; DDRC2 includes addresses 0x40, 0xC0, 0x140, and 0x1C0.

[0082] Scenario 1: Copy 192 bytes of data (number 1) from source address 0x00 to destination address 0x100.

[0083] like Figure 4As shown, based on the interleaving granularity information, the calculation unit can determine that the data to be copied, 1, comprises three data sub-blocks: data sub-block 1, data sub-block 2, and data sub-block 3. Specifically, the source address of data sub-block 1 is 0x00, and the destination address is 0x100. The source address of data sub-block 2 is 0x40, and the destination address is 0x140. The source address of data sub-block 3 is 0x80, and the destination address is 0x180. According to the memory interleaving algorithm, the calculation unit can determine that source addresses 0x00 and 0x80, and destination addresses 0x100 and 0x180, all belong to DDRC1, while source address 0x40 and destination address 0x140 both belong to DDRC2. That is, the source and destination addresses of data sub-blocks 1 and 3 both belong to DDR1, and the source and destination addresses of data sub-block 2 both belong to DDR2.

[0084] The copy instructions for data sub-block 1 and data sub-block 3 can be combined into the same message. The computing unit sends message 1 to DDR1, which includes the source address (0x00) and destination address (0x100) of data sub-block 1, as well as 128 bytes of data length indication information. Since data sub-block 1 and data sub-block 3 are contiguous in the same DDR, message 1 can include only the source and destination addresses of the lower-address data sub-block (i.e., data sub-block 1), and the copy of data sub-block 3 can be implicitly indicated through the data length indication information. Of course, message 1 can also carry the source address, destination address, and corresponding data length information for data sub-block 1 and data sub-block 3 respectively; this is not restricted here. The computing unit sends message 2 to DDR2, which includes the source address (0x40) and destination address (0x140) of data sub-block 2, as well as 64 bytes of data length indication information.

[0085] After receiving message 1, copy unit 1 in DDR1 determines that the destination address 0x100 belongs to DDR1, and that data sub-block 1 and data sub-block 3 are internal copies of DDR1. It reads 128B of data from the source address 0x00, that is, reads data sub-block 1 and data sub-block 3, and then writes it to the destination address 0x100, thereby completing the copy of data sub-block 1 and data sub-block 3.

[0086] After receiving message 2, copy unit 2 in DDR2 determines that destination address 0x140 belongs to DDR2 and data sub-block 2 is an internal copy of DDR2. It reads 64B of data from source address 0x40, i.e., reads data sub-block 2, and then writes it to destination address 0x140, thus completing the copy of data sub-block 2.

[0087] Scenario 2: 192 bytes of data (1) need to be copied from source address 0x00 to destination address 0xC0.

[0088] like Figure 5As shown, based on the interleaving granularity information, the calculation unit can determine that the data to be copied, 1, comprises three data sub-blocks: data sub-block 1, data sub-block 2, and data sub-block 3. Specifically, the source address of data sub-block 1 is 0x00, and the destination address is 0xC0. The source address of data sub-block 2 is 0x40, and the destination address is 0x100. The source address of data sub-block 3 is 0x80, and the destination address is 0x140. According to the memory interleaving algorithm, the calculation unit can calculate that source address 0x00 belongs to DDRC1, and the corresponding destination address 0xC0 belongs to DDRC2, meaning that the source address of data sub-block 1 belongs to DDR1, and the destination address belongs to DDR2. Similarly, source address 0x80 belongs to DDRC1, and the corresponding destination address 0x140 belongs to DDRC2, meaning that the source address of data sub-block 3 belongs to DDR1, and the destination address belongs to DDR2. The source address 0x40 belongs to DDRC2, and the corresponding destination address 0x100 belongs to DDRC1. That is, the source address of data sub-block 2 belongs to DDR2, and the destination address belongs to DDR1.

[0089] The copy instructions for data sub-block 1 and data sub-block 3 can be combined into the same message. The computing unit sends message 3 to DDR1, which includes the source address (0x00) and destination address (0xC0) of data sub-block 1, as well as 128 bytes of data length indication information. Since data sub-block 1 and data sub-block 3 are contiguous in the same DDR, message 3 can include only the source and destination addresses of the lower-address data sub-block (i.e., data sub-block 1), and the copy of data sub-block 3 can be implicitly indicated through the data length indication information. Of course, message 3 can also carry the source address, destination address, and corresponding data length information for data sub-block 1 and data sub-block 3 respectively; this is not restricted here. The computing unit sends message 4 to DDR2, which includes the source address (0x40) and destination address (0x100) of data sub-block 2, as well as 64 bytes of data length indication information.

[0090] After receiving message 3, copy unit 1 in DDR1 determines that the destination address 0xC0 belongs to DDR2, meaning that data sub-blocks 1 and 3 are copied across DDR. It then reads 128 bytes of data from the source address 0x00, i.e., reads data sub-blocks 1 and 3. Copy unit 1 in DDR1 sends the destination address 0xC0, along with data sub-blocks 1 and 3, to DDR2. Copy unit 2 in DDR2 receives the destination address 0xC0, data sub-blocks 1 and 3, and writes them back to the destination address 0xC0, thus completing the cross-DDR copy of data sub-blocks 1 and 3.

[0091] After receiving message 4, copy unit 2 in DDR2 determines that destination address 0x100 belongs to DDR1, meaning data sub-block 2 is a cross-DDR copy. It then reads 64 bytes of data from source address 0x40, i.e., reads data sub-block 2. Copy unit 2 in DDR2 sends destination address 0x100 and data sub-block 2 to DDR1. Copy unit 1 in DDR1 receives destination address 0x100 and data sub-block 2, and writes it to destination address 0x100, thus completing the cross-DDR copy of data sub-block 2.

[0092] It should be noted that the examples above should not be construed as limiting this application. In practice, when a DDR includes multiple data sub-blocks belonging to the same data, the multiple data sub-blocks may not be copied across DDRs, or they may all be copied across DDRs, or some may be copied across DDRs and some may not. Furthermore, the DDR may or may not copy data sub-blocks from other DDRs, depending on the actual situation, and this application does not impose any restrictions on this.

[0093] like Figure 6 As shown, Figure 6 This is a flowchart illustrating a data copying method provided in this application. This embodiment is... Figure 2 The copy unit in the data copying system is used for implementation. Taking the first memory stick out of M memory sticks in the data copying system as an example, the first memory stick includes a first copy unit. This embodiment includes the following steps:

[0094] S601: The first copy unit obtains a first message, which is used to instruct the copying of the first data at the first address in the first memory module to the second address in the first memory module.

[0095] The first data is a part of the target data, which is stored in M ​​memory modules through memory interleaving. The target data includes K data sub-blocks, and each of the M memory modules stores at least one data sub-block. The first data includes N data sub-blocks from the K data sub-blocks. K and M are integers greater than or equal to 2, and N is an integer greater than or equal to 1.

[0096] The first message may include the source address (i.e., the first address) of the first data, the destination address (i.e., the second address) of the first data, and data length indication information of the first data. Optionally, the first message may also include overlap indication information. The message format of the first message can be found in the relevant description above, so it will not be repeated here.

[0097] S602: According to the first message, the first copy unit copies the first data in the first memory module to the second address.

[0098] The source and destination addresses of the first data both belong to the first memory module. The copying of the first data can be completed within the first memory module through the first copy unit, thereby reducing the data copy path length, reducing the occupation of the communication bus, and improving the data copying efficiency.

[0099] The process of the first data copying unit copying the first data according to the first message can be referred to the relevant description above, so it will not be repeated here.

[0100] Optionally, this embodiment may further include the following steps:

[0101] S603: The first copy unit obtains a second message, which is used to instruct the copying of the second data at the third address in the first memory module to the fourth address in the second memory module. The second data includes at least one data sub-block, and the second memory module is one of the M memory modules.

[0102] S604: According to the second message, the first copy unit sends the second data and the fourth address to the second memory module.

[0103] The content of the second message and the process by which the first copy unit copies the second data based on the second message can be found in the relevant description above, so they will not be repeated here.

[0104] S603 and S604 in Figure 6 The dashed boxes are used to indicate this. It should be noted that there is no specific order between S601-S602 and S603-S604.

[0105] In this embodiment, a distributed copy unit is employed, with copy units set up within each memory module, allowing the copy units to perform data copying locally. For data sub-blocks whose source and destination addresses belong to the same memory module, the copy unit within that memory module can complete the data copying within the memory module itself, eliminating the need for data transmission via the communication bus. This reduces the data copying path and improves data copying efficiency. For data sub-blocks copied across memory modules, the data copying can also be completed in a single transmission, reducing the occupancy of the communication bus and improving copying efficiency. Furthermore, for data copies that do not cross memory modules (i.e., data copies within the same memory module), the copy unit determines whether to use descending or ascending address order for data copying based on whether the address ranges corresponding to the source and destination addresses of the data overlap. This ensures that the data is completely copied to the destination address, guaranteeing data accuracy and integrity.

[0106] like Figure 7 As shown, Figure 7 This is a flowchart illustrating another data copying method provided in this application. The execution entity in this embodiment is... Figure 2The computational unit within the [process]. This embodiment includes the following steps:

[0107] S701: Based on the source address of the target data, the destination address of the target data, the length of the target data, and the memory interleaving algorithm, determine the first distribution information and the second distribution information of the K data sub-blocks of the target data in M ​​memory modules. The first distribution information includes the memory module to which each data sub-block in the K data sub-blocks in the source address belongs, and the second distribution information includes the memory module to which each data sub-block in the K data sub-blocks in the destination address belongs. K is an integer greater than or equal to 2, and M is an integer greater than or equal to 2.

[0108] S702: Based on the first distribution information and the second distribution information, determine whether the source address and destination address of each data sub-block belong to the same memory module.

[0109] S703: If the source address and destination address of the first data in the first memory stick of M memory sticks belong to the same memory stick, then send a first message to the first memory stick. The first data includes N data sub-blocks out of K data sub-blocks. The first message is used to indicate that the first data is copied from the first address to the second address in the first memory stick. The first address is the source address of the first data, the second address is the destination address of the first data, and N is an integer greater than or equal to 1.

[0110] Optionally, this embodiment further includes the following steps:

[0111] S704: If the destination address of the second data in the first memory stick of M memory sticks belongs to the second memory stick, then send a second message to the first memory stick. The first data includes at least one of the K data sub-blocks. The second message is used to instruct that the second data be copied from the third address in the first memory stick to the fourth address in the second memory stick. The third address is the source address of the second data, and the fourth address is the destination address of the second data.

[0112] The specific implementation of S701-S704 in this embodiment can be found in the relevant description of the computing unit above, so it will not be repeated here.

[0113] In this embodiment, a distributed copy unit is employed, with copy units set up within each memory module, enabling the copy units to perform data copying locally. The calculation unit determines whether the source and destination addresses of each data sub-block belong to the same memory module based on the first and second distribution information of each data sub-block. For data sub-blocks where the source and destination addresses belong to the same memory module, the calculation unit instructs the corresponding memory module to complete the data copy within that memory module using its copy unit, thus eliminating the need for data transmission via the communication bus, reducing the data copy path, and improving data copy efficiency. For data sub-blocks copied across memory modules, the calculation unit instructs the corresponding memory module to perform cross-memory module copying, which can also be completed in a single transmission, reducing the occupation of the communication bus and improving copy efficiency. Furthermore, for data copies not across memory modules (i.e., data copies within the same memory module), the calculation unit can determine whether the source and destination address ranges of the data to be copied overlap. This allows the addition of overlap indication information to the messages sent to the memory modules, instructing them to perform data copying in descending or ascending address order, ensuring that the data is completely copied to the destination address, guaranteeing data accuracy and integrity.

[0114] Based on the same inventive concept, this application also provides... Figure 6 and Figure 7 Corresponding device embodiments. For example... Figure 8 As shown, Figure 8 This is a schematic diagram of a data copying device provided in this application. The data copying device 800 is applied to a first copying unit, which is disposed in a first memory module.

[0115] The data copying device 800 includes an acquisition module 801, used to acquire a first message, the first message indicating that first data at a first address in a first memory module is copied to a second address in the first memory module. A copying module 802 is used to copy the first data from the first memory module to the second address according to the first message.

[0116] In one possible implementation, the first data is a portion of the target data, which is interleaved across M memory modules. The target data comprises K data sub-blocks, and each of the M memory modules stores at least one data sub-block. The first data comprises N data sub-blocks from the K data sub-blocks, and the first memory module is one of the M memory modules. K and M are integers greater than or equal to 2, and N is an integer greater than or equal to 1. When the target data is interleaved across multiple memory modules, the distributed copy unit can complete the copying of data sub-blocks locally, thereby reducing the number of times the target data is transmitted through the communication bus, reducing the occupation of the communication bus, and shortening the data copying path, thus improving data copying efficiency.

[0117] In one possible implementation, the acquisition module 801 is further configured to acquire a second message, the second message being configured to instruct the copying of second data at a third address in the first memory module to a fourth address in the second memory module, the second data including at least one data sub-block, the second memory module being one of M memory modules; the copy module 802 is configured to send the second data to the second memory module by the first copy unit according to the second message.

[0118] In one possible implementation, the length of each of the N data sub-blocks is the interleaving granularity of the memory interleaving. The first message also includes data length indication information, which indicates the length of the first data. The data length indication information is the product of N and the interleaving granularity, or the data length indication information is N, where N is an integer greater than or equal to 1. Therefore, when multiple data sub-blocks have source addresses belonging to the same memory module and destination addresses belonging to the same memory module, they can be merged into a single message for data copy indication, reducing the number of messages and improving data copy efficiency.

[0119] In one possible implementation, the copy unit is configured to determine whether the second address is within the first address range based on the first message, wherein the first address range is an address range defined by the length of the first address and the first data; the copy unit is configured to copy the first data in the first address range to the second address range in descending order when the second address is within the first address range, wherein the second address range is an address range defined by the length of the second address and the first data; and the copy unit is configured to copy the first data in the first address range to the second address range in ascending order when the second address is not within the first address range.

[0120] In one possible implementation, the first message further includes overlap indication information, which is used to indicate whether the second address is within the range of the first address. The copying unit is used to determine whether the second address is within the range of the first address based on the overlap indication information.

[0121] In one possible implementation, the copy unit is used to determine the first address range based on the first address and data length information; and to determine whether the second address is within the first address range.

[0122] In one possible implementation, the first memory module further includes a first memory module controller, and the first copy unit is disposed in the first memory module controller.

[0123] like Figure 9 As shown, Figure 9This application provides a schematic diagram of another data copying device. The data copying device 900 is applied to a computing unit. The data copying device 900 includes: a processing module 901, used to determine, based on the source address of the target data, the destination address of the target data, the length of the target data, and a memory interleaving algorithm, the first distribution information and the second distribution information of K data sub-blocks of the target data in M ​​memory modules. The first distribution information includes the memory module to which each data sub-block in the K data sub-blocks of the source address belongs, and the second distribution information includes the memory module to which each data sub-block in the K data sub-blocks of the destination address belongs, where K is an integer greater than or equal to 2, and M is an integer greater than or equal to 2; the processing module 901 is used to... Based on the first distribution information and the second distribution information, it is determined whether the source address and destination address of each data sub-block belong to the same memory module; the transceiver module 902 is used to send a first message to the first memory module when the source address and destination address of the first data in the first memory module of M memory modules belong to the same memory module. The first data includes N data sub-blocks in K data sub-blocks. The first message is used to instruct the first data to be copied from the first address to the second address in the first memory module. The first address is the source address of the first data, the second address is the destination address of the first data, and N is an integer greater than or equal to 1.

[0124] In one possible implementation, the transceiver module 902 is used to send a second message to the first memory module when the destination address of the second data in the first memory module out of M memory modules belongs to the second memory module. The second data includes at least one of K data sub-blocks, and the first data is different from the second data. The second message is used to instruct the second data to be copied from a third address in the first memory module to a fourth address in the second memory module, where the third address is the source address of the second data and the fourth address is the destination address of the second data.

[0125] In one possible implementation, processing module 901 is used to determine a first address range based on the length of the first address and the first data; processing module 901 is also used to determine whether the second address is within the first address range to obtain overlap indication information. The overlap indication information is used to indicate whether the second address is within the first address range. The first address range is the address range defined by the length of the first address and the second data.

[0126] like Figure 10 As shown, Figure 10 This is a schematic diagram of a data copying device provided in an embodiment of this application. In this embodiment, the data copying device 1000 may be... Figure 2 The copy unit, DDRC, and DDR are mentioned. Alternatively, the data copy device 1000 can be... Figure 2 The computational unit in the process.

[0127] The data copying device 1000 includes a bus 1001, a processor 1002, a communication interface 1003, and a memory 1004. The processor 1002, the memory 1004, and the communication interface 1003 communicate with each other via the bus 1001.

[0128] Bus 1001 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0129] The processor 1002 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0130] The memory 1004 may include volatile memory, such as random access memory (RAM).

[0131] The memory 1004 can be used to store software code related to the data copying method, and the processor 1002 can execute the steps of the data copying method and schedule other units to achieve the corresponding functions.

[0132] It should be understood that the data copying device 1000 can be a centralized or distributed device, and the processor 1002 in the data copying device 1000 can be a hardware circuit (such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.) or a combination of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or a DSP, or a hardware system without instruction execution capabilities, such as an ASIC or an FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0133] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, implements the data copying method flow of the above method embodiments.

[0134] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0135] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, implements the data copying method flow of the above method embodiments.

[0136] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between devices or units, and may be electrical or other forms.

[0138] The units described as discrete components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of this application can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A data copying method, characterized in that, The method is applied to a first copy unit, which is located in a first memory module. The method includes: The first copy unit acquires a first message, which instructs that the first data at a first address in the first memory module be copied to a second address in the first memory module. According to the first message, the first copy unit copies the first data in the first memory module to the second address.

2. The method according to claim 1, characterized in that, The first data is a part of the target data, which is stored in M ​​memory modules through memory interleaving. The target data includes K data sub-blocks, and each of the M memory modules stores at least one of the data sub-blocks. The first data includes N of the K data sub-blocks. The first memory module is one of the M memory modules. K and M are integers greater than or equal to 2, and N is an integer greater than or equal to 1.

3. The method according to claim 2, characterized in that, The method further includes: The first copy unit obtains a second message, which is used to instruct the copying of second data at the third address in the first memory stick to the fourth address in the second memory stick. The second data includes at least one of the data sub-blocks, and the second memory stick is one of the M memory sticks. According to the second message, the first copy unit sends the second data and the fourth address to the second memory module.

4. The method according to claim 2 or 3, characterized in that, The length of each of the N data sub-blocks is the interleaving granularity of memory interleaving. The first message also includes data length indication information, which is used to indicate the length of the first data. The data length indication information is the product of N and the interleaving granularity, or the data length indication information is N, where N is an integer greater than or equal to 1.

5. The method according to claim 4, characterized in that, According to the first message, the first copy unit copies the first data in the first memory module to the second address, including: Based on the first message, it is determined whether the second address is within the first address range, where the first address range is the address range defined by the length of the first address and the first data. If the second address is within the range of the first address, then the first data in the first address range is copied to the second address range in descending order of address. The second address range is the address range defined by the length of the second address and the first data. If the second address is not within the first address range, the first data in the first address range is copied to the second address range in ascending order of address.

6. The method according to claim 5, characterized in that, The first message further includes overlap indication information, which is used to indicate whether the second address is within the first address range. Determining whether there is overlap between the first address range and the second address range in the first memory module based on the first message includes: Based on the overlap indication information, determine whether the second address is within the range of the first address.

7. The method according to claim 5, characterized in that, The step of determining whether the second address is within the range of the first address based on the first message includes: The first address range is determined based on the first address and the data length information; Determine whether the second address is within the range of the first address.

8. A data copying method, characterized in that, The method includes: Based on the source address of the target data, the destination address of the target data, the length of the target data, and the memory interleaving algorithm, the first distribution information and the second distribution information of the K data sub-blocks of the target data in M ​​memory modules are determined. The first distribution information includes the memory module to which each of the K data sub-blocks in the source address belongs, and the second distribution information includes the memory module to which each of the K data sub-blocks in the destination address belongs. K is an integer greater than or equal to 2, and M is an integer greater than or equal to 2. Based on the first distribution information and the second distribution information, determine whether the source address and destination address of each data sub-block belong to the same memory module; If the source address and destination address of the first data in the first memory block of the M memory blocks belong to the same memory block, then a first message is sent to the first memory block. The first data includes N data sub-blocks among the K data sub-blocks. The first message is used to instruct the first data to be copied from the first address to the second address in the first memory block. The first address is the source address of the first data, the second address is the destination address of the first data, and N is an integer greater than or equal to 1.

9. A data copying device, characterized in that, The apparatus includes modules for implementing the method of any one of claims 1 to 8.

10. A data copying device, characterized in that, Including processor and memory: The processor is configured to execute a computer program or instructions stored in the memory, wherein when the processor executes the computer program or instructions, the method described in any one of claims 1 to 8 is performed.

11. A chip, characterized in that, The method includes a processor coupled to a memory for executing a computer program or instructions stored in the memory, wherein when the processor executes the computer program or instructions, the method described in any one of claims 1 to 8 is performed.

12. A computer-readable storage medium, characterized in that, The system stores instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 8.

13. A computer program product, characterized in that, The device stores computer-readable instructions that, when read and executed by the data copying device, cause the data copying device to perform the method as described in any one of claims 1 to 8.

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