Trap management device, processor, chip and electronic equipment
By using a hardware-coordinated trap management scheme to pause instruction issuance by processor threads, the problem of low resource utilization in existing technologies is solved, achieving more efficient resource utilization and energy efficiency.
CN122152643APending Publication Date: 2026-06-05MOORE THREADS TECH CO LTD
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Patent Information
- Application Number
- CN202610628786.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-09
- Publication Date
- 2026-06-05
AI Technical Summary
Technical Problem
In existing technologies, trap management relies on software implementation, which causes the processor to occupy hardware resources while waiting for trap events, resulting in low resource utilization and unnecessary power consumption.
Method used
By introducing a processor-level trap management unit and a core-level trap control unit, the instruction issuance of threads is paused through hardware coordination, and interaction with external debuggers is achieved through interrupts and registers, thereby reducing the consumption of processor computing resources.
Benefits of technology
It improves the processor's resource utilization efficiency in debugging or monitoring scenarios, reduces unnecessary usage, and enhances resource utilization and energy efficiency.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention relates to the technical field of computers, in particular to a trap management device, a processor, a chip and electronic equipment, and the device comprises at least one processing core which is used for executing threads; a processor trap management unit coupled to the at least one processing core; the interrupt reporting unit is coupled with the processor trap management unit; wherein the processing core responds to the situation that a thread executed in the processing core meets a trap condition, pauses execution of the thread and reports a trap event to the processor trap management unit; and the processor trap management unit responds to the received trap event, performs coordination management and triggers the interrupt reporting unit to report the interrupt to an external debugger. According to the embodiment of the invention, the resource utilization efficiency of the processor in a debugging or monitoring scene can be effectively improved.
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