An espi and lpc bus diagnostic method and apparatus

Abstract

The application relates to the technical field of bus diagnosis, and discloses an ESPI and LPC bus diagnosis method and device. The method is as follows: the STRAP pin level of a master control chip is configured through a jump cap short circuit state, so that the master control chip enters an LPC bus working mode or an ESPI bus working mode; a target mainboard is connected; an I / O write operation initiated by the target mainboard in a POST self-checking stage is listened to; when a frame start signal is detected, a start field of a bus frame is analyzed and determined as an I / O write operation type; an address field in the bus frame of the I / O write operation type is analyzed and matched with a target listening address; when the address is matched successfully, a POST Code diagnosis code is acquired from the bus frame. The application realizes a dynamic switching mechanism of the LPC and ESPI double bus protocols through hardware jump cap configuration of the STRAP pin, solves the technical problem that a diagnosis card only supports a single bus protocol in the prior art, and enables a single diagnosis card device to be compatible with all X86 platform mainboards.

Description

Technical Field

[0001] This invention relates to the field of bus diagnostics technology, and in particular to a diagnostic method and apparatus for ESPI and LPC buses. Background Technology

[0002] With the rapid development of the x86 platform in the PC industry, motherboard bus architecture has evolved from the low-speed LPC bus to the high-speed ESPI bus. The LPC bus inside the bridge chip has been completely replaced by the ESPI bus to meet the demands of higher data transfer rates and system performance. However, existing PC motherboard diagnostic cards have significant technical limitations. A single diagnostic card only supports one protocol, either the LPC bus or the ESPI bus, and cannot achieve cross-generational platform compatibility diagnostics. During prototype debugging and after-sales repair, engineers need to deal with motherboards with different bus architectures, including older platforms like H61, B75, and H81 with LPC buses, and newer platforms like H510, H610, and B760 with ESPI buses. Due to the lack of unified diagnostic tools, engineers must carry and maintain multiple sets of different types of fault detection equipment, which not only increases the complexity of equipment management and procurement costs but also reduces the efficiency of fault diagnosis. Summary of the Invention

[0003] The main objective of this invention is to provide a diagnostic method and device for both ESPI and LPC buses. This invention achieves a dynamic switching mechanism between LPC and ESPI dual bus protocols by configuring the STRAP pin with a hardware jumper cap, which solves the technical problem that existing diagnostic cards only support a single bus protocol, enabling a single diagnostic card device to be compatible with all X86 platform motherboards.

[0004] To achieve the above objectives, the present invention provides a diagnostic method for ESPI and LPC buses, comprising the following steps: Configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip can enter the LPC bus working mode or the ESPI bus working mode. Connect to the target motherboard via LPC pin header according to the LPC bus operating mode or via ESPI pin header according to the ESPI bus operating mode; The system monitors I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the system parses the start field of the bus frame and determines it to be an I / O write operation type. The address field in the bus frame of the I / O write operation type is parsed and matched with the target listening address. When the address matches successfully, the POST Code diagnostic code is obtained from the bus frame.

[0005] Optionally, in a first implementation of the first aspect of the present invention, configuring the STRAP pin level of the main control chip by shorting the jumper cap, thereby enabling the main control chip to enter LPC bus operating mode or ESPI bus operating mode, includes: When the jumper cap shorts the first and second pins of the three-pin jumper socket, the STRAP pin is pulled low by the pull-down resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a low level is read, the mode bit of the configuration register is written to the first logic value, and the LPC interface pin group is enabled while the ESPI interface pin group is disabled to enter the LPC bus working mode. When the jumper cap shorts the second and third pins of the three-pin jumper socket, the STRAP pin is pulled high through the pull-up resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a high level is read, the mode bit of the configuration register is written to the second logic value, and the ESPI interface pin group is enabled while the LPC interface pin group is disabled to enter the ESPI bus working mode.

[0006] Optionally, in a second implementation of the first aspect of the present invention, connecting the target motherboard via an LPC connector according to the LPC bus operating mode or via an ESPI connector according to the ESPI bus operating mode includes: When the main control chip is in the LPC bus working mode, the clock signal pin, frame synchronization signal pin, address data multiplexing signal pin, and reset signal pin of the LPC pin socket are connected to the corresponding pins of the LPC interface of the target motherboard via a ribbon cable. When the main control chip is in the ESPI bus working mode, the chip select signal pin, serial clock signal pin, data input / output signal pin, and reset signal pin of the ESPI socket are connected to the corresponding pins of the ESPI interface of the target motherboard via a ribbon cable. The main control chip is connected to the bus of the target motherboard as a bus slave device through the ribbon cable connection, and the bus interface pin of the main control chip and the bus pin of the target motherboard form an electrical path to enter the bus listening state.

[0007] Optionally, in a third implementation of the first aspect of the present invention, the I / O write operation initiated by the target motherboard during the POST self-test phase is monitored. When a frame start signal is detected, the start field of the bus frame is parsed and determined to be an I / O write operation type, including: When the main control chip is in the LPC bus working mode, it listens to the level change of the frame synchronization signal pin. When the frame synchronization signal changes from the first level to the second level, it is identified as a frame start signal. After the frame start signal of the LPC bus working mode is detected, the start field data is sampled through the address data multiplexing signal pin on the rising edge of the clock. When the start field data conforms to the I / O write cycle identifier, it is determined to be an I / O write operation type. When the main control chip is in the ESPI bus working mode, it listens to the level transition of the chip select signal pin. When the chip select signal is detected to transition from the first level to the second level, it is identified as the frame start signal. After the frame start signal of the ESPI bus working mode is detected, the command field data is sampled through the data input signal pin on the rising edge of the clock. When the command field data matches the I / O write command identifier, it is determined to be an I / O write operation type.

[0008] Optionally, in the fourth implementation of the first aspect of the present invention, after detecting the frame start signal of the ESPI bus operating mode, command field data is sampled through the data input signal pin on the rising edge of the clock. When the command field data conforms to the I / O write command identifier, it is determined to be an I / O write operation type, including: When the frame start signal of the ESPI bus operating mode is detected, the command field data is obtained by sampling through the data input signal pin on the rising edge of the clock. The command field data is compared bit by bit with the preset identifier value of the I / O write command to obtain the comparison result. When the comparison result is consistent, it is determined to be an I / O write operation type.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, parsing the address field in the bus frame of the I / O write operation type and matching it with the target listening address, and when the address match is successful, obtaining the POST Code diagnostic code from the bus frame, including: Within a continuous clock cycle after determining that it is an I / O write operation, the address field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin, and the address field data is compared bit by bit with the target listening address to obtain the address matching result. When the address matching result is a successful match, the data field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles, and the data field data is used as the POST Code diagnostic code.

[0010] Optionally, in a sixth implementation of the first aspect of the present invention, when the address matching result is a successful match, data field data is continuously sampled and obtained through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles, and the data field data is used as a POST Code diagnostic code, including: When the address matching result is a successful match, in LPC bus working mode, the data field data is obtained by segmenting the data through the address data multiplexing signal pin on the continuous rising edge of the clock after skipping the acknowledgment cycle, or in ESPI bus working mode, the data field data is obtained by sampling the data input signal pin on the continuous rising edge of the clock. The sampled segments of the data field are concatenated bit by bit to obtain the concatenated complete data, and the concatenated complete data is stored in a temporary data register as a POST Code diagnostic code.

[0011] Optionally, in a seventh implementation of the first aspect of the present invention, the ESPI and LPC bus diagnostic method further includes: After the sampling and acquisition of the POST Code diagnostic code is completed, a data valid signal is generated. On the trigger edge of the data valid signal, the POST Code diagnostic code stored in the temporary data register is latched and transmitted to the display data register. The POST Code diagnostic code output by the display data register is decomposed bit by bit, and the high-order bit segment is extracted as the high-order data and the low-order bit segment is extracted as the low-order data. The high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POST Code diagnostic code is displayed on a two-digit LED display using a dynamic scanning method.

[0012] Optionally, in the eighth implementation of the first aspect of the present invention, the high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POST Code diagnostic code is displayed on a two-digit LED display using a dynamic scanning method, including: The high-order data is used as the first lookup table index to read the corresponding high-order seven-segment code, and the low-order data is used as the second lookup table index to read the corresponding low-order seven-segment code. The high-order and low-order digit displays are alternately enabled according to a preset scanning frequency. When the high-order digit display is enabled, the high-order seven-segment code is output to drive the high-order digit display to show the high-order hexadecimal digits. When the low-order digit display is enabled, the low-order seven-segment code is output to drive the low-order digit display to show the low-order hexadecimal digits.

[0013] The present invention also provides an ESPI and LPC bus diagnostic device, comprising: The configuration module is used to configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip can enter the LPC bus working mode or the ESPI bus working mode. A connection module is used to connect to the target motherboard via an LPC pin header according to the LPC bus working mode or to the target motherboard via an ESPI pin header according to the ESPI bus working mode. The detection module is used to monitor the I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the start field of the bus frame is parsed and determined to be an I / O write operation type. The matching module is used to parse the address field in the bus frame of the I / O write operation type and match it with the target listening address. When the address match is successful, the POST Code diagnostic code is obtained from the bus frame.

[0014] In summary, this invention achieves a dynamic switching mechanism between the LPC and ESPI dual-bus protocols by configuring the STRAP pin with a hardware jumper cap. This solves the technical problem of existing diagnostic cards supporting only a single bus protocol, enabling a single diagnostic card device to be compatible with all x86 platform motherboards. This dual-bus switching mechanism controls the enable and disable states of the LPC and ESPI interface pin groups through configuration register mode bits, avoiding bus conflicts and ensuring signal integrity. The dual-interface design of the LPC and ESPI pin headers, combined with the ribbon cable connection method, allows for flexible selection of the corresponding pin header to establish an electrical connection based on the target motherboard's bus type, enabling fault diagnosis tasks on different platforms without replacing the diagnostic card hardware. The precise monitoring mechanism for the 80h port can capture the diagnostic code sequence written by the PC motherboard BIOS during the POST self-test phase in real time. Through a complete process of frame start signal detection, start field parsing, and address field matching, it accurately identifies the I / O write operation type and extracts the diagnostic code data. This invention combines seven-segment code lookup table decoding with dynamic scanning drive technology to intuitively display the POST Code diagnostic code in hexadecimal format using a two-digit LED display. This enables rapid location of fault nodes at each stage of CPU initialization, memory testing, graphics card initialization, and peripheral loading. This invention reduces equipment procurement and maintenance costs, improves the efficiency and accuracy of fault diagnosis, and solves the problem of engineers frequently changing equipment during hybrid platform maintenance tasks. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the steps of the ESPI and LPC bus diagnostic method in one embodiment of the present invention; Figure 2 This is a circuit diagram showing the STRAP pin mode configuration in an embodiment of the present invention; Figure 3 This is a power supply configuration jumper circuit diagram in an embodiment of the present invention; Figure 4 This is a schematic diagram of the pin connection of two seven-segment LED displays in an embodiment of the present invention; Figure 5 This is a power supply voltage conversion circuit diagram in an embodiment of the present invention; Figure 6 This is a schematic diagram of the ESPI bus interface connection circuit in an embodiment of the present invention; Figure 7 This is a block diagram of the ESPI and LPC bus diagnostic device in an embodiment of the present invention.

[0016] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Reference Figure 1 This embodiment provides a diagnostic method for ESPI and LPC buses, including the following steps: S1, configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip enters the LPC bus working mode or the ESPI bus working mode. S2, connect to the target motherboard via LPC pin header according to the LPC bus working mode or connect to the target motherboard via ESPI pin header according to the ESPI bus working mode; S3, listen for I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, parse the start field of the bus frame and determine it as an I / O write operation type. S4, parse the address field in the bus frame of the I / O write operation type and match it with the target listening address. When the address match is successful, obtain the POST Code diagnostic code from the bus frame.

[0019] In one example, the STRAP pin level of the main control chip is configured by shorting the jumper cap, enabling the main control chip to enter LPC bus operating mode or ESPI bus operating mode, including: When the jumper cap shorts the first and second pins of the three-pin jumper socket, the STRAP pin is pulled low by the pull-down resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a low level is read, the mode bit of the configuration register is written to the first logic value, and the LPC interface pin group is enabled while the ESPI interface pin group is disabled to enter the LPC bus working mode. When the jumper cap shorts the second and third pins of the three-pin jumper socket, the STRAP pin is pulled high through the pull-up resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a high level is read, the mode bit of the configuration register is written to the second logic value, and the ESPI interface pin group is enabled while the LPC interface pin group is disabled to enter the ESPI bus working mode.

[0020] Figure 2 This is a circuit diagram of the STRAP pin mode configuration circuit of the present invention. In the diagram, pin 1 of the three-pin jumper DBJJ2 is connected to ground (GND) via pull-down resistor DBR23, and pin 3 is connected to the 3.3V power supply (3VSB) via pull-up resistor DBR25. Pin 2 is the middle connection pin JP3 of the jumper cap, used to configure the STRAP pin level of the main control chip by shorting the jumper cap. When pins 1 and 2 are shorted by the jumper cap, the STRAP pin is pulled low by pull-down resistor DBR23, and the main control chip enters LPC bus operating mode; when pins 2 and 3 are shorted by the jumper cap, the STRAP pin is pulled high by pull-up resistor DBR25, and the main control chip enters ESPI bus operating mode.

[0021] In this example, a three-pin jumper socket, designated J1, is placed on the diagnostic card PCB. Pins 1, 2, and 3 are connected. Pin 1 is connected to ground (GND) via a 10kΩ pull-down resistor. Pin 3 is connected to the 3.3V power supply (VCC) via a pull-up resistor of the same value. Pin 2 is directly connected to the STRAP configuration pin (e.g., pin 46) of the main control chip. This pin is used to read the voltage level during power-on reset to determine the chip's operating mode. When the engineer shorts the jumper cap between pins 1 and 2 of J1, the STRAP pin is pulled low because pin 1 is connected to ground and forms an electrical path with the STRAP pin through the pull-down resistor R1. After the main control chip powers on and completes the reset process, its internal configuration logic immediately reads the level state of the STRAP pin. Upon recognizing a low level, it automatically writes the first logic value (logic 0) to bit 0 of the mode bit in the configuration register (e.g., the register at address 0x2E). Simultaneously, the control circuit enables the LPC interface pin group and disables the ESPI interface pin group, entering the LPC bus operating mode. In this mode, the chip's LCLK, LFRAME#, LAD0 to LAD3, and LRESET# pins are configured as input / output pins with specific functions for communication with the LPC bus on the motherboard. Meanwhile, ESPI-related pins such as CS#, SCLK, MISO, and MOSI are all set to a high-impedance state to avoid bus conflicts caused by signal interference. When the engineer shorts the jumper between pins 2 and 3 of J1, the STRAP pin is pulled to a logic high level because pin 3 is connected to a 3.3V power supply and is electrically connected to the STRAP pin through pull-up resistor R2. When a high-level signal is detected when the chip is reset and the STRAP pin status is read again, the configuration logic writes the second logic value, i.e., logic 1, to bit 0 of the 0x2E register and immediately enables the ESPI interface pin group while disabling the LPC interface pin group. At this time, the chip enters the ESPI bus working mode. In this mode, ESPI-related pins such as CS#, SCLK, MISO, MOSI, RESET#, and ALERT# are activated and configured as push-pull output or input modes as needed, while all LPC-related pins enter a high-impedance disabled state.

[0022] Figure 3 This is a circuit diagram of the power supply jumper circuit for this invention. In the diagram, pin 1 of the three-pin jumper connector DBJI4 is connected to the 3.3V backup power supply 3VSB, pin 2 is the intermediate connection pin outputting a 3.3V_SIO signal, and pin 3 is connected to the 3.3V main power supply VCC3. In the default configuration, the jumper cap shorts pins 1 and 2, allowing the diagnostic card to be powered through the backup power supply 3VSB, ensuring that the diagnostic card can still function normally when the motherboard is in standby mode.

[0023] In one example, connecting the target motherboard via an LPC header according to the LPC bus operating mode or via an ESPI header according to the ESPI bus operating mode includes: When the main control chip is in the LPC bus working mode, the clock signal pin, frame synchronization signal pin, address data multiplexing signal pin, and reset signal pin of the LPC pin socket are connected to the corresponding pins of the LPC interface of the target motherboard via a ribbon cable. When the main control chip is in the ESPI bus working mode, the chip select signal pin, serial clock signal pin, data input / output signal pin, and reset signal pin of the ESPI socket are connected to the corresponding pins of the ESPI interface of the target motherboard via a ribbon cable. The main control chip is connected to the bus of the target motherboard as a bus slave device through the ribbon cable connection, and the bus interface pin of the main control chip and the bus pin of the target motherboard form an electrical path to enter the bus listening state.

[0024] In this example, the hardware switching of the protocol mode is completed based on the level state of the STRAP pin. When the main control chip is configured to LPC bus operating mode, its internal configuration logic will automatically enable the LPC pin group, including the LCLK clock input pin, the LFRAME# frame synchronization signal pin, the four address-data multiplexed pins LAD0 to LAD3, and the LRESET# reset pin. At this time, all ESPI related pins enter a high-impedance disabled state to avoid signal conflicts. The engineer uses a 14-pin ribbon cable to precisely connect the LPC pin header J2 on the diagnostic card PCB to the LPC interface of the target motherboard. The header adopts a standard 2×7 dual-row structure. Pins 5 to 10 correspond to the LCLK, LFRAME#, and LAD0 to LAD3 signal pins of the main control chip, respectively. Pin 11 corresponds to the LRESET# reset signal. The remaining pins are used for power and ground connections. After the connection is made through the ribbon cable, the LPC pin group of the main control chip forms a complete electrical path with the LPC bus of the motherboard chipset, realizing the mounting of the main control chip on the LPC bus and entering the bus listening state. When the main control chip is in ESPI bus operating mode, its configuration logic activates the ESPI pin group, including the CS# chip select signal pin, SCLK serial clock pin, MOSI data input pin, MISO data output pin, RESET# reset pin, and ALERT# alarm pin. LPC-related pins are set to high impedance and disabled to prevent bus interference. In this mode, engineers use a 10-pin ribbon cable to connect the ESPI header J3 on the diagnostic card to the target motherboard's ESPI interface. The ESPI header has a 2×5 structure, with pins 5 through 9 corresponding to the core signal lines CS#, SCLK, MISO, MOSI, and RESET#, respectively. This physical connection completes the slave-to-master connection between the main control chip and the motherboard's ESPI bus. Regardless of the bus mode, the diagnostic card's main control chip acts as a slave device, forming a master-slave communication structure with the motherboard chipset. The connection between the chip's bus interface pins and the motherboard bus pins establishes a signal transmission path, ensuring that the diagnostic card can receive bus operation requests initiated by the motherboard BIOS during the POST self-test in real time. Based on this, the main control chip starts the internal bus state machine, continuously listens to the start flag and address field of the bus transaction frame or command packet, and determines in real time whether it is an I / O write operation of port 80h, thereby entering the sampling and display process of diagnostic codes.

[0025] In one example, the system listens for I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the start field of the bus frame is parsed and determined to be an I / O write operation type, including: When the main control chip is in the LPC bus working mode, it listens to the level change of the frame synchronization signal pin. When the frame synchronization signal changes from the first level to the second level, it is identified as a frame start signal. After the frame start signal of the LPC bus working mode is detected, the start field data is sampled through the address data multiplexing signal pin on the rising edge of the clock. When the start field data conforms to the I / O write cycle identifier, it is determined to be an I / O write operation type. When the main control chip is in the ESPI bus working mode, it listens to the level transition of the chip select signal pin. When the chip select signal is detected to transition from the first level to the second level, it is identified as the frame start signal. After the frame start signal of the ESPI bus working mode is detected, the command field data is sampled through the data input signal pin on the rising edge of the clock. When the command field data matches the I / O write command identifier, it is determined to be an I / O write operation type.

[0026] In this example, when the main control chip is in LPC bus operating mode, its internal bus state machine continuously monitors the level changes of the LFRAME# frame synchronization signal pin. Specifically, in the default high-level maintenance state, when the LFRAME# signal is detected to transition from high to low (i.e., a negative transition edge occurs), it is identified as the start of a new LPC transaction. The main control chip enters the frame start detection state and triggers a sampling operation on the first rising edge of the LCLK clock after the falling edge of LFRAME#. It obtains 4-bit start field data through the four address-data multiplexed pins LAD0 to LAD3. This field is used to identify the type of the current transaction. The main control chip has a preset protocol rule: when the sampling result is binary code 0010, it indicates that the transaction belongs to an I / O write cycle. The state machine then automatically switches from the frame start detection state to the address receive state, determining this bus operation as an I / O write operation. When the main control chip is in ESPI bus operating mode, its LPC-related pins enter a high-impedance disabled state. The state machine logic switches to the ESPI transaction monitoring path and monitors the level of the CS# chip select signal pin in real time. When a negative edge signal transitioning from high to low is detected on this pin, it is recognized as the start signal of an ESPI transaction. This transition edge means that the main control chip is about to initiate a complete ESPI bus operation. Subsequently, the main control chip's state machine triggers a sampling operation on the first rising edge of the SCLK serial clock and reads the first byte of data as the command field through the MOSI data input pin. The main control chip has a built-in ESPI protocol command recognition mechanism. When the 8-bit data of the command field is equal to 0x02, it is determined to be an I / O write command. The state machine then switches to the address capture stage to prepare for sampling the subsequent address and data fields and marks this transaction as an I / O write operation.

[0027] In one example, after detecting the frame start signal of the ESPI bus operating mode, command field data is sampled on the rising edge of the clock via the data input signal pin. When the command field data matches the I / O write command identifier, it is determined to be an I / O write operation type, including: When the frame start signal of the ESPI bus operating mode is detected, the command field data is obtained by sampling through the data input signal pin on the rising edge of the clock. The command field data is compared bit by bit with the preset identifier value of the I / O write command to obtain the comparison result. When the comparison result is consistent, it is determined to be an I / O write operation type.

[0028] In this example, when the main control chip is in ESPI bus operating mode, its internal state machine continuously monitors the level of the ESPI chip select signal CS# pin. Upon detecting the negative edge of the ESPI chip select signal transitioning from high to low, it identifies the current communication cycle as the start of an ESPI bus frame and switches the state machine to the command field sampling stage. The main control chip uses the rising edge of the SCLK serial clock signal as the sampling timing, initiating a synchronous sampling operation for eight consecutive clock cycles. It sequentially acquires the transmitted 8-bit command field data through the MOSI data input signal pin, accurately latching each bit into the internal command register at the corresponding rising edge of the clock. After the command field data sampling is complete, the command comparison logic module inside the main control chip compares the 8-bit command field bit-by-bit with the standard I / O write command identifier value pre-configured in the read-only memory unit. The standard I / O write command identifier value is fixed at hexadecimal 0x02, corresponding to the standard I / O write transaction command code defined in the ESPI bus protocol. The bit-by-bit comparison process uses an XOR logic judgment method, which compares each bit of the command field with the corresponding bit of the preset command code. When all bits match, i.e. the XOR result is zero, it indicates that the current ESPI transaction is a valid I / O write operation. The main control chip then updates the internal flag bit to confirm that the current transaction type is an I / O write operation, and drives the state machine to enter the address field sampling stage to obtain the target address.

[0029] In one example, the address field in the bus frame of the I / O write operation type is parsed and matched against the target listening address. When the address match is successful, a POST Code diagnostic code is obtained from the bus frame, including: Within a continuous clock cycle after determining that it is an I / O write operation, the address field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin, and the address field data is compared bit by bit with the target listening address to obtain the address matching result. When the address matching result is a successful match, the data field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles, and the data field data is used as the POST Code diagnostic code.

[0030] In this example, after the main control chip determines that the current bus transaction is an I / O write operation based on the command field, its internal bus state machine enters the address field sampling stage and selects the corresponding pin and timing mechanism for sampling operation according to the current working mode. If the main control chip is in LPC bus working mode, it performs continuous sampling operation through the four address-data multiplexed signal pins LAD0 to LAD3, relying on the rising edge of the LCLK clock signal, divided into four LCLK cycles. Each cycle samples 4 bits of data, which are used to form a complete 16-bit I / O address field. In each sampling cycle, the state machine stores the 4 bits of data on the LAD bus at the current moment into the internal address register bit by bit. After the four sampling cycles are completed, the 16-bit address field is compared bit by bit with the preset target listening address, i.e., the hexadecimal address 0x0080 corresponding to port 80h. The comparison process is completed by the address comparator deployed in the hardware circuit, using a bit-level logic equality judgment method to ensure that the sampled address and the listening address are consistent. When the address match is complete (i.e., the comparator outputs the address match valid signal ADDR_MATCH), the state machine confirms that the target of the current I / O write operation is the expected port 80h and enters the data field sampling phase. During the sampling phase, the main control chip uses LAD0 to LAD3 pins to sample the lower 4 bits and higher 4 bits of the POST Code on the rising edges of the next two LCLK clock cycles, and combines the two sampling results into an 8-bit diagnostic code, which is written into the data register as valid information for this POST Code. If the main control chip is in ESPI bus operating mode, after recognizing the I / O write command, it performs four consecutive byte sampling operations via the MOSI data input pin on the rising edge of the SCLK clock cycle, acquiring a complete 32-bit address field. The main control chip extracts only the lower 16 bits as the valid address value and compares them bit-by-bit with the target address 0x0080. If the addresses match, the state machine enters the data sampling state, continuing to sample an 8-bit data field via the MOSI pin on subsequent rising edges of SCLK, and writes this data into the diagnostic code register as valid content for the current POST Code.

[0031] In one example, when the address matching result is a successful match, data field data is continuously sampled through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles. This data field data is then used as a POST Code diagnostic code, including: When the address matching result is a successful match, in LPC bus working mode, the data field data is obtained by segmenting the data through the address data multiplexing signal pin on the continuous rising edge of the clock after skipping the acknowledgment cycle, or in ESPI bus working mode, the data field data is obtained by sampling the data input signal pin on the continuous rising edge of the clock. The sampled segments of the data field are concatenated bit by bit to obtain the concatenated complete data, and the concatenated complete data is stored in a temporary data register as a POST Code diagnostic code.

[0032] In this example, when the address matching result is successful, in LPC bus operating mode, the master control chip identifies and skips the acknowledgment cycle following the address cycle in the I / O write transaction. That is, after the state machine completes the address identification phase, it automatically ignores the subsequent two LCLK clock cycles as a TAR acknowledgment process, performs no sampling operations, and starts the data reception logic after the acknowledgment cycle ends. During the two consecutive rising edges of LCLK, the master control chip performs two-stage data sampling through the LAD0 to LAD3 address-data multiplexing signal pins, acquiring the lower 4 bits and higher 4 bits of the POST Code respectively. Bits 3 to 0 of the data are latched in the first sampling cycle, and bits 7 to 4 are acquired in the second sampling cycle. Each sampling operation accurately captures the corresponding data segment through the internal latch register, ensuring that the data stability is not affected by bus jitter. When the main control chip is in ESPI bus operating mode, after completing the sampling of the 32-bit address field and confirming the target address match through address comparison, its status machine controls the MOSI data input pin to perform a continuous 8-bit data sampling operation on the subsequent rising edge of the SCLK clock. The sampling is completed in one go, and the obtained byte is the complete content of the POST Code. In both modes, the collected data field is stored in an intermediate buffer in the form of two or one fragment. The main control chip's splicing logic splices all sampled segments bit by bit. First, the content of the lower segment is shifted left by a certain number of bits and then a bitwise OR operation is performed with the content of the higher segment to construct an 8-bit POST Code. The spliced ​​complete data is written into data register 0x32 as the content of the temporary data register.

[0033] Figure 4This is a schematic diagram of the pin connections for the two-digit seven-segment display device of the present invention. In the diagram, the seven-segment device DBU7 is a two-digit common-anode seven-segment display. Its pins include the high-digit digit selection pin DIG3, the low-digit digit selection pin DIG2, and the seven-segment display pins including G-segment pin 1, NC-segment pin 2, A-segment pin 3, F-segment pin 4, DI# pin 5, B-segment pin 6, C-segment pin 7, E-segment pin 8, D-segment pin 9, and DH# pin 10. The main control chip controls the enable of the high-digit and low-digit seven-segment displays through the digit selection pins, and outputs segment code signals through the seven-segment pins to drive the corresponding segments to light up and display hexadecimal digits.

[0034] Figure 5 This is a circuit diagram of the 3.3V to 1.8V power supply voltage conversion circuit of the present invention. In the diagram, the input terminal VIN of the voltage conversion chip UP0109 is connected to the 3.3V power supply 3VSB through the filter capacitor DBC379. The enable terminal VDDO_VTT_EN is connected to the ground through the voltage divider resistors DBR389 and DBR390. The reference terminal REF is grounded through the capacitor DBC374. The output terminal VOUT outputs the 1.8V power supply 1.8VSB through the filter capacitors DBC6, DBC9, and DBC372, providing a stable power supply for the main control chip or other circuit modules that require 1.8V power.

[0035] In one example, the ESPI and LPC bus diagnostic method further includes: After the sampling and acquisition of the POST Code diagnostic code is completed, a data valid signal is generated. On the trigger edge of the data valid signal, the POST Code diagnostic code stored in the temporary data register is latched and transmitted to the display data register. The POST Code diagnostic code output by the display data register is decomposed bit by bit, and the high-order bit segment is extracted as the high-order data and the low-order bit segment is extracted as the low-order data. The high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POST Code diagnostic code is displayed on a two-digit LED display using a dynamic scanning method.

[0036] In this example, when the main control chip completes the full sampling of the POST Code diagnostic code and successfully concatenates the data and writes it to the temporary data register, the internal state machine triggers the data validity determination logic. It compares the currently acquired 8-bit POST Code data bit by bit with the original output value in the display data register. If any bit difference is found between the two data contents, it is determined that the diagnostic code has been updated, and a rising edge pulse signal from low to high is generated as the data validity signal. The data validity signal serves as the timing trigger for the display control process. When its rising edge arrives, it drives a D flip-flop circuit connected to the clock input of the display data register, causing the currently stored 8-bit POST Code in the temporary data register to be immediately latched and transferred to the display data register, completing the valid transmission of the diagnostic code and maintaining a stable output state until the next valid data generation triggers another update. After latching, the 8-bit POST Code output from the display data register is input into the decoding logic module. The module decomposes the 8-bit data bit by bit, extracting the high 4 bits (bits 7 to 4) as high-order data and the low 4 bits (bits 3 to 0) as low-order data. These two sets of data correspond to the high and low nibbles of the POST Code, respectively. After data separation, the lookup table decoding circuit integrated inside the main control chip inputs the high-order seven-segment code decoding lookup table ROM_H, using 4 bits as the index address to look up the corresponding seven-segment display code. For example, the value 0 corresponds to 0x3F to illuminate segments a to f, 1 corresponds to 0x06 to illuminate segments b and c, and so on, to achieve matching of display codes for numbers and letters. The low-order data is input into the low-order seven-segment code lookup table ROM_L for independent decoding, outputting another set of seven-segment codes. These two sets of segment codes are loaded into the high-order segment code register SEG_H and the low-order segment code register SEG_L, respectively, and output to the segment control terminals of the two-digit common-anode seven-segment display through seven independent segment code drive pins SEG_A to SEG_G. At the same time, the display circuit uses the 2 kHz scanning timer inside the main control chip to drive the dynamic bit selection signal. In the first half of a scan cycle, the DIG1 pin outputs a low level to turn on the common anode of the high-order LED1, making LED1 light up to display the high-order segment code. In the second half of the cycle, the DIG2 pin is switched to a low level to turn on LED2 to display the low-order segment code. Through rapid alternating scanning, a stable visual holding effect is formed, thus presenting a two-digit POST Code hexadecimal diagnostic code display on a time scale perceptible to the human eye.

[0037] In one example, the high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POST Code diagnostic code is displayed on a two-digit LED display using a dynamic scanning method, including: The high-order data is used as the first lookup table index to read the corresponding high-order seven-segment code, and the low-order data is used as the second lookup table index to read the corresponding low-order seven-segment code. The high-order and low-order digit displays are alternately enabled according to a preset scanning frequency. When the high-order digit display is enabled, the high-order seven-segment code is output to drive the high-order digit display to show the high-order hexadecimal digits. When the low-order digit display is enabled, the low-order seven-segment code is output to drive the low-order digit display to show the low-order hexadecimal digits.

[0038] In this example, the main control chip's built-in seven-segment code decoding logic initiates a lookup table reading mechanism. The high-order data is used as the index value of the first lookup table and input into the high-order seven-segment code lookup table ROM_H. The high-order seven-segment code lookup table stores the seven-segment display codes corresponding to 16 hexadecimal characters from 0 to F. Each entry is a 7-bit segment code used to control the lighting status of segments a to g, and outputs the high-order seven-segment code. At the same time, the low-order data is used as the index of the second lookup table and input into the low-order seven-segment code lookup table ROM_L to obtain the corresponding low-order seven-segment code. The two sets of segment codes are written to the high-order segment code register SEG_H and the low-order segment code register SEG_L, respectively, in preparation for outputting the drive signal. To avoid current superposition and visual confusion caused by the simultaneous lighting of two digital tubes, the main control chip is designed with a dynamic scan control timer. It generates a scan cycle at a preset frequency (e.g., 2 kHz) and divides the drive timing into two alternating half-cycles within each cycle. In the first half-cycle, the main control chip outputs a low level to pin DIG1, ​​turning on the PNP transistor to provide an anode current path for the high-order digital tube. At the same time, the SEG_A to SEG_G seven-segment drive pins output the high-order seven-segment code stored in SEG_H, causing the high-order digital tube to light up and display the corresponding hexadecimal character. In the next half-cycle, the main control chip pulls DIG1 high and DIG2 low to switch the display focus to the low-order digital tube. At the same time, the SEG_A to SEG_G pins switch to output the low-order seven-segment code stored in SEG_L, thereby driving the low-order digital tube to display the low-order hexadecimal character.

[0039] Figure 6This is a circuit schematic of the ESPI bus interface connection circuit of the present invention. The ESPI bus signals, including the chip select signal ESPI_CS, the serial clock signal ESPI_CLK, and the reset signal ESPI_RST, are connected to the ESPI pin header HEADER_2X5 through circuit traces, and are also connected to the corresponding pins of the main control chip DBF30. Specifically, ESPI_RST is connected to pin 2 of the chip, ESPI_RESET; ESPI_CS is connected to pin 4, ESPICLK; and ESPI_CLK is connected to pin 6, ESPICS. The data signals ESPI0, ESPI1, ESPI2, and ESPI3 are connected to the ESPI data pins ESPIALAD0 to ESPIALAD3 of the chip, realizing the electrical connection between the diagnostic card and the target motherboard's ESPI interface.

[0040] Reference Figure 7 This embodiment provides an ESPI and LPC bus diagnostic device, including: Configuration module 1 is used to configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip can enter the LPC bus working mode or the ESPI bus working mode. Connection module 2 is used to connect to the target motherboard via an LPC pin header according to the LPC bus working mode or via an ESPI pin header according to the ESPI bus working mode. Detection module 3 is used to monitor the I / O write operation initiated by the target motherboard during the POST self-test phase. When the frame start signal is detected, the start field of the bus frame is parsed and determined to be an I / O write operation type. Matching module 4 is used to parse the address field in the bus frame of the I / O write operation type and match it with the target listening address. When the address match is successful, the POST Code diagnostic code is obtained from the bus frame.

[0041] In this embodiment, the specific implementation of each unit in the above device embodiment is described in the above method embodiment, and will not be repeated here.

[0042] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0043] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A diagnostic method for ESPI and LPC buses, characterized in that, include: Configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip can enter the LPC bus working mode or the ESPI bus working mode. Connect to the target motherboard via LPC pin header according to the LPC bus operating mode or via ESPI pin header according to the ESPI bus operating mode; The system monitors I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the system parses the start field of the bus frame and determines it to be an I / O write operation type. The address field in the bus frame of the I / O write operation type is parsed and matched with the target listening address. When the address matches successfully, the POST Code diagnostic code is obtained from the bus frame.

2. The diagnostic method for ESPI and LPC buses according to claim 1, characterized in that, Configure the STRAP pin level of the main control chip by shorting the jumper cap, enabling the main control chip to enter LPC bus operating mode or ESPI bus operating mode, including: When the jumper cap shorts the first and second pins of the three-pin jumper socket, the STRAP pin is pulled low by the pull-down resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a low level is read, the mode bit of the configuration register is written to the first logic value, and the LPC interface pin group is enabled while the ESPI interface pin group is disabled to enter the LPC bus working mode. When the jumper cap shorts the second and third pins of the three-pin jumper socket, the STRAP pin is pulled high through the pull-up resistor; when the main control chip is powered on and reset, the level state of the STRAP pin is read. When a high level is read, the mode bit of the configuration register is written to the second logic value, and the ESPI interface pin group is enabled while the LPC interface pin group is disabled to enter the ESPI bus working mode.

3. The diagnostic method for the ESPI and LPC bus according to claim 1, characterized in that, Connecting to the target motherboard via an LPC header according to the LPC bus operating mode or via an ESPI header according to the ESPI bus operating mode includes: When the main control chip is in the LPC bus working mode, the clock signal pin, frame synchronization signal pin, address data multiplexing signal pin, and reset signal pin of the LPC pin socket are connected to the corresponding pins of the LPC interface of the target motherboard via a ribbon cable. When the main control chip is in the ESPI bus working mode, the chip select signal pin, serial clock signal pin, data input / output signal pin, and reset signal pin of the ESPI socket are connected to the corresponding pins of the ESPI interface of the target motherboard via a ribbon cable. The main control chip is connected to the bus of the target motherboard as a bus slave device through the ribbon cable connection, and the bus interface pin of the main control chip and the bus pin of the target motherboard form an electrical path to enter the bus listening state.

4. The diagnostic method for ESPI and LPC buses according to claim 1, characterized in that, The system monitors I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the system parses the start field of the bus frame and determines it to be an I / O write operation, including: When the main control chip is in the LPC bus working mode, it listens to the level change of the frame synchronization signal pin. When the frame synchronization signal changes from the first level to the second level, it is identified as a frame start signal. After the frame start signal of the LPC bus working mode is detected, the start field data is sampled through the address data multiplexing signal pin on the rising edge of the clock. When the start field data conforms to the I / O write cycle identifier, it is determined to be an I / O write operation type. When the main control chip is in the ESPI bus working mode, it listens to the level transition of the chip select signal pin. When the chip select signal is detected to transition from the first level to the second level, it is identified as the frame start signal. After the frame start signal of the ESPI bus working mode is detected, the command field data is sampled through the data input signal pin on the rising edge of the clock. When the command field data matches the I / O write command identifier, it is determined to be an I / O write operation type.

5. The ESPI and LPC bus diagnostic method according to claim 4, characterized in that, Upon detecting the frame start signal of the ESPI bus operating mode, command field data is sampled via the data input signal pin on the rising edge of the clock. When the command field data matches the I / O write command identifier, it is determined to be an I / O write operation type, including: When the frame start signal of the ESPI bus operating mode is detected, the command field data is obtained by sampling through the data input signal pin on the rising edge of the clock. The command field data is compared bit by bit with the preset identifier value of the I / O write command to obtain the comparison result. When the comparison result is consistent, it is determined to be an I / O write operation type.

6. The diagnostic method for ESPI and LPC buses according to claim 1, characterized in that, The address field in the bus frame of the I / O write operation type is parsed and matched with the target listening address. When the address match is successful, the POST Code diagnostic code is obtained from the bus frame, including: Within a continuous clock cycle after determining that it is an I / O write operation, the address field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin, and the address field data is compared bit by bit with the target listening address to obtain the address matching result. When the address matching result is a successful match, the data field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles, and the data field data is used as the POSTCode diagnostic code.

7. The diagnostic method for the ESPI and LPC bus according to claim 6, characterized in that, When the address matching result is successful, data field data is obtained by sampling through the address data multiplexing signal pin or the data input signal pin in subsequent clock cycles. This data field data is used as a POST Code diagnostic code, including: When the address matching result is a successful match, in LPC bus working mode, the data field data is obtained by segmenting the data through the address data multiplexing signal pin on the continuous rising edge of the clock after skipping the acknowledgment cycle, or in ESPI bus working mode, the data field data is obtained by sampling the data input signal pin on the continuous rising edge of the clock. The sampled segments of the data field are concatenated bit by bit to obtain the concatenated complete data, and the concatenated complete data is stored in a temporary data register as a POST Code diagnostic code.

8. The diagnostic method for the ESPI and LPC bus according to claim 7, characterized in that, The ESPI and LPC bus diagnostic method also includes: After the sampling and acquisition of the POST Code diagnostic code is completed, a data valid signal is generated. On the trigger edge of the data valid signal, the POST Code diagnostic code stored in the temporary data register is latched and transmitted to the display data register. The POST Code diagnostic code output by the display data register is decomposed bit by bit, and the high-order bit segment is extracted as the high-order data and the low-order bit segment is extracted as the low-order data. The high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POST Code diagnostic code is displayed on a two-digit LED display using a dynamic scanning method.

9. The diagnostic method for the ESPI and LPC bus according to claim 8, characterized in that, The high-order data and the low-order data are decoded using a seven-segment code lookup table, and the POSTCode diagnostic code is displayed on a two-digit LED display using a dynamic scanning method, including: The high-order data is used as the first lookup table index to read the corresponding high-order seven-segment code, and the low-order data is used as the second lookup table index to read the corresponding low-order seven-segment code. The high-order and low-order digit displays are alternately enabled according to a preset scanning frequency. When the high-order digit display is enabled, the high-order seven-segment code is output to drive the high-order digit display to show the high-order hexadecimal digits. When the low-order digit display is enabled, the low-order seven-segment code is output to drive the low-order digit display to show the low-order hexadecimal digits.

10. A diagnostic device for ESPI and LPC buses, characterized in that, The steps for implementing the ESPI and LPC bus diagnostic method according to any one of claims 1 to 9 include: The configuration module is used to configure the STRAP pin level of the main control chip by shorting the jumper cap, so that the main control chip can enter the LPC bus working mode or the ESPI bus working mode. A connection module is used to connect to the target motherboard via an LPC pin header according to the LPC bus working mode or to the target motherboard via an ESPI pin header according to the ESPI bus working mode. The detection module is used to monitor the I / O write operations initiated by the target motherboard during the POST self-test phase. When a frame start signal is detected, the start field of the bus frame is parsed and determined to be an I / O write operation type. The matching module is used to parse the address field in the bus frame of the I / O write operation type and match it with the target listening address. When the address match is successful, the POST Code diagnostic code is obtained from the bus frame.

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