Memory system, access method, communication interface, and electronic device

Abstract

Embodiments of the present application provide a memory system, an access method, a communication interface and an electronic device. The memory system comprises a PCM and a memory controller. A communication interface is arranged between the memory controller and the PCM. The communication interface comprises a plurality of command address transmission terminals. The command address transmission terminals are used to respectively transmit command information and address information of a same access request in a plurality of transmission periods.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, specifically to a memory system, access method, communication interface, and electronic device. Background Technology

[0002] In the von Neumann computing architecture, a large amount of data needs to be read and stored between DRAM (Dynamic Random Access Memory) and SSD (Solid State Disk). Due to the significant performance gap between DRAM and SSD, current performance improvements in the von Neumann computing system have encountered a bottleneck.

[0003] 3D-PCM (3 Dimensions-Phase Change Material) possesses random access memory characteristics. Its read latency can reach approximately 100 ns (nanoseconds), and its write speed can reach the hundreds of nanoseconds level. Therefore, 3D-PCM can be used as a memory replacement for DRAM in many scenarios. Furthermore, due to its unique structural advantages, 3D-PCM can achieve higher density and larger single-die capacity than DRAM. In summary, compared to NAND flash memory, 3D-PCM offers superior performance and durability; while compared to DRAM, it boasts lower cost, larger capacity, and non-volatility.

[0004] Compared to DRAM, 3D-PCM offers larger memory capacity at a lower unit price. Compared to pure DRAM applications, PCM memory, or a pooled application combining PCM and DRAM, offers a lower total cost of ownership (TCO) while maintaining essentially the same performance. Therefore, in enterprise-level in-memory computing, by appropriately combining 3D-PCM and DRAM in different application scenarios, larger capacity memory modules can be provided while reducing the TCO, while ensuring performance. In other words, 3D-PCM will largely replace server DRAM in the future. However, PCM is a different storage medium from DRAM, with completely different operating principles, read / write operation characteristics, and other performance parameters. Therefore, if an interface protocol similar to DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is adopted, a new I / O (Input / Output Interface) protocol and hardware structure need to be designed for PCM to overcome compatibility issues. Summary of the Invention

[0005] In view of the above, embodiments of this application provide a memory system, an access method, a communication interface, and an electronic device.

[0006] On one hand, embodiments of this application provide a memory system, the memory system including: a PCM and a memory controller;

[0007] A communication interface is provided between the memory controller and the PCM;

[0008] The communication interface includes: multiple command address transmission terminals; wherein, the command address transmission terminals are used to transmit command information and address information of the same access request in multiple transmission cycles respectively.

[0009] In some embodiments, the number of command address transmission endpoints is less than the total number of bits in the address information of the PCM.

[0010] In some embodiments, the command information includes: a command identifier and configuration information; the command address transmission terminal is specifically used for:

[0011] Within the plurality of transmission cycles, the command identifier is transmitted in one or more transmission cycles, and the address information and the configuration information are transmitted in a plurality of transmission cycles following the transmission of the command identifier.

[0012] In some embodiments, for the same access request, the command address transmission end transmits the command identifier in the first transmission cycle.

[0013] In some embodiments, the PCM includes a plurality of memory banks; the address information includes: memory bank addresses;

[0014] Specifically, for the same access request, the command address transmission end transmits the storage address in the next transmission cycle after transmitting the command identifier.

[0015] In some embodiments, the number of bits in the memory address is less than or equal to the number of command address transmission terminals;

[0016] During the transmission cycle of transmitting the memory address, the remaining command address transmission end is used to transmit other address information and / or configuration information.

[0017] In some embodiments, the address information further includes burst length information; wherein, for the same access request, the command address transmission end transmits the burst length information in any transmission cycle after transmitting the memory address; or, the command address transmission end transmits the burst length information in the same transmission cycle as transmitting the memory address.

[0018] In some embodiments, the number of bits in the burst length information is less than the number of command address transmission ends;

[0019] During the transmission period of the burst length, the remaining command address transmission end is used to transmit other address information and / or configuration information.

[0020] In some embodiments, the address information further includes row address and column address;

[0021] The number of bits in the row address or the column address is greater than or equal to the number of command address transmission ends, and the row address and the column address are transmitted in one or more cycles.

[0022] In some embodiments, for the same access request, the command address transmitting end transmits part of the row address or the column address within the same transmission cycle of transmitting the memory address, and transmits the remaining row address and column address in one or more transmission cycles after transmitting the memory address.

[0023] In some embodiments, for the same access request, the command address transmission terminal transmits at least a portion of the configuration information in one or more transmission cycles after transmitting the address information.

[0024] On the other hand, embodiments of this application also provide a method for accessing a PCM memory, the method being applied to a memory controller; the method includes:

[0025] The command and address information of the same access request are transmitted separately by multiple command address transmission terminals in multiple transmission cycles.

[0026] In some embodiments, the command information includes: a command identifier and configuration information; the transmission of the command information and address information of the same access request through the plurality of command address transmission terminals in multiple transmission cycles includes:

[0027] The command identifier is transmitted in one or more transmission cycles;

[0028] The address information and configuration information of the same access request are transmitted in multiple transmission cycles following the transmission of the command identifier.

[0029] In some embodiments, transmitting the command identifier in one or more transmission cycles includes:

[0030] The command identifier is transmitted in the first transmission cycle.

[0031] In some embodiments, the PCM includes a plurality of memory banks; the address information includes: memory bank addresses;

[0032] The transmission of the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes:

[0033] The memory address is transmitted in the next transmission cycle after the command identifier is transmitted.

[0034] In some embodiments, the number of bits in the memory address is less than the number of command address transmission terminals;

[0035] The method of transmitting the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes:

[0036] During the transmission cycle of transmitting the memory address, other address information and / or configuration information are transmitted.

[0037] In some embodiments, the address information further includes burst length information; the transmission of the address information and the configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes:

[0038] The burst length information is transmitted in any transmission cycle following the transmission of the memory address;

[0039] Or the burst length information may be transmitted in the same transmission cycle as the memory address.

[0040] In some embodiments, the number of bits in the burst length information is less than the number of command address transmission ends;

[0041] The method of transmitting the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes:

[0042] During the transmission period of the burst length, other address information and / or configuration information are transmitted synchronously.

[0043] In some embodiments, the address information further includes row address and column address; the number of bits in the row address or the column address is greater than or equal to the number of command address transmission ends;

[0044] The transmission of the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes:

[0045] Transmit a portion of the row address or the column address within the same transmission cycle that transmits the memory address; and / or

[0046] The remaining row address and column address are transmitted in one or more transmission cycles after the transmission of the memory address.

[0047] In some embodiments, transmitting the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes:

[0048] At least a portion of the configuration information of the same access request is transmitted in at least one transmission cycle after the transmission of the address information.

[0049] In another aspect, embodiments of this application also provide a communication interface, which is the communication interface in any of the above-mentioned memory systems.

[0050] In another aspect, embodiments of this application also provide an electronic device, including a processor and any of the aforementioned memory systems.

[0051] This application embodiment utilizes the characteristics of PCM to establish a communication interface architecture that time-multiplexes multiple command address transmission ends across multiple transmission cycles. The multiple command address transmission ends of this communication interface can transmit the command information and address information of the same access request in multiple transmission cycles respectively. Since the read latency of PCM is slightly greater than that of DRAM, the time-multiplexing of command address transmission ends does not significantly impact PCM performance. Furthermore, it reduces the number of required command address transmission ends, thereby reducing the occupation of communication interface pin resources. Even if PCM requires more power pin resources, there is no need to increase the total number of pins, thus saving chip area and packaging costs. This is beneficial for the compatibility design of PCM memory system architecture with existing DDR architecture. Attached Figure Description

[0052] Figure 1 A schematic diagram illustrating the principle of read / write operations for DRAM memory;

[0053] Figure 2 A schematic diagram illustrating the performance characteristics of various types of memory;

[0054] Figure 3 This application provides a schematic diagram of the structure of a memory system according to an embodiment of the present application.

[0055] Figure 4 A schematic diagram of the communication interface in the memory system provided in the embodiments of this application;

[0056] Figure 5 A timing diagram of the command address transmission end in a memory system provided in an embodiment of this application;

[0057] Figure 6 A flowchart illustrating a PCM memory access method provided in an embodiment of this application;

[0058] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0059] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0063] For ease of understanding, the relevant technical concepts involved in the embodiments of this application will be introduced first:

[0064] Compared to SRAM (Static Random Access Memory), DRAM has a simpler structure and consumes less area, making it suitable for manufacturing large-capacity storage chips outside of logic chips, such as RAM chips. DRAM is currently the most widely used RAM memory in electronic system architectures. The mainstream capacities for DRAM are currently 16Gb or 24Gb, etc.

[0065] DRAM uses the DDR protocol to communicate with the memory controller. DDR stands for DDR SDRAM (Synchronous Dynamic Random Access Memory), which features a separation between the memory chip and the CPU (Central Processing Unit). The CPU accesses the memory chip via a bus to read data from it. DDR allows data transmission on both the rising and falling edges of the clock pulse, its main function being to synchronize with the CPU frequency, thereby greatly improving data transfer efficiency. DRAM I / O specifications have gone through four generations: first-generation SDR SDRAM, second-generation DDR SDRAM, third-generation DDR2 SDRAM, fourth-generation DDR3 SDRAM, and the current DDR5 SDRAM.

[0066] To meet the requirements of memory access speed, DRAM needs to have very low read latency and write completion time to reduce system latency. The read latency of mainstream products is currently in the range of 20-30ns. The design of DDR IO interface of different generations, as well as the command settings of DRAM, are all based on reducing latency and improving IO transmission speed.

[0067] The following is a brief introduction to the DRAM read / write access mechanism, such as... Figure 1 As shown, taking reading as an example:

[0068] First, DRAM uses address addressing to determine the Bank Group (BG), Bank (BA), and rows and columns. This process requires pre-charging the corresponding bit lines in the DRAM. This pre-charging step can be completed within the execution period of the previous command.

[0069] After pre-charging, the rows in the memory cell array 100 need to be activated (Act) by sending row address 111 and the signal RAS (Row Address Strobe). After the row is activated by the row decoding circuit 110, the entire row of data is flushed to the DRAM sensing amplifier circuit 120. The sensing amplifier circuit 120 performs circuit detection and amplifies the charge stored in the row. This process typically takes tens of nanoseconds, and this step can also be completed within the execution period of the previous command.

[0070] Finally, column address 131 and column signal CAS (Column Address Strobe) are sent, and data on the bit line is obtained through column strobe circuit 130 and transmitted to DQ (Data input / output).

[0071] Based on the read / write access characteristics of DRAM, DRAM read / write operations employ a time-division multiplexing method, transmitting the address in two steps (i.e., first transmitting the row address and RAS, then transmitting the column address and CAS). This does not affect latency and reduces the use of I / O pin resources, thereby lowering manufacturing costs (manufacturing costs mainly depend on the number of I / O pins in the package). In practice, the maximum number of read steps may be three commands: a precharge command, an activation command, and a read command.

[0072] This limitation on I / O pins has had a long-term impact on DRAM architecture. Most DRAM address pins are still multiplexed, meaning that two different parts of the data address are sent through the same pin at different times, rather than using more address pins to send the entire address at once (e.g., sending the row address and column address simultaneously).

[0073] 3D-PCM features random access memory, with read latency down to 100 nanoseconds and write speeds up to several hundred nanoseconds, making it suitable as a memory alternative to DRAM in many scenarios.

[0074] Performance and applications of various types of memory, such as Figure 2 As shown, hard disk drives (HDDs) and NAND flash memory are characterized by slow read / write speeds, non-volatility, and low cost, making them suitable for storing "cold data." DRAM, on the other hand, has fast read / write speeds, volatility, and high cost, making it suitable for storing "hot data." Newer types of memory, such as PCM memory, combine the characteristics of both, offering performance and cost advantages that fall between the two. Therefore, they can be used for persistent memory, enabling the storage of "warm data." Among these, 3D-PCM can replace DRAM in many scenarios, improving storage performance.

[0075] 3D-PCM, used as memory, offers performance similar to DRAM and is expected to significantly replace DRAM in various applications. Therefore, for 3D-PCM storage architecture design, it is advisable to adopt IO protocols similar to DDR, especially the DC (Direct Current) and AC (Alternating Current) electrical characteristics of the signals, and various POR (Power-On Reset) adjustments, to achieve high-speed IO transmission and facilitate the promotion of the application ecosystem.

[0076] However, PCM is a different storage medium from DRAM, with completely different working principles, read / write operation characteristics, and other performance parameters, specifically reflected in:

[0077] First, they have different command types:

[0078] PCM lacks the precharge command, activation command, and self-refresh command of DRAM. However, PCM has special settings different from DRAM, such as force write command, normal write command, and burst read / write command.

[0079] Second, they have different read and write operation sequences:

[0080] PCM reading does not involve precharging, row-by-row brushing, or column-by-column data retrieval. Instead, it requires obtaining complete row / column address information before it can access data bit by bit.

[0081] Third, the capacity is different. The current mainstream capacity of PCM is 128Gb / 256Gb, and the address space is 8 to 16 times that of DRAM. It has 3 to 4 more address bits. In the future, the capacity of PCM may be even larger, and the address space will far exceed that of DRAM.

[0082] Fourth, there is no concept of a Bank Group (BG), and BG addresses are not required.

[0083] Fifth, PCM's read latency is in the tens of nanoseconds (close to 100ns), and its write completion time is in the hundreds of nanoseconds, which is slightly slower than DRAM.

[0084] Sixth, more power pin resources are needed.

[0085] Because of the different commands and address spaces, the I / O protocol between PCM and the memory controller is different from that of DDR. If the same I / O pins and similar CA (Command-Address) definitions as DDR are used, the advantages of PCM cannot be brought into play. Instead, it increases the I / O pin resources, resulting in higher chip area and packaging costs.

[0086] Given the proximity of 3D-PCM and DRAM applications and the unique characteristics of PCM media, this application proposes a CA IO pin and CA definition for 3D-PCM and memory controllers. This design does not affect the basic performance of PCM and saves IO pin resources, thereby reducing chip area and packaging costs. This memory system architecture not only saves chip costs and improves memory performance but also facilitates compatibility designs with existing architectures such as DDR4.

[0087] The following is a detailed description of the solution provided in this application:

[0088] like Figure 3 As shown, this application embodiment provides a memory system 200, including: PCM 210 and memory controller 220; a communication interface 230 is provided between memory controller 220 and PCM 210.

[0089] The communication interface 230 includes: multiple command address transmission terminals 231; wherein, the command address transmission terminals 231 are used to transmit command information and address information of the same access request in multiple transmission cycles respectively.

[0090] In this embodiment, the communication interface between the PCM and the memory controller may include multiple signal transmission terminals, each of which can transmit one bit of data in one transmission cycle. These signal transmission terminals may be pins of the chip or other types of connection terminals.

[0091] In some embodiments, the communication interface further includes multiple power signal terminals.

[0092] The signal transmission end includes multiple command and address transmission ends (CA ends), each of which can transmit one bit of command or address information in one transmission cycle. The signal transmission end also includes multiple power signal ends to provide the necessary power signals to the PCM. Compared to DRAM, PCM may require more power signal ends; therefore, using fewer command and address transmission ends eliminates the need to increase the number of signal transmission ends in the communication interface, thus saving pin resources.

[0093] For a single access, the memory controller needs to transmit both the command and address information of the access request to the PCM. Since the total number of bits in this information is quite large, a time-division multiplexing command and address transmission method is adopted here, transmitting the command and address information separately through multiple transmission cycles.

[0094] Since the read and write latency of PCM memory is slightly greater than that of DRAM, multiple transmissions will not significantly impact PCM performance as long as the number of transmission cycles required for a single access request is set appropriately. For example, if the total number of bits for transmitting command and address information is over forty (e.g., 46 bits), six command and address transmission terminals can be configured to transmit over eight transmission cycles, or eight command and address transmission terminals can be configured to transmit over six transmission cycles. Of course, the specific number of command and address transmission terminals and the number of transmission cycles required for each access can be set according to the parameters of the actual product. For example, the setting can be based on the actual capacity of the PCM memory and the types of operations that can be accessed. Additionally, the number of transmission cycles can be set based on the read and write latency of the PCM memory to minimize the impact of multiple transmissions on read and write performance. In other words, the impact on read and write latency and the number of pins occupied can be balanced by setting the number of transmission cycles and pins used for each access.

[0095] In this way, the number of CA pins can be greatly reduced compared to DRAM. In addition, apart from the above-mentioned periodic transmission settings, other electrical characteristics can be set under the compatibility architecture of the original DDR4 architecture, and more power pin resources required for PCM can be set without increasing the total number of pins, thus avoiding higher chip and packaging costs.

[0096] In some embodiments, the number of command address transmission endpoints is less than the total number of bits in the PCM address information.

[0097] Because PCM has a larger capacity and a larger address space than DRAM, transmitting all address information in parallel within a single transmission cycle would require a large number of transmission pins or connection terminals. Therefore, the number of command address transmission terminals set here is less than the total number of bits of address information, and address information can be transmitted over multiple transmission cycles. In other words, the same command address transmission terminal can not only transmit command information and address information sequentially in a time-division multiplexing manner, but also transmit address information multiple times.

[0098] For example, the memory address, row address, column address, etc., can be transmitted sequentially through different transmission cycles, thereby effectively saving the required number of pins or connection terminals.

[0099] In some embodiments, the command information includes: a command identifier (CMD) and configuration information; the command address transmission end is specifically used for:

[0100] Within multiple transmission cycles, the command identifier is transmitted in one or more transmission cycles, and address information and configuration information are transmitted in multiple transmission cycles following the transmission of the command identifier.

[0101] Here, the command identifier is the code or information used to distinguish different commands, and can, for example, consist of one or more binary digits. Operations for PCM may include forced write commands, normal write commands, burst read commands, burst write commands, etc., and these commands can be represented by multiple different combinations of numbers.

[0102] In this embodiment of the application, for the same access request, it is necessary to indicate what type of command the access corresponds to. Therefore, the command identifier can be transmitted through one or more transmission cycles.

[0103] In addition, the above configuration information may include some parameters that need to be configured for this access, such as user operations, firmware configuration, and configuration information of various PCM internal registers.

[0104] It should be noted that after the PCM receives the command identifier, it needs to perform corresponding logical control. Different command types may require different logical control. Therefore, in this embodiment, for the same access request, the command identifier is first transmitted through the communication interface to inform the PCM of the current access command type, thus facilitating the PCM to quickly initiate the corresponding internal logical control. Simultaneously, the PCM continues to receive subsequent address and configuration information. This allows for synchronous execution of logical control across multiple transmission cycles following the transmission of the command identifier, effectively utilizing the time available for the PCM to initiate internal logical control without additional waiting, thereby reducing read / write latency.

[0105] In some embodiments, for the same access request, the command address transmission end transmits the command identifier in the first transmission cycle.

[0106] Since the number of PCM command types is not large, they can be represented by a few bits of binary data and transmitted within a single transmission cycle using multiple command address transmission endpoints. Therefore, only the command identifier is transmitted in the first transmission cycle. This serves two purposes: firstly, it provides the command type to the PCM immediately, facilitating rapid initiation of the PCM's internal logic control; secondly, this transmission format is simple. The content transmitted in the second and subsequent transmission cycles contains the address information and configuration information of the access request.

[0107] For example, if the total number of command address transmission endpoints is n, then in the first transmission cycle, n bits of data are used to transmit the command identifier, and the maximum number of command identifier types can be 2. n indivual.

[0108] In some embodiments, the PCM includes multiple banks; the address information includes: bank address BA[k-1,0]; the number of bits in the bank address is k bits.

[0109] Specifically, for the same access request, the command address transmission end transmits the storage address in the next transmission cycle after transmitting the command identifier.

[0110] Since a memory bank address represents a portion of the memory area in a PCM (Process Control Model), such as a memory array consisting of rows and columns, the memory bank address can be transmitted first during address information transmission. This allows the PCM to execute the logical operation to start the corresponding memory bank, and then the specific row and column addresses can be transmitted. Therefore, for the same access request, the command identifier can be transmitted first, followed by the memory bank address.

[0111] This allows the PCM to initiate the corresponding logical control of the memory bank upon receiving its address, while simultaneously continuing to receive other address and configuration information. This enables the PCM to initiate the logical control of the internal memory bank while transmitting address information, effectively utilizing the time spent initiating internal logical control for command and address information transmission, thereby reducing read / write latency.

[0112] In some embodiments, the number of bits in the above-mentioned storage address is less than or equal to the number of command address transmission ends;

[0113] During the transmission cycle of the storage address, the remaining command address transmission end is used to transmit other address information and / or configuration information.

[0114] Since k in the memory address BA[k-1,0] can be less than or equal to the number of command address transmission endpoints n, the aforementioned memory address can be transmitted within one transmission cycle. For example, if the number of bits k in the memory address is equal to the number of command address transmission endpoints n, then for each access request, the command identifier is transmitted in the first transmission cycle, the memory address is transmitted in the second transmission cycle, and other address information and configuration information are transmitted in the third and subsequent one or more transmission cycles.

[0115] If the number of bits k in the storage address is less than the number n in the command address transmission, then for each access request, the command identifier is transmitted in the first transmission cycle, the storage address BA[k-1,0] is transmitted in the first k bits of the second transmission cycle, and the remaining nk bits can be used to transmit at least some other address information or configuration information.

[0116] For example, if the row address or column address can be transmitted after the memory address, then a portion of the row address or column address, i.e., the nk bit portion, can be transmitted synchronously with the memory address in the same transmission cycle, and the remaining address information and configuration information can be transmitted in one or more subsequent transmission cycles. This improves the utilization rate of each command address transmission endpoint and allows for the rational allocation of transmission resources.

[0117] Of course, configuration information can also be transmitted in the remaining bits of the current transmission cycle for the memory address, or these remaining bits can be left idle so that subsequent address and configuration information can be transmitted in the next transmission cycle. In practical applications, the transmission position can be adjusted reasonably according to the actual number of address bits and the type and number of bits of configuration information; no restrictions are imposed here.

[0118] In some embodiments, the address information may further include burst length information. When the address information includes burst length information, for the same access request, the command address transmission end may transmit the burst length information in any transmission cycle after transmitting the memory address; or, the command address transmission end may also transmit the burst length information in the same transmission cycle as transmitting the memory address.

[0119] Burst length is an important concept in memory technology, referring to the amount of data transferred in a single burst transfer, i.e., the number of consecutive data units that can be transferred in a single access operation. In some memory designs, the burst length can be set through a mode register.

[0120] In this embodiment, the burst length information can be transmitted via an access request, and transmitted as part of the address information in a transmission cycle following the transmission command identifier and the memory address, or in the same transmission cycle as the memory address. For example, the column address can be transmitted first to initiate logical operations in the BL (Bit Line) direction within the PCM, followed by the burst length information to determine the number of bits accessed, and then the row address can be transmitted to initiate logical operations in the WL (Word Line) direction. Alternatively, the row address can be transmitted first, followed by the burst length information, and finally the column address. Or, the burst length information can be transmitted first, followed by the row and column addresses respectively.

[0121] It should be noted that the row address, column address, and burst length information mentioned above can be transmitted through different transmission cycles. For example, the column address can be transmitted in one or more transmission cycles, the burst length information in the next transmission cycle, and the row address in the following one or more transmission cycles. That is, the row address, column address, and burst length information are transmitted in different transmission cycles. Alternatively, they can be continuously distributed across multiple transmission cycles, transmitting the row and column addresses and burst length information sequentially. For example, the column address can be transmitted in one or more transmission cycles, and if there is a spare space in the last transmission cycle of transmitting the column address, the burst length information or row address can be transmitted. In other words, this address information can be transmitted bit-by-bit continuously across multiple transmission cycles without needing to divide the transmission cycles into different segments. In practical applications, this can be configured according to requirements, and no limitations are imposed here.

[0122] In some embodiments, the number of bits in the burst length information is less than the number of command address transmission ends; during the transmission period of the burst length, the remaining command address transmission ends are used to transmit other address information and / or configuration information.

[0123] Since the burst length information indicates the length of data accessed in a single session, which can be represented by a small number of bits in binary, the number of bits in the burst length information can be less than the number of command address transmitters. For example, the number of command address transmitters may be 6, 8, or 10, while the number of bits in the burst length information can be as low as 4 bits or more. Thus, the transmission cycle for transmitting the burst length may also include one or more remaining command address transmitters. These remaining command address transmitters can be used to transmit at least a portion of the remaining address information, or to transmit one or more configuration information. Configuration information can also be transmitted in some of the remaining command address transmitters, while at least a portion of the remaining address information is transmitted when additional remaining command address transmitters are present.

[0124] In some embodiments, the address information further includes row addresses and column addresses, and the number of command address transmission endpoints is less than the number of bits in the row address, and / or the number of command address transmission endpoints is less than the number of bits in the column address. That is, the number of bits in the row address or column address is greater than or equal to the number of command address transmission endpoints, and the row address and column address can be transmitted in one or more cycles.

[0125] Because PCM memory has a large storage capacity and address space, each row and column address in the memory bank requires multiple bits of data to represent. In this embodiment, the number of command address transmission endpoints can be less than the number of row addresses, thus requiring more than one transmission cycle to transmit the row address. Similarly, the number of command address transmission endpoints can be less than the number of column addresses, again requiring more than one transmission cycle to transmit the column address. Of course, for certain small-capacity PCM memory products, the number of bits for the row and column addresses can be equal to or less than the number of command address transmission endpoints. In this case, only the number of transmission cycles needs to be adjusted. That is, the number of transmission cycles can be adjusted according to the actual number of address bits, thereby allowing the interface of the memory system provided in this embodiment to meet various design requirements and be flexibly configured and used.

[0126] In some embodiments, for the same access request, the command address transmitting end transmits part of the row address or column address within the same transmission cycle of transmitting the memory address, and transmits the remaining row address and column address in one or more transmission cycles after transmitting the memory address.

[0127] In other words, since the column address or the number of bits in the column address can be greater than the number of command address transmission endpoints, while the number of bits in the memory address is less than the number of possible command address transmission endpoints, a portion of the row address or column address can be transmitted during the transmission cycle of transmitting the memory address, and the remaining row address and column address can continue to be transmitted in the following transmission cycle. That is, whether it is the row address, column address, memory address, or other information, in this embodiment of the application, they can all be split or combined and transmitted in different transmission cycles.

[0128] In some embodiments, the number of bits in the above configuration information may be greater than or equal to the total number of command address transmission terminals; for the same access request, the command address transmission terminal transmits at least part of the configuration information in one or more transmission cycles after transmitting the address information.

[0129] The aforementioned configuration information can be used to configure different user operations or registers, meaning it can include different types of configuration information. Each type of configuration information may consist of one or more bits. Therefore, different types of configuration information can be interspersed within the transmission cycle that transmits the address information, and transmitted through the remaining command address transmission end. Furthermore, it can also include configuration information indicated by multiple bits of data, such as user option control information. This configuration information can be specifically transmitted in one or more transmission cycles after the address information is transmitted.

[0130] In other embodiments, the number of bits in the configuration information may be less than the total number of command address transmission terminals. For the same access request, the configuration information can be split into different transmission cycles and transmitted synchronously with other information (such as address information).

[0131] In this way, the information transmitted in each transmission cycle can be flexibly configured, reducing the total number of command address transmission ends while minimizing transmission latency and reducing the impact on PCM read and write performance.

[0132] This application also provides the following examples in its embodiments:

[0133] Given the proximity of 3D-PCM to DRAM applications and the unique characteristics of PCM media, embodiments of this application provide a CA IO pin and CA definition for a DDR4-based 3D-PCM and its memory controller. This solution does not affect the basic performance of the PCM and saves IO pin resources, thereby reducing chip area and packaging costs.

[0134] Specifically, n CA pins are configured, and each major read / write access request transmits the command and address over m transmission cycles. In this scheme, the DC and AC electrical characteristics of the signals are compatible with DDR4, and various POR power-on test methods are also compatible with DDR4. The communication architecture is as follows: Figure 4 As shown, a communication interface with multiple pins is provided between the memory controller 410 and the memory 420. These pins may include a clock signal terminal CK, a command address transmission terminal CA[n-1:0], a strobe signal terminal CS_N, a data selection signal terminal DQS, and a data signal terminal DQ[n-1:0], etc.

[0135] Figure 5 The transmission method of the clock signal CK and the command address transmission terminals CA[n-1:0] is shown, as follows: Figure 5 As shown, this scheme adopts a multi-cycle instruction format, where the instruction information of the command address bus is contained in multiple transmission cycles. For example, m transmission cycles are used to complete one instruction transmission. The first transmission cycle can contain all operation instruction information, i.e., the aforementioned command identifier CMD. The remaining transmission cycles can contain address information and other configuration information. Furthermore, there are many types of read / write operations, and each type can be transmitted in the first transmission cycle.

[0136] To minimize read / write latency, the command or address information transmitted in each transmission cycle of the access request can be configured in the following order, as shown in Table 1 below:

[0137]

[0138]

[0139] Table 1

[0140] The first transmission cycle: Transmission command identifier (CMD) is used to confirm what operation to perform, thereby quickly initiating the corresponding logic control within the PCM.

[0141] The second transmission cycle: transmit the memory address BK, confirm the memory to be operated on, and start the logic control of the corresponding memory.

[0142] The second to fourth transmission cycles: transmit column addresses and initiate operations in the BL direction within the PCM.

[0143] The fifth transmission cycle transmits burst length information (BL), such as burst read length or burst write length.

[0144] The sixth to seventh transmission cycles: transmit the row address and initiate the WL direction operation within the PCM.

[0145] The eighth transmission cycle: Transmits configuration information such as user option controls.

[0146] In another embodiment, the transmission format shown in Table 2 below can also be used:

[0147]

[0148] Table 2

[0149] In Table 2 above, the first transmission cycle is the transmission command identifier (CMD), which is used to confirm what operation to perform, thereby quickly initiating the corresponding logic control within the PCM.

[0150] The second transmission cycle: transmits the memory address BK, confirms the memory to be operated on, and initiates the logic control of the corresponding memory. The remaining command address transmission end can be used to transmit the burst length information BN.

[0151] The third to fourth transmission cycles: transmit column address and initiate BL direction operation inside PCM.

[0152] Fifth transmission cycle: If there are still column addresses remaining, part of the command address transmission end is used to transmit column addresses, and the remaining command address transmission end is used to transmit row addresses.

[0153] The sixth to seventh transmission cycles: Transmit the remaining row addresses and initiate the WL direction operation within the PCM.

[0154] Eighth transmission cycle: If there are still remaining row addresses, transmission continues. The remaining empty spaces can be used to transmit configuration information such as user option controls.

[0155] It should be noted that the command formats shown in Tables 1 and 2 above are optional implementation methods. The embodiments of this application are not limited to the two mentioned above. Other methods that use multiple cycles to transmit commands and address information separately are also within the protection scope of this application.

[0156] For example, regarding the situation in Table 1 above, the specific instruction format can be found in Table 3 below:

[0157]

[0158] Table 3

[0159] In Table 2 above, BA[3:0] represents the memory address, ADDR[24:0] represents the row and column address, BN[3:0] represents the burst length, and UOP represents user option configuration information, etc. The bits of the X state represent empty bits and can be set to any state. The arrangement of each piece of information in Table 2 above is only an example. In actual applications, the above arrangement can also be adjusted according to the PCM structure and instruction requirements.

[0160] The storage architecture and CA design provided in this application differ from DDR4 in the following ways:

[0161] First, DDR4 requires 24 or more CA pins, while in the embodiments of this application, the required number of CA pins is much less than 24, such as only 6 CA pins in the example above.

[0162] Secondly, DDR4 read operations require two transfer cycles (2 cycles) for activation and reading, while in the embodiments of this application, an access request requires multiple transfer cycles, such as the above example which requires 8 transfer cycles.

[0163] Compared to DDR4, the above design has the following advantages:

[0164] First, fewer pins are required, which can effectively save I / O pin resources, thereby reducing chip area cost and packaging cost.

[0165] Secondly, each major read / write command is divided into 8 transmission cycles to transmit command information and address information respectively, which can support more types of commands and different types of configuration information.

[0166] Third, by prioritizing the acquisition of relevant information through PCM operations, the order of command and address information is reasonably arranged. Even with 8 transmission cycles, the impact on performance such as read / write latency can be small or even negligible at operating frequencies above 1.6 GHz.

[0167] Fourth, the DC and AC electrical characteristics of the signal are compatible with DDR4, which is conducive to the promotion of the system ecosystem.

[0168] Fifth, the various debugging methods for POR power-on are compatible with DDR4, which is conducive to the promotion of the system ecosystem.

[0169] Based on the same inventive concept, embodiments of this application also provide a method for accessing a PCM memory, which is applied to a memory controller; such as Figure 6 As shown, the method includes:

[0170] Step S601: Transmit the command information and address information of the same access request through multiple command address transmission terminals in multiple transmission cycles.

[0171] Understandably, a single access to memory, such as a read or write access, requires the memory controller to provide command information to the memory, informing it of the type of memory access, as well as address information, in order to activate the corresponding memory space to realize the access.

[0172] In this embodiment, by time-division multiplexing multiple command address transmission terminals, the required command and address information can be transmitted in multiple transmission cycles, effectively reducing the number of command address transmission terminals and saving pin resources. Furthermore, based on the principles and characteristics of PCM, as long as the number of transmission cycles is controlled within a certain range, it will not significantly affect the PCM read / write latency, thus not impacting the overall performance of PCM.

[0173] In some embodiments, the command information includes: a command identifier and configuration information; the step S501 above, in which the command information and address information of the same access request are transmitted through multiple command address transmission terminals in multiple transmission cycles, includes:

[0174] Transmit command identifiers in one or more transmission cycles;

[0175] The address and configuration information of the same access request are transmitted in multiple transmission cycles following the transmission command identifier.

[0176] Since the PCM memory needs to start the corresponding internal control logic after receiving the command identification information, the command identification can be transmitted in multiple transmission cycles to inform the PCM memory of the type of instruction currently being accessed.

[0177] In this way, subsequent command and address information can be transmitted while the PCM memory starts its internal control logic, thereby reducing read and write latency.

[0178] In some embodiments, transmitting a command identifier in one or more transmission cycles includes:

[0179] The command identifier is transmitted in the first transmission cycle.

[0180] In some embodiments, the PCM includes multiple memory banks; address information includes: memory bank addresses;

[0181] The above-mentioned transmission of address information and configuration information for the same access request in multiple transmission cycles following the transmission command identifier includes:

[0182] The memory address is transmitted in the next transmission cycle following the transmission command identifier.

[0183] In other words, the command identifier can be transmitted in the first transmission cycle, and the memory address can be transmitted in the second transmission cycle. At this time, the PCM memory can also start the corresponding control logic of the memory, while continuing to receive the remaining address information and other configuration information.

[0184] In some embodiments, the number of bits in the memory address is less than or equal to the number of command address transmission endpoints;

[0185] The above-mentioned transmission of address information and configuration information of the same access request in multiple transmission cycles after the transmission command identifier also includes:

[0186] During the transmission cycle of the memory address, other address information and / or configuration information are transmitted.

[0187] Since the number of bits required for the memory address is relatively small, other information can be transmitted synchronously during the transmission cycle of the memory address. This allows for the efficient use of each transmission cycle and improves transmission efficiency.

[0188] In some embodiments, the address information further includes burst length information; the above-mentioned transmission of the address information and configuration information of the same access request in multiple transmission cycles after the transmission command identifier further includes:

[0189] Transmit burst length information in any transmission cycle following the transmission of the memory address;

[0190] Or the burst length information may be transmitted in the same transmission cycle as the memory address.

[0191] In some embodiments, the number of bits in the burst length information is less than the number of command address transmission ends; the above-mentioned transmission of the address information and configuration information of the same access request in multiple transmission cycles after the transmission command identifier further includes:

[0192] During the transmission period of the burst length, other address information and / or configuration information are transmitted synchronously.

[0193] Since the number of bits required for burst length information is also relatively small, other information can be transmitted synchronously during the transmission period of this burst length information, thereby improving transmission efficiency.

[0194] In some embodiments, the address information further includes row address and column address; the number of bits in the row address or the column address is greater than or equal to the number of command address transmission ends;

[0195] The above-mentioned transmission of address information and configuration information for the same access request in multiple transmission cycles following the transmission command identifier includes:

[0196] Transmit a portion of the row address or the column address within the same transmission cycle that transmits the memory address; and / or

[0197] The remaining row address and column address are transmitted in one or more transmission cycles after the transmission of the memory address.

[0198] It should be noted that the order in which row addresses or column addresses are transmitted can be set according to actual needs. For example, column addresses can be transmitted first and then row addresses in different transmission cycles, or row addresses and column addresses can be encoded into a whole and transmitted in multiple transmission cycles in a set order. This application does not limit this.

[0199] In some embodiments, the number of bits in the configuration information may be greater than or equal to the total number of command address transmission endpoints; the above-mentioned transmission of the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier includes:

[0200] At least a portion of the configuration information for the same access request is transmitted in at least one transmission cycle following the transmission of address information.

[0201] In this way, by transmitting the command information and address information of the same access request in the above order and arrangement, read and write latency can be minimized and PCM read and write performance can be improved.

[0202] Based on the same inventive concept, this application also provides a communication interface, which is the communication interface in any of the above-mentioned memory systems.

[0203] Based on the same inventive concept, embodiments of this application also provide an electronic device, such as... Figure 7 As shown, the electronic device 700 includes a processor 701 and any of the aforementioned memory systems 702. Exemplarily, this device can be a computer device, a server device, or any other electronic device that requires memory chips.

[0204] It should be noted that the various embodiments / implementations provided in this application can be combined with each other without creating contradictions. Furthermore, the above descriptions are merely preferred embodiments of this application and are not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory system, characterized in that, The memory system includes: a phase-change memory (PCM) and a memory controller; A communication interface is provided between the memory controller and the PCM; The communication interface includes: multiple command address transmission terminals; wherein, the command address transmission terminals are used to transmit command information and address information of the same access request in multiple transmission cycles respectively.

2. The memory system according to claim 1, characterized in that, The number of command address transmission endpoints is less than the total number of bits in the address information of the PCM.

3. The memory system according to claim 1, characterized in that, The command information includes: command identifier and configuration information; the command address transmission terminal is specifically used for: Within the plurality of transmission cycles, the command identifier is transmitted in one or more transmission cycles, and the address information and the configuration information are transmitted in a plurality of transmission cycles following the transmission of the command identifier.

4. The memory system according to claim 3, characterized in that, For the same access request, the command address transmission end transmits the command identifier in the first transmission cycle.

5. The memory system according to claim 3, characterized in that, The PCM includes multiple memory banks; the address information includes: memory bank addresses; Specifically, for the same access request, the command address transmission end transmits the storage address in the next transmission cycle after transmitting the command identifier.

6. The memory system according to claim 5, characterized in that, The number of bits in the memory address is less than or equal to the number of command address transmission terminals; During the transmission cycle of transmitting the memory address, the remaining command address transmission end is used to transmit other address information and / or configuration information.

7. The memory system according to claim 5, characterized in that, The address information also includes burst length information; wherein, for the same access request, the command address transmission end transmits the burst length information in any transmission cycle after transmitting the memory address; or, the command address transmission end transmits the burst length information in the same transmission cycle as transmitting the memory address.

8. The memory system according to claim 7, characterized in that, The number of bits in the burst length information is less than the number of command address transmission terminals; During the transmission period of the burst length, the remaining command address transmission end is used to transmit other address information and / or configuration information.

9. The memory system according to claim 5, characterized in that, The address information also includes row address and column address; The number of bits in the row address or the column address is greater than or equal to the number of command address transmission ends, and the row address and the column address are transmitted in one or more cycles.

10. The memory system according to claim 9, characterized in that, For the same access request, the command address transmission end transmits part of the row address or the column address within the same transmission cycle of transmitting the memory address, and transmits the remaining row address and column address in one or more transmission cycles after transmitting the memory address.

11. The memory system according to claim 3, characterized in that, For the same access request, the command address transmission terminal transmits at least a portion of the configuration information in one or more transmission cycles after transmitting the address information.

12. A method for accessing a PCM memory, characterized in that, The method is applied to a memory controller; the method includes: The command and address information of the same access request are transmitted separately by multiple command address transmission terminals in multiple transmission cycles.

13. The access method according to claim 12, characterized in that, The command information includes: command identifier and configuration information; the transmission of the command information and address information of the same access request through the multiple command address transmission terminals in multiple transmission cycles includes: The command identifier is transmitted in one or more transmission cycles; The address information and configuration information of the same access request are transmitted in multiple transmission cycles following the transmission of the command identifier.

14. The access method according to claim 13, characterized in that, The transmission of the command identifier in one or more transmission cycles includes: The command identifier is transmitted in the first transmission cycle.

15. The access method according to claim 13, characterized in that, The PCM includes multiple memory banks; the address information includes: memory bank addresses; The transmission of the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes: The memory address is transmitted in the next transmission cycle after the command identifier is transmitted.

16. The access method according to claim 15, characterized in that, The number of bits in the memory address is less than or equal to the number of command address transmission terminals; The method of transmitting the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes: During the transmission cycle of transmitting the memory address, other address information and / or configuration information are transmitted.

17. The access method according to claim 15, characterized in that, The address information also includes burst length information; the transmission of the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes: The burst length information is transmitted in any transmission cycle following the transmission of the memory address; Or the burst length information may be transmitted in the same transmission cycle as the memory address.

18. The access method according to claim 17, characterized in that, The number of bits in the burst length information is less than the number of command address transmission terminals; The method of transmitting the address information and configuration information of the same access request in multiple transmission cycles after transmitting the command identifier further includes: During the transmission period of the burst length, other address information and / or configuration information are transmitted synchronously.

19. The access method according to claim 15, characterized in that, The address information also includes row address and column address; the number of bits in the row address or the column address is greater than or equal to the number of command address transmission ends; The transmission of the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes: Transmit a portion of the row address or the column address within the same transmission cycle that transmits the memory address; and / or The remaining row address and column address are transmitted in one or more transmission cycles after the transmission of the memory address.

20. The access method according to claim 13, characterized in that, The transmission of the address information and configuration information of the same access request in multiple transmission cycles following the transmission of the command identifier includes: At least a portion of the configuration information of the same access request is transmitted in at least one transmission cycle after the transmission of the address information.

21. A communication interface, characterized in that, The communication interface is the communication interface in any of the memory systems described in claims 1 to 11.

22. An electronic device, characterized in that, Includes a processor and a memory system as described in any one of claims 1 to 11.

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