Method for verifying function of multi-mode redundancy reinforced circuit by using scan chain structure
By constructing a scan chain structure and automatically generating test stimulus sequences, the functional verification process of multi-mode redundancy hardened circuits is simplified, achieving efficient circuit functional verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 安徽芯纪元科技有限公司
- Filing Date
- 2026-03-03
- Publication Date
- 2026-06-05
AI Technical Summary
Functional verification of multi-mode redundancy hardened circuits is complex, and existing technologies make it difficult to perform verification simply and effectively.
The functional verification of multi-mode redundancy hardened circuits is carried out using a scan chain structure. This is achieved by constructing a scan chain structure, replacing the redundant hardened units step by step, and using the ATPG tool to automatically generate test stimulus sequences. The test response sequences are then compared to verify the circuit function.
The process of generating test stimulus sequences is simplified, which can effectively verify the functionality of multi-mode redundancy hardened circuits and improve verification efficiency.
Smart Images
Figure CN122154585A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to multi-mode redundancy hardened circuits, and more specifically to a method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure. Background Technology
[0002] In harsh electromagnetic environments such as outer space, chips are often affected by single-event upsets (SEUs). Memory and register files, used for storing all instructions and data as well as temporarily storing data between arithmetic units, are more susceptible to SEUs due to their large size.
[0003] The key to radiation-hardened design lies in employing various structural hardening techniques. Currently, multi-mode redundancy (MMR) is a relatively effective and widely used hardening technique. However, MMR-hardened circuits have lower fault tolerance. For example, in a triple-mode-redundant register system, if one register permanently fails, the system will degrade to a dual-mode-redundant system, significantly reducing its fault tolerance to subsequent transient faults. Therefore, functional verification of MMR-hardened circuits is crucial.
[0004] However, the addition of multimode redundancy registers makes circuit functional verification more complex. Against this backdrop, this invention provides a method for functional verification of multimode redundancy hardened circuits using a scan chain structure, which simplifies the generation of test stimulus sequences and effectively verifies the functionality of multimode redundancy hardened circuits. Summary of the Invention
[0005] (a) Technical problems to be solved
[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure, which can effectively overcome the shortcomings of the prior art in that it is difficult to effectively and conveniently verify the functionality of multi-mode redundancy hardened circuits.
[0007] (II) Technical Solution
[0008] To achieve the above objectives, the present invention provides the following technical solution:
[0009] A method for functional verification of multi-mode redundancy hardened circuits using a scan chain structure includes the following steps:
[0010] S1. Construct a scan chain structure for the original function registers;
[0011] S2. Perform multi-mode redundancy replacement operations on the original function registers step by step to form multiple redundancy hardening units with a scan chain structure.
[0012] S3. During functional verification, a test stimulus sequence is automatically generated and input into the first group of redundant hardening units. Data is transmitted on multiple redundant hardening units, and the test response sequence is output by the last group of redundant hardening units.
[0013] S4. Functional verification of the multi-mode redundancy hardened circuit is performed by comparing the test stimulus sequence and the test response sequence.
[0014] Preferably, in S1, a scan chain structure is constructed for the original function registers, including:
[0015] Multiple SDFF flip-flops are cascaded by connecting the output Q of the previous SDFF flip-flop to the SI terminal of the next SDFF flip-flop, thus constructing a scan chain structure for the original function registers.
[0016] Preferably, in S2, a multi-modal redundancy replacement operation is performed on the original function registers in steps to form multiple redundancy-hardened units with a scan chain structure, including:
[0017] S21. Copy the SDFF type flip-flops at each level, and add the corresponding number of DFF type flip-flops in each level according to the redundancy modulus;
[0018] S22. After physical design placement and clock tree synthesis, replace the SDFF type flip-flops in each stage with DFF type flip-flops, and add a data selector in each stage;
[0019] S23. Add a voting device to each level to form multiple redundant hardened units with a scanning chain structure.
[0020] Preferably, in S21, the SDFF type flip-flops at each stage are replicated, and a corresponding number of DFF type flip-flops are added to each stage according to the redundancy modulus, including:
[0021] Connect the input terminals D of all the flip-flops in each stage together.
[0022] Preferably, in S22, after physical design placement and clock tree synthesis, the SDFF type flip-flops in each stage are replaced with DFF type flip-flops, and a data selector is added in each stage, including:
[0023] Within each level, connect the output Y of the data selector to the input D of all DFF type flip-flops;
[0024] Between each stage, connect the output Q of the previous stage DFF type flip-flop to the I terminal of the next stage data selector.
[0025] Preferably, in S23, a voting device is added to each level to form multiple redundant hardened units with a scanning chain structure, including:
[0026] Within each level, connect the output Q of all DFF type flip-flops to the input of the voter;
[0027] Between each level, the output of the previous level voter is connected to the 1st end of the next level data selector, forming multiple redundant hardened units with a scan chain structure.
[0028] Preferably, during functional verification in S3, a test stimulus sequence is automatically generated and input into the first group of redundant hardening units. Data is transmitted across multiple redundant hardening units, and the last group of redundant hardening units outputs a test response sequence, including:
[0029] During functional verification, the test stimulus sequence test_si is automatically generated using the ATPG tool and input into the first data selector MUX1 of the first group of redundant hardening units. After the data is selected by the first voter, it is transmitted to the second group of redundant hardening units. Finally, the test response sequence test_so is obtained at the output of the nth voter of the last group of redundant hardening units.
[0030] Where n is the redundancy modulus.
[0031] Preferably, in step S4, the multi-mode redundancy hardened circuit is functionally verified by comparing the test stimulus sequence with the test response sequence, including:
[0032] Compare the test stimulus sequence test_si with the test response sequence test_so. If the two sequences are the same, the function of the multi-mode redundancy hardening circuit is verified to be correct; if the two sequences are different, the function of the multi-mode redundancy hardening circuit is verified to be incorrect, thus effectively verifying the functionality of the multi-mode redundancy hardening circuit.
[0033] (III) Beneficial Effects
[0034] Compared with the prior art, the method for functional verification of multimode redundancy hardened circuits using a scan chain structure provided by the present invention restores the functional characteristics of the scan chain by chaining multimode redundancy registers together. This enables the automatic generation of test stimulus sequences using the ATPG tool. Through the present invention, not only can the process of generating test stimulus sequences be simplified, but the functionality of multimode redundancy hardened circuits can also be effectively verified by test stimulus sequences based on the scan chain structure. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0036] Figure 1 This is a schematic diagram of the multi-mode redundancy hardening circuit in this invention;
[0037] Figure 2 This is a schematic diagram of constructing a scan chain structure for the original functional registers in this invention;
[0038] Figure 3 This is a schematic diagram illustrating the replication of SDFF type flip-flops at each stage in this invention, where a corresponding number of DFF type flip-flops are added to each stage based on the redundancy modulus.
[0039] Figure 4 This is a schematic diagram illustrating the replacement of SDFF-type triggers with DFF-type triggers in each stage of the present invention, and the addition of a data selector in each stage;
[0040] Figure 5 This is a schematic diagram illustrating the addition of a voting device at each level in this invention to form multiple redundant hardened units with a scanning chain structure. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0042] The following examples illustrate the use of a scanning chain structure to strengthen multi-mode redundancy circuits (such as...) provided by this invention. Figure 1 The specific process and technical effects of the functional verification method (shown) are described.
[0043] S1. Construct a scan chain structure for the original function registers, such as... Figure 2 As shown, it includes:
[0044] Multiple SDFF flip-flops are cascaded by connecting the output Q of the previous SDFF flip-flop to the SI terminal of the next SDFF flip-flop, thus constructing a scan chain structure for the original function register (i.e., multiple SDFF flip-flops).
[0045] S2. Perform multi-modal redundancy replacement operations on the original function registers in steps to form multiple redundancy-hardened units with a scan chain structure, including:
[0046] S21. Copy the SDFF type flip-flops at each stage, and add the corresponding number of DFF type flip-flops (e.g., based on the redundancy modulus) to each stage. Figure 3As shown, taking triple-modulus redundancy as an example, two DFF type flip-flops are added in each stage.
[0047] S22. After physical design placement and clock tree synthesis, replace the SDFF type flip-flops in each stage with DFF type flip-flops, and add a data selector (e.g., ...) in each stage. Figure 4 (as shown)
[0048] S23. Add a voting device to each level to form multiple redundant hardened units with a scanning chain structure (such as...). Figure 5 (As shown).
[0049] Specifically, in S21, the SDFF type flip-flops at each stage are replicated, and the corresponding number of DFF type flip-flops are added to each stage according to the redundancy modulus, such as... Figure 3 As shown, it includes:
[0050] Connect the input terminals D of all the flip-flops in each stage together.
[0051] Specifically, in S22, after physical design placement and clock tree synthesis, the SDFF type flip-flops in each stage are replaced with DFF type flip-flops, and a data selector is added to each stage, such as... Figure 4 As shown, it includes:
[0052] Within each level, connect the output Y of the data selector to the input D of all DFF type flip-flops;
[0053] Between each stage, connect the output Q of the previous stage DFF type flip-flop to the I terminal of the next stage data selector.
[0054] Specifically, in S23, a voting unit is added to each level, forming multiple redundant hardened units with a scan chain structure, such as... Figure 5 As shown, it includes:
[0055] Within each level, connect the output Q of all DFF type flip-flops to the input of the voter;
[0056] Between each level, the output of the previous level voter is connected to the 1st end of the next level data selector, forming multiple redundant hardened units with a scan chain structure.
[0057] S3. During functional verification, a test stimulus sequence is automatically generated and input into the first group of redundant hardening units. Data is transmitted across multiple redundant hardening units, and the last group of redundant hardening units outputs the test response sequence, such as... Figure 5 As shown, it includes:
[0058] During functional verification, the test stimulus sequence test_si is automatically generated using the ATPG tool and input into the first data selector MUX1 of the first group of redundant hardening units. After the data is selected by the first voter, it is transmitted to the second group of redundant hardening units. Finally, the test response sequence test_so is obtained at the output of the nth voter of the last group of redundant hardening units.
[0059] Where n is the redundancy modulus.
[0060] S4. Functional verification of the multi-mode redundancy hardened circuit is performed by comparing the test stimulus sequence and the test response sequence, including:
[0061] Compare the test stimulus sequence test_si with the test response sequence test_so. If the two sequences are the same, the function of the multi-mode redundancy hardening circuit is verified to be correct; if the two sequences are different, the function of the multi-mode redundancy hardening circuit is verified to be incorrect, thus effectively verifying the functionality of the multi-mode redundancy hardening circuit.
[0062] In the technical solution of this application, by chaining multi-mode redundancy registers together, the functional characteristics of the scan chain are restored, and the test stimulus sequence can be automatically generated using the ATPG tool. Through this invention, not only can the process of generating the test stimulus sequence be simplified, but the functionality of the multi-mode redundancy hardened circuit can also be effectively verified by the test stimulus sequence based on the scan chain structure.
[0063] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure, characterized in that: Includes the following steps: S1. Construct a scan chain structure for the original function registers; S2. Perform multi-mode redundancy replacement operations on the original function registers step by step to form multiple redundancy hardening units with a scan chain structure. S3. During functional verification, a test stimulus sequence is automatically generated and input into the first group of redundant hardening units. Data is transmitted on multiple redundant hardening units, and the test response sequence is output by the last group of redundant hardening units. S4. Functional verification of the multi-mode redundancy hardened circuit is performed by comparing the test stimulus sequence and the test response sequence.
2. The method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure according to claim 1, characterized in that: S1 constructs a scan chain structure for the original function registers, including: Multiple SDFF flip-flops are cascaded by connecting the output Q of the previous SDFF flip-flop to the SI terminal of the next SDFF flip-flop, thus constructing a scan chain structure for the original function registers.
3. The method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure according to claim 2, characterized in that: In S2, the original function registers are replaced step by step with multi-mode redundancy replacement operations to form multiple redundancy-hardened units with a scan chain structure, including: S21. Copy the SDFF type flip-flops at each level, and add the corresponding number of DFF type flip-flops in each level according to the redundancy modulus; S22. After physical design placement and clock tree synthesis, replace the SDFF type flip-flops in each stage with DFF type flip-flops, and add a data selector in each stage; S23. Add a voting device to each level to form multiple redundant hardened units with a scanning chain structure.
4. The method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure according to claim 3, characterized in that: In S21, SDFF type flip-flops at each level are replicated, and a corresponding number of DFF type flip-flops are added to each level according to the redundancy modulus, including: Connect the input terminals D of all the flip-flops in each stage together.
5. The method for functional verification of multi-mode redundancy hardened circuits using a scan chain structure according to claim 4, characterized in that: In S22, after physical design placement and clock tree synthesis, the SDFF type flip-flops in each stage are replaced with DFF type flip-flops, and a data selector is added to each stage, including: Within each level, connect the output Y of the data selector to the input D of all DFF type flip-flops; Between each stage, connect the output Q of the previous stage DFF type flip-flop to the I terminal of the next stage data selector.
6. The method for functional verification of multi-mode redundancy hardened circuits using a scan chain structure according to claim 5, characterized in that: In S23, a voting unit is added to each level, forming multiple redundant hardened units with a scan chain structure, including: Within each level, connect the output Q of all DFF type flip-flops to the input of the voter; Between each level, the output of the previous level voter is connected to the 1st end of the next level data selector, forming multiple redundant hardened units with a scan chain structure.
7. The method for functional verification of multi-mode redundancy hardened circuits using a scanning chain structure according to claim 3, characterized in that: During functional verification in S3, a test stimulus sequence is automatically generated and input into the first set of redundant hardening units. Data is transmitted across multiple redundant hardening units, and the last set of redundant hardening units outputs a test response sequence, including: During functional verification, the test stimulus sequence test_si is automatically generated using the ATPG tool and input into the first data selector MUX1 of the first group of redundant hardening units. After the data is selected by the first voter, it is transmitted to the second group of redundant hardening units. Finally, the test response sequence test_so is obtained at the output of the nth voter of the last group of redundant hardening units. Where n is the redundancy modulus.
8. The method for functional verification of multi-mode redundancy hardened circuits using a scan chain structure according to claim 7, characterized in that: In S4, the multi-mode redundancy hardened circuit is functionally verified by comparing the test stimulus sequence and the test response sequence, including: Compare the test stimulus sequence test_si with the test response sequence test_so. If the two sequences are the same, the function of the multi-mode redundancy hardening circuit is verified to be correct; if the two sequences are different, the function of the multi-mode redundancy hardening circuit is verified to be incorrect, thus effectively verifying the functionality of the multi-mode redundancy hardening circuit.