Circuit timing processing method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a circuit timing processing method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits. The method comprises: obtaining a timing violation path in a chip circuit and a timing margin of the timing violation path; the timing margin of the timing violation path does not satisfy a timing constraint condition; determining interface attribute information of an interface connection through which the timing violation path passes; based on the interface attribute information and the timing margin, determining a physical position of a delay unit to be inserted in the timing violation path; and generating a control instruction according to the physical position of the delay unit, the control instruction being used to instruct insertion of the delay unit at the physical position. The present scheme can improve the efficiency of circuit timing processing.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and more specifically, to a circuit timing processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the back-end design flow of digital chips, static timing analysis tools are widely used to detect setup and hold timing violations. When a hold timing violation is detected, engineers usually call the Engineering Change Order (ECO) of the Electronic Design Automation (EDA) tool and automatically decide to add delay units through the internal algorithm of the EDA tool to complete the repair.

[0003] However, this traditional circuit timing processing method, and the engineering change instruction decision of electronic design automation tools, rely entirely on internal black-box algorithms. These algorithms are invisible to users, unconfigurable, and undebuggable, which leads to problems such as added delay units easily clustering in local low-density areas, forming clusters, detours, short circuits, SI (Signal Integrity), IR (IR Drop), and winding, etc. These problems often require multiple rounds of engineering change ECO iterations to achieve the expected repair effect, resulting in low efficiency in circuit timing processing.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a circuit timing processing method, apparatus, electronic device, and computer-readable storage medium that can insert delay units at more accurate physical locations, making the layout of delay units more uniform, reducing physical conflicts, improving the success rate of circuit timing repair, thereby reducing the number of ECO iterations for engineering changes and improving the efficiency of circuit timing processing.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to a first aspect of the present disclosure, a circuit timing processing method is provided, the method comprising: obtaining a timing violation path and a timing margin of the timing violation path in a chip circuit; the timing margin of the timing violation path does not satisfy timing constraints; obtaining interface attribute information of the interface connection points traversed by the timing violation path; determining the physical location of a delay unit to be inserted in the timing violation path based on the interface attribute information and the timing margin; and generating a control instruction based on the physical location of the delay unit, the control instruction being used to instruct the insertion of the delay unit at the physical location.

[0008] In this example embodiment, by obtaining the timing violation path in the chip circuit where the timing margin does not meet the timing constraints, and the timing margin of the timing violation path, the interface attribute information of the interface connection traversed by the timing violation path can be obtained. This interface attribute information can reflect interface-related information such as interface geometry and port type. Based on this interface attribute information and timing margin, the physical location of the delay unit to be inserted in the timing violation path can be accurately determined. Then, control instructions are generated according to the physical location of the delay unit to instruct the insertion of the delay unit at the physical location. This engineering change ECO decision is more transparent and debuggable, avoiding complete reliance on internal black-box algorithms that are invisible and undebuggable to the user, which can lead to delay units being concentrated in local low-density areas, forming clustering, detours, short circuits, SI (Signal Integrity), and IR (Inverse Relationship). To address issues such as drop (voltage drop) and the increased complexity of winding, inserting delay units at more precise physical locations results in a more uniform layout of delay units, reduces physical conflicts, improves the success rate of circuit timing repair, and consequently reduces the number of ECO iterations for engineering changes, thereby improving the efficiency of circuit timing processing.

[0009] Furthermore, traditional circuit timing processing methods, such as inserting delay cells during large-scale ECO processing, tend to concentrate the insertion location in local areas, triggering a large number of place refinements and detours, which further amplifies the delay deviation between the actual introduced delay and the delay estimation result.

[0010] In this embodiment, the physical location of the delay unit can be accurately determined and the delay unit can be inserted at that physical location. Even when a large-scale timing violation path occurs, the delay unit will not be inserted into a local area, thus avoiding a large number of layout adjustments and detours. This can prevent deviations in the actual delay introduced in the timing violation path.

[0011] In some example embodiments of this disclosure, based on the aforementioned scheme, obtaining interface attribute information at the interface connection point traversed by the timing violation path includes: determining the target circuit partition traversed by the timing violation path; and obtaining the interface attribute information of the target circuit partition at the interface connection point.

[0012] In this example embodiment, by determining the target circuit partition through which the timing violation path passes, the interface attribute information of the target circuit partition at the interface connection can be obtained more quickly. This avoids the problem of low circuit timing processing efficiency caused by processing the interface attribute information of all circuit partitions through which the timing violation path passes. Therefore, the physical location of the unit to be inserted can be determined more quickly based on the interface attribute information of the target circuit partition, thereby improving the efficiency of circuit timing processing.

[0013] In some example embodiments of this disclosure, determining the target circuit partition traversed by the timing violation path based on the foregoing scheme includes: if the timing violation path traverses at least two candidate circuit partitions, determining the free area information of each candidate circuit partition at its respective interface connection; and determining the target circuit partition from at least two candidate circuit partitions based on the free area information of each candidate circuit partition at its respective interface connection.

[0014] In this example embodiment, if the timing violation path passes through at least two candidate circuit partitions, the free area information of each candidate circuit partition at its respective interface connection is determined. Based on the free area information, the target circuit partition can be accurately determined from at least two candidate circuit partitions, and then a delay unit can be inserted into the target circuit partition to reduce the uncertainty of inserting delay units across circuit partitions. At the same time, it avoids the problems of overcrowding of inserted delay units, such as clustering, detour, short circuit, SI (Signal Integrity), IR (IR Drop), and winding.

[0015] In some example embodiments of this disclosure, based on the aforementioned scheme, and based on interface attribute information and timing margin, determining the physical location of the delay unit to be inserted in the timing violation path includes: determining the physical configuration parameters of the delay unit to be inserted in the target circuit partition based on the timing margin; determining the insertion direction of the delay unit to be inserted in the target circuit partition based on the interface attribute information; and determining the physical location of the delay unit to be inserted in the target circuit partition according to the physical configuration parameters of the delay unit to be inserted and the insertion direction of the delay unit to be inserted.

[0016] In this example embodiment, the physical configuration parameters of the delay units to be inserted in the target circuit partition can be accurately determined based on timing margins, and the insertion direction of the delay units to be inserted in the target circuit partition can be accurately determined based on interface attribute information. Therefore, according to the physical configuration parameters and the insertion direction, the physical location of the delay units to be inserted can be accurately determined, and the corresponding target delay can be accurately inserted to perform timing repair processing on timing violation paths. This effectively avoids secondary violations or iterative rework caused by incorrect direction or configuration mismatch in traditional black-box ECO. Furthermore, each delay unit can be orderly distributed in the determined physical location in the target circuit partition, effectively avoiding disorderly clustering in local void areas. This reduces physical risks such as metal short circuits, signal integrity (SI) degradation, and power network voltage drop (IR drop) caused by high-density insertion, thereby improving routing success rate and manufacturing yield.

[0017] In some example embodiments of this disclosure, based on the aforementioned scheme, the interface attribute information includes interface geometry information and port type; based on the interface attribute information, determining the insertion direction of the delay unit to be inserted in the target circuit partition includes: determining the interface normal of the target circuit partition at the interface boundary according to the interface geometry information; determining the logic direction of the target circuit partition at the interface boundary according to the port type; and determining the insertion direction of the delay unit to be inserted in the timing violation path based on the interface normal and the logic direction.

[0018] In this example embodiment, by determining the interface normal of the target circuit partition at the interface boundary based on the interface geometry information, and combining the port type to determine the logic direction of the target circuit partition at the interface boundary, the delay units can be arranged in a regular direction pointing inwards from the interface normal to the target circuit partition. For interfaces located at the boundary of the circuit partition, this insertion direction can avoid the delay units being inserted obliquely into the adjacent area of ​​the interface, and can also avoid the delay units being inserted beyond the interface boundary into the outside of the target circuit partition, thereby improving the consistency and regularity of the delay unit arrangement, improving the overall efficiency of circuit timing processing, and reducing the error risk caused by manual judgment of the insertion direction.

[0019] In some example embodiments of this disclosure, based on the foregoing scheme, determining the logical direction of the target circuit partition at the interface boundary according to the port type includes: if the port type is an input port, then determining that the logical direction of the target circuit partition at the interface boundary is to extend forward along the logical path of the timing violation path; if the port type is an output port, then determining that the logical direction of the target circuit partition at the interface boundary is to extend backward along the logical path of the timing violation path.

[0020] In this example embodiment, by determining the logical direction of the target circuit partition at the interface boundary based on the port type, different port types are mapped to different logical directions. The insertion direction of the delay unit can be determined more accurately based on the determined logical direction, so that the insertion direction of the delay unit is coordinated with the signal propagation direction, thereby improving the accuracy of delay unit insertion and thus improving the accuracy and reliability of ECO repair.

[0021] In some example embodiments of this disclosure, based on the foregoing scheme, the physical configuration parameters include the type and quantity of delay units; based on timing margin, the physical configuration parameters of the delay units to be inserted in the target circuit partition are determined, including: based on timing margin, determining the target delay to be added in the target circuit partition; the duration of the target delay is greater than or equal to the duration of the timing margin; and determining the type and quantity of delay units to be inserted according to the target delay.

[0022] In this example embodiment, by determining the target delay to be added in the target circuit partition based on the timing margin, and determining the type and number of delay units to be inserted based on the target delay, the abstract delay compensation requirement can be transformed into specific delay unit configuration parameters, thereby avoiding insufficient timing repair due to insufficient delay unit configuration, or increased area and power consumption due to excessive delay unit configuration.

[0023] In some example embodiments of this disclosure, based on the foregoing scheme, the method further includes: aggregating each timing violation path to obtain at least one timing violation path set; and for at least two timing violation paths in the timing violation path set, performing the step of obtaining interface attribute information at the interface connection points traversed by the timing violation path.

[0024] In this example embodiment, each timing violation path is aggregated to obtain at least one set of timing violation paths. Then, the timing violation paths can be replaced with the set of timing violation paths for batch processing, reducing duplicate insertions and conflicting insertions. Furthermore, batch processing of multiple timing violation paths can improve data throughput and circuit timing processing efficiency, meeting the requirements of modern high-performance chips for large-scale timing convergence during the approval stage.

[0025] In some example embodiments of this disclosure, based on the aforementioned scheme, each timing violation path is aggregated to obtain at least one set of timing violation paths, including: obtaining path information of at least two dimensions for each timing violation path; determining each timing violation path with overlapping circuit partitions based on the path information of at least two dimensions, and aggregating each timing violation path with overlapping circuit partitions to obtain at least one set of timing violation paths. Obtain the interface attribute information of the interface connection points traversed by the timing violation path, including: determining the target circuit partition from each overlapping circuit partition in the timing violation path set, and obtaining the interface attribute information of the target circuit partition at the interface connection points.

[0026] In this example embodiment, by first acquiring path information in at least two dimensions for each timing violation path, and then determining and aggregating the timing violation paths with overlapping circuit partitions based on the path information in at least two dimensions, multiple timing violation paths related to the same set of overlapping circuit partitions can be identified. Furthermore, by determining the target circuit partition from the overlapping circuit partitions of this timing violation path set and acquiring the interface attribute information of the target circuit partition at the interface connection point, the process of determining the target circuit partition and acquiring interface attribute information for a single path can be transformed into a centralized determination and acquisition for the same set of timing violation paths. This reduces repetitive partition filtering and interface attribute information acquisition operations, and ensures that the partition objects and interface attribute information used to determine the subsequent physical locations of multiple timing violation paths within the same set remain consistent, thereby improving the efficiency of batch timing violation processing and the consistency of subsequent physical location determination.

[0027] According to a second aspect of the present disclosure, a circuit timing processing apparatus is provided, comprising: a timing violation path acquisition module, configured to acquire timing violation paths in a chip circuit and timing margins of the timing violation paths; wherein the timing margins of the timing violation paths do not satisfy timing constraints; an interface attribute information acquisition module, configured to acquire interface attribute information of the interface connections traversed by the timing violation paths; a physical location determination module, configured to determine the physical location of a delay unit to be inserted in the timing violation path based on the interface attribute information and the timing margins; and a control instruction generation module, configured to generate control instructions based on the physical location of the delay units, wherein the control instructions are used to instruct the insertion of delay units at the physical location.

[0028] According to a third aspect of the present disclosure, an electronic device is provided, including: a processor; and a memory storing computer-readable instructions, which, when executed by the processor, implement the circuit timing processing method as described in the first aspect.

[0029] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the circuit timing processing method as described in the first aspect.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 A schematic diagram of a circuit timing processing method according to some embodiments of the present disclosure is shown. Figure 2 The illustration shows a flowchart illustrating the steps of determining the physical location of a delay unit to be inserted in a timing violation path based on interface attribute information and timing margin, according to some embodiments of the present disclosure. Figure 3 A schematic diagram of a circuit timing processing apparatus according to some embodiments of the present disclosure is shown. Figure 4 The schematic diagram illustrates the structural schematic of a computer system of an electronic device according to some embodiments of the present disclosure; Figure 5 A schematic diagram of a computer-readable storage medium according to some embodiments of the present disclosure is shown.

[0033] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification.

[0035] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] In this example embodiment, a circuit timing processing method is first provided. This method can be applied to electronic design automation systems with physical awareness of ECO (Enhanced Execution of Code) capabilities, specifically including but not limited to: physical implementation platforms running advanced node digital back-end processes, such as chip physical design workstations supporting 7nm and below processes, cloud-based EDA computing clusters, or integrated circuit (IC) design environments. These electronic design automation systems can be configured with placement and routing tools (such as Synopsys ICC2, Cadence Innovus, Siemens Aprisa), static timing analysis engines (such as PrimeTime, Tempus), and an external explicit rule-driven ECO decision module. This module is independent of the internal automatic repair engine of the placement and routing tools and can be integrated with the main toolchain through script interfaces (such as Tcl, Python) or plug-in mechanisms.

[0037] This electronic design automation (EDA) system can be further equipped with a database interface for parsing circuit partition structures (such as tiles, IPs, or user-defined partitions). It can extract interface attribute information such as geometric boundaries, port types (input / output / bidirectional), and signal flow direction at the interface connections of each target circuit partition. Simultaneously, it can support the generation of delay cell placement schemes that conform to manufacturing rules based on preset physical placement rules. Furthermore, the EDA system can integrate a control command generator to output standard-format ECO scripts (such as native tool commands) to drive the placement and routing tools to accurately insert delay cells at specified physical locations. This circuit timing processing method can efficiently repair timing violation paths, effectively avoiding cell clustering, detours, short circuits, SI (Signal Integrity), IR (IR Drop), routing congestion, and multi-round ECO iteration problems caused by reliance on black-box algorithms, thus improving circuit timing processing efficiency and enhancing physical implementation quality.

[0038] In some implementations, chip circuitry can be modularly divided into multiple circuit partitions. Each circuit partition can carry functions such as computing, storage, interface, or dedicated processing, and interact with other circuit partitions or top-level circuitry through its own interface. These circuit partitions can be tiles, IP cores, chiplets, macrocell regions, or user-defined layout partitions. For very large-scale chips, as the number of circuit partitions and cross-partition signal paths increases, the timing reports output by static timing analysis tools such as PrimeTime (PT) during the timing approval stage may contain hundreds of thousands to millions of timing violation paths, with a large number of these paths concentrated near the interface connection areas between circuit partitions. For this type of scenario, multiple timing violation paths can be grouped, aggregated, and processed by combining the circuit partitions, interfaces, port types, and violation characteristics involved, thereby improving the efficiency of large-scale timing violation processing and reducing the number of ECO iterations for engineering changes.

[0039] In some implementations, timing reports containing hundreds of thousands of timing violation paths can be parsed and processed in a single run to support batch ECO decisions and executions in the timing approval stage of VLSI chips.

[0040] Figure 1 A schematic flowchart illustrating a circuit timing processing method according to some embodiments of the present disclosure is shown. (Reference) Figure 1 As shown, the timing processing method for this circuit may include the following steps: Step S110: Obtain the timing violation path and timing margin of the timing violation path in the chip circuit; the timing margin of the timing violation path does not meet the timing constraint conditions. Step S120: Obtain the interface attribute information of the interface connection points traversed by the timing violation path; Step S130: Based on interface attribute information and timing margin, determine the physical location of the delay unit to be inserted in the timing violation path; Step S140: Generate control instructions based on the physical location of the delay unit. The control instructions are used to instruct the insertion of the delay unit at the physical location.

[0041] Understandably, traditional circuit timing processing methods rely on the internal black-box algorithms of electronic design automation (EDA) tools for ECO decisions. Users cannot control or debug these algorithms, resulting in untraceable ECO decision bases, limited and opaque parameter tuning space, high costs for problem localization and debugging, and an inability to control the physical location of inserted delay cells. Furthermore, when executing engineering change ECOs, EDA tools typically specify the logical insertion location of delay cells via ECO commands (e.g., inserting a delay cell between points A and B), without specifying the concrete physical location. Instead, they employ random insertion or fixed-point insertion methods. Since the actual delay introduced by hold-time repair depends not only on the type of delay cell but also on its final physical location, wiring configuration, and surrounding physical resources, specifying the logical location of delay cells via ECO commands is insufficient to accurately control the delay introduced in timing violation paths. This necessitates multiple rounds of engineering change ECO iterations to achieve the desired repair effect, resulting in low efficiency in circuit timing processing.

[0042] Therefore, according to the circuit timing processing method in this example embodiment, by obtaining the timing violation path in the chip circuit where the timing margin does not meet the timing constraint conditions and the timing margin of the timing violation path, the interface attribute information of the interface connection point traversed by the timing violation path can be obtained. This interface attribute information can reflect the interface-related information traversed by the timing violation path, such as interface geometry information and port type. Based on this interface attribute information and timing margin, the physical location of the delay unit to be inserted in the timing violation path can be accurately determined. Then, control instructions are generated according to the physical location of the delay unit to instruct the insertion of the delay unit at the physical location. This engineering change ECO decision basis, such as timing margin and interface attribute information, is completely traceable, more transparent and debuggable. It can avoid relying entirely on internal black-box algorithms that are invisible and undebuggable to the user, which can lead to delay units being concentrated in local low-density areas, forming clustering, detours, short circuits, SI (Signal Integrity), and IR (Inverse Relationship). To address issues such as drop (voltage drop) and increased complexity due to routing, inserting delay cells at more precise physical locations allows for controllable routing increments and delay cell distribution after each iteration. This reduces physical conflicts, minimizes significant offsets caused by refinement, and ensures greater consistency between actual and estimated delays. Consequently, it reduces the need for multiple ECO iterations, improves the success rate of timing repair, and ultimately enhances timing processing efficiency. Furthermore, even if timing issues require debugging, the ECO decision-making process and the more transparent timing process itself facilitate rapid problem identification and debugging, reducing debugging costs.

[0043] Understandably, on the one hand, the rule-driven automated process and avoidance of repetitive path parsing reduce the generation time of ECO control instructions by more than 90% compared to traditional black-box methods; on the other hand, due to the accurate repair location and sufficient delay compensation, the number of ECO iterations is reduced by more than 60% on average, which greatly shortens the closed-loop cycle from time-series analysis to physical approval and improves the overall efficiency of ECO.

[0044] Meanwhile, in ultra-large-scale time-series data scenarios, if the number of time-series violation paths reaches hundreds of thousands or millions, the traditional ECO operation time and resource consumption are unpredictable. It may get stuck for a long time or terminate abnormally, or even fail to reach the script generation stage. There is a high risk that ECO operation is not scalable and cannot be completed.

[0045] The aforementioned circuit timing processing method can efficiently handle hundreds of thousands to millions of timing violation paths, significantly improving the timing processing efficiency of ultra-large-scale chips (such as multi-tile AI accelerators and chiplet-based SoCs), expanding the number of timing violation paths in ECO operations, and reducing the risk of failure due to prolonged stalls or abnormal terminations. Furthermore, the ECO decision-making process is completely transparent, traceable, and debuggable. Design engineers can view the repair criteria for each path through a standard interface, flexibly adjust rule parameters, achieve efficient human-machine collaborative optimization, and improve engineering debugging efficiency and solution reliability.

[0046] The circuit timing processing method in this example embodiment will be further explained below.

[0047] In step S110, the timing violation path and the timing margin of the timing violation path in the chip circuit are obtained; the timing margin of the timing violation path does not meet the timing constraint conditions.

[0048] In this context, a chip circuit refers to an integrated circuit design that has completed logic synthesis or physical implementation. This chip circuit can contain multiple interconnected logic units (such as NAND gates, flip-flops, memory macros, etc.), signal interconnections, and a clock network for synchronous operation. This chip circuit can be an intermediate design in the placement and routing stage, or a nearly completed physical layout, existing in the form of a netlist and physical database for subsequent timing verification and engineering change handling.

[0049] Timing violations refer to situations where the propagation of a signal along a timing path fails to meet timing constraints. Static timing analysis tools can be used to analyze each timing path, and the timing margin in the analysis results can be used to determine if a timing violation exists. When the timing margin does not meet the timing constraints, a timing violation can be identified for the corresponding timing path. In some implementations, timing violations are hold-time violations, meaning that the data signal changes prematurely after the valid clock edge, causing the timing margin of the corresponding timing path to fail to meet the timing constraints.

[0050] A timing violation path refers to a signal propagation path that is identified as containing a timing violation during static timing analysis. Specifically, this timing violation path can start from a timing start point, pass through multiple logic units and interconnects, and finally reach a timing end point. The timing start point can be the output of a register or an input pin of a chip, and the timing end point can be the data input of a register or an output pin of a chip.

[0051] Timing slack refers to the safety margin remaining at the timing endpoint of a timing violation path. Timing constraints are the conditions used to determine whether a path is a timing violation path.

[0052] Understandably, if the delay of a timing violation path is exactly equal to the maximum allowable delay of the clock cycle, the timing margin is zero; if the path delay is less than the allowable value, the margin is positive, indicating that there is sufficient capacity; if the path delay exceeds the allowable value, the margin is negative, indicating that the signal failed to stabilize within the specified time, and a timing violation has occurred. The larger the absolute value of the negative timing margin, the more severe the timing problem, and the greater the amount of delay compensation required.

[0053] Timing constraints are used to determine whether a timing path meets timing requirements. Timing constraints can include setup time constraints and hold time constraints, among others. It is understood that if a timing path does not meet a given timing constraint, it can be considered a timing violation path.

[0054] In some embodiments, timing constraints may include a timing margin greater than or equal to 0 ns (nanoseconds). In other embodiments, timing constraints may also include a timing margin greater than a specified value, such as -0.1 ns (nanoseconds), +0.01 ns (nanoseconds), etc., and are not limited thereto.

[0055] For example, if the hold time margin of timing violation path A is -0.15 nanoseconds, it may be necessary to insert a delay unit with a target delay of 0.15 nanoseconds to make the data signal delay long enough to meet the hold time requirement.

[0056] In other embodiments, timing constraints can also be set as needed, such as the master clock period corresponding to the target operating frequency of the chip circuit, which can be used to limit the maximum allowable delay of signal propagation between adjacent registers, or various setup time constraints, which can specify the minimum time window in which the data signal must stably arrive at the register input before the effective edge of the clock, or various hold time constraints, which can specify the shortest time that the data signal must continue to remain stable after the effective edge of the clock, and so on.

[0057] In some implementations, timing analysis can be performed using the static timing analysis function in electronic design automation tools to generate a timing report, which can then be parsed to extract timing violation paths and timing margins in the chip circuit.

[0058] For example, you can call Synopsys PrimeTime, Cadence Tempus or similar tools to perform timing analysis on the entire path or critical path after loading the netlist, parasitic parameters and timing constraints of the chip circuit. This will generate a timing report, which can include timing violation paths that do not meet the timing constraints and their specific timing margins.

[0059] In other implementations, the path direction of the timing violation path, the circuit partition information of the circuit partition through which the timing violation path passes, and the location information related to each circuit partition and interface can also be extracted from the timing report, and so on.

[0060] In other embodiments, timing violation paths and timing margins can also be obtained in other ways, such as calling the application programming interface provided by the electronic design automation platform to query the timing violation paths and their timing margins in real time from the physical implementation database (such as Synopsys Milkyway or Cadence OpenAccess), or using a scripting language (such as Tcl or Python) to drive the STA (Static Timing Analysis Engine) to perform incremental timing analysis and extract the timing violation paths and their timing margins, etc.

[0061] In step S120, the interface attribute information of the interface connection points traversed by the timing violation path is obtained.

[0062] In this context, an interface connection refers to the physical connection area within a chip's circuitry where signal interaction occurs between different circuit partitions or the top-level circuitry. For timing paths, an interface connection refers to the connection point where the timing path enters, exits, or crosses the boundary of a circuit partition; it can correspond to connection points related to design boundaries, hierarchical module boundaries, or physical partition boundaries. In physical implementation, an interface connection can be represented as a port at the boundary of a circuit partition and its corresponding connection area. Therefore, interface geometry information, port type, and other interface attribute information can be obtained based on the interface connection.

[0063] Interface attribute information refers to attribute data describing the physical and logical properties of an interface connection. This interface attribute information may include interface geometry and port type, as well as signal flow direction, identification of the circuit partition to which it belongs, available wiring resource information, etc., and is not limited to these.

[0064] In some implementations, the aforementioned interface attribute information can be obtained by parsing the circuit partition definition, module I / O list, and timing path traversal record in the chip physical database (such as Milkyway or OpenAccess).

[0065] In other implementations, interface attribute information of the interface connections traversed by timing violation paths can be obtained by calling the interface query command or script interface provided by the electronic design automation tool in the layout and routing environment.

[0066] In other implementations, other methods can be used to obtain the interface attribute information of the interface connection points traversed by the timing violation path, which are not limited here.

[0067] In some embodiments, the interface attribute information of each interface connection along the timing violation path can be directly obtained.

[0068] In other embodiments, the target interface connection points traversed by the timing violation path can also be determined, and the interface attribute information of each target interface connection point can be obtained. The target interface connection point can be one or more of the interface connection points traversed by the timing violation path.

[0069] In some other embodiments, obtaining interface attribute information at the interface connection traversed by the timing violation path includes: determining the target circuit partition traversed by the timing violation path; and obtaining the interface attribute information of the target circuit partition at the interface connection.

[0070] In this context, a target circuit partition refers to a sub-region with clearly defined boundaries that is divided within the chip circuit during the physical implementation or logic design phase, and which is inserted as a delay unit. This target circuit partition can be a functional unit defined based on a modular architecture, such as a tile (computation unit block), IP core (e.g., processor core, memory controller, SerDes interface), chiplet, or macrocell (e.g., SRAM (Static Random-Access Memory), PLL (Phase-Locked Loop)). It can also be a layout region defined by the user through physical constraint files (e.g., FP constraints, partitioning directives). Each target circuit partition occupies a continuous physical coordinate range within the chip circuit and interacts with adjacent circuit partitions or the top-level circuit through a pre-defined interface.

[0071] In some implementations, the target circuit partition can be determined based on the positional relationship between the circuit partitions traversed by the timing violation path and the path critical nodes in the timing violation path. The path critical nodes can be timing endpoints or boundary nodes corresponding to cross-partition connections.

[0072] For example, the distance between each circuit partition and the key node of the path can be determined separately, and the circuit partition with the smallest or second smallest distance can be determined as the target circuit partition.

[0073] In other implementations, the target circuit partition can be determined based on the local implementation conditions of each circuit partition traversed by the timing violation path at the interface connection. These local implementation conditions may include, but are not limited to, routing congestion at the interface connection, cell layout density, available routing resources, or design rule constraints.

[0074] For example, circuit partitions with lower wiring congestion, lower cell layout density, or more available wiring resources can be identified as target circuit partitions.

[0075] In some other specific implementations, determining the target circuit partition traversed by the timing violation path includes: if the timing violation path traverses at least two candidate circuit partitions, determining the free area information of each candidate circuit partition at its respective interface connection; and determining the target circuit partition from the at least two candidate circuit partitions based on the free area information of each candidate circuit partition at its respective interface connection.

[0076] The free area information refers to information about unoccupied free areas located at the interface connections of circuit partitions. This free area information may include the size of the free area, and may also include at least one of the following: the number of available metal rails, the continuous free length in the vertical / horizontal direction, the offset range from the interface boundary, whether an ECO-dedicated area is reserved, and whether there are DRC (Design Rule Check) restrictions in the area.

[0077] Candidate circuit partitioning refers to the sub-regions with clear boundaries that are divided during the physical implementation or logic design phase of a chip circuit, and through which timing violation paths pass.

[0078] In some implementations, the free area information of each candidate circuit partition at its respective interface connection can be determined by combining information such as the relationship between timing violation paths across circuit partitions, interface locations, local resources, risks, and design constraints.

[0079] In other implementations, information on the free space at each interface connection of each circuit partition can be obtained by parsing the placement density map, routing congestion map, or dedicated ECO reservation markers in a physical database (such as Milkyway or OpenAccess).

[0080] In other implementations, other methods may be used to determine the target circuit partition from at least two candidate circuit partitions, which are not limited here.

[0081] In other embodiments, if the timing violation path passes through a circuit partition, then that circuit partition is directly used as the target circuit partition.

[0082] In traditional circuit timing processing methods, it is difficult to accurately select the circuit partition to perform circuit timing repair for violation paths involving multiple circuit partitions, leading to an increase in the uncontrollable risk of ECO processing. However, in this embodiment, if the timing violation path passes through at least two candidate circuit partitions, the free area information at each candidate circuit partition's interface connection is determined. Based on this free area information, the target circuit partition can be accurately determined from at least two candidate circuit partitions. This allows delay units to be inserted into the target circuit partition for circuit timing repair, thereby reducing the uncontrollable risk of ECO processing.

[0083] In step S130, the physical location of the delay unit to be inserted in the timing violation path is determined based on the interface attribute information and timing margin.

[0084] The delay unit refers to a logic unit used to adjust the signal propagation delay. It may include a buffer, an inverter, or a dedicated delay chain. Its function is to increase the propagation time of the path without changing the logic function, so as to correct hold-time violations or fine-tune the setup time margin.

[0085] The physical location refers to the specific coordinate region of the delay cell in the timing violation path, which may include its layout center point in the X and Y directions, its metal layer, orientation, and spacing with adjacent cells.

[0086] In some embodiments, the number and insertion direction of delay units to be inserted in the target circuit partition can be determined based on interface attribute information and timing margin, and the physical location of each delay unit can be determined based on the number and insertion direction.

[0087] Understandably, interface attribute information (such as port type, boundary normal, signal flow direction, etc.) is used to define the insertion direction of delay units. For example, if the interface attribute information includes an output port and the signal flow direction is from inside the partition to the outside, the delay unit can be placed in the adjacent area outside the boundary of the target circuit partition and arranged sequentially along the signal propagation direction; if it is an input port, it can be placed inside the target circuit partition to avoid cross-partition routing.

[0088] Timing margin is used to determine the total amount of delay to be inserted, which in turn determines the number, type, and specific arrangement length of delay units within the available free area. For example, if the timing margin is -0.2 ns and a single buffer provides approximately 0.05 ns of delay, then four buffers need to be cascaded and the corresponding physical space needs to be allocated on consecutive free tracks at the interface connection.

[0089] In step S140, a control command is generated based on the physical location of the delay unit. The control command is used to instruct the insertion of the delay unit at the physical location.

[0090] Control commands refer to engineering change commands that can be recognized and executed by electronic design automation tools (such as placement and routing tools). These control commands may include the physical location where each delay unit needs to be inserted, as well as the type of delay unit, its identifier, etc., and are not limited to these.

[0091] In some embodiments, control commands can be input into an electronic design automation (EDA) tool, and the EDA tool can insert delay units at physical locations in response to the control commands.

[0092] For example, you can use a script to call the native commands of the place-and-route tool (such as create_inst+place_inst in Innovus, or add_buffer_tree in ICC2) to directly create and fix delay cells at the physical location.

[0093] For example, the SDC (Synopsys Design Constraints) extension instruction can be used in conjunction with physically-aware constraint markers to guide subsequent optimization processes to retain the insertion operation.

[0094] In other embodiments, control instructions for each timing violation path can be merged to generate an ECO script, which is then imported into an electronic design automation (EDA) tool for execution and verification. The ECO script may also include, but is not limited to, the insertion object (i.e., delay cell), the target circuit partition into which the delay cell is to be inserted, the number of delay cells, the type of delay cell, physical constraints, and physical configuration parameters.

[0095] In some implementations, the control commands generated for each timing violation path or set of timing violation paths can also be associated and recorded with the corresponding timing data, target circuit partition information, interface geometry information, port type information, and physical configuration parameters. Therefore, the insertion object, insertion direction, physical location, and corresponding control commands of the delay unit can all be traced back to the corresponding timing margin, path information, or circuit partition boundary geometry information, making the ECO decision-making process more transparent and facilitating subsequent debugging, verification, and rule adjustment.

[0096] Furthermore, since the control commands corresponding to each delay unit can be associated with the corresponding timing data, path information, or circuit partition boundary geometry information, each ECO decision result has a clear data source and rule basis, which makes it easy for designers to quickly locate the impact of rule parameters, path information, or interface geometry information on the repair results, thereby making the debugging process clearer and improving debugging efficiency.

[0097] In other embodiments, control instructions for each timing violation path or set of timing violation paths can be merged to generate a structured ECO script, which is then imported into an electronic design automation (EDA) tool for execution and verification. The structured ECO script may include information such as the insertion object, the target circuit partition, the number of delay cells, the type of delay cells, physical constraints, and physical configuration parameters.

[0098] Understandably, multiple control instructions in the ECO script can be used to perform timing repair on timing violation paths in batches, and hundreds of thousands of paths can be parsed and repaired in a single run.

[0099] In other embodiments, the control instructions may further include electrical connection information, such as specifying that the input of the delay unit is connected to the upstream node of the original path, the output is connected to the downstream node, and automatically updating the connection relationships in the netlist.

[0100] In other embodiments, the control instructions may also include a physical verification exemption flag to avoid issues in subsequent DRC / LVS (Layout Versus Schematic). Figure 1 (Inconsistency check) A false alarm was triggered during the check due to the addition of a new unit.

[0101] The contents of steps S110 to S140 will be described in detail below.

[0102] In an example embodiment of this disclosure, such as Figure 2 As shown, based on interface attribute information and timing margin, the physical location of the delay unit to be inserted in the timing violation path is determined, including the following steps S210 to S230: Step S210: Based on the timing margin, determine the physical configuration parameters of the delay units to be inserted in the target circuit partition.

[0103] The physical configuration parameters refer to the configuration parameters describing the delay unit at the physical implementation level. These parameters may include the type (such as buffer, inverter, or dedicated delay cell) and number of delay units, as well as the physical spacing between adjacent delay units (which can be any specified distance), the initial offset of the delay unit along the interface normal to the target circuit partition port, and the offset of the delay unit along the interface tangential direction (up / down / left / right), and are not limited to these.

[0104] For example, physical configuration parameters may include the type and number of delay unit groups extending into the target circuit partition along the normal direction (e.g., 5 consecutive buffers), the physical spacing between adjacent delay units, the initial offset of the delay unit relative to the tile port along the normal direction, and the offset of the delay unit group along the interface tangential direction (top / bottom left / right). This offset of the delay unit group along the interface tangential direction (top / bottom left / right) can be used to avoid congestion, MACRO (macrocell), or special DRC regions.

[0105] Specifically, the relationship between preset timing margins and physical configuration parameters can be obtained. Based on this relationship and the timing margins, the physical configuration parameters of the delay units to be inserted in the target circuit partition can be determined. The preset relationship between timing margins and physical configuration parameters can be one or more forms such as a pre-configured correspondence table or formula.

[0106] For example, if the timing margin is -0.18 nanoseconds and the single-stage delay of an X2 buffer in the technology library is approximately 0.06 nanoseconds, then three X2 buffers can be configured. If free space is limited, a single-stage large-size cell with high drive strength can be configured to save space. This configuration process can be completed through table lookup, linear interpolation, or calling the timing model from the cell library, ensuring that the selected configuration meets both timing repair requirements and area and power consumption constraints.

[0107] In other embodiments, the physical configuration parameters of the delay unit to be inserted in the target circuit partition can be pre-configured by default, or can be configured in real time or obtained by adjusting the physical configuration parameters of the default configuration, and are not limited thereto.

[0108] In other embodiments, the physical configuration parameters include the type and number of delay units; determining the physical configuration parameters of the delay units to be inserted in the target circuit partition based on timing margin includes: determining the target delay to be added in the target circuit partition based on timing margin; the duration of the target delay is greater than or equal to the duration of the timing margin; and determining the type and number of delay units to be inserted according to the target delay.

[0109] The target delay refers to the amount of signal propagation delay that needs to be inserted to correct timing violation paths. The target delay can be set based on the timing margin: since a negative timing margin (e.g., -0.15 nanoseconds) indicates that the current path delay is too short or arrives too early relative to the clock edge, a delay unit must be inserted to lengthen the signal transmission time. The duration of the target delay can be set to a value greater than or equal to the absolute value of this negative margin to ensure that the corrected path meets timing constraints and to allow for certain process or environmental fluctuations. For example, if the timing margin is -0.12 nanoseconds, the target delay can be set to 0.12 nanoseconds, 0.15 nanoseconds, etc., and the specific value can be adjusted according to the design convergence strategy and physical implementation conditions.

[0110] The type of delay cell refers to the specific category of a predefined standard cell used to provide controllable delay. In the standard cell library of digital integrated circuits, delay cell types can include buffers, inverters, and dedicated delay chain cells. Buffers are used to increase delay without changing the signal's logic polarity; inverters invert signal polarity while providing delay and are typically used in pairs to maintain logic functionality; dedicated delay chain cells are multi-stage structures designed for precise delays, offering more stable delay characteristics. Each type can be further subdivided into different sizes based on drive capability, such as X1, X2, X4, X8, etc. Larger numbers indicate stronger drive current and larger cell area, but the delay per stage may vary slightly.

[0111] In some implementations, the aforementioned delay unit may be a buffer unit or other unit used to increase the signal propagation delay.

[0112] Based on the target delay, determine the type and quantity of delay cells to be inserted from the set of available delay cells provided by the technology library. The technology library can contain various types of buffers, inverters, or dedicated delay cells, each with known propagation delay and drive capability under specific operating conditions (such as voltage, temperature, and load).

[0113] In some implementations, the timing model of the cell library (such as the Liberty file) can be consulted to select a combination of schemes that can achieve the target latency with the fewest number of cells and the least area overhead. For example, if a single X2 buffer provides a latency of about 0.05 nanoseconds, three X2 buffers can be cascaded to achieve a target latency of 0.15 nanoseconds; if space is limited but higher power consumption is permissible, a high-drive-strength X8 cell can also be selected.

[0114] This selection process can be implemented using greedy algorithms, dynamic programming, or lookup table mapping, taking into account factors such as fan-out load, signal polarity preservation (to avoid introducing an odd number of inverters that could lead to logic errors), and the feasibility of subsequent wiring. The final output physical configuration parameters are the specific type of the selected delay unit (e.g., "BUF_X2") and its series quantity (e.g., 3), which serve as the basic input for determining the physical location and generating control commands.

[0115] In other implementations, the type and number of delay units to be inserted corresponding to the target delay can be directly queried through a pre-configured correspondence between delays and delay units.

[0116] It is understood that the type, number, and corresponding physical distance rules of the delay units can be adjusted as needed and are not limited here. For example, different combinations of delay units, spacing rules, or offset rules can be adopted according to different process library conditions, resource conditions in the interface's adjacent area, or target delay requirements. As long as the corresponding delay compensation can be achieved, they can all be used as alternative implementation methods of this disclosure.

[0117] In traditional circuit timing processing, electronic design automation tools struggle to support configurable control over the interstage spacing, relative port offset, and left and right offset along the boundary tangential direction of a group of delay cells (such as multiple consecutive buffer / delay cells), making it difficult to adapt to the interface resources and avoidance requirements of different circuit partitions.

[0118] In this embodiment, the physical configuration parameters such as the type and number of delay units to be inserted can be accurately determined based on the target delay. When there are multiple delay units, the physical positions of multiple delay units to be inserted in the target circuit partition can be accurately determined based on the physical configuration parameters of the delay units to be inserted and the insertion direction of the delay units to be inserted. This adapts to the interface resources and avoidance requirements of different target circuit partitions and accurately controls the interstage spacing, relative port offset, and left and right offset along the boundary tangential direction between multiple delay units.

[0119] Step S220: Based on the interface attribute information, determine the insertion direction of the delay unit to be inserted in the target circuit partition.

[0120] The insertion direction refers to the direction in which the delay unit is inserted into the target circuit partition. This insertion direction can include the interface normal and the logic direction. For example, if the interface port type is an output port and the signal flows from inside the target circuit partition to the outside, the insertion direction can be extended backward along the interface normal; if it is an input port and the signal flows from the outside into the partition, the insertion direction is extended forward along the interface normal. In addition, for bidirectional ports or complex interfaces, the insertion direction can be dynamically determined based on the actual signal propagation direction.

[0121] Understandably, this insertion direction ensures that the delay unit is placed on the path through which the signal naturally flows, avoiding reverse routing or cross-zone jumpers, thereby maintaining wiring simplicity and signal integrity.

[0122] Specifically, the interface attribute information includes interface geometry information and port type; based on the interface attribute information, the insertion direction of the delay unit to be inserted in the target circuit partition is determined, including: determining the interface normal of the target circuit partition at the interface boundary according to the interface geometry information; determining the logic direction of the target circuit partition at the interface boundary according to the port type; and determining the insertion direction of the delay unit to be inserted in the timing violation path based on the interface normal and the logic direction.

[0123] The interface geometry information refers to the physical shape (shape of the quadrilateral or polygonal interface boundary) and spatial characteristics of the target circuit partition at the interface boundary. This can include at least one of the following: the coordinate range of the interface boundary, the direction of line segments, curvature (such as a straight line), and the orientation of the interface in the global coordinate system of the chip circuit. Based on this interface geometry information, the interface normal at the interface boundary of the target circuit partition can be directly determined; that is, the interface normal is perpendicular to the line segment of the interface boundary.

[0124] For example, if the interface geometry of the target circuit partition at the interface boundary on the right is a vertical line segment, then its interface normal is horizontal to the right (outer side) or to the left (inner side).

[0125] It should be noted that the interface normal can be completely perpendicular to the interface line segment of the interface geometry, or it can be within a specified angle range with the interface line segment. For example, the interface normal can be within the range of 89-91 degrees with the interface line segment.

[0126] Port type refers to the functional direction attribute of the signal pins at the interface, including input port, output port, or bidirectional port.

[0127] Since timing violation paths have a definite starting point (e.g., register Q) and an ending point (e.g., register D), they together form a directed logical path along which signals propagate unidirectionally. Therefore, the logical direction is determined by combining the actual signal flow direction of the timing violation path at that interface.

[0128] The port type determines the logical flow of the signal at the interface: for input ports, the logical direction is from outside the target circuit partition to inside; for output ports, the logical direction is from inside the target circuit partition to outside; for bidirectional ports, it can be dynamically determined based on the actual propagation direction of the timing violation path.

[0129] Understandably, in interface boundary scenarios with multiple circuit partitions, the circuit partitions may be rectangular or polygonal in shape, and the physical implementation constraints of the interface's adjacent areas are complex. Different areas may have different constraints, such as the difference in constraints between the core area (CORE) and the input / output area (IO). Traditional solutions often struggle to accurately determine the direction in which delay units should be inserted during ECO processing, leading to issues like oblique insertion, insertion beyond the interface boundary (out-of-bounds), or insertion positions deviating from the target area, thus increasing the uncertainty of physical implementation. Manually determining the insertion direction by engineers is inefficient and inconsistent.

[0130] In this embodiment, the interface normal at the interface boundary can be determined based on the interface geometry information, and the logical direction at the interface boundary can be determined based on the port type. Then, the insertion direction of the delay unit can be determined based on the interface normal and the logical direction, so that the delay unit is arranged along the direction of the interface normal pointing into the target circuit partition. This improves the accuracy and efficiency of delay unit insertion, and also improves the consistency of the insertion direction of the delay unit.

[0131] In some embodiments, if the port type is an input port, the logical direction of the target circuit partition at the interface boundary is determined to be a forward logical path along the timing violation path; if the port type is an output port, the logical direction of the target circuit partition at the interface boundary is determined to be a backward logical path along the timing violation path.

[0132] When the port type is an input port, it indicates that the interface is used to receive signals from the outside. In this case, if a timing violation path passes through this interface and enters the target circuit partition, the signal propagation direction at that location is from the outside in. Therefore, the logic direction is determined to be the forward extension of the logic path along the timing violation path, i.e., pointing towards the interior of the target circuit partition and toward the end of the path. Delay units should be arranged in this direction to apply a delay to the signal entering the partition.

[0133] When the port type is output port, it indicates that the interface is used to drive signals from within the target circuit partition to the outside. In this case, if a timing violation path originates within the target circuit partition and exits through this interface, the signal propagation direction is from the inside out. Therefore, the logic direction is determined as either extending backward along the logic path of the timing violation path (i.e., pointing in the opposite direction to the logic direction) or within the target circuit partition. The delay unit should be placed inside the target circuit partition. That is, the insertion direction is along the interface normal pointing into the target circuit partition.

[0134] In some embodiments, if the port type is an input port, the insertion direction may be along the interface normal pointing into the adjacent area of ​​the input port of the target circuit partition; if the port type is an output port, the insertion direction may be along the interface normal pointing into the adjacent area of ​​the output port of the target circuit partition.

[0135] In some embodiments, after obtaining the interface normal and the logic direction, the two can be merged to determine the insertion direction of the delay unit, and the insertion direction points along the interface normal to the logic direction. Specifically, if the logic direction extends forward along the logic path of the timing violation path, and the interface normal has a component pointing to the inside of the partition, then the insertion direction is along the interface normal and points to the inside of the target circuit partition; if the logic direction extends backward along the logic path of the timing violation path, then the insertion direction is along the interface normal and points to the inside of the target circuit partition.

[0136] Ultimately, the insertion direction is along the interface normal pointing to the logical direction, ensuring that the delay unit is located on the natural signal propagation path, which meets electrical connection requirements and avoids cross-zone routing or reverse drive.

[0137] For example, if a timing violation path enters an SRAM macrocell (input port) from the main logic area and the interface normal points inside the SRAM, the delay unit will be placed in the adjacent free area inside the interface boundary of the input port; conversely, if a timing violation path outputs from the IP core to the bus (output port), the delay unit will be placed inside the interface boundary of the output port (within the IP core).

[0138] Understandably, calculating the interface normal based on the interface geometry information and determining the signal propagation side by combining the port type and path logic flow not only significantly reduces manual intervention but also lowers the probability of direction misjudgment, further ensuring the correctness and robustness of ECO timing processing.

[0139] It is understandable that the rules for determining the insertion direction can be adjusted as needed, and are not limited here. For example, different methods for determining the interface normal, logical direction, or insertion direction fusion can be used.

[0140] Step S230: Determine the physical location of the delay unit to be inserted in the target circuit partition based on the physical configuration parameters of the delay unit to be inserted and the insertion direction of the delay unit to be inserted.

[0141] After obtaining the physical configuration parameters and insertion direction, continuous free physical space can be allocated along the insertion direction in the vicinity of the interface connection of the target circuit partition for inserting one or more delay units.

[0142] Specifically, the physical coordinates of each delay unit can be calculated based on the total width and height of the delay unit, combined with the available track resources in the adjacent area of ​​the interface connection and the minimum spacing rule.

[0143] In some implementations, after determining the physical location of each delay unit based on its physical configuration parameters and insertion direction, a regularized physical location distribution can be generated based on the determined insertion direction and parameterized physical constraints. These parameterized physical constraints may include the physical spacing between adjacent delay units within a group, the initial offset of the delay unit group relative to the port at the interface connection, the offset along the interface tangential direction, and the number of extensions along the normal direction into the target circuit partition. By adopting a regularized physical location distribution, the wiring increment and delay unit distribution after each ECO insertion round can be more controllable, reducing large offsets caused by layout fine-tuning, making the actual introduced delay more consistent with the estimated delay, thereby reducing the need for multiple ECO iterations.

[0144] For example, multiple delay units can be continuously inserted into the target circuit partition along the interface normal. The spacing between each delay unit and the offset relative to the port are determined by preset parameters to form a regularly arranged delay unit group.

[0145] In some implementations, for a port located at the interface connection of a target circuit partition, a set of delay units extending into the target circuit partition along the interface normal can be automatically generated. The insertion direction of this set of delay units, the spacing between adjacent delay units within the set, the initial offset relative to the port, and the offset along the interface tangential direction can all be configured by preset parameters. This allows multiple delay units located at the interface connection to be arranged in a regular manner along the interface normal, thereby improving the controllability and consistency of delay unit insertion in the vicinity of the interface.

[0146] In some implementations, the parameters such as the insertion direction, the spacing between adjacent delay units within a group, the initial offset relative to the port, and the offset along the interface tangential direction can be set separately for different circuit partitions or different interfaces. Specifically, a set of default parameters can be preset, and the corresponding parameters can be adjusted individually for the physical resources, congestion conditions, or layout constraints of some circuit partitions or interfaces. Therefore, the arrangement of delay units can be differentiated according to the implementation conditions of adjacent areas of different interfaces, thereby improving the adaptability of parameter configuration.

[0147] Furthermore, the physical resources, congestion conditions, and obstacle avoidance requirements in the adjacent areas of different circuit partitions or interfaces may vary. Therefore, the above embodiments can set parameters such as the spacing between adjacent delay units within a group, the initial offset relative to the port, the offset along the interface tangential direction, and the number of units extending inward along the normal direction for different circuit partitions or interfaces, to adapt to the implementation conditions of different interface regions. This can improve the adaptability of parameter configuration to different interface scenarios and enhance the specificity of delay unit arrangement results.

[0148] In some implementations, the aforementioned circuit timing processing method can determine the insertion object, insertion direction, physical configuration parameters, and physical location of delay cells based on observable timing margin and path information from static timing analysis results, combined with geometric and interface information at the circuit partition level, without relying on the invisible automatic repair decision-making process within the placement and routing tool. Therefore, ECO processing can be completed based on explicit data input and rule-based flows, improving the interpretability and debuggability of the processing. Thus, the aforementioned circuit timing processing method can serve as an engineering change ECO processing approach based on explicit rule calculation.

[0149] Understandably, traditional ECO processes typically estimate the latency and network impact of delay units based on library models. The actual latency introduced after inserting a delay unit usually depends on its physical location and wiring configuration, and is also affected by surrounding physical resources. However, because the physical placement of delay units is uncontrollable, and related wiring is usually handled automatically by the tool's internal algorithms, there is a significant discrepancy between the actual introduced latency and the pre-estimated latency. This results in inaccurate ECO latency estimation, leading to unpredictable timing repair effects after delay unit insertion. Furthermore, the actual latency introduced after a single ECO process often differs from the required latency, requiring multiple rounds of iterative "analysis-insertion-implementation-reanalysis," significantly lengthening the signoff (approval / final acceptance) cycle.

[0150] In this embodiment, based on the timing margin of the timing violation path, the target delay to be added in the target circuit partition is accurately determined. Then, based on this target delay, the physical configuration parameters such as the type and quantity of the delay units to be inserted can be accurately determined. Therefore, based on the physical configuration parameters of the delay units to be inserted and their insertion direction, the physical location of the delay units to be inserted in the target circuit partition can be determined more accurately. That is, inserting delay units at this physical location makes the actual introduced delay more consistent with the required target delay, improving the accuracy of ECO delay estimation, and thus predicting and improving the timing repair effect of the delayed unit insertion circuit. Furthermore, in this embodiment, a single round of circuit timing processing can introduce an actual delay more consistent with the required delay in the timing violation path. Only a few rounds or one iteration are needed to complete the repair of the timing violation path, shortening the signoff (sign-off / final acceptance) cycle.

[0151] In some embodiments, the method further includes: aggregating each timing violation path to obtain at least one set of timing violation paths; and for at least two timing violation paths in the set of timing violation paths, performing the step of obtaining interface attribute information at the interface connection points traversed by the timing violation paths.

[0152] The timing violation path set is a set that includes at least two timing violation paths. In some implementations, the aforementioned timing violation path set can also serve as an ECO task unit. This ECO task unit may include at least two timing violation paths that are related in terms of circuit partition, interface, port type, or violation characteristics, and is used as the processing object for subsequent batch determination of target circuit partition, interface attribute information, and control commands.

[0153] Specifically, the process of aggregating timing violation paths to obtain at least one set of timing violation paths includes: obtaining path information of at least two dimensions for each timing violation path; determining each timing violation path with overlapping circuit partitions based on the path information of at least two dimensions, and aggregating each timing violation path with overlapping circuit partitions to obtain at least one set of timing violation paths; and determining the target circuit partition traversed by the timing violation path, including: determining the target circuit partition from each overlapping circuit partition in the set of timing violation paths.

[0154] The path information, which includes at least two dimensions, may include at least two of the following: circuit partition, interface, port type, and violation characteristics. It may also include other dimensions, such as the timing characteristics and functional semantics of timing violation paths, and is not limited to these. Overlapping circuit partitions refer to the same circuit partition that multiple timing violation paths traverse in the physical implementation.

[0155] In some specific implementations, path information in at least two dimensions can be parsed to determine the circuit partitions traversed by each timing violation path, and the circuit partitions traversed by each timing violation path can be compared to determine the timing violation paths that have overlapping circuit partitions.

[0156] In some embodiments, a target circuit partition can be determined from at least two overlapping circuit partitions based on the free area information of each overlapping circuit partition at its respective interface connection. Specifically, the overlapping circuit partition with the largest free area at its interface connection can be determined as the target circuit partition.

[0157] In other embodiments, an overlapping circuit partition can be randomly selected from each overlapping circuit partition as the target circuit partition.

[0158] In other embodiments, other methods can also be used to aggregate each timing violation path, such as clustering based on the timing violation path endpoint register, grouping by clock domain or power domain, classifying and aggregating according to signal function category (such as address bus, control signal, data channel), or spatial clustering combined with layout features such as wiring congestion area and physical proximity, etc., which are not limited here.

[0159] In one embodiment, another circuit timing processing method is also provided, which can be applied to timing repair scenarios in multi-circuit partition architecture chips. The multi-circuit partition architecture chip may include multiple circuit partitions, and the circuit partitions interact with each other through boundary interfaces. The method includes steps S1 to S8: Step S1: Obtain the timing report and extract the basic path data.

[0160] During the timing approval phase, static timing analysis tools can be used to perform timing analysis on the chip design and generate a timing report. This report can contain hundreds of thousands of timing violation paths. At this point, the timing report can be batch-parsed to extract a set of timing violation paths. For each timing violation path, its timing margin, path direction, involved circuit partition information, and location information related to interface connections can be further extracted to form the basis for subsequent ECO (Engineering Change) decisions.

[0161] Step S2: Group and aggregate the time-series violation paths based on the basic path data.

[0162] Based on fundamental path information such as timing margin, path direction, circuit partition information, and location information related to interface connections, each timing violation path can be further grouped and aggregated according to dimensions such as circuit partition, interface, port type, and violation characteristics to obtain a set of timing violation paths that can be processed in batches. This set of timing violation paths can also serve as an ECO task unit. Multiple timing violation paths that are near the same circuit partition interface, have the same or similar port types, and have similar violation characteristics can be aggregated into a single set of timing violation paths. This approach reduces duplicate and conflicting insertions and improves batch processing capabilities in large-scale path scenarios.

[0163] Step S3: Determine the corresponding target circuit partition for each timing violation path set.

[0164] If the same set of timing violation paths involves multiple candidate circuit partitions, the relevant candidate circuit partitions can be comprehensively evaluated by combining the path's cross-circuit partition relationship, interface location, local resources, implementation risks, and design constraints to determine the target circuit partition, so that ECO circuit timing processing can be performed within the target circuit partition.

[0165] Specifically, the process begins by identifying the free area information at the corresponding interface connection point for each candidate circuit partition. This free area information can include the size of the free area adjacent to the interface, the number of available metal tracks, the continuous free length, the offset range from the interface boundary, and whether design rule checks or restrictions apply. Then, by combining the interface location, local congestion, local routing resources, and the relative positions of critical nodes along the path for each candidate circuit partition, a target circuit partition can be determined from at least two candidate circuit partitions. This improves the controllability of the ECO execution location in cross-circuit partition scenarios and reduces the uncertainty introduced by cross-circuit partition implementation.

[0166] Step S4: Determine the physical configuration parameters of the delay units to be inserted in the target circuit partition based on the timing margin.

[0167] After determining the target circuit partition, the physical configuration parameters of the delay units to be inserted in the target circuit partition can be determined based on the timing margins of each timing violation path in the corresponding timing violation path set and the target repair strategy. Specifically, the target delay to be compensated can be calculated based on the timing margins. This target delay can be set to a value greater than or equal to the absolute value of the negative timing margin corresponding to the path to be repaired, so that the corresponding path meets the hold-time constraint after repair. Based on this target delay, buffer units or delay units for insertion can be selected from the technology library, and the type and quantity of delay units can be determined. In some scenarios, a group of multiple consecutively inserted delay units can be used to meet the target delay requirements.

[0168] Step S5: Obtain the interface attribute information of the target circuit partition at the interface connection point, and determine the insertion direction of the delay unit to be inserted in the target circuit partition based on the interface attribute information.

[0169] After determining the target circuit partition, the interface attribute information of the corresponding interface connection point can be obtained by combining the extracted positioning information related to the interface connection point. Based on the interface attribute information, the insertion direction of the delay unit to be inserted in the target circuit partition can be determined.

[0170] Specifically, interface attribute information can include interface geometry and port type. The boundary geometry of the target circuit partition can be rectangular or polygonal. Interface geometry information can include the start and end coordinates of the interface boundary line segments, the direction of the line segments, and the orientation of the interface in the global coordinate system. Based on this interface geometry information, the interface normal at the interface boundary can be automatically determined.

[0171] Furthermore, the logical direction of the target circuit partition at the interface boundary can be determined by combining the port type. When the interface port type is an input port, the logical direction can be determined to extend forward along the logical path; when the interface port type is an output port, the logical direction can be determined to extend backward along the logical path. Then, by combining the interface normal and the logical direction, the insertion direction of the delay unit can be determined to be a regular direction along the interface normal and pointing towards the interior of the target circuit partition. In this way, the delay units can be arranged along the interface normal pointing towards the interior of the target circuit partition, thereby avoiding problems such as oblique insertion and insertion outside the target circuit partition.

[0172] Step S6: Configure parameterized physical constraints based on the insertion direction.

[0173] After determining the insertion direction of the delay units, parameterized physical constraints can be further configured for each circuit partition interface or each timing violation path set. These parameterized physical constraints can include the physical spacing between adjacent delay units within a group, the initial offset of the delay unit group relative to the port at the interface connection, the offset of the delay unit group along the interface tangential direction, and the number of units extending into the circuit partition along the normal direction. The physical spacing between adjacent delay units can be any specified distance; the initial offset can control the starting position of the delay unit group relative to the port at the interface connection along the normal direction; the offset along the interface tangential direction can be used to shift the entire delay unit group upwards, downwards, leftwards, or rightwards to avoid congested areas, macrocells, or special design rule check areas; the number of units extending inwards along the normal direction can determine the number of consecutive units inserted into the delay unit group along the normal direction, such as five consecutive buffer units. These parameters can be set separately for different circuit partitions or different interfaces, or default parameters can be preset and individually adjusted for some interfaces based on local resources, congestion conditions, or layout constraints to achieve differentiated processing.

[0174] Step S7: Based on physical configuration parameters, insertion direction, and parameterized physical constraints, determine the physical location of the delay unit to be inserted in the target circuit partition.

[0175] After obtaining the physical configuration parameters of the delay cells to be inserted, the insertion direction of the delay cells to be inserted, and the parameterized physical constraint configuration, the physical location of the delay cells to be inserted in the target circuit partition can be further determined. Specifically, multiple delay cells can be continuously inserted into the target circuit partition along the interface normal, and each delay cell can be arranged according to the preset intra-group spacing, initial normal offset, and interface tangential offset. For ports located at the interface of the circuit partition, a group of delay cells extending into the circuit partition along the interface normal can be automatically generated. The spacing, offset, and direction of this group of delay cells are all configured by the aforementioned parameters. Through this regularized physical distribution method, the cell distribution and routing increment after each round of ECO insertion can be more controllable, reducing the large offset caused by layout fine-tuning, making the actual introduced delay more consistent with the delay estimation result, thereby reducing the need for multiple rounds of ECO iteration processing.

[0176] Existing solutions typically only determine the logical insertion location of delay units. However, the final physical location of the delay unit, its corresponding wiring configuration, and changes in physical resources in the adjacent area can all lead to delay discrepancies between the actual introduced delay and the estimated delay. The delay estimation result is an estimate of the signal propagation delay that may be introduced after the delay unit is inserted. In this embodiment, by using the aforementioned regularized physical distribution method based on interface attribute information, insertion direction, and parameterized physical constraints, the deviation between the actual introduced delay and the estimated delay can be reduced, improving the stability of the timing repair results.

[0177] Step S8: Generate control commands based on the physical location of the delay unit and execute batch ECO processing.

[0178] After determining the physical location of the delay cells to be inserted in the target circuit partition corresponding to each timing violation path set, control commands can be generated based on the physical location of the delay cells. Furthermore, the ECO decision results corresponding to each timing violation path or each set of timing violation paths can be merged to generate a structured ECO script. This structured ECO script can include the insertion object, target circuit partition, number of cells, cell type, physical location, intra-group spacing, initial normal offset, tangential offset, and other physical constraint parameters. Then, this structured ECO script can be imported into a place-and-route tool for execution, and the execution results can be verified. In this way, timing reports containing hundreds of thousands of paths can be parsed and processed in a single run, enabling batch ECO decision-making and execution in ultra-large-scale timing violation scenarios.

[0179] Furthermore, in this embodiment, each ECO decision result can be associated and recorded with corresponding timing data, path information, circuit partition boundary geometry information, and parameter configuration. Thus, the insertion object, insertion direction, physical location, target circuit partition, and control command of any delay unit can be traced back to the corresponding timing data or circuit partition geometry information, making the debugging process clearer and improving debugging efficiency.

[0180] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0181] Furthermore, in this exemplary embodiment, a circuit timing processing apparatus is also provided, with reference to... Figure 3As shown, the circuit timing processing device 300 includes: a timing violation path acquisition module 310, an interface attribute information acquisition module 320, a physical location determination module 330, and a control command generation module 340. Wherein: The timing violation path acquisition module 310 is used to acquire timing violation paths in the chip circuit and the timing margin of the timing violation paths; the timing margin of the timing violation paths does not meet the timing constraints. The interface attribute information acquisition module 320 is used to acquire the interface attribute information of the interface connection points traversed by the timing violation path; The physical location determination module 330 is used to determine the physical location of the delay unit to be inserted in the timing violation path based on interface attribute information and timing margin. The control command generation module 340 is used to generate control commands based on the physical location of the delay unit. The control commands are used to instruct the insertion of the delay unit at the physical location.

[0182] In some example embodiments of this disclosure, based on the foregoing scheme, the interface attribute information acquisition module 320 is configured as follows: Determine the target circuit partition through which the timing violation path passes; Obtain the interface attribute information of the target circuit partition at the interface connection point.

[0183] In some example embodiments of this disclosure, based on the foregoing scheme, the interface attribute information acquisition module 320 is configured as follows: If the timing violation path passes through at least two candidate circuit partitions, then determine the free area information of each candidate circuit partition at its respective interface connection. Based on the information of the free area at the interface connection of each candidate circuit partition, the target circuit partition is determined from at least two candidate circuit partitions.

[0184] In some example embodiments of this disclosure, based on the foregoing scheme, the physical location determination module 330 is configured as follows: Based on timing margin, determine the physical configuration parameters of the delay units to be inserted in the target circuit partition; Based on interface attribute information, determine the insertion direction of the delay unit to be inserted in the target circuit partition; Based on the physical configuration parameters of the delay unit to be inserted and the insertion direction of the delay unit to be inserted, determine the physical location of the delay unit to be inserted in the target circuit partition.

[0185] In some example embodiments of this disclosure, based on the foregoing scheme, the interface attribute information includes interface geometry information and port type; the physical location determination module 330 is configured as follows: Based on the interface geometry information, determine the interface normal of the target circuit partition at the interface boundary; Determine the logical direction of the target circuit partition at the interface boundary based on the port type; Based on the interface normal and logical direction, the insertion direction of the delay unit to be inserted in the timing violation path is determined.

[0186] In some example embodiments of this disclosure, based on the foregoing scheme, the physical location determination module 330 is configured as follows: If the port type is an input port, then the logical direction of the target circuit partition at the interface boundary is determined to be the logical path extending forward along the timing violation path; If the port type is an output port, then the logical direction of the target circuit partition at the interface boundary is determined to be the logical path extending backward along the timing violation path.

[0187] In some example embodiments of this disclosure, based on the foregoing scheme, the physical configuration parameters include the type and number of delay units; the physical location determination module 330 is configured as follows: Based on the timing margin, determine the target delay that needs to be added in the target circuit partition; the duration of the target delay is greater than or equal to the duration of the timing margin. Based on the target delay, determine the type and number of delay units to be inserted.

[0188] In some example embodiments of this disclosure, based on the foregoing scheme, the above-mentioned apparatus further includes a path aggregation module, which is configured to aggregate each timing violation path to obtain at least one set of timing violation paths. The interface attribute information acquisition module 320 is configured to: acquire the interface attribute information of the interface connection points traversed by at least two timing violation paths in the timing violation path set.

[0189] In some example embodiments of this disclosure, based on the foregoing scheme, the path aggregation module is configured to: obtain path information of at least two dimensions for each timing violation path; determine each timing violation path with overlapping circuit partitions based on the path information of at least two dimensions, and aggregate each timing violation path with overlapping circuit partitions to obtain at least one set of timing violation paths. The interface attribute information acquisition module 320 is configured to: determine the target circuit partition from each overlapping circuit partition of the timing violation path set, and acquire the interface attribute information of the target circuit partition at the interface connection.

[0190] The specific details of each module of the above circuit timing processing device have been described in detail in the corresponding circuit timing processing methods, so they will not be repeated here.

[0191] It should be noted that although several modules or units of the circuit timing processing apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0192] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the circuit timing processing method described above is also provided.

[0193] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0194] The following reference Figure 4 To describe an electronic device 400 according to such an embodiment of the present disclosure. Figure 4 The electronic device 400 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0195] like Figure 4 As shown, the electronic device 400 is presented in the form of a general-purpose computing device. The components of the electronic device 400 may include, but are not limited to: at least one processing unit 410, at least one storage unit 420, a bus 430 connecting different system components (including storage unit 420 and processing unit 410), and a display unit 440.

[0196] The storage unit stores program code that can be executed by the processing unit 410, causing the processing unit 410 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 410 can perform actions such as... Figure 1 In step S110, the timing violation path and timing margin of the timing violation path in the chip circuit are obtained; the timing margin of the timing violation path does not meet the timing constraint conditions; in step S120, the interface attribute information of the interface connection point traversed by the timing violation path is obtained; in step S130, the physical location of the delay unit to be inserted in the timing violation path is determined based on the interface attribute information and timing margin; in step S140, a control instruction is generated according to the physical location of the delay unit, and the control instruction is used to instruct the insertion of the delay unit at the physical location.

[0197] Storage unit 420 may include readable media in the form of volatile storage units, such as random access memory (RAM) 421 and / or cache memory 422, and may further include read-only memory (ROM) 423.

[0198] Storage unit 420 may also include a program / utility 424 having a set (at least one) of program modules 425, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0199] Bus 430 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0200] Electronic device 400 can also communicate with one or more external devices 470 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 400, and / or with any device that enables electronic device 400 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 450. Furthermore, electronic device 400 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 460. As shown, network adapter 460 communicates with other modules of electronic device 400 via bus 430. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0201] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0202] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0203] refer to Figure 5 As shown, a program product 500 for implementing the circuit timing processing method described above according to an embodiment of the present disclosure is illustrated. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0204] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0205] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0206] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0207] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0208] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0209] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0210] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only.

[0211] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A circuit timing processing method, characterized in that, The method includes: Obtain the timing violation path in the chip circuit and the timing margin of the timing violation path; the timing margin of the timing violation path does not meet the timing constraint conditions. Obtain the interface attribute information of the interface connections traversed by the timing violation path; Based on the interface attribute information and the timing margin, the physical location of the delay unit to be inserted in the timing violation path is determined; A control command is generated based on the physical location of the delay unit, and the control command is used to instruct the insertion of the delay unit at the physical location.

2. The circuit timing processing method according to claim 1, characterized in that, The step of obtaining the interface attribute information of the interface connection traversed by the timing violation path includes: Determine the target circuit partition traversed by the timing violation path; Obtain the interface attribute information of the target circuit partition at the interface connection point.

3. The circuit timing processing method according to claim 2, characterized in that, Determining the target circuit partition traversed by the timing violation path includes: If the timing violation path passes through at least two candidate circuit partitions, then determine the free area information of each candidate circuit partition at its respective interface connection. Based on the free area information of each candidate circuit partition at its respective interface connection, a target circuit partition is determined from at least two candidate circuit partitions.

4. The circuit timing processing method according to claim 2, characterized in that, Determining the physical location of the delay unit to be inserted in the timing violation path based on the interface attribute information and the timing margin includes: Based on the timing margin, the physical configuration parameters of the delay units to be inserted in the target circuit partition are determined; Based on the interface attribute information, the insertion direction of the delay unit to be inserted in the target circuit partition is determined; The physical location of the delay unit to be inserted in the target circuit partition is determined based on the physical configuration parameters of the delay unit to be inserted and the insertion direction of the delay unit to be inserted.

5. The circuit timing processing method according to claim 4, characterized in that, The interface attribute information includes interface geometry information and port type; determining the insertion direction of the delay unit to be inserted in the target circuit partition based on the interface attribute information includes: Based on the interface geometry information, determine the interface normal of the target circuit partition at the interface boundary; Based on the port type, determine the logical direction of the target circuit partition at the interface boundary; Based on the interface normal and the logical direction, the insertion direction of the delay unit to be inserted in the timing violation path is determined.

6. The circuit timing processing method according to claim 5, characterized in that, Determining the logical direction of the target circuit partition at the interface boundary based on the port type includes: If the port type is an input port, then the logical direction of the target circuit partition at the interface boundary is determined to be an extension of the logical path along the timing violation path. If the port type is an output port, then the logical direction of the target circuit partition at the interface boundary is determined to be an extension of the logical path of the timing violation path.

7. The circuit timing processing method according to claim 4, characterized in that, The physical configuration parameters include the type and quantity of the delay units; determining the physical configuration parameters of the delay units to be inserted in the target circuit partition based on the timing margin includes: Based on the timing margin, the target delay to be added in the target circuit partition is determined; the duration of the target delay is greater than or equal to the duration of the timing margin. Based on the target delay, determine the type and number of the delay units to be inserted.

8. The circuit timing processing method according to any one of claims 1 to 7, characterized in that, The method further includes: Aggregate the aforementioned timing violation paths to obtain at least one set of timing violation paths; For at least two timing violation paths in the set of timing violation paths, the step of obtaining the interface attribute information of the interface connection traversed by the timing violation path is executed.

9. The circuit timing processing method according to claim 8, characterized in that, The aggregation of each of the timing violation paths to obtain at least one set of timing violation paths includes: Obtain path information in at least two dimensions for each of the aforementioned timing violation paths; Based on the path information of at least two dimensions, each timing violation path with overlapping circuit partitions is determined, and the timing violation paths with overlapping circuit partitions are aggregated to obtain at least one set of timing violation paths. The step of obtaining the interface attribute information of the interface connection traversed by the timing violation path includes: The target circuit partition is determined from each of the overlapping circuit partitions in the timing violation path set, and the interface attribute information of the target circuit partition at the interface connection is obtained.

10. A circuit timing processing device, characterized in that, include: A timing violation path acquisition module is used to acquire timing violation paths in the chip circuit and the timing margin of the timing violation paths. The timing margin of the timing violation path does not meet the timing constraint conditions; The interface attribute information acquisition module is used to acquire the interface attribute information of the interface connection points traversed by the timing violation path; The physical location determination module is used to determine the physical location of the delay unit to be inserted in the timing violation path based on the interface attribute information and the timing margin. A control command generation module is used to generate control commands based on the physical location of the delay unit, the control commands being used to instruct the insertion of the delay unit at the physical location.

11. An electronic device, characterized in that, include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the circuit timing processing method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the circuit timing processing method as described in any one of claims 1 to 9.

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