A macrocell automatic synthesis method based on splicable analog cells

Abstract

The application discloses a macro unit automatic synthesis method based on splicable analog unit and belongs to the technical field of electronic design automation (EDA). The method aims to solve the problem that device matching constraint, layout area efficiency and design rule check cannot be considered in the existing analog layout automatic process. The method mainly comprises the following steps: receiving a circuit netlist with layout intention annotation, mapping devices into Acells; placing initial row bases according to a symmetric mode; executing a compression algorithm for keeping constraints, optimizing area by removing specific redundant polysilicon structures at the interfaces of adjacent Acells; performing legalization processing based on contact polysilicon spacing and power ground line spacing; finally, adopting a wiring method based on the satisfiability of module theory, automatically generating internal connections under the premise of ensuring geometric symmetry. The application can generate analog macro units meeting the requirements of DRC / LVS, compact in area and high in matching characteristics, and can be directly integrated into a digital layout and wiring process.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) technology, specifically to an automated method for the physical design of analog integrated circuits, and particularly to an automated synthesis method capable of generating synthesizable, splicable analog macrocells that meet strict matching requirements. Background Technology

[0002] As integrated circuit process nodes continue to shrink, the physical design (layout design) of analog circuits faces enormous challenges. Traditional full-custom manual design flows heavily rely on engineers' experience, resulting in long design cycles and limited reusability. While artificial intelligence (AI)-based design tools have emerged in recent years, the layouts generated by these tools often fail rigorous Design Rule Checks (DRC) and layout principles. Figure 1 It requires consistency checks (LVS) and is often less efficient in terms of area than hand-designed systems.

[0003] To improve automation, researchers have proposed a method based on "A-cells," which borrows design concepts from digital standard cells to package analog devices into standard-height, directly combinable units. However, existing A-cell-based processes have significant drawbacks: they often neglect crucial device matching and symmetry constraints in analog circuits. For example, in differential pairs and current mirrors, failure to guarantee strict geometric symmetry can lead to parasitic parameter mismatches, severely impacting circuit performance (e.g., increasing op-amp input offset voltage). Furthermore, simple A-cell splicing introduces redundant edge structures, resulting in wasted layout area.

[0004] Therefore, there is an urgent need for a new automated method that can retain the splicability and DRC cleaning properties of Acell, while automatically handling complex symmetry constraints and optimizing the area. Summary of the Invention

[0005] The purpose of this invention is to provide an automated synthesis method for macrocells based on splicable analog cells (AmacroSyn). This method can automatically extract matching structures from the circuit netlist and synthesize compact, clean DRC / LVS cells that meet strict symmetry requirements.

[0006] The technical solution adopted in this invention is as follows:

[0007] This invention provides an automated macrocell synthesis method based on connectable analog units, comprising the following steps:

[0008] Step S1: Receive a circuit schematic or netlist with device matching relationships and symmetry mode parameter annotations, extract the device group to be matched according to the annotations, and map the device to the basic connectable analog unit in the process library;

[0009] Step S2: Based on the symmetry mode parameters, the parameters are parsed into specific physical geometric constraints through the constraint transformation engine. The mapped splicable simulation units are initially arranged in the preset placement rows according to the cocentroid structure, interdigitated structure or cluster structure to form the initial macro unit structure.

[0010] Step S3: Perform constraint-preserving compression processing on the initial macrocell layout structure. Under the premise of maintaining the splicing relationship and symmetry constraints between the splicable analog cells, identify and remove redundant pseudo-polysilicon structures at the splicing interface of adjacent splicable analog cells. The redundant pseudo-polysilicon structures are non-functional protective polysilicon at the boundary of adjacent cells. Compress the cell spacing to the minimum allowable value that meets the process design rules.

[0011] Step S4: Legalize the compressed layout structure and adjust the boundary size of the macro cells to meet the mesh alignment requirements of the standard cells to obtain the unwired macro cell layout.

[0012] Step S5: Construct an SMT routing model based on the satisfiability modulus theory, solve for metal interconnection schemes that satisfy connectivity, design rules, symmetry constraints and pin access constraints on the macrocell layout, and generate the final analog macrocell Amacro.

[0013] In the above scheme, the specific rule for removing redundant pseudo-polycrystalline silicon structures in step S3 is as follows: at the splicing interface of horizontally adjacent left and right splicable simulation units, remove the second-to-last pseudo-polycrystalline silicon from the rightmost side of the left splicable simulation unit, and remove the first pseudo-polycrystalline silicon from the leftmost side of the right splicable simulation unit.

[0014] In the above scheme, the total width of the j-th row after compression in step S3 is... The calculation formula is:

[0015]

[0016] in, Let be the number of connectable simulation units in the j-th row. The width of the combinable analog unit in the j-th row and i-th column is... The distance between the centers of the two removed pseudo-polycrystalline silicon strands.

[0017] In the above scheme, the legalization process in step S4 specifically includes: adjusting the total width of the macrocell. Adjust to an integer multiple of the contact polysilicon spacing CPP:

[0018]

[0019] Where row is the total number of rows in the macro unit. This represents the width of each line after compression. This represents the function for rounding up.

[0020] In the above scheme, the SMT routing model in step S5 is defined on a discrete routing mesh, and its constraint formula is... include:

[0021]

[0022] in:

[0023] For connectivity constraints, ensure that the source end of the network is connected to the load end;

[0024] To ensure that the line width, spacing, and through holes meet the process requirements, the design rules are constrained.

[0025] As a symmetry constraint, ensure that the geometric paths of the matching wire mesh pairs are symmetrical;

[0026] Pin access constraints ensure that each pin selects a valid access mode.

[0027] In the above scheme, the symmetry constraint Specific requirements: For a pair of wire meshes that are mirror images of each other, the trajectories of the metal line segments on the wiring grid are mirror symmetrical about a preset axis of symmetry, and the total path length and the number of vias of this pair of wire meshes are equal.

[0028] In the above scheme, the modular analog unit in step S1 has a standardized unit height, which is determined by the power rail and the ground rail, and the unit boundary is aligned to the contact polysilicon spacing CPP and the power ground spacing PGP.

[0029] In the above scheme, the analog macro cell generated in step S5 includes a standard physical view and an abstract view. The abstract view includes pin locations, power and ground rails, and congestion information, which is used to support the integration of top-level digital automatic placement and routing tools.

[0030] The beneficial effects of this invention are as follows:

[0031] Area Optimization: By employing the "constraint-preserving compression processing" in step S3 and specific pseudo-polysilicon removal rules, the area waste caused by direct A-cell splicing is resolved, achieving an improvement in the integration density of analog macrocells. In traditional cell-based designs, A-cells use redundant protective pseudo-polysilicon at the boundaries to ensure process independence. This invention identifies adjacent cell interfaces and precisely removes the second-to-last pseudo-polysilicon from the left cell and the first from the right cell, compressing the cell spacing to the process limit while ensuring compliance with Design Rules (DRC). Experimental data shows that this technique reduces the average layout area by approximately 15.3%, significantly improving the utilization rate of chip unit area.

[0032] High-performance matching: By applying the forced geometric constraints based on the SMT routing model in step S5, the problem of automated routing failing to meet the stringent matching requirements of analog circuits is solved, achieving electrical performance comparable to manual design. Analog circuits are extremely sensitive to parasitic parameter mismatches. This invention abandons traditional heuristic algorithms and adopts Satisfiable Mode Theory (SMT) modeling, using symmetry constraints as hard logical conditions for the routing scheme. This method forces that the matching nets be strictly mirrored in the grid coordinates, and that the path length and the number of vias be exactly equal. In the 28nm LDO design verification, the generated layout input offset voltage was only 0.74 mV, far superior to the 11.20 mV of the traditional automated process, reaching the level of expert-level manual design.

[0033] Full-process compatibility: Through steps S4 and S5, the problem of seamless integration between analog macrocells and fully automated digital EDA processes is resolved. For a long time, analog layouts, due to their irregular dimensions, have been difficult to utilize in mature commercial digital place-and-route (APR) tools. This invention, through legalization processing, adjusts the macrocell width to an integer multiple of the contact polysilicon pitch (CPP) and generates a standard abstract view containing pin positions and blocking information. This allows analog macrocells to be directly identified and routed by top-level tools just like standard digital cells, significantly shortening the design cycle of mixed-signal chips.

[0034] Synergistic Effect: This invention combines "A-cell-based modular architecture" with "SMT-based symmetrical constraint routing" to achieve a synergistic effect of "correct construction," resolving the contradiction between "efficiency" and "performance" in automated design. While A-cell splicing (A) alone is efficient, it lacks matching performance; while symmetrical routing (B) alone is extremely difficult to solve on non-standard layouts and prone to DRC violations. This invention provides a regular underlying physical environment through A-cells, offering a discretized search space for SMT routing; simultaneously, it uses SMT routing to compensate for potential matching losses in automated layout. This combination produces a highly efficient integrated solution: it retains the rapid iterative capabilities of digital processes while ensuring the physical symmetry of analog circuits through logical constraints, achieving efficient automated production of high-performance analog macrocells. Attached Figure Description

[0035] Figure 1 This is an overall flowchart of the AmacroSyn synthesis method of the present invention.

[0036] Figure 2 This diagram compares the structures of A-cell and P-cell. (a) shows the P-cell transistor structure; (b) shows the A-cell transistor structure, as indicated by the diagram labels.

[0037] 1-Active area, 2-Contact hole, 3-Metal, 4-Interpolation finger, 5-Interpolation finger length L, 6-Interpolation finger width FW, 7-M wiring tracks, 8-Contact hole to polysilicon distance CPP, 9-Power supply pin, 10-Vertical wiring track, 11-Gate pin, 12-Lateral wiring track, 13-Drain pin, 14-Source pin, 15-Layout wiring boundary, 16-Ground pin, 17-N contact holes to polysilicon distance;

[0038] Figure 3 This diagram illustrates various symmetrical placement modes supported by the present invention. (a) Clustered structure, where A and B represent two different transistors, distinguished by AB; (b) Clustered structure containing multiple transistors; (c) Common centroid (CC) structure; (d) Common centroid structure with different transistor ratios (1:8); (e) Multi-row common centroid structure with dummy transistors; (f) Common centroid structure containing multiple transistors; (g) Clustered structure with dummy transistors; (h) Multi-row common centroid structure with different transistor ratios (1:8).

[0039] Figure 4A schematic diagram illustrating the principle of constrained compression steps demonstrates the removal process of pseudo-polycrystalline silicon and further illustrates the overall flow of the AmacroSyn synthesis method. The five steps are: connectable simulated cells in the netlist, placement, compression, legalization, and routing. Detailed Implementation

[0040] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0041] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0042] An automated macrocell synthesis method based on splicable analog units includes:

[0043] Acell mapping: Maps devices in a circuit schematic to basic modular analog cells (Acells) in the technology library.

[0044] Initial placement: Based on the symmetry requirements of the circuit (such as common centroid, interdigitated structure, etc.), Acells are initially arranged in rows.

[0045] Constraint-preserving compaction: For the initially arranged structure, the script automatically identifies the interface between adjacent A-cells, removes excess dummy polysilicon to eliminate redundant spacing, and strictly maintains the symmetry between devices.

[0046] Legalization: Quantizes the compressed macrocell size into integer multiples of CPP and PGP to ensure that it can be processed by top-level tools like a digital standard cell.

[0047] SMT routing: Internal wiring is performed using an algorithm based on modular satisfiability (SMT). This algorithm transforms the routing problem into a mathematical logic proposition, forcing strictly symmetrical geometric paths of matching signal lines, thereby guaranteeing circuit performance at the physical level.

[0048] The present invention will be further described in detail below with reference to specific embodiments.

[0049] 1. Basic Unit Definition (Acells) This invention is designed based on the existing technology Acells:

[0050] Acell is a standardized analog layout structure with a uniform height (determined by power and ground rails) and a width that is an integer multiple of the contact-to-polysilicon pitch (CPP). Pin locations are quantized onto routing rails, ensuring that direct splicing of cells in the horizontal and vertical directions does not result in DRC violations.

[0051] 2. Comprehensive Process Detailed Explanation: The AmacroSyn process of this invention comprises four key stages:

[0052] Phase 1: Initial Placement. The system reads the labeled netlist (e.g., label pattern: common-centroid, row: 2). The row base placer arranges Acells closely according to these labels. For example, for a difference pair of a common-centroid pattern, it is broken down and arranged in multiple rows in the order ABBA or ABAB.

[0053] Phase Two: Constraint-preserving Compaction. To address the area waste caused by direct splicing, this invention introduces a compression algorithm. To ensure independence, A-cells typically have dummy polysilicon (DPI) at their left and right boundaries for protection. When two A-cells are spliced ​​adjacently, two adjacent DPI lines appear in the contact area, resulting in wasted space. The compression rule in this embodiment is: identify the i-th and i-th... For the splicing interface of Acell, remove the second-to-last dummy poly of the left Acell (column i) and the right Acell (column i). The first positive dummy poly in the i-th column of Acell is deleted. It's worth noting that deleting the second-to-last dummy poly in column i and the first positive dummy poly in column i+1 can maintain design compliance after compression. Deleting other dummy polys would lead to issues during the Design Rule Check (DRC) process, such as active areas being too close together and short circuits between pre-defined metal pin structures. After compression, the width of row j... The calculation is as follows: This step, while retaining the outermost protective structure, eliminated internal redundancy, achieving an average area reduction of 15.3%. Let be the number of connectable simulation units in the j-th row. The width of the combinable analog unit in the j-th row and i-th column is... The distance between the centers of the two removed pseudo-polycrystalline silicon strands.

[0054] Phase 3: Legalization. To ensure compatibility with digital place-and-route tools, the generated macrocells must conform to a standard mesh. The total width of the analog macrocell macrocell is then determined. Round up to an integer multiple of CPP. This step ensures that Amacro can be seamlessly embedded into the standard cell rows of the top-level design.

[0055] Phase Four: SMT-based Routing This invention abandons traditional maze search algorithms and employs an SMT solver (such as Z3) for routing to satisfy stringent symmetry constraints. We define variables... The wiring problem is modeled as a quantifierless linear integer arithmetic (QF_LIA) problem. This indicates whether mesh n uses the mesh segment at coordinate (t, l) of the k-th layer, where t represents the horizontal index and l represents the vertical index. The logical formula for solving this problem is as follows: Among them, symmetry constraints The key is that it mandates that the coordinates of paired matched signals (such as differential inputs) on the mesh must be exactly mirrored about the central axis, and restricts the total length of the two paths and the number of vias to be exactly equal. This applies to meshes marked as symmetrical pairs. and In logical formulas, it is mandatory that: if Then its axis of symmetry mirror position variable , This represents the x-coordinate of the Amacro's horizontal axis of symmetry. This "construction-correct" approach avoids repeated iterative corrections after wiring. To ensure connectivity constraints and that the source and load ends of the mesh are connected, constraints are constructed using a flow model for each mesh n to ensure that there are no dangling segments in the middle of the mesh path. To ensure that line width, spacing, and through holes meet process requirements, design rules are enforced. Pin access constraints ensure that each pin selects a valid access mode.

[0056] 3. Example Verification: At the 28nm process node, a charge pump, a low-dropout linear regulator (LDO), and an operational amplifier (OPAMP) were designed using the method of this invention. LDO Test Results: The LDO layout generated using this method has an input offset voltage of 0.74 mV, which is very close to the 0.80 mV of a fully custom hand-designed layout. In contrast, the offset voltage of the A-cell layout without the symmetrical wiring of this invention is as high as 11.20 mV. This proves that this method achieves the performance level of expert-level hand-designed systems while ensuring automation.

Claims

1. An automated macrocell synthesis method based on connectable analog units, characterized in that, Includes the following steps: Step S1: Receive a circuit schematic or netlist with device matching relationships and symmetry mode parameter annotations, extract the device group to be matched according to the annotations, and map the device to the basic connectable analog unit in the process library; Step S2: Based on the symmetry mode parameters, the parameters are parsed into specific physical geometric constraints through the constraint transformation engine. The mapped splicable simulation units are initially arranged in the preset placement rows according to the cocentroid structure, interdigitated structure or cluster structure to form the initial macro unit structure. Step S3: Perform constraint-preserving compression processing on the initial macrocell layout structure. Under the premise of maintaining the splicing relationship and symmetry constraints between the splicable analog cells, identify and remove redundant pseudo-polysilicon structures at the splicing interface of adjacent splicable analog cells. The redundant pseudo-polysilicon structures are non-functional protective polysilicon at the boundary of adjacent cells. Compress the cell spacing to the minimum allowable value that meets the process design rules. Step S4: Legalize the compressed layout structure and adjust the boundary size of the macro cells to meet the mesh alignment requirements of the standard cells to obtain the unwired macro cell layout. Step S5: Construct an SMT routing model based on the satisfiability modulus theory, solve for metal interconnection schemes that satisfy connectivity, design rules, symmetry constraints and pin access constraints on the macrocell layout, and generate the final analog macrocell Amacro.

2. The method according to claim 1, characterized in that, The specific rules for removing redundant pseudo-polycrystalline silicon structures in step S3 are as follows: At the splicing interface between horizontally adjacent left and right splicable simulation units, remove the second-to-last pseudo-polycrystalline silicon from the rightmost side of the left splicable simulation unit, and remove the first pseudo-polycrystalline silicon from the leftmost side of the right splicable simulation unit.

3. The method according to claim 2, characterized in that, The total width of the j-th row after compression in step S3 The calculation formula is: in, Let be the number of connectable simulation units in the j-th row. The width of the combinable analog unit in the j-th row and i-th column is... The distance between the centers of the two removed pseudo-polycrystalline silicon strands.

4. The method according to claim 1, characterized in that, The legalization process in step S4 specifically includes: adjusting the total width of the macrocell. Adjust to an integer multiple of the contact polysilicon spacing CPP: Where row is the total number of rows in the macro unit. This represents the width of each line after compression. This represents the function for rounding up.

5. The method according to claim 1, characterized in that, The SMT routing model in step S5 is defined on a discrete routing mesh, and its constraint formula is... include: in: For connectivity constraints, ensure that the source end of the network is connected to the load end; To ensure that the line width, spacing, and through holes meet the process requirements, the design rules are constrained. As a symmetry constraint, ensure that the geometric paths of the matching wire mesh pairs are symmetrical; Pin access constraints ensure that each pin selects a valid access mode.

6. The method according to claim 5, characterized in that, The symmetry constraint Specific requirements: For a pair of wire meshes that are mirror images of each other, the trajectories of the metal line segments on the wiring grid are mirror symmetrical about a preset axis of symmetry, and the total path length and the number of vias of this pair of wire meshes are equal.

7. The method according to claim 1, characterized in that, The modular analog units in step S1 have a standardized unit height, which is determined by the power rail and the ground rail, and the unit boundaries are aligned to the contact polysilicon spacing CPP and the power ground spacing PGP.

8. The method according to claim 1, characterized in that, The analog macrocell generated in step S5 contains a standard physical view and an abstract view. The abstract view includes pin locations, power and ground rails, and congestion information, which are used to support the integration of top-level digital automatic placement and routing tools.

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