A method for quantitatively evaluating measures based on ic-level emc data assets

Abstract

The application discloses a kind of based on IC level EMC data assets measure quantification evaluation method, comprising: constructing read-only measure sensitivity database, extracting the quantification contribution value of target IC from IC level EMC data assets as measure sensitivity data;According to design mode or diagnosis mode, measure sensitivity data is called to predict measure effect and generate optimization scheme;Verification data is stored to user local application knowledge base, and local correction coefficient is generated for subsequent secondary correction.The present application converts EMC optimization from experience trial and error to quantitative calculation, supports pre-design reference and diagnosis rectification, and realizes user EMC design knowledge self-growth.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic compatibility (EMC) design and testing technology, specifically involving a quantitative evaluation method for measures based on integrated circuit (IC) level EMC data assets. Background Technology

[0002] In the development of electronic products, EMC design has long been in a "trial and error" mode: after the product prototype is completed, EMC testing is conducted, and modifications are made based on the test results, repeating this process multiple times until the standard is met. This process relies heavily on the personal experience of engineers, and the effect of each modification is difficult to quantify and predict, resulting in long development cycles and high costs.

[0003] In the prior art, several methods have attempted to evaluate the electromagnetic compatibility (EMC) performance of chips or provide optimization suggestions from different perspectives. For example, patent application CN111487489A discloses a method for evaluating chip immunity by combining aging tests with EFT injection to assess the change in chip immunity with aging. However, this method relies on physical testing and aging tests and does not involve a quantitative evaluation of design measures based on IC-level data assets. Patent application CN119881506A provides a chip EMC analysis method by collecting electromagnetic radiation data from multiple dimensions, constructing an electromagnetic interference influence matrix, and performing feature decomposition to obtain the distribution of interference sources and propagation paths. However, it focuses on the post-processing analysis of test data and does not provide quantitative suggestions for reference before PCB design. Patent application CN119575144A discloses a comprehensive testing system for chips in new energy vehicles, including an EMC testing module that analyzes faults through machine learning. However, it still belongs to the testing phase and lacks quantitative prediction of the effectiveness of design phase measures. Patent application CN119827847A discloses a testing device and method for conducted emission voltage of chip pins, assessing electromagnetic compatibility by directly contacting and measuring the pin emission voltage. However, it is merely a testing method and does not involve design optimization based on data assets. Patent application CN118428291A uses a neural network to predict conducted emissions of SiP chips and constructs an EMI current source model. However, it relies on test data specific to a particular chip and lacks a systematic utilization of the sensitivity to general IC measures. Patent application CN119227467A relates to an electromagnetic interference suppression method for chips, identifying interference and generating suppression strategies by constructing a multiphysics model. However, this method requires complex simulation modeling and does not fully utilize IC-level intrinsic data.

[0004] In summary, existing technologies lack a method to quantitatively assess the impact of different design measures (such as filtering, shielding, and grounding) on ​​EMC performance based on IC-level EMC data assets. Furthermore, it is difficult to provide quantitative references before PCB design or to offer precise rectification solutions after testing and diagnosis. Summary of the Invention

[0005] The purpose of this invention is to provide a quantitative evaluation method for measures based on IC-level EMC data assets, in order to solve the problems in the prior art where the effects of EMC measures cannot be quantitatively predicted and optimization schemes rely on experience. It can provide reference and prediction before design and guide precise rectification after testing.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A quantitative assessment method for measures based on IC-level EMC data assets includes the following:

[0008] Construction of the Measure Sensitivity Database: For the target IC, baseline test data, baseline simulation data, and extended layer test data and simulation data under each design variable are obtained from the IC-level EMC data assets. The quantitative contribution value of each design variable change relative to the baseline is extracted as the measure sensitivity data, and a read-only measure sensitivity database is constructed. "Read-only" means that the data in this database originates from the IC-level EMC data assets and cannot be modified by the user; it can only be queried and accessed. The measure sensitivity database includes at least the IC's identification information, baseline test data, baseline simulation data, and the quantitative contribution value of each design variable change relative to the baseline.

[0009] Predicting the effect of measures: Obtain the identification information and target measure information of the IC to be evaluated, retrieve the measure sensitivity data corresponding to the IC from the measure sensitivity database, select the design mode or diagnostic mode according to the application scenario, and predict the change in EMC performance after the target measures are applied.

[0010] In design mode, the effect is predicted directly based on the sensitivity data of the measures, without the need for layout parameter correction, and can be used as a reference for prediction before PCB design.

[0011] In diagnostic mode, it is also necessary to obtain the current PCB layout parameters, correct the prediction results based on the layout parameters, and generate corrected prediction results that match the actual layout for rectification and optimization after product testing.

[0012] Optimization scheme generation: Based on the predicted effect of the measures and combined with the preset optimization objectives, at least one optimization scheme is generated. The optimization scheme includes the measure type, measure parameters and expected effect.

[0013] Furthermore, the construction of the measure sensitivity database further includes:

[0014] Baseline data acquisition: Obtain baseline test data and baseline simulation data of the target IC from IC-level EMC data assets. The baseline test data reflects the EMC characteristics of the IC under intrinsic operating conditions, and the baseline simulation data is simulation model data calibrated with the baseline test data.

[0015] Extended data acquisition: Obtain extended layer test data and extended layer simulation data of the IC in at least one extended dimension from IC-level EMC data assets. The extended layer test data and extended layer simulation data reflect the impact of changes in a single design variable on EMC performance.

[0016] Quantitative analysis: Obtain the quantitative contribution value of each design variable change stored in the IC-level EMC data asset. The quantitative contribution value includes at least one of the following: change relative to the benchmark, influence coefficient of continuous variables, and comprehensive effect value of measures.

[0017] Furthermore, the design variables include at least one of the following types:

[0018] Filtering measures variables include the presence, type, and parameters of the filter circuit;

[0019] Variables of shielding measures include the presence, material, size, and grounding method of the shielding cover;

[0020] Grounding optimization variables include the number, location, and connection method of grounding vias;

[0021] Layout adjustment variables include the position of the IC on the PCB and the layout of peripheral components;

[0022] Software configuration variables include configurable spread spectrum function, drive strength, slew rate, and operating mode parameters within the IC.

[0023] Furthermore, in diagnostic mode, the prediction of the effectiveness of the measures further includes:

[0024] Obtain the layout parameters of the current PCB, including at least one of IC position, trace length, and reference layer integrity;

[0025] The sensitivity data of the measures are corrected based on the layout parameters to generate a corrected prediction result that matches the actual layout.

[0026] Furthermore, the modification includes:

[0027] A layout impact factor model is established to quantify the degree of influence of different layout parameters on the effectiveness of measures. The layout impact factor model is constructed based on the quantitative contribution value of layout adjustment variables in IC-level EMC data assets, and the mapping relationship between layout parameters and the change in the effectiveness of measures is established through interpolation or fitting.

[0028] The sensitivity data of the measures are weighted and calculated with the layout influence factors to obtain the corrected prediction effect.

[0029] Furthermore, the generation of the optimization scheme further includes:

[0030] Multi-objective optimization: Taking into account at least two objectives among EMC performance improvement, measure cost, space occupation, and reliability impact, an optimized combination of measures is generated;

[0031] Pre-visualization of effects: The expected effects of the optimization scheme are displayed graphically, including before and after comparison of the interference spectrum and decomposition of the contribution of the measures.

[0032] Furthermore, the method also includes verification of the effectiveness of the measures and accumulation of local knowledge:

[0033] Record the EMC test data after the actual measures are applied;

[0034] The actual test data is compared with the prediction results to calculate the prediction error;

[0035] When the prediction error exceeds a preset threshold, the actual test data, layout parameters, and prediction error are associated and stored in the user's local application knowledge base for reuse of local experience in subsequent design references.

[0036] The user-local application knowledge base is independent of the measure sensitivity database and does not modify the original data in the measure sensitivity database.

[0037] Furthermore, it also includes the generation and application of local correction coefficients:

[0038] Based on historical verification data in the user's local application knowledge base, local correction coefficients are statistically generated for specific application scenarios.

[0039] In predicting the effects of subsequent measures, the local correction coefficient can be optionally applied to perform a secondary correction on the prediction results;

[0040] The local correction coefficient is stored only in the user's local application knowledge base and does not affect the original data in the measure sensitivity database.

[0041] Furthermore, the measure sensitivity database has a hierarchical structure and includes at least:

[0042] The IC basic information layer stores the identification information, functional classification, and packaging type of the target IC;

[0043] The reference data layer stores the reference layer test data and reference layer simulation data of the target IC;

[0044] The measure sensitivity layer stores quantitative contribution value data for at least one measure dimension, including measure type, measure parameters, applicable frequency band, improvement amount, and confidence level.

[0045] The correction factor layer stores the correction coefficients for the effect of different layout parameters on the measures. These correction coefficients are constructed based on the quantitative contribution values ​​of layout adjustment variables in IC-level EMC data assets.

[0046] This invention also provides a quantitative assessment system for measures based on IC-level EMC data assets, comprising:

[0047] The IC-level EMC data asset interface is used to obtain IC baseline test data, baseline simulation data, extended layer test data, and extended layer simulation data from locally stored IC-level EMC data assets.

[0048] The measure sensitivity database is constructed based on the data obtained from the IC-level EMC data asset interface and stores read-only measure sensitivity data for multiple ICs.

[0049] The measure query module is used to receive the IC identifier and target measure information input by the user, and select the design mode or diagnostic mode according to the application scenario.

[0050] The effect prediction module is used to retrieve the corresponding measure sensitivity data from the measure sensitivity database and predict the change in EMC performance after the target measure is applied.

[0051] The scheme generation module is used to generate optimized schemes based on the prediction results;

[0052] The output module is used to output the optimization scheme and the expected results.

[0053] In diagnostic mode, the system also includes:

[0054] The layout parameter acquisition module is used to obtain the layout parameters of the current PCB.

[0055] A correction module is used to correct the prediction results based on the layout parameters;

[0056] The verification feedback module is used to record the EMC test data after the actual measures are applied and compare it with the prediction results. The actual test data, layout parameters and prediction results are associated and stored in the user's local application knowledge base.

[0057] The beneficial effects of this invention are:

[0058] First, based on the measure sensitivity data in IC-level EMC data assets, this invention enables quantitative prediction of the effectiveness of EMC measures, transforming EMC optimization from "experience-based trial and error" to "quantitative calculation." It can provide quantitative reference and prediction before design, and guide precise rectification and optimization after testing.

[0059] Second, by introducing a layout parameter correction mechanism, this invention solves the problem of discrepancies between measure sensitivity data under general testing conditions and actual application scenarios, effectively improving the accuracy of predictions in diagnostic mode.

[0060] Third, the multi-objective optimization function of this invention can comprehensively consider multiple factors such as EMC improvement effect, cost, and space, and provide engineers with optimized combination of measures.

[0061] Fourth, by constructing a user-local application knowledge base and local correction coefficients, this invention enables users to accumulate design experience locally, realize the self-growth of user EMC design knowledge, and does not affect the original data assets, thus protecting the commercial value of the data assets.

[0062] Fifth, this invention can be integrated into intelligent EMC design aids to provide engineers with real-time rectification suggestions and effect pre-visualization, which helps improve EMC design efficiency and reduce R&D costs. Attached Figure Description

[0063] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0064] Figure 1 This is a flowchart of the method of the present invention.

[0065] Figure 2 This is a schematic diagram of the sensitivity database structure of the measures of this invention.

[0066] Figure 3 This is a flowchart of the prediction and correction process for the effects of the measures in this invention.

[0067] Figure 4 This is a schematic diagram illustrating the generation of the multi-objective optimization scheme of the present invention.

[0068] Figure 5 This is a flowchart of the verification and feedback process for the effectiveness of the measures in this invention. Detailed Implementation

[0069] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0070] The overall process of this invention includes: S1 Constructing a read-only measure sensitivity database based on IC-level EMC data assets; S2 Obtaining the identification information and target measure information of the IC to be evaluated, and selecting a design mode or a diagnostic mode according to the application scenario; S3 Retrieving the corresponding measure sensitivity data from the measure sensitivity database; In design mode, directly proceeding to S5 Predicting the effect of the measure; In diagnostic mode, S4 Obtaining and correcting the layout parameters of the current PCB; S5 Predicting the effect of the measure; S6 Generating an optimization scheme; S7 Outputting the scheme and expected effect; S8 Actual testing and verification, and storing the actual test data, layout parameters, and prediction results in the user's local application knowledge base.

[0071]

Example 1

[0072] This embodiment uses a power management IC of a certain model (model: PMIC-XY123, operating frequency 2.2MHz) as an example to illustrate the application of the present invention in the design mode.

[0073] First, a sensitivity database for mitigation measures is constructed. Baseline test data, baseline simulation data, and extended layer test and simulation data for each design variable of the power IC are obtained from IC-level EMC data assets. The quantified contribution value of each design variable change relative to the baseline is extracted as the sensitivity data for mitigation measures. For example:

[0074] Reference layer data: The IC has a peak radiation of 48 dBμV / m at a fundamental frequency of 2.2 MHz and 42 dBμV / m at the second harmonic of 4.4 MHz.

[0075] Extended layer data and quantified contribution values:

[0076] - Filtering measures: After adding a π-type filter, the 2.2MHz radiation decreased to 36dBμV / m, an improvement of 12dB; after adding ferrite beads, the improvement was 8dB.

[0077] - Shielding measures: Local shielding improves performance by 15dB, and overall shielding improves performance by 18dB.

[0078] - Grounding optimization: Adding grounding vias improves performance by 5dB.

[0079] - Software configuration: Enabling spread spectrum function improves performance by 7dB, while reducing drive intensity improves performance by 4dB.

[0080] Organize this data into a read-only measure sensitivity database.

[0081] An engineer is designing a power module for an industrial controller, but the PCB layout has not yet been completed. He wants to assess the EMC risks of the power IC in advance and reserve optimization space. The system receives the IC identifier "PMIC-XY123" and selects the design mode. The engineer inputs the target measure type "filtering," and the system retrieves the sensitivity data of the IC's filtering measures, displaying: "Adding a π-type filter is expected to improve by 12dB, and adding ferrite beads is expected to improve by 8dB." The system further combines multi-objective optimization (considering cost and space) and generates a suggestion: "It is recommended to reserve space for a π-type filter in the schematic, which is expected to reduce the 2.2MHz radiation from 48dBμV / m to 36dBμV / m, helping to meet the radiation limits of industrial equipment." Based on this, the engineer adds a filtering circuit in the schematic without the need for layout parameter correction.

[0082] This example demonstrates the value of design patterns in providing quantitative references before design.

[0083]

Example 2

[0084] This embodiment takes a certain RS-485 transceiver (model: RS485-678, operating frequency 10MHz) as an example.

[0085] The IC-level data assets of this IC contain the following measures sensitivity data:

[0086] - Filtering measures: After adding a common-mode choke, conducted emissions at 10MHz are reduced by 15dB;

[0087] - Layout optimization: Differential routing was changed to tight coupling, reducing conducted emissions by 8dB.

[0088] An engineer used this RS-485 transceiver when designing an industrial fieldbus node. Prototype testing revealed that conducted emissions exceeded the limit at the 10MHz frequency (measured at 68dBμV, limit 55dBμV). The engineer hopes to reduce the emissions below the limit through modifications.

[0089] System analysis: The current exceedance is 13dB. Sensitivity data for this IC was retrieved from the sensitivity database, showing that adding a common-mode choke can reduce the limit by 15dB, and layout optimization can reduce it by 8dB. Further system analysis revealed the following layout parameters: differential trace length is 25mm, loose parallel traces are used, and the reference layer is incomplete.

[0090] The system calculates the corrected prediction effect based on the correction factor stored in the database (the filtering effect decreases by 8% for every 5mm increase in trace length):

[0091] - Add a common-mode choke: 15dB × (1 - 40%) = 9dB;

[0092] - Layout optimization (changed to tight coupling): 8dB × correction factor 0.9 = 7.2dB;

[0093] - Combined effect (considering synergistic effect): (9+7.2)×1.05 = 17dB.

[0094] The system generates an optimization plan:

[0095] Option 1: Adding only a common-mode choke is expected to improve emissions by 9dB, reducing the emission level to 59dBμV, but still exceeding the limit by 4dB, so it is not recommended.

[0096] Option 2: Optimize the layout only, expected to improve by 7.2dB, reducing the emission to 60.8dBμV, but still exceeding the limit;

[0097] Option 3: Implement both measures simultaneously, which is expected to improve performance by 17dB, reducing the emission level to 51dBμV, thus meeting the requirements.

[0098] The system recommends Scheme 3 and provides specific suggestions: add a common-mode choke (model XXX, inductance value XXX) to the bus and change the differential traces to tight coupling (spacing ≤ 2 times the trace width), which is expected to reduce the 10MHz conducted emission by 17dB, with the final emission being approximately 51dBμV.

[0099] After the engineers adopted the recommendations, the measured conducted emission dropped to 53 dBμV, close to the predicted 51 dBμV. The system stores the actual test data, layout parameters, and prediction results in the user's local application knowledge base for subsequent experience reuse, enabling the user's EMC design knowledge to grow automatically.

[0100]

Example 3

[0101] This embodiment takes a certain type of 25MHz crystal oscillator (model: OSC-25M) as an example.

[0102] The IC-level data assets of this IC contain the following measures sensitivity data:

[0103] - Grounding optimization: Increasing the number of grounding vias (from 3 to 8) reduced 25MHz radiation by 7dB;

[0104] - Layout adjustment: Moving the crystal oscillator from the edge to the center reduces radiation by 6dB.

[0105] An engineer was designing a wireless communication module when a 25MHz harmonic interference from the crystal oscillator affected the receiver sensitivity. The engineer hoped to solve the problem by optimizing the grounding and layout.

[0106] The system receives the IC identifier and retrieves the sensitivity data. Simultaneously, the system obtains the current layout parameters: the crystal oscillator is located at the edge of the PCB, with three grounding vias below it, and the reference layer is partially incomplete.

[0107] The system calculates the corrected prediction results:

[0108] - Grounding optimization: The baseline improvement is 7dB. The current number of vias is 3. Increasing the number to 8 can improve the improvement by 7dB. The correction factor is 1.0, and the expected improvement is 7dB.

[0109] - Layout adjustment: Moved from the edge to the center, baseline improvement of 6dB, correction factor 1.0, expected improvement of 6dB;

[0110] - Combined effect: The two measures are independent of each other, with an expected improvement of 13dB.

[0111] The system generates an optimization scheme and provides specific suggestions: It is recommended to increase the number of grounding vias below the crystal oscillator from 3 to 8 (expected improvement of 7dB), and move the crystal oscillator to the center of the PCB (expected improvement of 6dB). The combined expected improvement is 13dB, which can reduce the 25MHz radiation from the current 55dBμV / m to 42dBμV / m.

[0112] After the engineers implemented the recommendations, the measured radiation dropped to 44 dBμV / m, close to the predicted 42 dBμV / m. The system stores the actual test data in the user's local application knowledge base, updates the local correction coefficient for the IC, and optimizes subsequent predictions, enabling the user's EMC design knowledge to grow automatically.

[0113] Application Examples

[0114] 1. EMC risk pre-assessment during the design phase

[0115] During the product design phase, engineers can utilize the methods of this invention to simulate the expected effects of different combinations of measures and assess whether the design scheme has reserved sufficient optimization space. For example, if an IC has low sensitivity to filtering measures, more space needs to be reserved for other measures. This method can quantify these requirements and guide the early design phase. Engineers only need to input the IC model and the type of target measure to obtain quantified improvement expectations, thereby making better decisions during the schematic design phase and reducing the difficulty and risk of later rectification.

[0116] 2. Applications of intelligent EMC design aids

[0117] This invention can be integrated into intelligent EMC design aids. After the instrument locates the interference source through its self-diagnostic function, it automatically invokes this method to retrieve the corresponding IC's sensitivity data from its built-in sensitivity database. Combined with the current layout parameters, it generates quantified remediation suggestions and displays the expected effects in a visual manner to guide engineers in precise optimization.

[0118] 3. Application in the feasibility study of domestic substitution

[0119] In domestic substitution scenarios, the feasibility of substitution can be assessed by comparing the sensitivity data of imported and domestic ICs to filtering measures. Even if the intrinsic emission of domestic ICs is slightly higher, if they are highly sensitive to filtering measures, this can be compensated for by adding filtering measures. This method can quantitatively calculate the expected effect after compensation, providing a basis for substitution decisions.

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for quantitatively evaluating measures based on IC-level EMC data assets, characterized in that, Including the following: Construction of the measure sensitivity database: For the target IC, obtain the baseline test data, baseline simulation data, and extended layer test data and extended layer simulation data under each design variable from the IC-level EMC data assets. Extract the quantitative contribution value of each design variable change relative to the baseline as measure sensitivity data and construct a read-only measure sensitivity database. The sensitivity database for the measures includes at least the IC identification information, benchmark test data, benchmark simulation data, and the quantitative contribution value of each design variable change relative to the benchmark. Predicting the effect of measures: Obtain the identification information and target measure information of the IC to be evaluated, retrieve the measure sensitivity data corresponding to the IC from the measure sensitivity database, select the design mode or diagnostic mode according to the application scenario, and predict the change in EMC performance after the target measures are applied. Optimization scheme generation: Based on the predicted effect of the measures and combined with the preset optimization objectives, at least one optimization scheme is generated. The optimization scheme includes the measure type, measure parameters and expected effect.

2. The method according to claim 1, characterized in that, The construction of the sensitivity database for the aforementioned measures further includes: Baseline data acquisition: Obtain baseline test data and baseline simulation data of the target IC from IC-level EMC data assets. The baseline test data reflects the EMC characteristics of the IC under intrinsic operating conditions, and the baseline simulation data is simulation model data calibrated with the baseline test data. Extended data acquisition: Obtain extended layer test data and extended layer simulation data of the IC in at least one extended dimension from IC-level EMC data assets. The extended layer test data and extended layer simulation data reflect the impact of changes in a single design variable on EMC performance. Quantitative analysis: Obtain the quantitative contribution value of each design variable change stored in the IC-level EMC data asset. The quantitative contribution value includes at least one of the following: change relative to the benchmark, influence coefficient of continuous variables, and comprehensive effect value of measures.

3. The method according to claim 2, characterized in that, The design variables include at least one of the following types: Filtering measures variables include the presence, type, and parameters of the filter circuit; Variables of shielding measures include the presence, material, size, and grounding method of the shielding cover; Grounding optimization variables include the number, location, and connection method of grounding vias; Layout adjustment variables include the position of the IC on the PCB and the layout of peripheral components; Software configuration variables include configurable spread spectrum function, drive strength, slew rate, and operating mode parameters within the IC.

4. The method according to claim 1, characterized in that, In diagnostic mode, the prediction of the effectiveness of the measures further includes: Obtain the layout parameters of the current PCB, including at least one of IC position, trace length, and reference layer integrity; The sensitivity data of the measures are corrected based on the layout parameters to generate a corrected prediction result that matches the actual layout.

5. The method according to claim 4, characterized in that, The corrections include: Establish a layout influencing factor model to quantify the impact of different layout parameters on the effectiveness of measures; The sensitivity data of the measures are weighted and calculated with the layout influence factors to obtain the corrected prediction effect.

6. The method according to claim 1, characterized in that, The generation of the optimization scheme further includes: Multi-objective optimization: Taking into account at least two objectives among EMC performance improvement, measure cost, space occupation, and reliability impact, an optimized combination of measures is generated; Pre-visualization of effects: The expected effects of the optimization scheme are displayed graphically, including before and after comparison of the interference spectrum and decomposition of the contribution of the measures.

7. The method according to claim 1, characterized in that, It also includes verification of the effectiveness of the measures: Record the EMC test data after the actual measures are applied; The actual test data is compared with the prediction results to calculate the prediction error; When the prediction error exceeds a preset threshold, the actual test data, layout parameters, and prediction error are associated and stored in the user's local application knowledge base for reuse of local experience in subsequent design references.

8. The method according to claim 1, characterized in that, The sensitivity database for the measures has a hierarchical structure and includes at least: The IC basic information layer stores the identification information, functional classification, and packaging type of the target IC; The reference data layer stores the reference layer test data and reference layer simulation data of the target IC; The measure sensitivity layer stores quantitative contribution value data for at least one measure dimension, including measure type, measure parameters, applicable frequency band, improvement amount, and confidence level. The correction factor layer stores the correction coefficients for the effect of different layout parameters on the measures. These correction coefficients are constructed based on the quantitative contribution values ​​of layout adjustment variables in IC-level EMC data assets.

9. A quantitative assessment system for measures based on IC-level EMC data assets, characterized in that, include: The IC-level EMC data asset interface is used to obtain IC baseline test data, baseline simulation data, extended layer test data, and extended layer simulation data from locally stored IC-level EMC data assets. The measure sensitivity database is constructed based on the data obtained from the IC-level EMC data asset interface and stores read-only measure sensitivity data for multiple ICs. The measure query module is used to receive the IC identifier and target measure information input by the user, and select the design mode or diagnostic mode according to the application scenario. The effect prediction module is used to retrieve the corresponding measure sensitivity data from the measure sensitivity database and predict the change in EMC performance after the target measure is applied. The scheme generation module is used to generate optimized schemes based on the prediction results; The output module is used to output the optimization scheme and the expected results.

10. The system according to claim 9, characterized in that, In diagnostic mode, it also includes: The layout parameter acquisition module is used to obtain the layout parameters of the current PCB. A correction module is used to correct the prediction results based on the layout parameters; The verification feedback module is used to record the EMC test data after the actual measures are applied and compare it with the prediction results. The actual test data, layout parameters and prediction results are associated and stored in the user's local application knowledge base.

11. The method according to claim 1, characterized in that, It includes two application modes: Design mode: During the PCB design phase, the sensitivity data of the measures is retrieved as a design reference for the EMC protection scheme, guiding the pre-design of IC layout, filtering, shielding and other measures without the need for layout parameter correction; Diagnostic mode: During the product testing phase, the current PCB layout parameters are obtained and the prediction results are corrected to generate an optimized rectification plan for specific problems.

12. The method according to claim 1, characterized in that, This also includes building a local application knowledge base for users: The actual test data, layout parameters, prediction results, and actual improvement effects of each measure are linked and stored to form a local application knowledge base for users. The application knowledge base supports similarity-based retrieval, which can be used for the reuse of local experience in subsequent design references; The application knowledge base is independent of the measure sensitivity database and does not modify the original data in the measure sensitivity database.

13. The method according to claim 12, characterized in that, It also includes the generation and application of local correction factors: Based on historical verification data in the user's local application knowledge base, local correction coefficients are statistically generated for specific application scenarios. In predicting the effects of subsequent measures, the local correction coefficient can be optionally applied to perform a secondary correction on the prediction results; The local correction coefficient is stored only in the user's local application knowledge base and does not affect the original data in the measure sensitivity database.

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