Chip layout link tracing method based on scan line and R-tree

Abstract

The application discloses a chip layout link tracking method based on a scan line and an R tree, and belongs to the technical field of calculation, estimation or counting. The method comprises the following steps: analyzing an input layout file, constructing an event queue for a read graph, storing events into an R tree and traversing the R tree by using a scan line, and outputting a required graph set. The above method can effectively realize efficient processing of large-scale layout data and rapid extraction of multilayer links.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit EDA (Electronics Design Automation) and relates to calculation, estimation or counting. Specifically, it relates to a chip layout link tracing method based on scan lines and R-trees. Background Technology

[0002] Layout analysis is a crucial step in integrated circuit physical design and verification. One of its main tasks is to detect and trace the electrical connectivity between geometric objects in the layout, ensuring that the circuit meets logic and electrical performance requirements during actual manufacturing. With the development of advanced process nodes, the scale and complexity of integrated circuits have increased dramatically. Layouts typically contain dozens of process layers and millions to billions of polygons, with increasingly complex inter-layer interactions and design rules. Traditional layout connectivity analysis methods based on geometric traversal or region lookup face significant challenges in handling such high-density, high-dimensional data, including low computational efficiency, huge memory consumption, and poor scalability. Especially when performing multi-layer link tracing, traditional methods struggle to complete accurate analysis of the entire layout within a limited time, becoming one of the performance bottlenecks in the design flow.

[0003] In recent years, although some studies have attempted to combine parallel computing with spatial indexing to accelerate layout processing, several challenges remain in practical applications: First, strong data dependencies make efficient task partitioning and load balancing difficult; second, the interaction rules between multi-layer layouts are complex, and general spatial indexing structures are difficult to directly adapt to process-related constraints; third, existing methods often lack structured and visual support when outputting connected paths, hindering designers from subsequent rule debugging and optimization. Therefore, there is an urgent need for a layout multi-layer link tracing method that can balance efficiency, accuracy, and scalability to support the physical verification and approval process of highly complex integrated circuits. Summary of the Invention

[0004] To address the aforementioned issues, this invention discloses a chip layout link tracing method based on scan lines and R-trees. Specifically, this invention transforms layout geometric relationships into event sequences, combining the efficient spatial indexing capabilities of R-trees and disjoint-set data structures with parallel computing mechanisms to achieve rapid and accurate extraction of polygon connectivity relationships in large-scale multilayer layouts. This effectively supports the physical verification process of highly complex integrated circuits, shortens the design cycle, and improves automation levels.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: A chip layout link tracing method based on scan lines and R-trees comprises the following steps: Step S1: Load the input layout file and parse the polygon data layer by layer according to the process layer. During the parsing process, the system extracts and stores the vertex set and process layer number of each polygon, and calculates its minimum bounding box (MBB) and other information to accelerate subsequent spatial query operations; Step S2: Based on the overall boundary of the input map, divide it into multiple sub-regions for parallel processing. Within each sub-region, create two events for each polygon: a start event (corresponding to the x-coordinate of the left boundary of the polygon MBB) and an end event (corresponding to the x-coordinate of the right boundary). The event content includes the type, polygon pointer, coordinates, and layer information. Then, sort all events by x-coordinate to form an ordered event queue. Step S3: Establish a global disjoint-set data structure to record the connectivity relationships of all polygons. Scan the event queues of each sub-region in parallel. During the scan, each sub-region uses an R-tree to dynamically maintain the set of currently active polygons. When processing a start event, insert the corresponding polygon into the R-tree; when processing an end event, remove it from the R-tree. Whenever a new polygon is inserted, query all intersecting polygons in the R-tree and update their connectivity in the disjoint-set data structure. Ultimately, the disjoint-set data structure stores the connectivity information of the entire map. Step S4: Based on the disjoint set obtained in step S3, find all polygons connected to the specified starting polygon and output the results as structured data for subsequent analysis or visualization. As a further optimization of the layout link tracing method, the specific method for loading and parsing the layout file in step S1 is as follows: It supports parsing layout files in GDSII, OASIS, TXT, and DEF formats, and reads polygon data layer by layer; during the parsing process, the minimum bounding box of each polygon is calculated synchronously, and the polygon vertex coordinates, layer number, and minimum bounding box are stored in a custom data structure to establish a layer index.

[0006] As a further optimization of the layout link tracing method, the specific method for dividing the layout into blocks in step S2 is as follows: Based on the global bounding box of the entire layout, a uniform grid division strategy is adopted to divide the layout plane into K×K rectangular sub-regions, where K is a parameter dynamically determined based on the number of available processor cores and the layout size; each sub-region independently processes the event generation and sorting of its internal polygons.

[0007] As a further optimization of the layout link tracing method, the event structure created in step S2 includes the following fields: event type (start / end), pointer to the polygon object, event x-coordinate, process layer number, and minimum bounding box information of the polygon.

[0008] As a further optimization of the map link tracing method, the R-tree index used in step S3 is as follows: An R-tree is a balanced tree index structure designed for efficient management of multidimensional spatial data (such as geographic coordinates and rectangular boundaries). In this method, it is used to dynamically organize the minimum bounding boxes (MBBs) of various polygons intersecting the scan line. Its core idea is to aggregate the bounding boxes of spatially adjacent objects into a larger parent bounding box, thereby quickly eliminating a large number of irrelevant spatial regions during querying and transforming complex geometric relationship judgments into efficient bounding box pre-screening.

[0009] As a further optimization of the aforementioned map link tracing method, the data structure used to record connectivity relationships in step S3 is a disjoint-set data structure (Union-Set Union). A disjoint-set union is a highly efficient data structure specifically designed for handling element grouping and dynamic connectivity queries. Its core supports two operations: `find` (finding the representative element of the set containing an element) and `union` (merging the sets containing two elements). Through tree organization and path compression optimization, this structure can complete set merging and querying in approximately constant time, making it extremely suitable for handling the dynamic discovery and real-time merging of connectivity relationships between polygons in a map.

[0010] The specific application logic of this method is as follows: the system maintains an independent set for each polygon in a disjoint-set data structure. When it is confirmed through R-tree query and precise geometric judgment that the current polygon truly intersects with an existing polygon, the union operation of the disjoint-set data structure is called to merge the sets to which the two belong. This process ensures that all directly or indirectly connected polygons eventually belong to the same disjoint-set root node, thereby efficiently and completely recording the topological connectivity network of the entire map.

[0011] As a further optimization of the aforementioned multi-layer link tracing method for the layout, the system for outputting the results in step S4 is designed to have format extensibility. The system can output all polygons connected to a specified starting polygon and their topology information based on the connectivity relationships extracted from the disjoint-set data structure. It also supports generating result files in various formats to suit different downstream application scenarios. For example, the system can output a plain text file containing a unique polygon identifier, its process layer, and the ID of each connected component, facilitating programmatic processing; it can also generate a JSON structure file containing complete link topology relationships for direct use by visualization tools or data analysis software; furthermore, the system can convert the results into standard layout exchange formats (such as GDSII or OASIS), highlighting or marking connected paths in the original layout for analysis in a professional EDA environment. This design ensures that the method has sufficient flexibility and integration capabilities in the output stage.

[0012] A computer-readable storage medium having a computer program stored thereon, wherein the computer program executes the steps of the chip layout link tracing method described above when it is run.

[0013] The beneficial effects of this invention are as follows: (1) This invention proposes a chip layout link tracing method based on scan lines and R-trees. By converting layout polygon data into an event queue and combining dynamic R-tree spatial indexing with disjoint-set data structure connectivity maintenance, efficient geometric connectivity analysis of large-scale multi-layer layouts is achieved. This method is driven by scan line events, transforming the complex full layout traversal problem into a one-dimensional ordered processing flow. It quickly filters spatial candidate sets through R-trees and records and merges connectivity relationships in real time through disjoint-set data structures. Thus, while ensuring accuracy, it significantly reduces computational complexity and memory overhead, and improves the processing speed of the layout verification stage.

[0014] (2) This invention further enhances the scalability of the algorithm under large-scale data by combining multi-threaded parallel processing with an adaptive layout partitioning strategy. While retaining the efficiency of the scan-line algorithm, it achieves full utilization of computing resources through task partitioning and local index construction; at the same time, the system supports outputting various structured data formats, including layout exchange formats that can be directly integrated into existing EDA processes, enhancing the practicality and ease of integration of the method. Compared with traditional methods based on region traversal or full-graph construction, this method has significant advantages in terms of running efficiency, memory controllability, and engineering applicability. Attached Figure Description

[0015] Figure 1 This is a flowchart of the chip layout link tracing algorithm based on scan lines and R-trees of the present invention.

[0016] Figure 2 This is a schematic diagram of the R-tree index polygon established by this invention.

[0017] Figure 3 This is a schematic diagram of the union set and intersecting polygons used in this invention. Detailed Implementation

[0018] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] The chip layout link tracing method based on scan lines and R-trees described in this invention, such as... Figure 1 As shown, it includes steps S1 to S4.

[0020] S1. Load the input layout file and parse the polygon data layer by layer according to the process layer. For example, the system can parse input data in the following format, where "Metal1" represents the process layer name, and each subsequent line represents a polygon on that layer, defined by its vertex coordinate sequence: Metal1: (47775,54295),(47775,52805),(50025,52805),(50025,53165),(52505,53165),(52505,54295) (47775,59735),(47775,58245),(50025,58245),(50025,58605),(52505,58605),(52505,59735) (51915,65175),(51915,63685),(54165,63685),(54165,64045),(56645,64045),(56645,65175) During the parsing process, the system extracts and stores the vertex set and process layer number of each polygon, and calculates its minimum bounding box (MBB) and other information.

[0021] S2. The system first determines the spatial partitioning strategy based on the overall layout area extracted in step S1 (i.e., the MBB of the union of all polygons). In a specific embodiment, a regular grid partitioning method is used to divide the two-dimensional layout plane into rectangular sub-regions of equal or approximately equal size. The granularity of the partitioning can be dynamically adjusted according to the number of computing cores and data distribution to achieve load balancing among parallel tasks. Subsequently, the polygons contained in each sub-region are traversed independently: two events are created for each polygon—a start event and an end event. The x-coordinate value of the start event is taken from the x-value of the left boundary of the polygon's MBB, and the event type is marked as "start"; the x-coordinate value of the end event is taken from the x-value of the right boundary of the MBB, and the type is marked as "end". Each event object contains at least the following key attributes: event type, a reference (or unique identifier) ​​to the corresponding polygon data structure, the x-coordinate value of the event occurrence, and the process layer number to which the polygon belongs. After the event generation for all sub-regions is completed, the system aggregates all events and sorts them globally in ascending order according to their x-coordinate values. When the x-coordinates are the same, it is agreed that the start event takes precedence over the end event to ensure the correctness of the scanline algorithm.

[0022] S3. The system first initializes a global disjoint-set data structure to uniformly record and maintain the connectivity relationships between all polygons. Then, based on the event queue and pre-defined sub-regions generated in step S2, a parallel scanning process is initiated. Each computation thread is assigned to a different sub-region and independently executes the scan line algorithm. Within each thread, a local R-tree index is maintained to dynamically manage the set of "active" polygons covered by the current scan line (i.e., polygons whose MBB intersects with the current scan line position).

[0023] Each thread processes each event in its assigned event queue sequentially: when a start event is encountered, the corresponding polygon is inserted into the local R-tree; when an end event is encountered, it is removed from the R-tree. The key is that whenever a new polygon is inserted (processing the start event), such as... Figure 2 As shown, the system immediately uses the spatial query function of the R-tree to quickly retrieve the set of all candidate polygons intersecting with the given polygon MBB in the current R-tree. For each candidate polygon, a precise geometric intersection check is performed to confirm whether the two polygons are actually connected. If connection is confirmed, the global disjoint-set data structure's merge operation is invoked, such as... Figure 3 As shown, the sets containing these two polygons are merged to record their connectivity.

[0024] This process continues until all events are processed. Ultimately, the global disjoint-set data store the complete connected component information determined by geometric intersection of all polygons in the entire map, providing a direct data foundation for subsequent path extraction based on the origin. Through the combination of parallel processing and dynamic indexing, this step can complete the analysis of large-scale map data with high time efficiency.

[0025] S4. Based on the global disjoint-set data structure completed in step S3, the system extracts connected links according to one or more starting points specified by the user. The starting point can be a known polygon or a coordinate point on the map. When the starting point is a coordinate point, the system automatically locates and selects the polygon containing that point as the initial query object. In specific implementation, the system uses the disjoint-set search operation to locate the root node of the connected component to which each starting polygon belongs, thereby obtaining all polygon members within that component. This process ensures that all polygons directly or indirectly connected to the starting point through geometric intersection are completely retrieved.

[0026] To meet the needs of different downstream application scenarios, this system is designed with a flexible and configurable output module that can convert the extracted connected links into various structured data formats. For example, the system can generate plain text reports that clearly list the process layer to which each connected polygon belongs and its unique identifier; it can output JSON files that conform to standard exchange protocols, completely preserving the link topology and geometric information for easy visualization or data analysis software; it can also use connected paths as new geometric layers or marker layers and write them back to standard layout files such as GDSII or OASIS, thereby enabling link highlighting and interactive review in professional layout editing or verification environments.

[0027] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A chip layout link tracing method based on scan lines and R-trees, characterized in that, Includes the following steps: Step S1: Load and parse the input layout file, extract polygon data from each process layer, and calculate the geometric information and minimum bounding box of each polygon. Step S2: Divide the space into blocks according to the overall boundary of the map, create start events and end events for polygons in each sub-region, and build a globally ordered event queue based on the event coordinates; Step S3: Establish a global disjoint set, process the event queue in parallel, dynamically maintain an R-tree in each processing unit to manage the set of active polygons that intersect with the current scan line, discover the connectivity between polygons by querying the R-tree and performing geometric intersection judgment, and use the disjoint set to record and merge the connectivity. Step S4: Based on the disjoint set, extract all connected polygons according to the specified starting point, and output the result data representing the connected links.

2. The chip layout link tracing method based on scan lines and R-tree according to claim 1, characterized in that, In step S1, the parsed layout file format includes GDSII, OASIS, TXT, or DEF; during the parsing process, layer indexes are established synchronously and the vertex coordinates, layer numbers, and minimum bounding box information of polygons are stored.

3. The chip layout link tracing method based on scan lines and R-tree according to claim 2, characterized in that, In step S2, a uniform grid partitioning strategy is used to divide the layout plane into K×K rectangular sub-regions, where K is a parameter dynamically determined based on the number of processor cores and the layout size; the coordinates of the start event and the end event correspond to the x-coordinate values ​​of the left and right boundaries of the minimum bounding box of the polygon, respectively.

4. The chip layout link tracing method based on scan lines and R-tree according to claim 3, characterized in that, The event structure created in step S2 includes information such as event type, pointer to polygon object, event x-coordinate, process layer number, and minimum bounding box of the polygon.

5. The chip layout link tracing method based on scan lines and R-tree according to claim 4, characterized in that, In step S3, when the initial event inserts a new polygon into the R-tree, the following operations are performed: query all candidate polygons that intersect with its minimum bounding box through the R-tree; perform precise geometric intersection judgment for each candidate polygon; If the intersection is confirmed, the merge operation of the disjoint set is invoked to merge the sets to which the two polygons belong.

6. The chip layout link tracing method based on scan lines and R-tree according to claim 5, characterized in that, In step S4, the starting point is a known polygon or a coordinate point in the map; when the starting point is a coordinate point, the system automatically locates the polygon containing the coordinate point as the query starting object.

7. The chip layout link tracing method based on scan lines and R-tree according to claim 6, characterized in that, In step S4, the output results support multiple formats, including: plain text format listing polygon identifiers and layer numbers, JSON format containing complete topological relationships, or standard map exchange format highlighting connected paths in the original map file.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program executes the steps of the chip layout link tracing method according to claim 1 when it runs.

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