Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a light emitting element, a pixel circuit and a driving circuit. The driving circuit provides a control signal for the pixel circuit, and the pixel circuit is electrically connected with the light emitting element. The display panel comprises a first area and a second area. The pixel circuit comprises a first pixel circuit in the first area and a second pixel circuit in the second area. The length of the first pixel circuit in a first direction is less than the length of the second pixel circuit in the first direction. The driving circuit comprises a first driving circuit. The first driving circuit comprises a plurality of first shift registers cascaded along a second direction. The first direction and the second direction intersect. In the second direction, the first shift registers at least partially overlap with the light emitting element. The technical scheme can reduce the frame width of the display panel in the first direction, and even make the display panel realize the frameless design in the first direction.

Description

[0001] This application is a divisional application of the patent filed on August 16, 2024, with application number 202411127690.7 and invention title: A display panel and display device. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] The display panel is the main component of a display device that enables image display. Within the display panel, the light-emitting elements used for image display are connected to pixel circuits, which in turn are connected to driving circuits. The pixel circuits respond to the control of the driving circuits, controlling the light-emitting elements to display images.

[0004] In conventional display panels, the driving circuitry is typically located in the bezel area. Therefore, a bezel area needs to be set up on one side of the display panel to house the driving circuitry, resulting in a relatively wide bezel area. Summary of the Invention

[0005] In view of the above problems, this application provides a display panel and display device to achieve narrow bezels or even bezel-less displays. The specific solution is as follows:

[0006] The first aspect of this application provides a display panel, including:

[0007] Light-emitting elements;

[0008] The pixel circuit and the driving circuit are used. The driving circuit provides control signals to the pixel circuit, and the pixel circuit is electrically connected to the light-emitting element.

[0009] The display panel includes a first region and a second region. The pixel circuit includes a first pixel circuit located in the first region and a second pixel circuit located in the second region. The length of the first pixel circuit in the first direction is less than the length of the second pixel circuit in the first direction.

[0010] The driving circuit includes a first driving circuit, which includes a plurality of first shift registers cascaded along a second direction, wherein the first and second directions intersect; wherein,

[0011] In the second direction, the first shift register at least partially overlaps with the light-emitting element.

[0012] A second aspect of this application provides a display device including the aforementioned display panel.

[0013] By employing the above technical solution, in the display panel and display device provided by this application, since the size of the first pixel circuit in the first direction is smaller than the size of the second pixel circuit in the first direction, the layout space occupied by the first pixel circuit in the first direction can be reduced. This saves space in the display area of ​​the display panel for arranging the driving circuit. The first shift register of the first driving circuit in the driving circuit can at least partially overlap with the light-emitting element in the second direction, thereby allowing part or all of the driving circuit to be arranged in the display area. Therefore, the technical solution of this application can reduce the bezel width of the display panel in the first direction, and even enable the display panel to achieve a bezel-less design in the first direction. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0016] Figure 1 A top view of a display panel provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the circuit connections for the first driving circuit.

[0018] Figure 3a A schematic diagram of the circuit connection relationship of a pixel circuit provided in an embodiment of this application;

[0019] Figure 3b A schematic diagram of the circuit connection relationship of a second pixel circuit provided in an embodiment of this application;

[0020] Figure 4 A layout of a driving transistor provided for an embodiment of this application;

[0021] Figure 5 A layout of a driving transistor in a first pixel circuit provided in an embodiment of this application;

[0022] Figure 6A layout of a driving transistor in a second pixel circuit provided in an embodiment of this application;

[0023] Figure 7 A layout of pixel circuitry in a display panel provided in an embodiment of this application;

[0024] Figure 8 A layout of a first pixel circuit provided in an embodiment of this application;

[0025] Figure 9 A layout of a second pixel circuit provided in an embodiment of this application;

[0026] Figure 10 A partially enlarged view of a pixel circuit layout provided in an embodiment of this application;

[0027] Figure 11 A layout of another second pixel circuit provided in an embodiment of this application;

[0028] Figure 12 The layout of the driving transistor in the pixel circuit connected to the first light-emitting element;

[0029] Figure 13 The layout of the driving transistor in the pixel circuit connected to the second light-emitting element;

[0030] Figure 14 A layout of pixel circuitry in a display panel provided in an embodiment of this application;

[0031] Figure 15 for Figure 14 The layout of the polysilicon layer containing the active regions of the transistors corresponding to two adjacent first pixel circuits and two adjacent second pixel circuits in the same row;

[0032] Figure 16 A schematic diagram illustrating the layout of pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0033] Figure 17 A schematic diagram illustrating the layout of pixel circuits and driving circuits in a display panel, provided as an embodiment of this application;

[0034] Figure 18 A layout of a first shift register in a display panel provided in an embodiment of this application;

[0035] Figure 19 for Figure 18 The circuit diagram of the first shift register is shown below;

[0036] Figure 20 This is the layout of the first output transistor in the first shift register;

[0037] Figure 21 This is the layout of the second output transistor in the first shift register;

[0038] Figure 22 This is a schematic diagram showing the cascaded relationship of the second shift register in the second driving circuit;

[0039] Figure 23 A layout of a second shift register provided in an embodiment of this application;

[0040] Figure 24 The circuit diagram is for the second shift register;

[0041] Figure 25 A schematic diagram of the layout of the anode connection line of the light-emitting element in a display panel provided in an embodiment of this application;

[0042] Figure 26 A cross-sectional view of a display panel provided in an embodiment of this application;

[0043] Figure 27 A top view of a circuit and light-emitting element layout in a display panel provided in an embodiment of this application;

[0044] Figure 28 A top view of the display area of ​​a display panel provided in an embodiment of this application;

[0045] Figure 29 A top view of the display area of ​​another display panel provided in an embodiment of this application;

[0046] Figure 30 A top view of the display area of ​​another display panel provided in an embodiment of this application;

[0047] Figure 31 A cross-sectional view of a display panel provided in an embodiment of this application;

[0048] Figure 32 A cross-sectional view of another display panel provided in an embodiment of this application;

[0049] Figure 33 This application provides a schematic diagram of a display panel with different display areas in an embodiment.

[0050] Figure 34 This is a schematic diagram of another display panel with different display areas provided in an embodiment of this application;

[0051] Figure 35 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0052] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0053] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The terminology used in the embodiments of this application is only used to explain the specific embodiments of this application, and is not intended to limit this application.

[0054] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of the circuit connections for the first driving circuit. The display panel shown includes:

[0056] Light-emitting element 11;

[0057] The pixel circuit 12 and the driving circuit 13 are provided. The driving circuit 13 provides control signals to the pixel circuit 12. The pixel circuit 12 is electrically connected to the light-emitting element 11.

[0058] The display panel includes a first region AA1 and a second region AA2. The pixel circuit 12 includes a first pixel circuit 121 located in the first region AA1 and a second pixel circuit 122 located in the second region AA2. The length L11 of the first pixel circuit 121 in the first direction X is less than the length L12 of the second pixel circuit 122 in the first direction X, that is, L11 < L12.

[0059] The driving circuit 13 includes a first driving circuit 131, which includes a plurality of first shift registers 1311 cascaded along the second direction Y, where the first direction X and the second direction Y intersect.

[0060] In the second direction Y, the first shift register 1311 and the light-emitting element 11 at least partially overlap.

[0061] Both the first direction X and the second direction Y are parallel to the plane of the display panel. They can be perpendicular or intersect and not perpendicular. Optionally, the display panel has multiple light-emitting elements 11 arranged in an array. One of the first direction X and the second direction can be set to be the row direction of the array and the other to be the column direction of the array. For example, the first direction X is the row direction and the second direction Y is the column direction.

[0062] Since L11 < L12, the layout space occupied by the first pixel circuit 121 in the first direction X can be reduced, allowing more pixel circuits 12 to be set in the first region AA1. This allows pixel circuits 12 from other regions (such as the third region AA3 in the following text) to be moved into the first region AA1. In this way, space can be saved in the third region AA3 for arranging the first driving circuit 131.

[0063] In the display panel provided in this application embodiment, since L11 < L12, the layout space occupied by the first pixel circuit 121 in the first direction X can be reduced, thereby saving space in the display area of ​​the display panel for arranging the first driving circuit 131. The first shift register 1311 of the first driving circuit 131 can at least partially overlap with the light-emitting element 11 in the second direction Y, thereby allowing at least a portion of the driving circuit 13 to be arranged in the display area, thus reducing the border area formed by the driving circuit 13 in the first direction X. Therefore, the technical solution of this application can reduce the border width of the display panel in the first direction X, or even enable the display panel to achieve a borderless design in the first direction X.

[0064] The length of the pixel circuit 12 in the first direction X can be the length occupied by all the active regions of the transistors in the pixel circuit 12 in the first direction X.

[0065] In some embodiments, the display panel is designed with redundant positions so that if some light-emitting elements 11 fail, new light-emitting elements 11 can be added to the redundant positions to maintain normal display. In this case, the failed light-emitting element 11 may or may not be removed. In some embodiments, the display panel is not designed with redundant positions, and the failed light-emitting element 11 is directly removed and a new light-emitting element 11 is added to the original position to ensure normal display of the display panel.

[0066] like Figure 2 As shown, in the first driving circuit 131, there are n first shift registers 1311 cascaded sequentially in the second direction Y, where n is a positive integer greater than 1. Along the second direction Y, these n first shift registers 1311 are EVSR1, EVSR2, EVSR3, ..., EVSR... nThe output signals of the n first shift registers 1311 are EOUT1, EOUT2, EOUT3, ..., EOUT, respectively. n The n first shift registers 1311 are arranged sequentially along the second direction Y. The output of the previous first shift register 1311 is used as the input of the next adjacent first shift register 1311, so as to realize the sequential cascading of each first shift register 1311.

[0067] Optionally, the output signal EOUT of the first shift register 1311 can be used as the light emission control signal EMIT.

[0068] exist Figure 2 In the configuration shown, each pair of pixel circuits 12 is connected to a first shift register 1311. Each first shift register 1311 provides control signals to two adjacent rows of pixel circuits 12, and each first shift register 1311 drives two rows of pixel circuits 12.

[0069] In this embodiment, the display panel can be divided into multiple sub-display areas distributed sequentially in a first direction X, with different sub-display areas not overlapping each other. At least one sub-display area is designated as a first area AA1, at least one sub-display area is designated as a second area AA2, and at least one sub-display area is designated as a third area AA3. The first area AA1, the second area AA2, and the third area AA3 are different sub-display areas.

[0070] Since L11 < L12, the layout space occupied by the first pixel circuit 121 in the first direction X can be reduced, so that more pixel circuits 12 can be set in the first region AA1. Therefore, the pixel circuit 12 connected to the light-emitting element 11 in the third region AA3 can be set as the first pixel circuit 121 in the first display region AA1. If the light-emitting elements 12 in the first region AA1 and the third region AA3 are respectively connected to the first pixel circuit 121 in the first region AA1, it is equivalent to moving the pixel circuit 12 in the third region AA3 to the first region AA1. There is no need to set the pixel circuit 12 in the third region AA3, so that space can be left in the third region AA3 for the layout of the first driving circuit 131. At least part of the driving circuit 13 can be set in the third region AA3, so the border width of the display panel in the first direction X can be reduced, or even the display panel can achieve a borderless design in the first direction X.

[0071] refer to Figure 3a and Figure 3b , Figure 3a This is a schematic diagram of the circuit connection relationship of a first pixel circuit provided in an embodiment of this application. Figure 3bThis is a schematic diagram of the circuit connection relationship of a second pixel circuit provided in an embodiment of this application. Based on any of the above embodiments, the pixel circuit 12 may include a driving transistor M3, the gate of the driving transistor M3 is connected to a first node N1, the first electrode is connected to a second node N2, and the second electrode is connected to a third node N3.

[0072] Furthermore, such as Figure 3a and Figure 3b As shown, the pixel circuit 12 also includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6, both of which are turned on during the light-emitting phase, and the driving transistor M3 is also turned on to provide driving current to the light-emitting element 11, enabling the light-emitting element 11 to emit light for display. The gates of both the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are connected to the light-emitting control signal EMIT. The first terminal of the first light-emitting control transistor M1 is connected to the first power supply voltage PVDD, and the second terminal is connected to the second node N2. The first terminal of the second light-emitting control transistor M6 is connected to the third node N3, and the second terminal is connected to the fourth node N4.

[0073] The first electrode of the light-emitting element 11 is connected to the fourth node N4, and the second electrode is connected to the second power supply voltage PVEE. If the first power supply voltage PVDD is high and the second power supply voltage PVEE is low, then the fourth node N4 is connected to the anode of the light-emitting element 11; otherwise, the fourth node N4 is connected to the cathode of the light-emitting element 11.

[0074] Furthermore, such as Figure 3a and Figure 3b As shown, the pixel circuit 12 also includes a first reset transistor M5, which is used to reset the voltage of the first node N1 during the reset phase. The gate of the first reset transistor M5 is connected to the first scan signal S1, the first terminal is connected to the reset signal VREF, and the second terminal is connected to the first node N1.

[0075] Furthermore, such as Figure 3a and Figure 3b As shown, the pixel circuit 12 also includes a threshold compensation transistor M4, which is used to perform threshold compensation on the driving transistor M3. The gate of the threshold compensation transistor M4 is connected to the second scan signal S2, the first terminal is connected to the first node N1, and the second terminal is connected to the third node N3.

[0076] Furthermore, such as Figure 3a and Figure 3b As shown, the pixel circuit 12 also includes a data writing transistor M2, which is turned on during the data writing phase to write the data signal DATA to the second node N2. The gate of the data writing transistor M2 is connected to the second scan signal S2, the first terminal is connected to the second node N2, and the second terminal is connected to the data signal DATA.

[0077] Furthermore, such as Figure 3a and Figure 3b As shown, the pixel circuit 12 also includes a second reset transistor M7, which is used to perform voltage reset at the fourth node N4 during the reset phase. The gate of the second reset transistor M7 is connected to the scan signal, the first terminal is connected to the reset signal VREF, and the second terminal is connected to the fourth node N4. In the first pixel circuit 121, it can be configured as follows: Figure 3a As shown, the second reset transistor M7 is connected to the second scan signal S2; in the second pixel circuit 122, it can be as follows: Figure 3b As shown, the second reset transistor M7 is connected to the first scan signal S1.

[0078] In the pixel circuit 12, a storage capacitor CST is also connected between the first node N1 and the first pole of the first light-emitting control transistor M1.

[0079] In this embodiment, the first reset transistor M5 and the threshold compensation transistor M4 are illustrated as dual-gate transistors; however, they can also be single-gate transistors in other embodiments. Each transistor in the pixel circuit 12 can be a PMOS, which is turned on when the gate voltage is low and turned off when the gate voltage is high. In other embodiments, the transistors in the pixel circuit 12 can also be NMOS. NMOS transistors are turned off when the gate voltage is low and turned on when the gate voltage is high.

[0080] exist Figure 3a and Figure 3b In the illustration, the pixel circuit 12 is illustrated as a 7T1C circuit structure, which consists of 7 transistors and 1 capacitor. The pixel circuit 12 is not limited to a 7T1C circuit structure; capacitors or transistors can be added to improve the accuracy of controlling the light-emitting element 11.

[0081] refer to Figure 4 , Figure 4 The layout of a driving transistor provided in this application embodiment, based on any of the above embodiments, may include a pixel circuit 12 including a driving transistor M3. The driving transistor M3 includes at least a first sub-transistor M31 and a second sub-transistor M32. The gate g of the first sub-transistor M31 is connected to the gate g of the second sub-transistor M32. The first electrode s of the first sub-transistor M31 and the first electrode s of the second sub-transistor M32 are connected. The second electrode d of the first sub-transistor M31 is connected to the second electrode d of the second sub-transistor M32.

[0082] Figure 4In the illustrated configuration, the driving transistor M3 has multiple sub-transistors. The gates (g) of these sub-transistors are connected together, their first electrodes (s) are connected together, and their second electrodes (d) are connected together. This parallel connection of the sub-transistors improves the channel width-to-length ratio of the driving transistor M3, thereby enhancing its driving capability. In this configuration, one of the first electrode (s) and the other electrode (d) is the source, and the other is the drain.

[0083] In the same driving transistor M3, each sub-transistor has a source region a. The first electrode s and the second electrode d of the sub-transistor are electrically connected to the underlying active region a through corresponding vias. The via positions can be set according to circuit layout requirements. In the plane parallel to the active region a, the area where the gate g of the same sub-transistor overlaps with the active region is the channel region of the sub-transistor. The first electrode s and the second electrode d are located in the same metal layer, but in a different metal layer than the gate g. There is an insulating layer between the different metal layers.

[0084] exist Figure 4 The illustration uses a driving transistor M3 with two sub-transistors as an example. It should be noted that the driving transistor M3 can be configured to include two or any number of sub-transistors, depending on the requirements; it is not limited to this. Figure 4 The implementation shown has two sub-transistors. In this embodiment, the number of sub-transistors in the driving transistor M3 is not limited.

[0085] refer to Figure 5 and Figure 6 , Figure 5 This is a layout of a driving transistor in a first pixel circuit provided in an embodiment of this application. Figure 6 This is a layout of a driving transistor in a second pixel circuit provided in an embodiment of this application. Based on the above embodiments, as follows... Figure 5 As shown, in the first pixel circuit 121, the first sub-transistor M31 and the second sub-transistor M32 are arranged along the second direction Y; as Figure 6 As shown, in the second pixel circuit 122, the first sub-transistor M31 and the second sub-transistor M32 are arranged along the first direction X.

[0086] Figure 5 The driving transistor M3 shown can be used in the embodiments described below. Figure 8 The layout of the first pixel circuit 121 is shown. Figure 6 The driving transistor M3 shown can be used in the embodiments described below. Figure 9 The layout of the first pixel circuit 121 shown is as follows. Figure 6 The source and drain metal layers and corresponding vias connected to the first and second terminals of the sub-transistor are not shown in the figure.

[0087] In the first region AA1, since more pixel circuits 12 need to be arranged in the first direction X, the length of the pixel circuits 12 in the first region AA1 needs to be compressed in the first direction X. In the first pixel circuit 121, since the first sub-transistor M31 and the second sub-transistor M32 in the same driving transistor M3 are arranged along the second direction Y, the length of the first pixel circuit 121 in the first direction X can be reduced, thereby saving the layout space of the first pixel circuit 121 in the first region AA1 in the first direction X, so that more first pixel circuits 121 can be arranged in the first region AA1.

[0088] In the second region AA1, since there is no need to lay out the pixel circuits 12 in other regions, the second region AA2 has sufficient space in the first direction X to lay out the second pixel circuit 122. In the second pixel circuit 122, since the first sub-transistor M31 and the second sub-transistor M32 in the same driving transistor M3 are arranged along the first direction X, the size of the second pixel circuit 122 in the second direction Y will not increase, and the length of the pixel circuit 12 in the second region AA2 in the second direction Y can be shorter.

[0089] In some embodiments, the present invention can be applied to transparent displays. Furthermore, as described in the following embodiments, if the display panel is a transparent display panel, arranging the first sub-transistor M31 and the second sub-transistor M32 in the second pixel circuit 122 along the first direction X can also make the transparent area in the second region AA2 have a larger area.

[0090] When the display panel is used as a transparent display panel, the layout of the circuit board in the transparent display panel can be as follows: Figure 7 As shown.

[0091] refer to Figure 7 , Figure 7 This application provides a layout of pixel circuitry in a display panel. Figure 7 The diagram shows two rows of pixel circuits 12, with each row showing six pixel circuits 12 arranged consecutively in the first direction X. In the same row, the three pixel circuits 12 on the left are the first pixel circuits 121 located in the first region AA1, and the three pixel circuits 12 on the right are the second pixel circuits 122 located in the second region AA2.

[0092] like Figure 7 As shown, the display panel can have multiple pixel areas PA, each pixel area PA including a circuit area CA and a transmission area TA. In the first area AA1, the transmission area TA is the first transmission area TA1; in the second area AA1, the transmission area TA is the second transmission area TA2. The first pixel circuit 121 and the second pixel circuit 122 are located in the corresponding circuit area CA.

[0093] In this embodiment, transparent display can be achieved by designing the layout of each transistor in the pixel circuit 12 to form a transparent region PA in the first region AA1 and the second region AA2 respectively.

[0094] Optionally, the display panel has multiple pixel areas PA arranged in an array, each pixel area PA having one pixel. The pixel can be configured to include three light-emitting elements 11 with different light-emitting colors arranged sequentially in the first direction X. The three light-emitting elements 11 can emit red light, green light and blue light respectively.

[0095] In the second region AA2, the second pixel circuit 122 is a normal pixel circuit that does not require compression of the length in the first direction X. Each pixel region PA can be configured to have three second pixel circuits 122 to connect the three light-emitting elements 11 in the pixel region PA respectively.

[0096] In the first region AA1, since the length of the first pixel circuit 121 in the first direction X is less than the length of the second pixel circuit 122 in the first direction X, the number of first pixel circuits 121 in each pixel region P1 is greater than 3. Therefore, for a pixel region PA located in the first region AA1, three of the first pixel circuits 121 are used to connect to the three light-emitting elements 11 in the pixel region PA respectively, and the other first pixel circuits 121 are used to connect to the light-emitting elements 11 in the third region AA3.

[0097] Specifically, for pixel area PA located in the first region AA1, it can be configured with f first pixel circuits 121, where f is a positive integer greater than 3. f can be any positive integer greater than 3, and its value can be set according to requirements. To facilitate layout design in the first region AA1, f can be set to an integer multiple of 3. For example, if f=6, then 6 first pixel circuits 121 can be set in the first region AA1, which is equivalent to compressing the length of the normal pixel circuit 122 in the first direction X by half, so as to form 6 first pixel circuits 121 in one pixel area PA, thereby increasing the number of pixel circuits 12 in the first region AA1.

[0098] refer to Figure 8 and Figure 9 , Figure 8 This is a layout of a first pixel circuit provided in an embodiment of this application. Figure 9 This is a layout diagram of a second pixel circuit provided in an embodiment of this application. (In conjunction with...) Figure 3a , Figure 3b and Figure 8As shown, the pixel circuit 12 includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6. The first terminal of the driving transistor M3 is connected to the first power supply terminal through the first light-emitting control transistor M1, and the first power supply voltage PVDD is connected through the first power supply terminal. The second terminal of the driving transistor M3 is connected to the light-emitting element 11 through the second light-emitting control transistor M6.

[0099] like Figure 8 As shown, in the first pixel circuit 121, the distance between the first light-emitting control transistor M1 and the driving transistor M3 in the second direction Y is D11, and the distance between the second light-emitting control transistor M6 and the driving transistor M3 in the second direction is D12; Figure 9 As shown, in the second pixel circuit 122, the distance between the first light-emitting control transistor M1 and the driving transistor M3 in the second direction Y is D21, and the distance between the second light-emitting control transistor M6 and the driving transistor M3 in the second direction Y is D22; wherein, |D11-D12|>|D21-D22|.

[0100] It should be noted that, in the embodiments of this application, when marking the distance between two transistors in the second direction Y in the accompanying drawings, the distance between the active regions of the transistors in the second direction Y is marked by the distance between the center lines of the active regions of the transistors in the second direction Y.

[0101] In this embodiment, the length of the pixel circuit 12 in the first direction X can be adjusted by adjusting the distance between the two light-emitting control transistors in the pixel circuit 12 and the driving transistor M3. As mentioned above, |D11-D12|>|D21-D22| can be set, thereby increasing |D11-D12| to shorten the length of the first pixel circuit 121 in the first direction X, so that L11<L12, allowing a larger number of first pixel circuits 121 to be arranged in the first region AA1.

[0102] By setting different arrangements or positions of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the first pixel circuit 121 and the second pixel circuit 122, the lengths of the first pixel circuit 121 and the second pixel circuit 122 in the first direction X or the second direction Y can be adjusted. Figure 8 As shown, in the first pixel circuit 121, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are arranged in the second direction Y. In the second direction Y, the second light-emitting control transistor M6 is located on the side of the first light-emitting control transistor M1 away from the driving transistor M1. At this time, D12 > D11. Figure 9As shown, in the second pixel circuit 122, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are arranged in the first direction. In the second direction, the distance between the first light-emitting control transistor M1 and the driving transistor M3 is D21, which is equal to the distance between the second light-emitting control transistor M6 and the driving transistor M3 in the second direction, i.e., D21=D22.

[0103] In the first pixel circuit 121, such as Figure 8 As shown, the distance between the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the first direction X is D51, and the distance between the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the second direction Y is D52. In the second pixel circuit 122, as... Figure 9 As shown, the distance between the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the first direction X is D61, and the distance between the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the second direction Y is D62. Wherein, D51 < D61, and / or, D52 > D62.

[0104] It should be noted that, in the embodiments of this application, when marking the distance between two transistors in the first direction X in the accompanying drawings, the distance between the active regions of the transistors in the first direction X is marked by the distance between the center lines of the active regions of the transistors in the first direction X.

[0105] Optionally, in the first pixel circuit 121, it can be as follows: Figure 8 As shown, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are arranged opposite each other in the second direction Y, such that the center lines of their active regions in the first direction X coincide or nearly coincide, thereby making D51=0, so as to minimize the length of the first pixel circuit 121 in the first direction X. In other ways, D51 can also be set to >0.

[0106] In the first pixel circuit 121, while avoiding short circuits between the first light-emitting control transistor M1 and the second light-emitting control transistor M6, D52 can be reduced as much as possible within the limits allowed by process conditions, thereby reducing the length of the first pixel circuit 121 in the second direction Y. When used in a transparent display panel, the area of ​​the transmissive region in the first region AA1 can be increased.

[0107] Since the size of the pixel circuit 12 in the first direction X does not need to be compressed in the second region AA2, there is enough space in the second region AA2 to arrange the second pixel circuit 122. Since the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the second pixel circuit 122 are both input with the light-emitting control signal EMIT, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the second pixel circuit 122 can be arranged adjacent to each other in the first direction X.

[0108] In the second pixel circuit 122, as Figure 9 As shown, if the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are arranged adjacent to each other in the first direction X, then the center lines of the active regions of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the first direction X will not coincide, so D61>0.

[0109] In the second pixel circuit 122, as Figure 9 As shown, if the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are arranged adjacent to each other in the first direction X, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be connected to the same signal line that receives the light-emitting control signal EMIT, reducing the number of signal lines. Simultaneously, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be arranged facing each other in the first direction X, so that the center lines of the active regions of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 coincide or nearly coincide in the second direction Y, thereby enabling D62=0, thus reducing the size of the second pixel circuit 122 in the second direction Y. When used in a transparent display panel, setting D62=0 can reduce the size of the second pixel circuit 122 in the second direction Y, thereby increasing the area of ​​the transmissive region in the second region AA2.

[0110] In this embodiment, the relative two-sided boundaries of the pixel circuit 12 in the first direction X are the boundaries of the outermost transistor in the first direction X of the pixel circuit 12, and the relative two-sided boundaries of the pixel circuit 12 in the second direction Y can be the boundaries of the outermost transistor in the second direction Y of the pixel circuit 12.

[0111] For the first pixel circuit 121, Figure 8 Taking the illustrated layout as an example, the left boundary of the first pixel circuit 121 is the left boundary of the data writing transistor M2 connected to the data signal DATA; the right boundary of the first pixel circuit 121 is the right boundary of the driving transistor M3; the upper boundary of the first pixel circuit 121 is the upper boundary of the first reset transistor M5; and the lower boundary is the lower boundary of the second reset transistor M7. In the first pixel circuit 121, the second reset transistor M7 is located at the bottom, and the second reset transistor M7 is adjacent to the reset signal line of another first pixel circuit 121 in the second direction Y. In the same first pixel circuit 121, a large distance can be reserved between the second reset transistor M7 and the second light-emitting control transistor M6 in the second direction Y to form a transparent area, which can be used for transparent display.

[0112] For the second pixel circuit 122, Figure 9Taking the layout shown as an example, the left boundary of the second pixel circuit 122 is the left boundary of the second light-emitting control transistor M6; the right boundary of the second pixel circuit 122 is the right boundary of the data writing transistor M2; the upper boundary of the second pixel circuit 122 is the upper boundary of the first reset transistor M5 and / or the second reset transistor M7; and the lower boundary of the second pixel circuit 122 is the lower boundary of the first light-emitting control transistor M1 and / or the second light-emitting control transistor M6.

[0113] In one embodiment of this application, it can be as follows: Figure 8 As shown, D11 < D12, and / or, as shown in the figure, D21 = D22.

[0114] In the first pixel circuit 121, since D11 < D12, the two light-emitting control transistors can be placed on the same side of the driving transistor M3, and the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be arranged sequentially in the second direction Y, thereby reducing the length of the first pixel circuit 121 in the first direction X. In the same first pixel circuit 121, such as... Figure 8 As shown, the driving transistor M3, the first light-emitting control transistor M1, and the second light-emitting control transistor M6 can be arranged sequentially in the second direction Y, which makes it easier to adjust the distance between two adjacent transistors in the second direction Y, so as to reduce the length of the first pixel circuit 121 in the first direction X.

[0115] In the second pixel circuit 122, since D21=D22, the two light-emitting control transistors can be placed on the same side of the driving transistor, so that the center lines of their active regions in the second direction Y coincide or approximately coincide. This allows the first light-emitting control transistor M1 and the second light-emitting control transistor M6 to be positioned opposite each other in the first direction X, facilitating gate connection to the same scan signal line and reducing the length of the second pixel circuit 122 in the second direction Y. In the same second pixel circuit 122, such as... Figure 9 As shown, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be located on the same side of the driving transistor M3 in the second direction Y, and the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be arranged adjacent to each other in the first direction X. Their gates can be connected to the same light-emitting control signal line so that the light-emitting control signal can be input simultaneously, which can reduce the number of scanning signal lines.

[0116] As described above, the pixel circuit includes a first reset transistor M5. It can be as follows: Figure 8 or Figure 9As shown, the gate of the first reset transistor M5 is connected to the first scan signal line SL1, through which the first scan signal S1 can be input to the gate of the first reset transistor M5. The first terminal of the first reset transistor M5 is connected to the reset signal line SL3, through which the reset signal VREF can be input to the first terminal of the first reset transistor M5. The second terminal of the first reset transistor M5 is connected to the gate of the driving transistor M3. The reset signal line SL3 is located on the side of the first scan signal line SL1 away from the driving transistor M3. In this way, a portion of the active area of ​​the first reset transistor M5 and the reset signal line SL3 can overlap in the direction perpendicular to the plane of the display panel, thereby shortening the length of the pixel circuit 12 in the second direction Y.

[0117] in, Figure 8 The diagram not only shows the first scan signal line SL1 connected to the i-th first pixel circuit 121 in the second direction Y, but also... i and reset signal line SL3 i It also shows the first scan signal line SL1 to which the next first pixel circuit 121 is connected. i+1 and reset signal line SL3 i+1 . Figure 9 The first scan signal line SL1 connected to the i-th first pixel circuit 121 in the second direction Y is shown. i and reset signal line SL3 i i is a positive integer.

[0118] refer to Figure 10 , Figure 10 This is a partially enlarged view of a pixel circuit layout provided in an embodiment of this application. Figure 10 This is a partial enlarged view of the layout of pixel circuit 12 in the area corresponding to the first reset transistor M5. The first electrode s of the first reset transistor M5 and the reset signal line SL3 are both connected to the first connection portion LJ1; the first connection portion LJ1 partially overlaps with the first scan signal line SL1.

[0119] The overlapping portion of the first scan signal line SL1 and the active region a of the first reset transistor M5 in the third direction is multiplexed as the gate of the first reset transistor M5. The third direction is perpendicular to the first direction X and the second direction Y, that is, the third direction is perpendicular to the plane where the display panel is located.

[0120] Optionally, the first reset transistor M5 is a dual-gate transistor with two TFTs. In this case, the first scan signal line SL1 and the active region a of the first reset transistor M5 have two overlapping regions, which serve as gates of the TFTs respectively.

[0121] Combination Figures 8-10As shown in this embodiment, the first terminal s of the first reset transistor M5 can be connected to the reset signal line SL3 through the first connection portion LJ1. The reset signal provided by the reset signal line SL3 is provided to the first terminal s of the first reset transistor M5 through the first connection portion LJ1. The first connection portion LJ1 partially overlaps with the first scan signal line SL1, thereby compressing the length of the pixel circuit in the second direction Y. The second terminal d of the first reset transistor M5 is connected to the gate of the driving transistor M3, thereby realizing circuit interconnection.

[0122] The first connecting part LJ1 can be made of a different metal layer than the first scan signal line SL1, so that the first connecting part LJ1 can cross the first scan signal line SL1 insulated.

[0123] As described above, the pixel circuit 12 includes a data writing transistor M2 and a threshold compensation transistor M4, with the first terminal of the data writing transistor M2 connected to the first terminal of the driving transistor M3. Figure 8 and Figure 9 As shown, the second terminal of the data writing transistor M2 is connected to the data line SL5, so that the data signal DATA is input to the data writing transistor M2 through the data line SL5; the first terminal of the threshold compensation transistor M4 is connected to the gate of the driving transistor M3, and the second terminal of the threshold compensation transistor M4 is connected to the second terminal of the driving transistor M3. Figure 9 In the layout of the second pixel circuit 122 shown, the data signal line SL5 connected to the data writing transistor M2 in the second pixel circuit 122 is positioned on the side of the data writing transistor M2 away from the driving transistor M3, that is, the connected data signal line SL5 is positioned on the side of the data writing transistor M2 away from the driving transistor M3. Figure 9 On the right side, or on the side of the driving transistor away from the data writing transistor M2, or in other ways, the data signal line SL5 can be placed on the right side. Figure 9 On the left side. Figure 8 and Figure 9 The diagram shows the data line SL5 connected to the i-th pixel circuit 12 in the second direction Y. i .

[0124] In the first pixel circuit 121, it can be as follows: Figure 8 As shown, the distance between the data writing transistor M2 and the threshold compensation crystal M4 in the first direction X is D1; ​​in the second pixel circuit 122, it can be as follows: Figure 9 As shown, the distance between the data writing transistor M2 and the threshold compensation crystal M4 in the first direction X is D2.

[0125] In one embodiment of this application, the second pixel circuit 122 can be as follows: Figure 9As shown, the data writing transistor M2 and the threshold compensation crystal M4 are arranged on the same side of the driving transistor M3 and are adjacent in the first direction X. In this way, the data writing transistor M2 and the threshold compensation crystal M4 can be arranged between the first scan signal line SL1 and the driving transistor M3. At this time, it can be set that D1>D2 or D1 = D2.

[0126] Reference Figure 11 , Figure 11 is a layout of another second pixel circuit provided by an embodiment of the present application. Compared with Figure 9 the manner shown, Figure 11 in the manner shown, the distance D2 between the data writing transistor M2 and the threshold compensation crystal M4 in the second pixel circuit 122 in the first direction X is increased, such that D1<D2.

[0127] Compared with Figure 9 the manner shown, in Figure 11 the manner shown, D1<D2, and the distance between the threshold compensation transistor M4 and the data writing transistor M2 in the first direction X is increased, which can make the threshold compensation transistor M4 closer to the second light-emitting control transistor M6. At this time, combined with Figure 3a , Figure 3b and Figure 11 shown, the second pole of the threshold compensation transistor M4 is electrically connected to the first pole of the second light-emitting control transistor M6 at the third node N3. At this time, the third node N3 of the second pixel circuit 122 can be transferred from the polysilicon layer where the active region is located to the metal layer where the source and drain electrodes of the transistor are located, so as to reduce the impedance of the pixel circuit 12 at the third node N3 and thus reduce the voltage drop.

[0128] As described above, the pixel circuit 12 further includes a first reset transistor M5 and a second reset transistor M7. The first reset transistor M5 is connected to the gate of the driving transistor M3 and is used to provide a first reset signal for the gate of the driving transistor M3. The second reset transistor M7 is connected to the first electrode of the light-emitting element 11 and is used to provide a second reset signal for the first pole of the light-emitting element 11.

[0129] Optionally, the first reset signal and the second reset signal can be the same, and both can be the reset signal VREF. In other ways, the first reset signal and the second reset signal can also be different reset signals.

[0130] In the first pixel circuit 121, it is set that the first reset transistor M5 and the second reset transistor M7 are respectively connected to different reset signal lines. In this way, the first reset transistor M5 and the second reset transistor M7 can be arranged along the second direction Y, so as to reduce the length of the first pixel circuit 121 in the first direction X.

[0131] In particular, since the second terminal of the second light-emitting control transistor M6 and the second terminal of the second reset transistor M7 need to be connected through the second connection part LJ2, by setting the first reset transistor M5 and the second reset transistor M7 to be connected to different reset signal lines, the second connection part LJ2 can be extended to the next first pixel circuit 121, thereby avoiding the second connection line LJ2 from occupying the wiring space between the first pixel circuits 121, which is beneficial to reducing the distance between the first pixel circuits 121.

[0132] In the second pixel circuit 122, it can be as follows: Figure 9 or Figure 11 As shown, the gate of the first reset transistor M5 is connected to the first scan signal line SL1, and the gate of the second reset transistor M7 is also connected to the first scan signal line SL1. Since the second region AA2 does not require compression of the pixel circuit 12's length in the first direction X, there is sufficient space along the first direction X to arrange the second pixel circuit 122. Therefore, in the second pixel circuit 122, the first reset transistor M5 and the second reset transistor M7 can be arranged sequentially in the first direction X, allowing them to share the same first scan signal line SL1.

[0133] For the first pixel circuit 121, the second scan signal line SL2 connected to the first pixel circuit 121 in the i-th row is... i Multiplexed as the first scan signal line SL1 of the first pixel circuit 121 in the (i+1)th row i i is a positive integer. That is, for two adjacent first pixel circuits 121 in the second direction Y, the second scan signal line SL2 connected to the second reset transistor M7 in the previous first pixel circuit 121 is used as the first scan signal line connected to the first reset transistor M5 in the next first pixel circuit 121.

[0134] Figure 8 The diagram shows the first scan signal line SL1 connected to the i-th first pixel circuit 121 in the second direction Y. i The first scan signal line SL1 connected to the (i+1)th first pixel circuit 121 i+1 In the i-th first pixel circuit 121, the gate of the second reset transistor M7 is connected to the first scan signal line SL1. i+1 Multiplexing the first scan signal line S1L i+1 The second scan signal line SL2 is connected to the second reset transistor M7 in the i-th first pixel circuit 121. iThis method is equivalent to multiplexing the first scan signal line SL1 in the next row of the first pixel circuit 121 into the second scan signal line SL2 connected to the second reset transistor M7 in the previous row of the first pixel circuit 121. In this case, the second reset transistor M7 of the previous row of the first pixel circuit 121 can also be configured to input the reset signal VREF through the reset signal line LS3 of the next row of the first pixel circuit 121. This method not only reduces the length of the first pixel circuit 121 in the first direction X, but also avoids the problem of increased signal lines caused by the sequential distribution of the two reset transistors along the second direction Y.

[0135] For the same row of pixel circuits 12, there is a first trace SL2' for providing the second scan signal S2. Figure 8 The first trace SL2' connected to the pixel circuit 12 in the i-th row is shown in the figure. i The first trace SL2' is used to provide a second scan signal S2 to the data writing transistor M2 and the threshold compensation transistor M4 in the same row of pixel circuit 12. The first trace SL2' can be located between the first scan signal line SL1 and the driving transistor M3 in the connected pixel circuit 12.

[0136] In the first pixel circuit 121, such as Figure 8 As shown, the distance between the first reset transistor M5 and the driving transistor M3 in the second direction Y is D31, and the distance between the second reset transistor M7 and the driving transistor M3 in the second direction is D32. In the second pixel circuit 122, as... Figure 9 or Figure 11 As shown, the distance between the first reset transistor M5 and the driving transistor M3 in the second direction Y is D41, and the distance between the second reset transistor M7 and the driving transistor M3 in the second direction Y is D42; where |D31-D32|>|D41-D42|. Thus, in the second direction Y, the distance difference between the two reset transistors and the driving transistor M3 in the first pixel circuit 121 and the second pixel circuit 122 is different, and the distance difference corresponding to the first pixel circuit 121 is larger. This increases the length of the two reset transistors in the first pixel circuit 121 in the second direction Y, thereby shortening the distance between the two reset transistors in the first pixel circuit 121 in the first direction X, and thus reducing the length of the first pixel circuit 121 in the first direction X.

[0137] In the second region AA2, since there is no need to compress the length of the pixel circuit 12 in the first direction X, the first reset transistor M5 and the second reset transistor M7 can be arranged along the first direction X so that their gates can share the same first scan signal line SL1, and their first poles can share the same reset signal line SL3; the data writing transistor M2 and the threshold compensation transistor M4 can be arranged adjacent to each other in the first direction X so that their gates can share the same second scan signal line SL2; the first light-emitting control transistor M1 and the second light-emitting control transistor M6 can be arranged adjacent to each other in the first direction X so that their gates can share the same light-emitting control signal line SL4. Thus, the number of signal lines in the second region AA2 can be reduced.

[0138] Optionally, in the first pixel circuit 121, it can be set as Figure 8 shown that D31 < D32. When used for a transparent display panel, in the first pixel circuit 121, a transmissive region TA can be formed in the first pixel circuit 121 by utilizing the relatively large distance D32 between the second reset transistor M7 and the driving transistor M3 in the second direction. Specifically, if D31 < D32, as Figure 8 shown, a relatively large distance can be made between the second reset transistor M7 located below the driving transistor M3 and the driving transistor M3, so that a transmissive region TA can be formed between the second reset transistor M7 of the first pixel circuit 121 and other parts of the first pixel circuit 121, which can be used to form a transparent display panel.

[0139] When used for a transparent display panel, each first pixel circuit 121 can be correspondingly provided with a transmissive region TA. Among the second reset transistors in the same first pixel circuit 121, based on the relatively large distance D32, a transmissive region TA can be formed in the first pixel circuit 121. As Figure 8 shown, the transmissive region TA in the first pixel circuit 121 is located inside the first pixel circuit 121. Specifically, for the transmissive region TA of a first pixel circuit 121, the data signal line SL5 of this pixel circuit 121 is on the left side of the transmissive region TA, the second connection part LJ2 is on the right side of the transmissive region TA, the upper end of the transmissive region TA reaches the second light-emitting control transistor M6 in this first pixel circuit 121, and the lower end of the transmissive region TA reaches the reset signal line SL3 of the next first pixel circuit 121 adjacent in the second direction. Among them, the second connection part LJ2 is the signal line connected to the second pole of the second reset transistor M7 in the first pixel circuit 121.

[0140] In Figure 8As shown, for two adjacent first pixel circuits 121 in the second direction Y, the second reset transistor M7 of the previous first pixel circuit 121 is set to extend downward to the circuit area of ​​the next first pixel circuit 121 based on the second connection part LJ2. Compared with the scheme where the second reset transistor M7 extends upward to the upper end of the first pixel circuit 121 based on the second connection part LJ2, the second connection part LJ2 can avoid increasing the length of the circuit area in the first direction X.

[0141] Optionally, in the second pixel circuit 122, it can be as follows: Figure 9 or Figure 11 As shown, D41=D42. This allows the two reset transistors in the second pixel circuit 122 to face each other along the first direction, reducing the length of the second pixel circuit 122 in the second direction Y. Since there is sufficient layout space in the second region AA2 to accommodate the second pixel circuit 122, there is no need to compress its length in the first direction X. The layout space in the first direction X can be fully utilized to accommodate the two reset transistors in the second pixel circuit 122. When used in a transparent display panel, reducing the length of the second pixel circuit 122 in the second direction Y allows the second pixel circuit 122 to have a larger transparent area.

[0142] In the first pixel circuit 121, the distance between the second reset transistor M7 and the driving transistor M3 in the second direction Y is D32; in the second pixel circuit 122, the distance between the second reset transistor M7 and the driving transistor M3 in the second direction is D42; where D32 > D42. This allows the second connection portion LJ2 in the first pixel circuit 121, which connects the second electrode of the second light-emitting control transistor M6 to the second electrode of the second reset transistor M7, to extend to the next first pixel circuit 121. This avoids the second connection line LJ2 occupying the wiring space between the first pixel circuits 121, which helps to reduce the distance between the first pixel circuits 121, allowing for a greater number of first pixel circuits 121 to be placed in the same row in the first region AA1.

[0143] Furthermore, in this embodiment, setting D32 > D42 allows the first pixel circuit 121 to have a larger distance between the second reset transistor M7 and the driving transistor M3, thereby enabling the transparent region TA to be laid out based on this distance, facilitating transparent display. Moreover, by increasing D32, the length of the first pixel circuit 121 in the second direction Y can be increased, while the length of the first pixel circuit 121 in the first direction X can be decreased.

[0144] As described above, the pixel circuit 12 also includes a second light-emitting control transistor M6, and the second electrode of the driving transistor M3 is connected to the light-emitting element 11 through the second light-emitting control transistor M6; Figure 8As shown, in the first pixel circuit 121, the second terminal of the second reset transistor M7 is connected to the second terminal of the second light-emitting control transistor M6 through the second connection portion LJ2; as Figure 9 or Figure 11 As shown, in the second pixel circuit 122, the second terminal of the second reset transistor M7 is connected to the second terminal of the second light-emitting control transistor M6 through the third connection part LJ3; the length of the second connection part LJ2 in the second direction Y is greater than the length of the third connection part LJ3 in the second direction Y.

[0145] The length of the second connecting portion LJ2 in the second direction Y is greater than the length of the third connecting portion LJ3 in the second direction Y. Along the second direction Y, the distance between the second light-emitting control transistor M6 and the second reset transistor M7 in the first pixel circuit 121 is larger, while the distance between the second light-emitting control transistor M6 and the second reset transistor M7 in the second pixel circuit 122 is smaller. This can be achieved by increasing the length of the first pixel circuit 121 in the second direction Y, thereby reducing its length in the first direction X. Simultaneously, the first pixel circuit 121 can also define the relative two-sided boundaries of the corresponding transmittance region TA in the first direction X based on the connected data line SL5 and the second connecting portion LJ2. In the second pixel circuit 122, all transistors are located on the same side of the corresponding transmittance region TA. Furthermore, the second connecting portion LJ2 in the first pixel circuit 121 extends to the next first pixel circuit 121, preventing the second connecting line LJ2 from occupying the wiring space between the first pixel circuits 121. This helps reduce the distance between the first pixel circuits 121, allowing for a larger number of first pixel circuits 121 to be arranged in the same row in the first region AA1.

[0146] Each pixel circuit 12 has a corresponding transparent area. The transparent area TA corresponding to the first pixel circuit 121 is located inside the first pixel circuit 121. Therefore, in the first region AA1, the transparent areas of each first pixel circuit 121 are isolated from each other based on the transistors and wiring in the first pixel circuit 121.

[0147] The system has multiple pixel units arranged sequentially along a first direction X. Each pixel unit includes multiple light-emitting elements 11 arranged sequentially along the first direction X. A pixel unit can be configured to include three light-emitting elements 11 of different colors, used to emit red, green, and blue light respectively. For the same pixel unit, the transmittance region TA corresponding to the connected second pixel circuit 122 is a single transparent area. The single transparent areas corresponding to different pixel units are isolated based on data lines and also based on the non-transparent area where the second pixel circuit 12 is located.

[0148] In one embodiment of this application, such as Figure 9As shown, in the second pixel circuit 122, the first terminal of the first reset transistor M5 can be connected to the first terminal of the second reset transistor M7 via the fourth connection portion SL4; the fourth connection portion SL4 is connected to the reset signal line SL3 via the first connection portion SL1. In this method, the second reset transistor M7 is first connected to the first terminal of the first reset transistor M5 via the fourth connection portion SL4, and then both reset transistors are simultaneously connected to the reset signal line SL3 via the first connection portion SL1. This eliminates the need for the two reset transistors M5 to be connected to the reset signal line SL3 separately, simplifying the wiring. In this method, the first reset transistor M5 and the second reset transistor M7 are arranged close to each other in the first direction X. When the first reset transistor M5 is connected to the reset signal line SL3 sequentially via the fourth connection portion SL3 and the first connection portion SL1, the second reset transistor M7 can reuse the via connected to the first reset transistor M5 to connect to the same reset signal line SL3. Specifically, in conjunction with... Figure 9 and Figure 10 As shown, the second reset transistor M7 can share the via Via1 connected to the upper end and the via Via2 connected to the lower end of the first connection part LJ1.

[0149] The active region of the transistor can be fabricated using a polysilicon layer, the gate of the transistor can be fabricated using a first metal layer located above the polysilicon layer, and the source and drain can be fabricated using a second metal layer located above the first metal layer.

[0150] Optionally, the fourth connector LJ4 can be fabricated from a polycrystalline silicon layer. The first connector LJ1 can be fabricated from a second metal layer.

[0151] In another embodiment, the second pixel circuit 122 can also be as follows: Figure 11 As shown, in the first direction X, two reset transistors are respectively located on both sides of the driving transistor M3, so that there is a large layout space between the driving transistor M3 and the first scan signal line SL1, so that the threshold compensation transistor M4 can be laid out. The third node N3 of the second pixel circuit 122 can be transferred from the polysilicon layer where the active region is located to the metal layer where the source and drain of the transistor are located, so as to reduce the impedance of the pixel circuit 12 at the third node N3, thereby reducing the voltage drop.

[0152] exist Figure 11 In the configuration shown, the first terminal of the second reset transistor M7 needs to be connected to the reset signal line SL3 through the fifth connection part LJ5, and the second terminal of the second reset transistor M7 is connected to the second terminal of the second light-emitting control transistor M6 through the sixth connection part LJ6.

[0153] Optionally, the fifth connector LJ5 can be made of the second metal layer, and the sixth connector LJ6 can be made of a polycrystalline silicon layer.

[0154] In the embodiments of this application, the light-emitting element 11 can be a micro LED, such as a Mini LED, Micro LED, or Nano LED. The embodiments of this application do not limit the type of light-emitting element 11.

[0155] In one embodiment of this application, the light-emitting element 11 includes a first light-emitting element and a second light-emitting element with different light-emitting colors; the wavelength of the light emitted by the first light-emitting element is greater than the wavelength of the light emitted by the second light-emitting element. Optionally, the first light-emitting element can be a light-emitting element 11 that emits red light, and the second light-emitting element can be a light-emitting element 11 that emits green light or blue light.

[0156] Generally, the luminous efficiency of the light-emitting element 11 is negatively correlated with its emission wavelength; the longer the emission wavelength, the lower the luminous efficiency. Therefore, the luminous efficiency of the first light-emitting element is less than that of the second light-emitting element. For example, the luminous efficiency of the light-emitting element 11 emitting red light is less than that of the light-emitting element 11 emitting green or blue light. The first light-emitting element is a red light-emitting element, and the second light-emitting element is a green or blue light-emitting element.

[0157] refer to Figure 12 and Figure 13 , Figure 12 The layout of the driving transistor in the pixel circuit connected to the first light-emitting element. Figure 13 This is a layout of the driving transistor in the pixel circuit connected to the second light-emitting element. As described above, the pixel circuit 12 includes a driving transistor M3; wherein, the channel width-to-length ratio of the driving transistor M3 in the pixel circuit 12 corresponding to the first light-emitting element is A1; the channel width-to-length ratio of the driving transistor M3 in the pixel circuit 12 corresponding to the second light-emitting element is A2; wherein, A1 > A2.

[0158] The luminous efficiency of a light-emitting element varies with the magnitude of the driving current, and the size of the driving circuit required for different colored light-emitting elements at their maximum luminous efficiency is different. In some embodiments, the driving circuit provided by the pixel circuit 12 to the red light-emitting element is I1, and the luminous efficiency of the red light-emitting element is at its maximum; the driving circuit provided by the pixel circuit 12 to the blue light-emitting element is I2, and the luminous efficiency of the blue light-emitting element is at its maximum; the driving circuit provided by the pixel circuit 12 to the green light-emitting element is I3, and the luminous efficiency of the green light-emitting element is at its maximum; wherein, I1>I2, and / or I1>I3. Driving a display panel using red, blue, and green light-emitting elements requires a larger driving current. That is, when the luminous efficiencies of the red, blue, and green light-emitting elements are all close to their maximum luminous efficiency, the driving current required for the red light-emitting element is greater than that required for the blue or green light-emitting element. The magnitude of the driving current is related to the width-to-length ratio of the driving transistor. In pixel circuit 12, the driving transistor M3 has a large width-to-length ratio, and the driving current provided by pixel circuit 12 is large.

[0159] As mentioned above, the luminous efficiency of light-emitting elements 11 with different luminous colors is different. Since the first and second light-emitting elements have different emission wavelengths, they correspond to different luminous colors and have different luminous efficiencies. If the same driving capability (such as driving current) is used, the luminous efficiency of the red, blue, and green light-emitting elements cannot simultaneously approach the highest luminous efficiency of the display, thus failing to reach their respective maximum luminous brightness, resulting in limited luminous brightness of the entire display panel. To solve this problem, in this embodiment, A1 > A2. This allows the driving transistor M3 in the pixel circuit 12 connected to the first light-emitting element (e.g., the red light-emitting element) to have a larger channel width-to-length ratio, improving the driving capability of the driving transistor M3 and resolving the image display quality problem caused by the different luminous efficiencies of the first and second light-emitting elements.

[0160] For a driving transistor M3 with multiple parallel sub-transistors, the extension direction of the gate g of each sub-transistor is the width direction of the channel, and the length of the overlap between the gate g and the active region a in this direction is the channel width K; the distance between the first electrode s and the second electrode d is the channel length L. Generally, the channel width K and channel length L of each sub-transistor are set to be the same. The channel width and length of the driving transistor M3 are equal to the ratio of the sum of the channel widths of all sub-transistors to L.

[0161] like Figure 12As shown, for the pixel circuit 12 connected to the first light-emitting element, the channel width of the first sub-transistor M31 and the second sub-transistor M32 in the driving transistor M3 is set to K1, and the channel length of the first sub-transistor M31 and the second sub-transistor M32 is set to L1. Then the channel width-to-length ratio of the driving transistor M3 is A1 = 2·K1 / L1.

[0162] like Figure 13 As shown, for the pixel circuit 12 connected to the second light-emitting element, the channel width of the first sub-transistor M31 and the second sub-transistor M32 in the driving transistor M3 is set to K2, and the channel length of the first sub-transistor M31 and the second sub-transistor M32 is set to L2. Then the channel width-to-length ratio of the driving transistor M3 is A2 = 2·K2 / L2.

[0163] In the first pixel circuit 121, since the driving transistor M3 is a multi-subtransistor parallel structure, the other transistors are relatively short in length relative to the driving transistor M3 in the first direction X. Therefore, when used in a transparent display panel, in the first pixel circuit 121, if the channel width K of the transistors other than the driving transistor M3 is greater than the channel length L, the channel width K is set to be a dimension along the first direction X; conversely, if the channel width K is less than the channel length L, the channel width is set along the second direction X to reduce the length of the transistors in the second direction Y, thereby increasing the area of ​​the transmittance region TA in the first pixel circuit 121 and improving light transmission performance.

[0164] In one embodiment of this application, the channel width-to-length ratio of the driving transistor M3 in the first pixel circuit 121 corresponding to the first light-emitting element can be set to be equal to the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the first light-emitting element. At this time, regardless of whether the first light-emitting element is in the first region AA1 or the second region AA2, the driving transistor M3 in the pixel circuit 12 connected to the first light-emitting element has the same channel width-to-length ratio.

[0165] In one embodiment of this application, the channel width-to-length ratio of the driving transistor in the first pixel circuit 121 corresponding to the second light-emitting element can be set to be equal to the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the second light-emitting element. In this case, regardless of whether the first light-emitting element is located in the first region AA1 or the second region AA2, the driving transistor M3 in the pixel circuit 12 connected to the second light-emitting element has the same channel width-to-length ratio.

[0166] In one embodiment of this application, the channel width-to-length ratio of the driving transistor M3 in the first pixel circuit 121 corresponding to the first light-emitting element can be set to be equal to the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the first light-emitting element, and the channel width-to-length ratio of the driving transistor in the first pixel circuit 121 corresponding to the second light-emitting element can be equal to the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the second light-emitting element. In this way, in the pixel circuits 12 connected to the light-emitting elements 11 of the same emission color, the first pixel circuit 121 and the second pixel circuit 122 have driving transistors M3 with the same channel width-to-length ratio, which facilitates the parameter design and fabrication of the driving transistors M3 in the pixel circuits 12 connected to the same emission color.

[0167] In other methods, the channel width-to-length ratio of thin-film transistors with the same function in any two pixel circuits 12 can be set to be the same to facilitate the fabrication process of the pixel circuits in the display panel. For example, if the driving transistor M3 includes two sub-transistors, and the two sub-transistors of the driving transistor M3 in the pixel circuit 12 connected to the first light-emitting element are set to TFT1 and TFT2 respectively, and the two sub-transistors of the driving transistor M3 in the pixel circuit 12 connected to the second light-emitting element are set to TFT11 and TFT21 respectively, then the channel width-to-length ratio of TFT1 and TFT11 can be set to be the same, and the channel width-to-length ratio of TFT2 and TFT21 can be set to be the same; if the first light-emitting control transistor M1 includes two sub-transistors, and the two sub-transistors of the first light-emitting control transistor M1 in the pixel circuit 12 connected to the first light-emitting element are set to TFT3 and TFT4 respectively, then the channel width-to-length ratio of TFT1 and TFT21 can be set to be the same. FT4, in the pixel circuit 12 connecting the second light-emitting element, the two sub-transistors of the first light-emitting control transistor M1 are TFT31 and TFT41 respectively. Then, the channel width-to-length ratio of TFT3 and TFT31 can be set to be the same, and the channel width-to-length ratio of TFT4 and TFT41 can be set to be the same. If the second light-emitting control transistor M6 is a single transistor, and the single transistor of the second light-emitting control transistor M6 in the pixel circuit 12 connecting the first light-emitting element is set to be TFT5, and the single transistor of the second light-emitting control transistor M6 in the pixel circuit 12 connecting the second light-emitting element is set to be TFT51, then the channel width-to-length ratio of TFT5 and TFT51 can be set to be the same.

[0168] If the channel width-to-length ratios of the thin-film transistors with the same function in the two pixel circuits 12 are the same, including: the channel width-to-length ratios of the first light-emitting control transistor M1 in the two pixel circuits are the same; the channel width-to-length ratios of the data writing transistor M2 are the same; the channel width-to-length ratios of the driving transistor M3 are the same; the channel width-to-length ratios of the threshold compensation transistor M4 are the same; the channel width-to-length ratios of the first reset transistor M5 are the same; the channel width-to-length ratios of the second light-emitting control transistor M6 are the same; and the channel width-to-length ratios of the second reset transistor M7 are the same.

[0169] In one embodiment of this application, the channel width-to-length ratio of the driving transistor M3 in the first pixel circuit 121 corresponding to the first light-emitting element can be set to be different from the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the first light-emitting element; and / or, the channel width-to-length ratio of the driving transistor in the first pixel circuit 121 corresponding to the second light-emitting element can be different from the channel width-to-length ratio of the driving transistor M3 in the second pixel circuit 122 corresponding to the second light-emitting element. Thus, in the pixel circuits 12 connected to the light-emitting elements 11 of the same color, since the channel width-to-length ratios of the driving transistor M3 in the first pixel circuit 121 and the second pixel circuit 122 are different, the channel width-to-length ratios of the driving transistor M3 in the first pixel circuit 121 and the second pixel circuit 122 can be differentiated so that the length of the driving transistor M3 in the first pixel circuit 121 in the first direction X is less than its length in the second direction Y, thereby reducing the length of the first pixel circuit 121 in the first direction X and making the length of the driving transistor M3 in the second pixel circuit 122 in the first direction X greater than its length in the second direction Y.

[0170] refer to Figure 14 and Figure 15 , Figure 14 This application provides a layout of pixel circuitry in a display panel. Figure 15 for Figure 14 The layout of the polysilicon layer containing the active regions of the transistors corresponding to two adjacent first pixel circuits and two adjacent second pixel circuits in the same row.

[0171] like Figure 14 and Figure 15 As shown, in one embodiment of this application, the distance H1 between two adjacent first pixel circuits 121 in the first direction X is set to be less than the distance H2 between two adjacent second pixel circuits 122 in the first direction X.

[0172] exist Figure 14 and Figure 15In the first direction X, the distance between two pixel circuits 12 is represented by the spacing between the active regions of two adjacent transistors in two adjacent pixel circuits 12. As shown in 14, in the first direction X, the distance H1 between two adjacent first pixel circuits 121 is the spacing between the active region of the driving transistor M3 in the left first pixel circuit 121 and the active region of the data writing transistor M2 in the right first pixel circuit 121; the distance H3 between two adjacent first pixel circuits 121 and second pixel circuits 122 is the spacing between the active region of the driving transistor M3 in the first pixel circuit 121 and the active region of the second light-emitting control transistor M6 in the second pixel circuit 122; the distance H2 between two adjacent second pixel circuits 122 is the spacing between the active region of the data writing transistor M2 in the left second pixel circuit 122 and the active region of the second light-emitting control transistor M6.

[0173] exist Figure 14 and Figure 15 In the illustrated configuration, setting H1 < H2 allows the pixel circuits 12 in the first region AA1 to have a smaller spacing, which facilitates the layout of more first pixel circuits 121 and also reduces the length compression of the first pixel circuits 121 in the first direction X.

[0174] Optionally, in the first region AA1, the distance H1 between the first pixel circuits 121 can gradually increase along the first direction X. In the second region AA2, the distance H2 between the second pixel circuits 122 can gradually decrease along the first direction X. If used in a transparent display panel, the gradual setting of H1 and H2 can ensure that the length of the transparent area TA in the first region AA1 and the second region AA2 gradually changes along the first direction X, so as to realize the gradual distribution of different transparent areas TA in the transparent display panel, thereby reducing the large difference in the length of the transparent areas TA along the first direction X and preventing the problem of uneven transparent display caused by the large difference in the length of the transparent areas TA along the first direction X.

[0175] In this embodiment of the application, the first pixel circuit 121 can be configured as follows: Figure 14 As shown, the data line SL5 and the first pixel circuit 121 connected to it are arranged sequentially in the first direction X.

[0176] In the second region AA2, it is possible to... Figure 14As shown, for three second pixel circuits 122 consecutively arranged in the first direction X within the same pixel area, the data line SL5 connected to the second pixel circuit 122 closest to the first region AA1 is located on the side of the second pixel circuit 122 facing the first region AA1; the data lines SL5 connected to the other two second pixel circuits 122 are located on the side of the pixel area away from the first region AA1. The data lines SL5 connected to these two second pixel circuits 122 are connected to the corresponding data write transistor M2 based on the connecting line LJ7 extending along the first direction X. This method allows the data lines SL5 connected to multiple second pixel circuits 122 in the same pixel area to be arranged in two parts on both sides of the pixel area in the first direction X, preventing the problem of a wide wiring light-shielding area caused by the data lines SL5 being on the same side of the pixel area.

[0177] refer to Figure 16 , Figure 16 This is a schematic diagram illustrating the layout of pixel circuits and driving circuits in a display panel according to an embodiment of this application. Figure 15 and Figure 16 As shown, if H1 is less than H2, the first shift register 1311 can be set to be located on the side of the first pixel circuit 121 away from the second pixel circuit 122. This allows the pixel circuit 12 in the third region AA3 to be used as the first pixel circuit 121 and directly formed in the first region AA1. Only the circuit layout in the adjacent first region AA1 and third region AA3 needs to be changed, simplifying the circuit layout design.

[0178] This method places the first shift register 1311 on the side of the first pixel circuit 121 away from the second pixel circuit 122, avoiding the insertion of the first shift register 1311 between the first pixel circuits 121 and increasing the distance H1 between them, so as to satisfy H1 < H2. Furthermore, as described above, the first driving circuit 131 can be located in the third region AA3, which does not overlap with the second region AA2, thus allowing the first driving circuit 131 and the first pixel circuit 121 to be formed in different sub-display areas of the display area. Moreover, if the first shift register 1311 is located on the side of the first pixel circuit 121 away from the second pixel circuit 122, the third region AA3 can be located on the side of the first region AA1 away from the second region AA2. Compared to placing the first shift register 1311 between the first pixel circuit 121 and the second pixel circuit 122, the distance H3 between the first pixel circuit 121 and the adjacent second pixel circuit 122 can be reduced to a greater extent.

[0179] In one embodiment of the application, if H1 < H2, further, the distance H2 between two adjacent second pixel circuits 122 in the first direction X can be set to be greater than the distance H3 between the second pixel circuit 122 and its adjacent first pixel circuit 121. In this case, H1 < H2 and H2 > H3. Based on this method, H1, H3, and H2 can be further set to increase sequentially in the first direction X. When used for transparent display, the length of the transparent area in the first direction X can gradually change, so that the length of the transparent area TA in the first direction X transitions evenly, thereby achieving a more uniform transparent display effect.

[0180] In this embodiment of the application, if H1 < H2, further, the distance H1 between two adjacent first pixel circuits 121 in the first direction X can be set to be less than the distance H3 between the first pixel circuit 121 and the adjacent second pixel circuit 122. In this case, H1 < H2 and H1 < H3.

[0181] refer to Figure 17 , Figure 17 This is a schematic diagram of the layout of pixel circuits and driving circuits in a display panel according to an embodiment of this application. In this layout, the first shift register 1311 is located on the side of the first pixel circuit 121 closer to the second pixel circuit 122. This layout places the first driving circuit 131 between the first region AA1 and the second region AA2, enabling the first driving circuit 131 to provide control signals to both the first pixel circuit 121 and the second pixel circuit 122 respectively. This reduces the voltage drop of the control signal when the first driving circuit 131 provides control signals to the same row of pixel circuits 12, thereby reducing the load difference in the first direction X caused by the length of the control signal line.

[0182] Since the number of transistors in the first shift register 1311 is greater than the number of transistors in the pixel circuit 12, if used in a transparent display panel, the area of ​​the transparent region of the driving circuit 12, the first pixel circuit 121, and the second pixel circuit 122 decreases sequentially. Based on Figure 17 As shown, when used in a transparent display panel, the third region AA3 is located between the first region AA1 and the second region AA2. In this way, when multiple transparent display panels are spliced ​​together to form a large-size transparent display device, the low transmittance at the splicing edges can be avoided.

[0183] As described above, the first determining circuit 131 is located in the third region AA3, the first pixel circuit 121 is located in the first region AA1, and the second pixel circuit 122 is located in the second region AA2. Setting the first shift register 1311 to be located on the side of the first pixel circuit 121 close to the second pixel circuit 122 can make the third region AA3 located between the first region AA1 and the second region AA2.

[0184] exist Figure 17 In the illustrated configuration, the distance between two adjacent second pixel circuits 122 in the first direction X is less than the distance between the second pixel circuit 122 and its adjacent first pixel circuit 121, i.e., H2 < H3. This configuration is suitable for placing the third region AA3 between the first region AA1 and the second region AA2. Based on the larger size H3, a first shift register 1311 with a larger length in the first direction X can be set, which facilitates the placement of the third region AA3 between the first region AA1 and the second region AA2, and facilitates the layout of the first driving circuit 131 between the first region AA1 and the second region AA2.

[0185] refer to Figure 18 and Figure 19 , Figure 18 This application provides a layout of a first shift register in a display panel according to an embodiment of the present application. Figure 19 for Figure 18 The circuit diagram of the first shift register is shown. The length of the first shift register 1311 in the second direction Y is greater than the length of the first shift register 1311 in the first direction X.

[0186] exist Figure 18 and Figure 19 In the illustrated configuration, by increasing the length of the first shift register 1311 in the second direction Y, the length of the first shift register 1311 in the first direction X can be compressed. When the first driving circuit 131 is placed in the display area, the layout space of the first shift register 1311 in the first direction X can be reduced.

[0187] The first shift register 1311 includes sixteen transistors and three capacitors. The sixteen transistors are transistors Q1 to Q16, and the three capacitors are capacitors C1 to C3.

[0188] The first shift register 1311 includes a first output module 141, which includes a first output transistor and a second output transistor. A ninth transistor Q9 serves as the first output transistor, and a tenth transistor Q10 serves as the second output transistor. The first output module 141 is responsive to a gate access signal, causing the first output transistor Q9 and the second output transistor Q10 to be turned on in a time-division multiplexing manner, so as to output a high level VGH and a low level VGL sequentially through the output terminal EOUT.

[0189] In the first shift register 1311, the first transistor Q1 has its first terminal connected to the signal STVE, its second terminal connected to node a4, and its gate connected to the clock signal CKE. The thirteenth transistor Q13 has its first terminal connected to the signal STVE, its second terminal connected to node a7, and its gate connected to the clock signal CKE. The second transistor Q2 has its first terminal connected to a low level VGL, its second terminal connected to node a3, and its gate connected to the clock signal CKE. The third transistor Q3 has its first terminal connected to node a3, its second terminal connected to the clock signal CKE, and its gate connected to node a4. The third transistor Q3 can be a dual-gate transistor. The fifth transistor Q5 has its first terminal connected to a high level VGH, its second terminal connected to node a6, and its gate connected to node a3. The sixteenth transistor Q16 has its first terminal connected to node a4, its second terminal connected to a high level VGH, and its gate connected to the signal RST. The twelfth transistor Q12 has its first terminal connected to node a3, its second terminal connected to node a5 via the third capacitor C3, and its gate connected to a low level VGL. The sixth transistor Q6 has its first terminal connected to node a5, its second terminal connected to the clock signal XCKE, and its gate connected to the second terminal of the twelfth transistor Q12. The seventh transistor Q7 has its first terminal connected to node a5, its second terminal connected to node a1, and its gate connected to the clock signal XCKE. The eighth transistor Q8 has its first terminal connected to node a1, its second terminal connected to a high level VGH, and its gate connected to node a4. The ninth transistor Q9 has its first terminal connected to a high level VGH, its second terminal connected to the output terminal OUT, and its gate connected to node a1. The gate of the ninth transistor Q9 is connected to its first terminal via a first capacitor C1. The eleventh transistor Q11 has its first terminal connected to node a4, its second terminal connected to node a2, and its gate connected to a low level VGL. The fourth transistor Q4 has its first terminal connected to the clock signal XCKE, its second terminal connected to node a6, and its gate connected to node a8 via a second capacitor C2. The fourteenth transistor Q14 has its first terminal connected to node a7, its second terminal connected to node a8, and its gate connected to a low level VGL. The fifteenth transistor Q15 has both its first terminal and gate connected to node a8, and its second terminal connected to the second terminal of the tenth transistor Q10. The gate of the tenth transistor Q10 is connected to node a2, and its first terminal is connected to the output terminal OUT.

[0190] refer to Figure 20 , Figure 20 The layout of the first output transistor in the first shift register is shown below. The channel length direction of the first output transistor Q9 is parallel to the first direction X, and the channel width direction of the first output transistor Q9 is parallel to the second direction Y.

[0191] refer to Figure 21 , Figure 21 The layout of the second output transistor in the first shift register is shown. The channel length direction of the second output transistor is parallel to the first direction X, and the channel width direction of the second output transistor Q10 is parallel to the second direction Y.

[0192] Both the first output transistor Q9 and the second output transistor Q10 have multiple parallel sub-transistors to increase their driving capability. As described above, in the same transistor, the gates g of each sub-transistor are connected, the first terminals s of each sub-transistor are connected, and the second terminals d of each sub-transistor are connected. Here, L3 represents the channel length of the sub-transistor in the first output transistor Q9, and K3 represents the channel width of the sub-transistor in the first output transistor Q9; L4 represents the channel length of the sub-transistor in the second output transistor Q10, and K4 represents the channel width of the sub-transistor in the second output transistor Q10.

[0193] In this embodiment, the channel length direction of the first output transistor Q9 may be parallel to the first direction X, and the channel width direction of the first output transistor Q9 may be parallel to the second direction Y; or, the channel length direction of the second output transistor may be parallel to the first direction X, and the channel width direction of the second output transistor Q10 may be parallel to the second direction Y; or, the channel length direction of the first output transistor Q9 may be parallel to the first direction X, the channel width direction of the first output transistor Q9 may be parallel to the second direction Y, and the channel width direction of the second output transistor Q10 may be parallel to the second direction Y.

[0194] based on Figure 20 and Figure 21 As shown, in the first shift register 1311, the channel length direction of at least one output transistor is set to be parallel to the first direction X, and the channel width direction is set to be parallel to the second direction Y. This can reduce the length of the output transistor in the first direction X, thereby reducing the length of the first shift register 1311 in the first direction X.

[0195] like Figure 18 and Figure 19 As shown, along the second direction Y, the first switch module 142 is located between the first output transistor Q9 and the second output transistor Q10. In this configuration, all other transistors of the first shift register 1311 can be placed between the first output transistor Q9 and the second output transistor Q10, so that the length of the first shift register 1311 in the first direction X is less than its length in the second direction Y, thereby reducing the layout space of the first shift register 1311 in the first direction X. The other transistors in the first shift register 1311 besides the first output transistor Q9 and the second output transistor Q10 are as follows: Figure 19The connection is configured as the first switch module 142. Furthermore, since this method reduces the length of the first drive circuit 131 in the first direction X, it reduces the number of first pixel circuits 121 that require shorter lengths in the first direction X. This helps reduce the number of connecting lines between the light-emitting element 11 in the third region AA3 and the first pixel circuit 121 in the first region AA1, thereby saving wiring space. When used in a transparent display panel, it can increase the area of ​​the transparent region TA, thus improving the transparent display effect.

[0196] Optionally, the first driving circuit 131 provides a light-emitting control signal EMIT to the light-emitting control transistor of the pixel circuit 12. In this way, by setting the first shift register 1311 in the first driving circuit 131, which is at least used to provide the light-emitting control signal EMIT to the pixel circuit 12, in the display area of ​​the display panel, the border area of ​​the display panel used for arranging the first shift register 13111 can be saved.

[0197] refer to Figures 22-24 , Figure 22 This is a schematic diagram showing the cascaded relationship of the second shift register in the second driving circuit. Figure 23 This application provides a layout of a second shift register according to an embodiment of the present application. Figure 24 The circuit diagram for the second shift register is shown below. Based on any of the above embodiments, the driving circuit 13 further includes a second driving circuit 132, which includes a plurality of second shift registers 1321 cascaded along the second direction Y.

[0198] contrast Figure 18 and Figure 23 As shown, in this application implementation, the length D72 of the first shift register 1311 in the second direction Y is set to be greater than the length D82 of the second shift register 1321 in the second direction Y, and / or, the length D71 of the first shift register 1311 in the first direction X is less than the length D81 of the second shift register 1321 in the first direction.

[0199] When D72 > D82 and / or D71 < D81, relative to the second shift register 1321, the first shift register 1311 can have a larger length in the second direction Y and a smaller length in the first direction X. The length of the first shift register 1311 in the first direction X can be reduced by increasing the length D72 of the first shift register 1311 in the second direction Y. By sacrificing the layout in the second direction Y, the layout space of the first driving circuit 131 in the second first direction X can be reduced, thereby reducing the relative bezel width of the display panel in the first direction.

[0200] like Figure 22As shown, the second driving circuit 132 has N second shift registers 1321 cascaded sequentially in the second direction Y, where N is a positive integer greater than 1. Along the second direction Y, these N second shift registers 1321 are SVSR1, SVSR2, SVSR3, ..., SVSR... N The output signals of the N second shift registers 1321 are SOUT1, SOUT2, SOUT3, ... SOUT1, respectively. N The N second shift registers 1321 are arranged sequentially along the second direction Y. The output of the previous second shift register 1321 serves as the input of the adjacent second shift register 1321, thereby realizing the sequential cascading of the various second shift registers 1321. Optionally, the output signal SOUT of each stage of the second shift register 1321 can be used as the first scan signal S1 or the second scan signal S2 of the pixel circuit 12.

[0201] For ease of illustration Figure 22 Only one column of pixel circuit 12 is shown. In the second driving circuit 1321, the output signal SOUT1 of the first-stage second shift register SVSR1 serves as the first scan signal S1 of the first row of pixel circuits. The j-th stage second shift register SVSR j Output signal SOUT j The first scan signal S1 of the j-th row pixel circuit and the first scan signal S2 of the (j-1)-th row pixel circuit 12 are used. Here, j is a positive integer greater than 1 and not greater than N.

[0202] exist Figure 22 In the illustrated configuration, each row of pixel circuits 12 corresponds to a first-level second shift register 1321. Each second-level second shift register 1321 is used to provide a first scan signal for each row of pixel circuits 12, which is a one-to-one driving mode. In other configurations, each second-level second shift register 1321 can also be configured to correspond to multiple rows of pixel circuits 12, so as to provide first scan signals for multiple rows of pixel circuits 12 simultaneously, thereby realizing a one-to-many driving mode.

[0203] like Figure 24 As shown, the second shift register 1321 includes 8 transistors and 2 capacitors. The 8 transistors are, in order, the seventeenth transistor m1 to the twenty-fourth transistor m8, and the 2 capacitors are, in order, the fourth capacitor C4 and the fifth capacitor C5.

[0204] The seventeenth transistor m1 has its first terminal connected to the STVS signal, its second terminal connected to node b1, and its gate connected to the clock signal CKS. Transistor m1 can be a dual-gate transistor. The eighteenth transistor m2 has its first terminal connected to node b3, its second terminal connected to the clock signal CKS, and its gate connected to node b1. The nineteenth transistor m3 has its first terminal connected to a low level VGL, its second terminal connected to node b3, and its gate connected to the clock signal CKS. The twenty-first transistor m5 has its first terminal connected to a high level VGH, its gate connected to node b3, and its second terminal connected to the first terminal of the twentieth transistor m4. The gate of the twentieth transistor m4 is connected to the clock signal XCKS, and its second terminal connected to node b1. The twenty-second transistor m6 has its first terminal connected to node b1, its second terminal connected to node b2, and its gate connected to a low level VGL. The gate of the twenty-third transistor m7 is connected to node b3 and to its first terminal via capacitor C4, and its first terminal is connected to a high level VGH. Its second terminal is connected to the output terminal SOUT. The gate of the twenty-fourth transistor m8 is connected to node b2 and to its first terminal via capacitor C5. Its first terminal is connected to the output terminal SOUT, and its second terminal is connected to the clock signal XCKS.

[0205] The second shift register 1321 includes a second output module 151, which includes a twenty-third transistor m7 and a twenty-fourth transistor m8 for signal output. The second output module 151 is able to respond to the control of the gate access signal, causing the twenty-third transistor m7 and the twenty-fourth transistor m8 to be turned on in a time-division multiplexing manner, so as to output a high level VGH and a low level VGL through the output terminal SOUT in a timing sequence.

[0206] Optionally, in the second shift register 1321, both the twenty-third transistor m7 and the twenty-fourth transistor m8 have multiple parallel sub-transistors Q' to increase the driving capability of transistors m7 and m8.

[0207] In the second shift register 1321, the gate g of the sub-transistor Q' extends along the first direction X. Therefore, the channel length direction of the sub-transistor Q' is parallel to the second direction Y, and the channel width direction is parallel to the first direction X. This arrangement allows the length of the second shift register 1321 in the first direction X to be greater than its length in the second direction X. While ensuring that the second shift register 1321 has a smaller length in the second direction Y, it also ensures that the output transistor in the second shift register 1321 has a larger channel width-to-length ratio, thereby guaranteeing the driving capability of the second shift register 1321.

[0208] In this embodiment, the channel length direction of the 23rd transistor m7 can be set to be parallel to the second direction Y, and the channel width direction of the 23rd transistor m7 can be set to be parallel to the first direction X, so as to reduce the length of the 23rd transistor m7 in the second direction Y, and / or the channel length direction of the 24th transistor m8 can be set to be parallel to the second direction Y, and the channel width direction of the 24th transistor m8 can be set to be parallel to the first direction X, so as to reduce the length of the 24th transistor m8 in the second direction Y, thereby reducing the length of the second shift register 1321 in the second direction Y.

[0209] The second shift register 1321 also includes a second switching module 152, wherein the second switching module 152, the twenty-third transistor m7, and the twenty-fourth transistor m8 are arranged sequentially along the first direction X. Other transistors in the second shift register 1321 besides the twenty-third transistor m7 and the twenty-fourth transistor m8 include... Figure 24 The connection is for the second switch module 152.

[0210] The second switch module 152, the twenty-third transistor m7, and the twenty-fourth transistor m8 are arranged sequentially along the first direction X to reduce the length of the second shift register 1321 in the second direction Y. This arrangement allows the length of the second shift register 1321 in the first direction X to be greater than its length in the second direction X, while also ensuring a smaller length in the second direction Y. As mentioned above, the second shift register 1321 can be used to provide the pixel circuit 12 with either the first scan signal S1 or the second scan signal S2. In this case, one second shift register 1321 needs to be connected to a corresponding row of pixel circuits 12. Since the second shift register 1321 contains a large number of transistors, its length in the first direction X needs to be increased to reduce the layout space in the second direction Y. This is necessary for transparent displays to ensure the area of ​​the transparent region TA corresponding to the second shift register 1321, thereby improving the transparent display effect.

[0211] refer to Figure 25 , Figure 25 This application provides a schematic diagram of the layout of the anode connection line of a light-emitting element in a display panel. The display panel includes a first pixel column 161, a second pixel column 162, and a first circuit column 163 arranged sequentially along a first direction X. The first pixel column 161 includes pixels 17 arranged along a second direction Y, the second pixel column 162 includes pixels 17 arranged along a second direction Y, and the first circuit column 163 includes a pixel circuit group 18 arranged along a second direction Y. The display panel also includes a first anode connection line 19, which connects the pixel circuit 12 of the pixel 17 in the first pixel column 161 to the pixel circuit group 18 in the first circuit column 161. The first anode connection line 19 overlaps with the second pixel column 162.

[0212] exist Figure 25 In the illustrated configuration, the pixel 17 in the first pixel column 161 can be connected to the pixel circuit 12 in the first circuit column 163 via the corresponding first anode connection line 19, thereby freeing up layout space for the first driving circuit 131 in the first pixel column 161.

[0213] Pixel 17 includes a plurality of light-emitting elements 11 arranged sequentially along the first direction X. The light-emitting elements 11 in the first pixel column 161 and the second pixel column 162 are all connected to the pixel circuits 12 in the first circuit column 163 based on the corresponding first anode connection lines 19.

[0214] The first pixel column 161 and the second pixel column 162 are located in the third region AA3, and the first circuit column 163 is located in the first region AA1. The pixel circuit 12 in the first circuit column 163 is the first pixel circuit 121. The pixel circuit group 18 includes a plurality of first pixel circuits 121 arranged sequentially along the first direction X.

[0215] The display panel includes multiple arrayed pixels 17. Each pixel 17 includes three light-emitting elements 11 of different colors arranged sequentially in the first direction X. These three light-emitting elements 11 can be red light-emitting element R, green light-emitting element G, and blue light-emitting element B, respectively. Each light-emitting element 11 is connected to a pixel circuit 12.

[0216] In the first direction X, for pixels 17 in the same row, let the third region AA3 have d columns of pixels 17 and the first region AA1 have c pixels 17. If the pixel circuits 12 connected to the d pixels 17 in the third region AA3 are all arranged as first pixel circuits 121 in the first region AA1, then the length of the first pixel circuits 121 in the first region AA1 in the first direction X is no greater than P1, where P1 must satisfy:

[0217]

[0218] In this context, the center-to-center distance between two adjacent pixels 17 in the first direction X of P0 is the pixel pitch. In the second region AA2, each pixel 17 in the first direction X only needs to set the three second pixel circuits 122 required by its own three light-emitting elements 11. Therefore, the length of the second pixel circuit 122 in the first direction X is no more than one-third of P0.

[0219] If c=d=3, then P1=3·P0 / 18=P0 / 6.

[0220] refer to Figure 26 and Figure 27 , Figure 26 This is a cross-sectional view of a display panel provided in an embodiment of this application. Figure 27 This is a top view of the circuit and light-emitting element layout in a display panel according to an embodiment of this application. Based on any of the above embodiments, the display panel further includes: a substrate 20, with a driving circuit 13 and a pixel circuit 12 located on one side of the substrate 20; in a direction perpendicular to the plane of the substrate 20, a first shift register 1311 at least partially overlaps with the light-emitting element 11. The second trace SL6 consists of signal lines extending along the second direction Y connected to the first shift register 1311.

[0221] The direction perpendicular to the plane containing the substrate 20 is defined as the third direction Z, which is perpendicular to the first direction X and the second direction Y. Figure 26 and Figure 27 In the illustrated configuration, the first shift register 1311 and the light-emitting element 11 at least partially overlap in the third direction Z. In the XY plane, the space above the area where the first shift register 1311 is located can be used to arrange the light-emitting element 11, saving layout space for the light-emitting element 11 in the XY plane. Furthermore, when used in a transparent display panel, this configuration allows the light-emitting element 11 to be arranged in the non-transparent area above the area where the first shift register 1311 is located, thus avoiding the light-emitting element 11 affecting the area of ​​the transparent area.

[0222] Optionally, in the third direction Z, the vertical projection of the light-emitting element 11 into the circuit area where the first shift register 1311 is located can be completely located within the circuit area, or it can be partially located within the circuit area.

[0223] Based on any of the above embodiments, in the second direction Y, the length of the first pixel circuit 121 can be further set to be greater than the length of the second pixel circuit 122. This method increases the length of the first pixel circuit 121 in the second direction Y, utilizing the layout space in the second direction Y to reduce the length of the first pixel circuit 121 in the first direction X. This allows for the placement of a larger number of first pixel circuits 121 in the first region AA1, enabling the pixel circuit 12 connected to the light-emitting element 11 in the third region AA3 to be placed as the first pixel circuit 121 in the first region AA1. This also allows the first driving circuit 131 to be placed in the third region AA1, reducing the width of the border area opposite the display area in the first direction X.

[0224] The length of the pixel circuit 12 in the first direction X can be the length occupied by the active regions of all transistors in the pixel circuit 12 in the first direction X. The length of the pixel circuit 12 in the second direction Y can be the length occupied by the active regions of all transistors in the pixel circuit 12 in the second direction Y.

[0225] For the first pixel circuit 121, if the following is adopted Figure 8In the layout shown, the length of the first pixel circuit 121 in the first direction X can be characterized by the distance between the left boundary of the active region of the data writing transistor M2 and the right boundary of the active region of the driving transistor M7; the length of the first pixel circuit 121 in the second direction Y can be characterized by the distance between the upper end of the active region of the first reset transistor M5 and the lower end of the active region of the second reset transistor M7.

[0226] For the second pixel circuit 122, if using Figure 9 or Figure 11 As shown in the diagram, the length of the second pixel circuit 122 in the first direction X can be characterized by the distance between the left boundary of the active area of ​​the second light-emitting control transistor M6 and the right boundary of the active area of ​​the data writing transistor M2; the length of the second pixel circuit 122 in the second direction Y can be characterized by the distance between the upper end of the active area of ​​the first reset transistor M5 (or the second reset transistor M7) and the lower end of the active area of ​​the second light-emitting control transistor M6 (or the first light-emitting control transistor M1).

[0227] refer to Figure 28 , Figure 28 This application provides a top view of the display area of ​​a display panel, based on any of the above embodiments, and in conjunction with the accompanying drawings of the above embodiments. Figure 28 As shown, the display panel includes a pixel area PA, which includes a circuit area CA and a transparent area TA. The driving circuit 13, the pixel circuit 12, and the light-emitting element 11 are located in the circuit area CA. At least part of the transparent area TA is located between two adjacent circuit areas CA in the second direction Y.

[0228] exist Figure 28 In the illustrated method, a circuit area CA and a transparent area TA are set in the pixel area PA of the display area. The light-emitting element 11, pixel circuit 12, and driving circuit 13 are arranged in the circuit area CA, and transparent display can be achieved through the transparent area TA. This method can not only realize a transparent display panel, but also reduce the bezel width, realizing a narrow bezel or even a bezel-less design.

[0229] Optionally, each pixel region PA can correspond to a pixel 17, and different pixels 17 are located in different pixel regions PA.

[0230] refer to Figure 29 , Figure 29 This application provides another top view of the display area of ​​a display panel, based on any of the above embodiments, and in conjunction with the accompanying drawings of the above embodiments. Figure 29As shown, the transmission area TA of pixel area PA in the first region AA1 is set as the first transmission area TA1; the transmission area TA of pixel area PA in the second region AA2 is set as the second transmission area TA2; and the transmission area TA of pixel area PA in the third region AA3 is set as the third transmission area TA3.

[0231] In the first region AA1, for the same pixel region PA, the pixel region PA can be configured to have multiple separate first transmittance regions TA1 and an integrated circuit region CA. Each first pixel circuit 121 corresponds to one first transmittance region TA1, and the various first transmittance regions TA1 are isolated from each other based on the transistors or signal lines in the pixel circuit 12. In the second region AA2, for the same pixel region PA, the pixel region PA can be configured to have an integrated second transmittance region TA2 and an integrated circuit region CA. Each second pixel circuit 122 corresponds to the same second transmittance region TA2. In the third region AA3, for the same pixel region PA, the pixel region PA can be configured to have an integrated third transmittance region TA3 and an integrated circuit region CA.

[0232] Optionally, the transmittance zones TA in different regions are set to satisfy at least one of the following conditions: the area of ​​the first transmittance zone TA1 is smaller than the area of ​​the second transmittance zone TA2; the area of ​​the third transmittance zone TA3 is smaller than the area of ​​the second transmittance zone TA2; and the area of ​​the first transmittance zone TA1 is smaller than the area of ​​the third transmittance zone TA3.

[0233] For a display panel with a fixed size and resolution, the area of ​​the pixel area PA is a fixed constant. By setting the area of ​​the first light-transmitting area TA1 to be smaller than the area of ​​the second light-transmitting area TA2, the area of ​​the light-transmitting area TA in the first region AA1 can be reduced, thereby increasing the area of ​​the circuit area CA in the first region AA1. This allows more first pixel circuits 121 to be set in the pixel area PA in the first region AA1.

[0234] refer to Figure 30 , Figure 30 This application provides another top view of the display area of ​​a display panel, based on any of the above embodiments, and in conjunction with the accompanying drawings of the above embodiments. Figure 30 As shown, the display panel also includes a first alignment mark 21 and a second alignment mark 22, which are located in different transmission zones TA.

[0235] Each light-transmitting area (TA) may have at most one alignment mark. The number of first alignment marks 21 and second alignment marks 22 in the display panel can be set according to requirements. The number of first alignment marks 21 and second alignment marks 22 may both not exceed four. With a small number of alignment marks in the display panel, the impact of alignment marks on light transmittance is negligible for display panels with numerous pixel areas (PA).

[0236] Optionally, the areas of the first alignment mark 21 and the second alignment mark 22 are different. For example, the area of ​​the first alignment mark 21 can be set to be larger than the area of ​​the second alignment mark 22, and correspondingly, the area of ​​the transmission region TA with the first alignment mark 21 is larger than the area of ​​the transmission region TA with the second alignment mark 22.

[0237] In one embodiment, the area of ​​the first alignment mark 21 can be set to be larger than the area of ​​the second alignment mark 22. In this case, the larger area of ​​the first alignment mark 21 is used for alignment in the display panel manufacturing process; the second alignment mark 22 is used for alignment in the process of transferring the light-emitting element 11 in the display panel.

[0238] refer to Figure 31 , Figure 31 A cross-sectional view of a display panel provided in an embodiment of this application, based on any of the above-described embodiments, combined with... Figure 31 As shown in the accompanying drawings of the above embodiments, the display panel includes a substrate 20 and a driving layer 23 located on one side of the substrate 20. The driving layer 23 includes a pixel circuit 12 and a driving circuit 13. The driving layer 23 includes a first metal layer 241 and a second metal layer 242, with the second metal layer 242 located on the side of the first metal layer 241 away from the substrate 20. A first alignment mark 21 is located on the first metal layer 241, and a second alignment mark 22 is located on the second metal layer 242.

[0239] The driving layer 23 includes multiple metal layers stacked sequentially in the third direction Z. Any two of these metal layers can be used to prepare alignment marks. Of the two metal layers used to prepare the alignment marks, the one closer to the substrate 20 serves as the first metal layer 24, and the one farther from the substrate 20 serves as the second metal layer 242. In this embodiment, two metal layers in the driving layer 23 are reused as the first metal layer 241 and the second metal layer 242, respectively, to prepare the first alignment mark 21 and the second alignment mark 22. This eliminates the need to add separate metal layers to prepare the alignment marks, thus reducing the panel thickness.

[0240] refer to Figure 32 , Figure 32 A cross-sectional view of another display panel provided in an embodiment of this application. Figure 32 The illustration uses a cross-sectional view of the pixel circuit 12 in the YZ plane as an example, with the cross-section perpendicular to the gate of the second reset transistor M7. Based on any of the above embodiments, the driving layer 23 may include:

[0241] The semiconductor layer Sc located on the surface of the substrate 20 may be polysilicon and is used at least to form the active region a of the transistor and some traces in the circuit.

[0242] The gate metal layer ML1 located on the semiconductor layer Sc is used at least to fabricate the gate of the transistor and signal lines extending along the first direction X, such as the first scan signal line SL1, the second scan signal line SL2 and the light emission control signal line SL4.

[0243] The source / drain metal layer ML2 located above the gate metal layer ML1 is used to fabricate at least the source / drain electrodes of the transistor, as well as the data signal line SL5 and some signal lines extending along the second direction Y.

[0244] The first data metal layer ML3, located above the source / drain metal layer ML2, is used at least to fabricate the adapter wire for connecting the source / drain electrodes of the transistor to the electrode wires of the light-emitting element.

[0245] The second data metal layer ML4, located above the first data metal layer ML3, is used at least to fabricate electrode connection lines connecting the light-emitting element 11;

[0246] The capacitor metal layer ML5, located between the gate metal layer ML1 and the source / drain metal layer ML2, is used at least to prepare the two plates of the capacitor in the circuit, respectively, along with the gate metal layer ML1.

[0247] In a display panel, different metal layers and vias can be used to achieve cross insulation of signal lines to avoid short circuits between different signal lines.

[0248] Optionally, a light-shielding metal layer ML6 can be provided on the surface of the active region a of the transistor corresponding to the substrate 20 to prevent leakage current from the active region a of the transistor caused by light.

[0249] On the third direction Z, a light-shielding metal layer ML6, a semiconductor layer Sc, a gate metal layer ML1, a capacitor metal layer ML5, a source / drain metal layer ML2, a first data metal layer ML3, and a second data metal layer ML4 are sequentially stacked on top of the substrate 20, with an insulating layer between adjacent layers. Any two of the light-shielding metal layer ML6, the gate metal layer ML1, the capacitor metal layer ML5, the source / drain metal layer ML2, the first data metal layer ML3, and the second data metal layer ML4 can be used to create alignment marks.

[0250] Since the primary function of the light-shielding metal layer ML6 is to block light, its material and structural design are optimized to achieve this purpose, taking into account the light absorption and reflection characteristics. If the light-shielding metal layer ML6 is used as the alignment mark, it will affect the visualization of the alignment mark during optical detection and imaging, making it difficult to accurately identify and detect. If the first alignment mark 21 is used for alignment in the manufacturing of the display panel, it is preferable to use the gate metal layer ML1 to prepare the first metal layer for preparing the first alignment mark 21.

[0251] In display panel manufacturing, photolithography is an indispensable step used to pattern the film structure in the display panel. The gate metal layer ML1, as the bottom layer metal after the light-shielding metal layer ML6, serves as the basis for aligning subsequent patterned structures formed on top when the first alignment mark 21 is created using the gate metal layer ML1. Alternatively, alignment marks in the display panel manufacturing process can also be formed using other metal layers.

[0252] As described above, the light-emitting element 11 is a separately fabricated micro-LED. The light-emitting element 11 can be prefabricated and then transferred to the substrate 20 via a transfer process to fix it on the driving layer 23 and electrically connect it to the pixel circuit 12. To improve the accuracy and efficiency of batch transfer, alignment marks for the light-emitting element 11 during the transfer process need to be set on the substrate 20.

[0253] If the second alignment mark 22 is used for alignment during the transfer of the light-emitting element 11, it is preferable to use the uppermost second data metal layer ML4 of the driving layer 23 to prepare the second alignment mark. Using the uppermost second data metal layer ML4 of the driving layer 23 to prepare the alignment mark for the transfer of the light-emitting element 11 allows the alignment mark to be located at the top, facilitating clear identification of the alignment mark. Furthermore, it can reduce the cumulative error during the transfer process, thereby improving positioning accuracy and product yield.

[0254] In the embodiments of this application, it can be as follows Figure 1 As shown, the display area of ​​the display panel is divided into three sub-display areas along the first direction X, which are respectively used as the first area AA1, the second area AA2, and the third area AA3. The arrangement order of the first area AA1, the second area AA2, and the third area AA3 in the first direction X is not limited to... Figure 1 As shown, the order in which the three elements are arranged can be set arbitrarily.

[0255] refer to Figure 33 , Figure 33 This application provides a schematic diagram of a display panel with a divided display area. The display area AA can be further divided into at least five sub-display areas along a first direction X. Of the five consecutively arranged sub-display areas, the middle sub-display area serves as the second area AA2, the two sub-display areas on the left and right sides serve as the third area AA3, and the other two sub-display areas serve as the first area AA1. This method not only allows the first pixel circuit 121 to be set in the first area AA1 to house the driving circuit 13 within the display area AA, but also allows the driving circuit 13 to be arranged in the third areas AA3 on the left and right sides respectively, achieving dual-sided driving and improving driving capability.

[0256] refer to Figure 34 , Figure 34This is a schematic diagram illustrating the partitioning of a display panel in another embodiment of this application. If used for a transparent display panel, since the lower step cannot be bent to the back of the display panel, a border area BB needs to be set on one side of the display area AA in the second direction Y. This method can achieve a three-sided borderless structure.

[0257] If used for non-transparent display panels, the lower step can be bent to the back of the display panel, which can achieve a frameless structure on all four sides.

[0258] Based on any of the above embodiments, this application also provides a display device, which can perform as follows: Figure 35 As shown.

[0259] refer to Figure 35 , Figure 35 This is a schematic diagram of a display device provided in an embodiment of this application. The display device includes a display panel 10 provided in any of the above embodiments. The display device may include one display panel 10, or multiple display panels 10 spliced ​​and fixed together.

[0260] When used in large-size display scenarios, the display device may include multiple display panels 10 that are spliced ​​and fixed together.

[0261] The display device uses the display panel 10 provided in the above embodiment, which can set the driving circuit 12 in the display area AA, thereby removing the border area of ​​the splicing position at least in the first direction X, solving the problem that conventional display panels cannot display large-size transparent splicing displays.

[0262] The display device can be a large-size electronic display device for indoor and outdoor use, such as a large screen display device in public places such as squares and stations, or a vehicle display device, such as a transparent car window.

[0263] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0264] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0265] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally at the same time.

[0266] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0267] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Light-emitting elements; A pixel circuit and a driving circuit, wherein the driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the light-emitting element; The pixel circuit includes a driving transistor, a data writing transistor, and a threshold compensation transistor. The first terminal of the data writing transistor is connected to the first terminal of the driving transistor, and the second terminal of the data writing transistor is connected to a data line. The first terminal of the threshold compensation transistor is connected to the gate of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor. The display panel includes a first region and a second region distributed along a first direction, and the pixel circuit includes a first pixel circuit located in the first region and a second pixel circuit located in the second region. The driving circuit includes a first driving circuit, which includes a plurality of first shift registers cascaded along a second direction, wherein the first direction and the second direction intersect; wherein... In the first pixel circuit, the distance between the data writing transistor and the threshold compensation transistor in the first direction is D1; In the second pixel circuit, the distance between the data writing transistor and the threshold compensation transistor in the first direction is D2; wherein, D1 < D2.

2. The display panel according to claim 1, characterized in that, In the second pixel circuit, the data line is located on the side of the data writing transistor opposite to the driving transistor.

3. The display panel according to claim 1, characterized in that, In the second pixel circuit, the data line is located on the side of the driving transistor opposite to the data writing transistor.

4. The display panel according to claim 1, characterized in that, In the second pixel circuit, the data writing transistor and the threshold compensation transistor are located on the same side of the driving transistor.

5. The display panel according to claim 4, characterized in that, In the second pixel circuit, the data writing transistor and the threshold compensation transistor are arranged adjacent to each other in the first direction.

6. The display panel according to claim 4, characterized in that, The pixel circuit further includes a first reset transistor, the gate of which is connected to a first scan signal line, the first terminal of which is connected to a reset signal line, and the second terminal of which is connected to the gate of the driving transistor. In the second pixel circuit, the data writing transistor and the threshold compensation transistor are located between the first scan signal line and the driving transistor.

7. The display panel according to claim 6, characterized in that, The reset signal line is located on the side of the first scan signal line away from the driving transistor.

8. The display panel according to claim 7, characterized in that, In a plane perpendicular to the display panel, a portion of the active region of the first reset transistor overlaps with the reset signal line.

9. The display panel according to claim 7, characterized in that, The first terminal of the first reset transistor and the reset signal line are both connected to the first connection portion; the first connection portion partially overlaps with the first scan signal line.

10. The display panel according to claim 1, characterized in that, The driving transistor includes at least a first sub-transistor and a second sub-transistor, the gate of the first sub-transistor is connected to the gate of the second sub-transistor, the first terminal of the first sub-transistor is connected to the first terminal of the second sub-transistor, and the second terminal of the first sub-transistor is connected to the second terminal of the second sub-transistor.

11. The display panel according to claim 10, characterized in that, In the first pixel circuit, the first sub-transistor and the second sub-transistor are arranged along the second direction; In the second pixel circuit, the first sub-transistor and the second sub-transistor are arranged along the first direction.

12. The display panel according to claim 1, characterized in that, The light-emitting element includes a first light-emitting element and a second light-emitting element with different light-emitting colors; the wavelength of the light emitted by the first light-emitting element is greater than the wavelength of the light emitted by the second light-emitting element. The pixel circuit includes a driving transistor; wherein... The channel width-to-length ratio of the driving transistor in the pixel circuit corresponding to the first light-emitting element is A1; The channel width-to-length ratio of the driving transistor in the pixel circuit corresponding to the second light-emitting element is A2; Where A1 > A2.

13. The display panel according to claim 12, characterized in that, The channel width-to-length ratio of the driving transistor in the first pixel circuit corresponding to the first light-emitting element is equal to the channel width-to-length ratio of the driving transistor in the second pixel circuit corresponding to the first light-emitting element. And / or, The channel width-to-length ratio of the driving transistor in the first pixel circuit corresponding to the second light-emitting element is equal to the channel width-to-length ratio of the driving transistor in the second pixel circuit corresponding to the second light-emitting element.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

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