Display device

Abstract

The application relates to a display device, which comprises a display panel and a driving controller. The display panel comprises light emitting devices and pixel circuits for constituting display pixels. The driving controller is connected to the pixel circuits. The driving controller is configured to generate a corresponding first PWM data signal according to a preset first PAM data signal and a first image gray scale when the first image gray scale corresponding to the light emitting device is greater than or equal to a first preset gray scale value, and drive the pixel circuit according to the first PAM data signal and the generated first PWM data signal. The driving controller is configured to generate a corresponding second PAM data signal according to a preset second PWM data signal and a second image gray scale when the second image gray scale corresponding to the light emitting device is less than the first preset gray scale value, and drive the pixel circuit according to the second PWM data signal and the generated second PAM data signal. The display device has fine low gray scale transition, high middle and high gray scale light emitting uniformity, and good display effects of high brightness and low brightness.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device. Background Technology

[0002] Display devices have multiple light-emitting devices and corresponding pixel circuits. Due to their advantages such as small size, fast response speed, high luminous efficiency, strong stability and long service life, micro light-emitting diodes (micro LEDs, also known as micro LEDs or μLEDs) have gradually become the commonly used light-emitting devices in display devices.

[0003] In related technologies, pixel circuits typically employ a driving method combining pulse amplitude modulation (PAM) and pulse width modulation (PWM) to drive the light-emitting device with a constant current and adjust the screen brightness by controlling the emission time. However, this driving method suffers from poor low-grayscale control accuracy and uneven low-grayscale transitions, resulting in poor display quality. Summary of the Invention

[0004] Therefore, it is necessary to provide a display device that can improve the display quality.

[0005] A display device, comprising:

[0006] The display panel includes light-emitting devices for constituting display pixels and pixel circuits connected to the light-emitting devices;

[0007] A drive controller is connected to the pixel circuit; the drive controller is configured to:

[0008] When the gray level of the first image corresponding to the light-emitting device is greater than or equal to a first preset gray level value, a corresponding first PWM data signal is generated according to the preset first PAM data signal and the first image gray level, so as to drive the pixel circuit according to the first PAM data signal and the generated first PWM data signal; wherein, the first PAM data signal corresponding to different first image gray levels is the same, the first image gray level corresponding to different first PWM data signals is different, and the same first PAM data signal indicates that the pixel circuit drives the light-emitting device with a constant driving current.

[0009] When the gray level of the second image corresponding to the light-emitting device is less than the first preset gray level value, a corresponding second PAM data signal is generated according to the preset second PWM data signal and the gray level of the second image, so as to drive the pixel circuit according to the second PWM data signal and the generated second PAM data signal; wherein, the second PWM data signal corresponding to different gray levels of the second image is the same, the second image gray level corresponding to different second PAM data signals is different, and the same second PWM data signal indicates that the pixel circuit drives the light-emitting device with a constant driving duration.

[0010] In the aforementioned display device, when the first image grayscale of the light-emitting device is a mid-to-high grayscale value greater than or equal to a first preset grayscale value, the drive controller adjusts the first PWM data signal output to the pixel circuit according to the first image grayscale value to adjust the driving duration of the pixel circuit driving the light-emitting device to emit light. The drive controller also generates a driving current according to a preset first PAM data signal. Since the first PAM data signals corresponding to different first image grayscale values ​​are the same at this time, the same first PAM data signal indicates that the pixel circuit uses a constant driving current to drive the light-emitting device, thereby enabling the light-emitting device to be driven by a constant current, which can ensure the uniformity of light emission at mid-to-high grayscale values. When the image grayscale corresponding to the light-emitting device is a low grayscale value less than the first preset grayscale value, the drive controller outputs a preset second PWM data signal to the pixel circuit to keep the driving time of the light-emitting device constant and within the controllable range of the pixel circuit. Simultaneously, the drive controller adjusts the second PAM data signal based on the smaller second image grayscale. Thus, different image grayscales correspond to different second PAM data signals. While maintaining the segmentation accuracy of the second PWM data signal, the drive current output to the light-emitting device can be adjusted via the second PAM data signal to finely regulate the brightness of the light-emitting device, resulting in smooth transitions at low grayscale levels and precise control of low grayscale. Therefore, the display device exhibits excellent image quality in both high-brightness and low-brightness display scenarios. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the planar structure of a display device provided in some embodiments of this application;

[0013] Figure 2 A schematic diagram of a structure using PWM and PAM drives provided for related technologies;

[0014] Figure 3 A schematic diagram illustrating the structure of a hub and pixels connected via data signal lines, provided for related technologies;

[0015] Figure 4 This is a schematic diagram of the structure of a display device provided in some embodiments of this application;

[0016] Figure 5 A schematic diagram of the gamma curve of a display device provided in some embodiments of this application;

[0017] Figure 6 This is a schematic diagram showing the connection between the driver chip and the pixel data signal line provided in some embodiments of this application;

[0018] Figure 7 A schematic diagram of a pixel circuit provided in some embodiments of this application;

[0019] Figure 8 This is a schematic diagram of the pixel circuit structure provided in some embodiments of this application;

[0020] Figure 9 This is a schematic diagram of the pixel circuit provided in some other embodiments of this application;

[0021] Figure 10 for Figures 8-9 A driving timing diagram for a mid-pixel circuit;

[0022] Figure 11 A schematic diagram of a pixel circuit provided in other embodiments of this application;

[0023] Figure 12 This application provides schematic diagrams of the pixel circuit structure in some of its embodiments.

[0024] Figure 13 for Figure 12 A driving timing diagram for a mid-pixel circuit;

[0025] Figure 14 for Figure 12 Another driving timing diagram for the mid-pixel circuit. Detailed Implementation

[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0028] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0029] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0030] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0031] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0032] Figure 1 This is a plan view of a display device according to some embodiments of this application. Figure 1As shown, the display device includes a display panel, which includes light-emitting devices for constituting display pixels and pixel circuits connected to the light-emitting devices. Specifically, the display panel includes a pixel array unit 100, which includes multiple scan signal lines SL and multiple data signal lines DL disposed on a substrate, and multiple pixel units P respectively disposed at the intersections of the multiple scan signal lines SL and the multiple data signal lines DL. Each pixel unit P includes a light-emitting device constituting the display pixel and a pixel circuit composed of a thin-film transistor (TFT). The pixel circuit drives the light-emitting device to display an image based on scan signals provided by adjacent scan signal lines SL and data signals provided by adjacent data signal lines DL. Specifically, the pixel circuit may include at least one TFT and at least one capacitor (C), and the pixel circuit can drive the light-emitting device based on data signals. The light-emitting device may include μLED, minilight emitting diode (Mini LED), organic light-emitting diode (OLED), etc.

[0033] The display device also includes a drive controller 300, a data drive circuit 500 (e.g., a data driver), and a scan drive circuit 700 (e.g., a scan driver). The signals received by the pixel circuits in the following embodiments of this application are all provided by the aforementioned drive controller 300, data drive circuit 500, and scan drive circuit 700.

[0034] The drive controller 300 can generate pixel data corresponding to each display pixel based on the image signal. For example, the drive controller 300 can generate a data control signal based on a timing synchronization signal (TSS) to output the data control signal to the data drive circuit 500. According to some specific embodiments, the drive controller 300 generates a scan control signal based on the TSS, which may include a start signal and multiple scan clock signals (SCS), and outputs the scan control signal to the scan drive circuit 700. The drive controller 300 can also generate multiple carry clock signals (CCS) according to the drive mode of the scan drive circuit 700 to output the multiple CCS to the scan drive circuit 700. The data driving circuit 500 can be connected to multiple data signal lines DL disposed in the pixel array unit 100. The data driving circuit 500 can receive pixel data and data control signals output from the drive controller 300, and can receive multiple reference gamma voltages (RGV) provided by the power supply circuit. The data driving circuit 500 can use the data control signals and multiple RGVs to convert the pixel data into pixel-based analog data signals, and provide the pixel-based analog data signals to the corresponding data signal lines DL.

[0035] The scan driving circuit 700 can be connected to multiple scan signal lines SL disposed in the pixel array unit 100. Specifically, the scan driving circuit 700 can determine a predetermined sequence of scan signals based on the scan control signal provided by the drive controller 300, and can output the scan signals to the corresponding scan signal lines SL. As some specific embodiments, the scan driving circuit 700 is integrated on one or two edges of the substrate according to the TFT manufacturing process and connected to multiple scan signal lines SL in a corresponding relationship. For example, the scan driving circuit 700 is disposed in an integrated circuit and encapsulated in a substrate or flexible circuit film, and can also be connected to multiple scan signal lines SL in a one-to-one correspondence.

[0036] Figure 2 This is a schematic diagram of a method using PWM and PAM driving according to related technologies. Figure 3 This is a schematic diagram illustrating the connection between a pixel unit and a PAM data signal line in a display device according to related technologies. In related technologies, when a driving method combining PAM and PWM is used, such as... Figure 2As shown, the driver integrated circuit (Driver IC) 1 is connected to the PWM module 3 of the pixel circuit and outputs PWM data signals (i.e., pulse width modulation data signals) to the PWM module 3; the hub (hubboard) 2 is connected to the PAM module 4 of the pixel circuit and outputs PAM data signals (i.e., pulse amplitude modulation data signals) to the PAM module 4. The hub 2 can also be connected to the PWM module 3 and output a ramp signal to the PWM module 3. The PWM module 3 is also connected to the PAM module 4, and the PAM module 4 is also connected to the light-emitting device LED (e.g., μLED), and the light-emitting device LED is also connected to the ground signal VSS.

[0037] Combination Figure 2 and Figure 3 As can be seen, in related technologies, the PAM data signal lines of the entire screen 5 are typically interconnected, and a fixed voltage is output through HUB2, thereby using a constant current to drive the light-emitting device. It should be noted that... Figure 3 The red pulse amplitude modulation data signal represents the PAM data signal input to the red (Red, R) pixel, the green pulse amplitude modulation data signal represents the Data_PAM data signal input to the green (Green, G) pixel, and the blue pulse amplitude modulation data signal represents the Data_PAM data signal input to the blue (Blue, B) pixel.

[0038] When the voltage values ​​of the PAM data signals in all pixel circuits are the same, and the duration segmentation accuracy of PWM module 3 is fixed, if the image grayscale in the display device is low grayscale, compared with high grayscale, the current emitted by the light-emitting device is smaller, the efficiency is lower, the intensity is lower, and the duration is shorter. In other words, the smaller the grayscale, the more difficult it is for PWM module 3 to perform grayscale segmentation, while it generally has little impact on high grayscale. Therefore, if the grayscale is low (e.g., below grayscale 5), the required emission duration is likely to be less than the minimum segmentation accuracy of PWM module 3 (e.g., exceeding the segmentation capability). This will result in inaccurate or missed display of some low grayscale levels due to the inability to perform precise segmentation, leading to poor control accuracy of low grayscale, resulting in uneven transitions between low grayscale levels and poor image quality in low-brightness displays.

[0039] To address the aforementioned issues, this application provides a display device in which a driving controller generates a corresponding first PWM data signal based on a preset first PAM data signal and the first image grayscale value when the grayscale value of the first image corresponding to the light-emitting device is greater than or equal to a first preset grayscale value. This first PWM data signal drives the pixel circuit based on the first PAM data signal and the generated first PWM data signal. Specifically, the first PAM data signal corresponding to different first image grayscale values ​​is the same, while the first image grayscale values ​​corresponding to different first PWM data signals are different. The same first PAM data signal indicates that the pixel circuit uses a constant driving current to drive the light-emitting device. When the grayscale value of the second image corresponding to the light-emitting device is less than the first preset grayscale value, a corresponding second PAM data signal is generated based on a preset second PWM data signal and the second image grayscale value. This second PWM data signal drives the pixel circuit based on the second PWM data signal and the generated second PAM data signal. Specifically, the second PWM data signal corresponding to different second image grayscale values ​​is the same, while the second image grayscale values ​​corresponding to different second PAM data signals are different. The same second PWM data signal indicates that the pixel circuit uses a constant driving duration to drive the light-emitting device. Therefore, when the first image grayscale of the light-emitting device is a mid-to-high grayscale value greater than or equal to the first preset grayscale value, the drive controller adjusts the first PWM data signal output to the pixel circuit according to the first image grayscale value to adjust the driving duration of the pixel circuit driving the light-emitting device to emit light. The drive controller also generates a driving current according to the preset first PAM data signal. Since the first PAM data signals corresponding to different first image grayscale values ​​are the same, the same first PAM data signal allows the pixel circuit to use a constant driving current to drive the light-emitting device, thereby enabling the light-emitting device to be driven by a constant current and ensuring the uniformity of light emission at mid-to-high grayscale values. When the image grayscale corresponding to the light-emitting device is a low grayscale value less than the first preset grayscale value, the drive controller outputs a preset second PWM data signal to the pixel circuit to keep the driving time of the light-emitting device constant and within the controllable range of the pixel circuit. Simultaneously, the drive controller adjusts the second PAM data signal based on the smaller second image grayscale. Thus, different image grayscales correspond to different second PAM data signals. While maintaining the voltage segmentation accuracy of the second PWM data signal, the drive current output to the light-emitting device can be adjusted via the second PAM data signal to finely regulate the brightness of the light-emitting device, resulting in smooth transitions between low grayscale levels and precise control of low grayscale. Therefore, the embodiments of this application enable smooth transitions between low grayscale levels, achieving a wider range of low grayscale levels, thereby allowing the display panel and display device to display good image quality and excellent performance across low, medium, and high grayscale levels.

[0040] To facilitate a further understanding of the technical solutions in some embodiments of this application, the technical solutions of the display device and how these solutions solve the aforementioned technical problems are described in detail below, in conjunction with specific embodiments and accompanying drawings. Each embodiment can be combined with others, and the same or similar concepts or processes may not be repeated in some embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application.

[0041] This application provides a display device, which includes a display panel, such as... Figure 4 As shown, the display panel includes light-emitting devices (LEDs) for forming display pixels and pixel circuits 400 connected to the LEDs. It can be understood that there are multiple LEDs and corresponding pixel circuits 400, thus forming multiple arrayed pixel units.

[0042] The display device further includes a drive controller 300 connected to a pixel circuit 400. The drive controller 300 is configured to: when the grayscale of the first image corresponding to the light-emitting device LED is greater than or equal to a first preset grayscale value, generate a corresponding first PWM data signal based on a preset first PAM data signal and the first image grayscale, so as to drive the pixel circuit 400 according to the first PAM data signal and the generated first PWM data signal; wherein, the first PAM data signal corresponding to different first image grayscales is the same, the first image grayscale corresponding to different first PWM data signals is different, and the same first PAM data signal indicates that the pixel circuit 400 uses a constant driving current to drive the light-emitting device LED. When the grayscale of the second image corresponding to the light-emitting device LED is less than the first preset grayscale value, generate a corresponding second PAM data signal based on a preset second PWM data signal and the second image grayscale, so as to drive the pixel circuit 400 according to the second PWM data signal and the generated second PAM data signal; wherein, the second PWM data signal corresponding to different second image grayscales is the same, the second image grayscale corresponding to different second PAM data signals is different, and the same second PWM data signal indicates that the pixel circuit 400 uses a constant driving duration to drive the light-emitting device LED.

[0043] The first preset grayscale value can be set according to actual conditions, such as based on measured data or experience. For example, the first preset grayscale value can be 16 grayscale levels. Grayscale levels greater than or equal to the first preset grayscale value are considered mid-to-high grayscale levels within the range of 16 to 255 grayscale levels. The first image grayscale level can be any grayscale level within the mid-to-high grayscale range greater than or equal to the first preset grayscale value. Grayscale levels less than the first preset grayscale value are considered low grayscale levels within the range of 0 to 15 grayscale levels. The second image grayscale level can be any grayscale level within the low grayscale range less than the first preset grayscale value.

[0044] The drive controller 300 drives the pixel circuit 400 according to the PAM data signal and the PWM data signal, wherein the PAM data signal and the PWM data signal are respectively the first PAM data signal and the first PAM data signal corresponding to the gray level of the first image, or the PAM data signal and the PWM data signal are respectively the second PAM data signal and the second PAM data signal corresponding to the gray level of the second image. That is, when the gray level of the first image corresponding to the light-emitting device LED is greater than or equal to a first preset gray level value, the drive controller 300 drives the pixel circuit 400 according to the first PAM data signal and the first PWM data signal; when the gray level of the second image corresponding to the light-emitting device LED is less than the first preset gray level value, the drive controller 300 drives the pixel circuit 400 according to the second PAM data signal and the second PWM data signal.

[0045] The pixel circuit 400 outputs a drive current signal corresponding to the PAM data signal to drive the light-emitting device LED, and the driving duration of the output drive current signal to drive the light-emitting device LED corresponds to the PWM data signal, so as to adjust the proportion of the light-emitting duration of the light-emitting device LED to the current driving cycle (i.e., duty cycle).

[0046] In some embodiments, when the image grayscale corresponding to the light-emitting device LED is low, the drive controller 300 first generates a corresponding second PAM data signal based on the second image grayscale, and then outputs the generated second PAM data signal and a preset second PWM data signal to the pixel circuit 400. The method for generating the second PAM data signal is flexible. For example, the target PAM driving value corresponding to the grayscale value of the second image can be obtained through a lookup table or mapping function, and then the second PAM data signal is generated based on the target PAM driving value. In some embodiments, the drive controller 300 generates the corresponding second PAM data signal based on the voltage value (or the voltage range of the voltage value) of the preset PWM data signal and the grayscale of the second image. For example, the second PAM driving value corresponding to the grayscale value of the second image can be obtained by looking up a lookup table or mapping function corresponding to the voltage value of the preset second PWM data signal. The voltage value of the preset second PWM data signal does not need to be limited and can be set according to specific circumstances, such as by actual measurement based on factors such as the peak brightness of the display panel or by experience, to ensure that the light emission duration adjustment under low grayscale meets the control accuracy of the pixel circuit 400.

[0047] In this system, different gray levels of the second image correspond to the same second PWM data signal, while different second PAM data signals correspond to different gray levels of the second image. The same second PWM data signal indicates that the pixel circuit 400 drives the light-emitting device (LED) with a constant driving duration. Corresponding to the gray level of the second image, the pixel circuit 400 outputs a driving current signal to drive the LED for the same duration based on the same second PWM data signal. Since different gray levels of the second image correspond to different second PAM data signals, the driving current signal output by the pixel circuit 400 based on the second PAM data signal corresponds to each gray level of the second image. The higher the gray level of the second image, the greater the driving current, and the higher the brightness of the LED. Therefore, while maintaining the voltage segmentation accuracy of the PWM data signal, the driving current output to the LED can be adjusted through the second PAM data signal to finely adjust the low brightness of the LED, resulting in a smooth transition between low gray levels.

[0048] In some embodiments, when the image grayscale corresponding to the LED light-emitting device is at a medium to high grayscale, the drive controller 300 first generates a corresponding first PWM data signal based on the first image grayscale, and then outputs the generated first PWM data signal and a preset first PAM data signal to the pixel circuit 400. The method for generating the first PWM data signal is flexible. For example, the drive value corresponding to the grayscale value of the first image grayscale can be obtained by looking up a table or using a mapping function, and then the first PWM data signal is generated based on the drive value. In some embodiments, the drive controller 300 generates the corresponding first PWM data signal based on the voltage value (or the voltage range of the preset PAM data signal) and the first image grayscale. For example, the drive value corresponding to the grayscale value of the image grayscale can be obtained by looking up a table or using a mapping function corresponding to the voltage value of the first PAM data signal, and then the first PWM data signal is generated based on the drive value. The voltage value of the first PAM data signal does not need to be limited and can be set according to specific circumstances, such as by actual measurement based on factors such as the peak brightness of the display panel or by experience, to ensure that sufficient constant drive current is provided even at medium to high grayscale levels.

[0049] In this design, different first image gray levels correspond to the same first PAM data signal, while different first PWM data signals correspond to different first image gray levels. The same first PAM data signal indicates that the pixel circuit 400 uses a constant driving current to drive the light-emitting device (LED). For each first image gray level, the pixel circuit 400 outputs a constant driving current to drive the LED based on the same first PAM data signal, thereby ensuring uniform light emission at medium and high gray levels. Since different first image gray levels correspond to different first PWM data signals, the pixel circuit 400 also adjusts the duration of the output driving current signal driving the LED based on the first PWM data signal. The higher the image gray level, the longer the driving time of the generated first PWM data signal driving the LED, resulting in higher perceived brightness and thus achieving fine control over medium and high brightness.

[0050] It can be understood that identical PAM data signals refer to consistent PAM data signal voltages, and identical PWM data signals refer to consistent PWM data signal voltages. Consistent voltage includes equal voltages or voltage deviations not exceeding a preset threshold, which can be set according to the actual acceptable error range or circuit structure. "Constant" means that the corresponding parameters are the same or the deviation does not exceed a preset value. In some embodiments, the identical first PAM data signal indicates that the pixel circuit 400 uses a constant driving current to drive the LED. Specifically, it means that the first PAM data signals corresponding to different first image gray levels remain the same, and the pixel circuit 400 outputs a driving current that is equal or the deviation does not exceed a preset value based on the identical first PAM data signal, thus ensuring the uniformity of LED light emission. In some embodiments, the identical second PWM data signal indicates that the pixel circuit 400 uses a constant driving duration to drive the LED. Specifically, it means that the second PWM data signals corresponding to different second image gray levels remain the same, and the pixel circuit 400 outputs a driving current signal to drive the LED for the same duration or the deviation does not exceed a preset value based on the identical second PWM data signal.

[0051] The aforementioned display device can drive the LED with a constant current when the grayscale of the first image corresponding to the LED is a medium-high grayscale greater than or equal to a first preset grayscale value, ensuring uniform light emission at medium-high grayscale levels. When the grayscale of the image corresponding to the LED is a low grayscale less than the first preset grayscale value, the driving duration of the LED can be kept constant within the controllable range of the pixel circuit, while the corresponding driving current is output according to the second PAM data signal corresponding to the second image grayscale. Thus, while maintaining the voltage segmentation accuracy of the second PWM data signal, the driving current output to the LED can be adjusted through the second PAM data signal to finely adjust the brightness of the LED, resulting in a smooth transition at low grayscale levels and precise control of low grayscale. Therefore, the display device can cover a wide grayscale range, providing excellent image quality in both high and low brightness displays, meeting diverse display needs.

[0052] When the image grayscale of the LED light-emitting device is in the mid-to-high grayscale, the driver controller 300 inputs a fixed voltage PAM data signal, and the PWM data signal is split and input with different voltages to achieve the transition and expansion of the mid-to-high grayscale, forming a pattern such as... Figure 5 The image shows a mid-to-high grayscale gamma1 curve G1. When the image grayscale of the LED is low, the drive controller 300 inputs a fixed voltage PWM data signal, and the PAM data signal is split and input with different voltages, shortening the LED's emission time (within the controllable range of the pixel circuit). By adjusting the PAM data signal, the low grayscale transition is achieved, forming a low grayscale gamma2 curve G2. By stitching the gamma1 curve G1 and the gamma2 curve G2 together, a high-low grayscale dual-gamma stitching combination is achieved during gamma correction, enabling perfect expansion of all grayscale levels (low, medium, and high), making viewing more comfortable for the human eye.

[0053] The aforementioned drive controller 300 can be as follows: Figure 1 The drive controller 300 shown can also be Figure 6 The driver chip shown is 1, etc., but the specific application may vary. For example... Figure 6As shown, in some embodiments, the Data_PAM data signal line and Data_PWM data signal line connected to any column of pixel circuits are combined into one. Specifically, the PWM data signal line and PAM data signal line can be connected separately to a single channel of the driver chip 1, with the driver chip 1 outputting the PWM data signal and PAM data signal in a time-division multiplexing manner. In this case, each column of pixel circuits in the pixel unit can share a single line, or a single pixel circuit in the pixel unit can use a single line, which receives the PWM data signal and PAM data signal in a time-division multiplexing manner. By combining the PWM data signal line and PAM data signal line into one, and having the driver chip 1 input the PWM data signal and PAM data signal in a time-division multiplexing manner, it can be ensured that the two signals do not interfere with each other, improving the accuracy of the input signal. Furthermore, it can replace the multi-signal parallel wiring method in related technologies, saving the number of driver lines and reducing costs.

[0054] It is understood that when the pixel circuit adjusts the duration of the output drive current signal according to the PWM data signal, it can adjust the duration of the output drive current signal according to the voltage of the PWM data signal and the ramp signal (hereinafter referred to as the Sweep signal). This embodiment does not limit the changing trend and transmission method of the Sweep signal. In specific implementation, a HUB can be used to connect the Sweep signal line and transmit the Sweep signal. A single channel of the driver chip 1 can be connected to the PWM data signal line and the PAM data signal line respectively, and the PWM data signal and the PAM data signal can be output in a time-division multiplexing manner. Alternatively, the Sweep signal line, the PWM data signal line and the PAM data signal line can be combined into one, and the PAM data signal, the PWM data signal and the Sweep signal can be transmitted to the pixel circuit in a time-division multiplexing manner through a single channel.

[0055] To achieve precise control of the brightness of the light-emitting device at different low gray levels, the voltage value of a preset second PWM data signal can be dynamically adjusted according to the image gray level. In some embodiments, when the second image gray level of the light-emitting device is less than a first preset gray level value but greater than or equal to a second preset gray level value, the voltage value of the second PWM data signal is the first preset PWM voltage value. When the second image gray level is less than a second preset gray level value, the voltage value of the second PWM data signal is the second preset PWM voltage value. Wherein, the second preset gray level value is less than the first preset gray level value. When the second PWM data signal is at the second preset PWM voltage value, the duration for which the pixel circuit outputs the drive current signal to drive the light-emitting device is less than the duration for which the pixel circuit outputs the drive current signal to drive the light-emitting device when the second PWM data signal is at the first preset PWM voltage value.

[0056] The magnitudes of the second preset PWM voltage value and the first preset PWM voltage value can be set according to actual conditions, and this embodiment does not impose specific limitations on them. In some embodiments, the larger the voltage value of the second PWM data signal, the longer the time for the pixel circuit to output the drive current signal to drive the light-emitting device. In this case, the second preset PWM voltage value is less than the first preset PWM voltage value.

[0057] Since the second preset grayscale value is less than the first preset grayscale value, when the grayscale of the second image is within the grayscale range between the first and second preset grayscale values, the emission duration of the light-emitting device corresponds to the first preset PWM voltage value. When the grayscale of the second image is below the second preset grayscale value, the emission duration of the light-emitting device corresponds to the second preset PWM voltage value, and the emission duration is shorter than the duration corresponding to the first preset PWM voltage value. Therefore, by determining the voltage value of the second PWM data signal more precisely based on the grayscale range, the emission duration can be adjusted more precisely to adapt to different brightness display requirements.

[0058] In this embodiment, the segmentation voltage value of the second PWM data signal is determined according to the grayscale range of the second image, and the second PAM data signal is adaptively adjusted as the image grayscale changes. In the low grayscale range, by shortening the driving time and adjusting the driving current, the brightness control of the light-emitting device is more precise, which can improve the low grayscale display effect of the display device.

[0059] It is understandable that in practical applications, more grayscale ranges can be set depending on the specific situation. For each grayscale range, the second PWM data signal is divided into different voltage values, so the smaller the image grayscale, the shorter the fixed emission duration. For example, when the second image grayscale is in the first grayscale range between the first and second preset grayscale values, the preset voltage value of the second PWM data signal is the first preset PWM voltage value; when the second image grayscale is in the second grayscale range between the second and third preset grayscale values, the preset voltage value of the second PWM data signal is the second preset PWM voltage value; when the second image grayscale is in the third grayscale range between the third and fourth preset grayscale values, the preset voltage value of the second PWM data signal is the third preset PWM voltage value, and so on. Where the third preset grayscale value is less than the second preset grayscale value, and the fourth preset grayscale value is less than the third preset grayscale value. When the second PWM data signal is the third preset PWM voltage value, the emission time of the light-emitting device is shorter.

[0060] In some embodiments, when the grayscale of the first image of the light-emitting device is greater than or equal to a first preset grayscale value, the maximum voltage value of the generated first PWM data signal is a first PWM voltage limit corresponding to the first preset grayscale value, and the minimum voltage value of the first PWM data signal is a second PWM voltage limit corresponding to the maximum grayscale value of the first image. When the grayscale of the second image is less than the first preset grayscale value, the preset voltage value of the second PWM data signal is between the first PWM voltage limit and the second PWM voltage limit.

[0061] When the image grayscale of the light-emitting device is greater than or equal to the first preset grayscale value (i.e., a medium-high grayscale scene), the voltage of the first PWM data signal decreases as the grayscale increases. Specifically, the minimum value of the medium-high grayscale (e.g., grayscale 16) corresponds to the maximum first PWM voltage limit Vpwmmax, and the maximum value of the medium-high grayscale (e.g., grayscale 255) corresponds to the minimum second PWM voltage limit Vpwmmin. At this time, the voltage range of the second PWM data signal is [Vpwmmin, Vpwmmax], and the duty cycle is continuously changed by dynamically adjusting the voltage value, thereby precisely controlling the light-emitting duration of the light-emitting device.

[0062] When the image grayscale is less than the first preset grayscale value (i.e., low grayscale scene), the voltage of the second PWM data signal is constant. This constant voltage is a preset value between the first PWM voltage limit Vpwmmax and the second PWM voltage limit Vpwmmin, so as to limit the light emission time of the light-emitting device. At the same time, the brightness is finely adjusted by current drive by dynamically adjusting the second PAM data signal.

[0063] In this embodiment, in medium-to-high grayscale scenarios, the preset first PAM data signal keeps the driving current constant, while the voltage of the first PWM data signal changes with the grayscale level. This ensures uniform light emission while achieving a smooth transition between medium and high grayscale levels. In low grayscale scenarios, the preset second PWM data signal voltage is within the voltage limit range of the first PWM data signal in the medium-to-high grayscale range. This ensures the stability of the light emission time of the light-emitting device at low brightness, reduces flickering caused by fluctuations in the second PWM data signal, and provides a larger dynamic range for current adjustment of the second PAM data signal. This results in finer grayscale control and more delicate grayscale unfolding at low brightness.

[0064] In some embodiments, the voltage value of the first PAM data signal is a preset voltage value, which is less than the minimum voltage value of the second PAM data signal.

[0065] When the image grayscale is less than the first preset grayscale value (i.e., low grayscale scene), the voltage value of the second PAM data signal increases as the grayscale decreases. Specifically, the maximum grayscale value in the low grayscale (e.g., 15) corresponds to the minimum PAM voltage value Vpammin, and a grayscale value of 0 corresponds to the maximum PAM voltage value Vpammax. When the image grayscale is greater than or equal to the first preset grayscale value (i.e., medium-high grayscale scene), the voltage value of the first PAM data signal is fixed at a preset voltage value Vpam_base, which is set to be lower than the minimum PAM voltage value in the low grayscale scene (i.e., Vpam_base < Vpammin).

[0066] In this embodiment, in medium-high grayscale scenarios, the voltage of the first PAM data signal is a relatively low preset voltage value, which enables the light-emitting device to maintain high luminous efficiency under a large current. At the same time, the dynamic adjustment of the first PWM data signal meets the medium-high brightness requirements and improves the display effect.

[0067] The structure of the pixel circuit is not unique. In some embodiments, such as... Figure 7 As shown, the pixel circuit includes a drive current control module 410, an emission duration control module 420, and a state control module 430 (connection relationship diagram not shown) connected to the drive controller 300. The drive current control module 410 is connected to the emission duration control module 420, the state control module 430, and the light-emitting device LED. The drive current control module 410 generates a drive current signal based on the input PAM data signal. The emission duration control module 420 receives the PWM data signal and generates an emission duration control signal to adjust the duration of the drive current signal output by the drive current control module 410. The state control module 430 stores charge to ensure the output path of the drive current signal in the drive current control module 410 is active during the emission phase. The drive controller 300 is configured as follows:

[0068] During the data writing phase, when the grayscale of the first image corresponding to the LED is greater than or equal to the first preset grayscale value, a first PAM data signal is output to the drive current control module 410, and a generated first PWM data signal is output to the light emission duration control module 420. When the grayscale of the second image corresponding to the LED is less than the first preset grayscale value, a generated second PAM data signal is output to the drive current control module 410, and a second PWM data signal is output to the light emission duration control module 420.

[0069] During the state control phase, the state control module 430 controls the output path of the drive current signal of the drive current control module 410 according to the state control signal, and controls the state control module 430 to store the amount of charge corresponding to the state control signal, so as to keep the output path on during the light emission phase based on the stored charge.

[0070] During the light-emitting phase, the drive current control module 410 outputs a drive current signal corresponding to the PAM data signal to drive the LED light-emitting device, and the light-emitting duration control module 420 outputs a light-emitting duration control signal based on the PWM data signal. This light-emitting duration control signal is used to control the output path to disconnect, thereby regulating the duration for which the drive current control module 410 outputs the drive current signal to drive the LED. It can be understood that the PAM data signal and the PWM data signal are respectively the first PAM data signal and the second PAM data signal, or respectively the second PAM data signal and the second PAM data signal. Specifically, if during the data writing phase, the drive controller 300 outputs the first PAM data signal corresponding to the grayscale of the first image, then during the light-emitting phase, the drive current control module 410 outputs a drive current signal corresponding to the first PAM data signal, and the light-emitting duration control module 420 outputs a light-emitting duration control signal based on the first PWM data signal. If, during the data writing phase, the drive controller 300 outputs the second PAM data signal corresponding to the grayscale of the second image, then during the light emission phase, the drive current control module 410 outputs the drive current signal corresponding to the second PAM data signal, and the light emission duration control module 420 outputs the light emission duration control signal based on the second PWM data signal.

[0071] The state control stage follows the data writing stage, and the light emission stage follows the state control stage. During the data writing stage, the drive current control module 410 and the light emission duration control module 420 receive PAM data signals and PWM data signals, respectively. During the state control stage, under the control of the drive controller 300, the state control module 430 outputs a state control signal, activating the output path of the drive current signal in the drive current control module 410. Simultaneously, the storage capacitor in the state control module 430 stores the charge corresponding to the state control signal. During the light emission stage, the charge stored in the state control module 430 keeps the output path continuously active to prevent display abnormalities caused by current path interruption. During this light emission stage, the drive current control module 410 generates a drive current signal of corresponding amplitude based on the current PAM data signal, directly driving the LED to emit light; the light emission duration control module 420 generates a light emission duration control signal based on the PWM data signal, disconnecting the output path of the drive current signal, thereby precisely cutting off the drive current and achieving duty cycle adjustment of the light emission duration.

[0072] In this embodiment, when the grayscale of the second image corresponding to the LED is a low grayscale value less than the first preset grayscale value, the drive controller 300 outputs a preset second PWM data signal to the drive current control module 410 to reduce the light emission time. Simultaneously, the drive controller 300 also adjusts the second PAM data signal according to the grayscale value of the second image. Thus, while maintaining the segmentation accuracy of the light emission duration control module 420, the drive current output to the LED can be adjusted by the drive current control module 410 to finely adjust the brightness of the LED, resulting in a smooth transition at low grayscale levels and achieving precise control of low grayscale. When the grayscale of the first image corresponding to the LED is a medium-high grayscale value greater than or equal to the first preset grayscale value, the drive controller 300 adjusts the first PWM data signal output to the light emission duration control module 420 according to the first image grayscale value to adjust the light emission duration of the LED. Simultaneously, the drive controller 300 also outputs the same first PAM data signal to the drive current control module 410, ensuring constant current drive for the LED and thus guaranteeing uniformity of light emission at medium-high grayscale levels. In addition, the drive current control module 410, the light emission duration control module 420 and the state control module 430 are designed independently, so that the signal processing paths in high grayscale and low grayscale scenarios do not interfere with each other, and the circuit has strong anti-interference ability.

[0073] In some embodiments, such as Figure 8 As shown, the drive current control module 410 includes a first switching unit 411, a second switching unit 412, and a drive unit 413. The control terminal of the first switching unit 411 is connected to the state control module 430 and the light emission duration control module 420. The first terminal of the first switching unit 411 is connected to the first power supply voltage output terminal to receive the first power supply voltage signal VDD1. The second terminal of the first switching unit 411 is connected to the first terminal of the drive unit 413, and the first terminal of the drive unit 413 is also used to receive the PAM data signal Data_PAM. The second terminal of the drive unit 413 is connected to the first terminal of the second switching unit 412, and the second terminal of the second switching unit 412 is connected to the light-emitting device LED. The control terminal of the second switching unit 412 is connected to the drive controller. The drive controller is specifically configured as follows:

[0074] During the data writing phase, the first switching unit 411 is turned off by the light emission duration control module 420. When the gray level of the first image corresponding to the light-emitting device LED is greater than or equal to the first preset gray level value, the preset first PAM data signal is output to the driving unit 413, and the generated first PWM data signal is output to the light emission duration control module 420. When the gray level of the second image corresponding to the light-emitting device LED is less than the first preset gray level value, the generated second PAM data signal is output to the driving unit 413, and the preset second PWM data signal is output to the light emission duration control module 420.

[0075] During the state control phase, the state control module 430 turns on the first switching unit 411 according to the state control signal. During the light emission phase, the state control module 430 keeps the first switching unit 411 in the on state based on the stored charge.

[0076] During the light-emitting phase, the second switching unit 412 is turned on so that the driving unit 413 outputs a driving current signal corresponding to the PAM data signal Data_PAM based on the first power supply voltage signal VDD1 connected to the first power supply voltage output terminal to drive the light-emitting device LED; and the light-emitting duration control module 420 outputs a light-emitting duration control signal based on the PWM data signal Data_PWM to control the first switching unit 411 to turn off.

[0077] The drive unit 413 is connected to the first switch unit 411 and the second switch unit 412 respectively. The connection path of the three forms the output path of the drive current signal. When one of the first switch unit 411 and the second switch unit 412 is disconnected, the output path is disconnected.

[0078] During the data writing phase, the light emission duration control module 420 controls the first switching unit 411 to turn off, at which point the output path is in an open state. In the subsequent state control phase, the state control module 430 controls the first switching unit 411 to turn on according to the state control signal, at which point the second switching unit 412 is turned off, and the output path remains open. During the light emission phase, the state control module 430 keeps the first switching unit 411 on, at which point the second switching unit 412 is also on, the output path is on, and the driving current signal output by the driving unit 413 flows to the LED, causing the LED to emit light, until the first switching unit 411 receives the light emission duration control signal and turns off, the output path is disconnected, and the LED stops emitting light.

[0079] In this embodiment, when the gray level of the second image corresponding to the light-emitting device LED is a low gray level less than the first preset gray level value, the drive controller adjusts the PAM data signal Data_PAM according to the gray level of the second image so that the drive unit 413 outputs the corresponding drive current. Thus, while the segmentation accuracy of the light-emitting duration control module 420 remains unchanged, the drive current output to the light-emitting device LED can be adjusted by the drive unit 413 to finely adjust the brightness of the light-emitting device LED, making the low gray level transition delicate and achieving precise control of the low gray level.

[0080] Furthermore, the first switching unit 411 and the second switching unit 412 are independently controlled. During the data writing phase, the light emission duration control module 420 actively turns off the first switching unit 411, effectively blocking the potential interference of the first power supply voltage signal VDD1 to the driving unit 413, ensuring stable writing of the PAM data signal Data_PAM. Especially in low grayscale scenarios, accurate writing of the PAM data signal Data_PAM can improve the precise adjustment capability of the small driving current, thereby improving the accuracy of light emission control. Moreover, the light emission duration control module 420 outputs based on the PWM data signal Data_PWM and the gradually changing slope signal Sweep. During this process, its output may fluctuate or be unstable. If the output signal of the light emission duration control module 420 is directly provided to the driving unit 413, it may affect the stability of the driving current generated by the driving unit 413. In this embodiment, the light emission duration control signal is provided to the first switching unit 411, which controls the output path to control whether the driving unit 413 starts working. When the driving unit 413 is working, the driving current it generates will not be affected by the fluctuation of the light emission duration control module 420, and the current value will be more stable, thereby making the light emission state of the LED device more stable.

[0081] In practical implementation, the drive controller can output PAM data signal Data_PAM and PWM data signal Data_PWM simultaneously or in a time-sharing manner. In some embodiments, the two output terminals of the drive controller can be connected to the drive current control module 410 and the light emission duration control module 420 respectively, for example... Figure 8 As shown, one output terminal outputs a PAM data signal Data_PAM to the drive current control module 410, and the other output terminal outputs a PWM data signal Data_PWM to the light emission duration control module 420. The drive controller can output two data signals simultaneously. In some embodiments, one output terminal of the drive controller can be connected to both the drive current control module 410 and the light emission duration control module 420, for example... Figure 9 As shown, this output terminal combines the Data_PAM data signal line and the Data_PWM data signal line into one, and outputs the PAM data signal Data_PAM and the PWM data signal Data_PWM in a time-division multiplexing manner to reduce one signal trace.

[0082] In some embodiments, where the drive controller outputs two data signals in a time-sharing manner, the data writing stage includes a first writing stage and a second writing stage, with the second writing stage following the first writing stage. The drive controller is configured to: in the first writing stage, output a PAM data signal Data_PAM to the drive current control module 410; and in the second writing stage, output a PWM data signal Data_PWM to the light emission duration control module 420. Because the capacitor in the drive current control module 410 has a larger capacitance, when writing the PAM data signal Data_PAM and the PWM data signal Data_PWM in a time-sharing manner, the leakage current generated by writing the PAM data signal Data_PAM first is smaller, resulting in a more precise drive current provided for the subsequent light emission stage and more reliable light emission control.

[0083] It is understood that in other embodiments, the PWM data signal Data_PWM can be output to the light emission duration control module 420 in the first writing stage, and the PAM data signal Data_PAM can be output to the drive current control module 410 in the second writing stage. The specific settings can be made according to the actual situation.

[0084] In some embodiments, such as Figure 8 or Figure 9 As shown, the light emission duration control module 420 includes a third switching unit 421 and a duration control unit 422. The control terminal of the third switching unit 421 is connected to the drive controller, and the first terminal of the third switching unit 421 is connected to the second power supply voltage output terminal to receive the second power supply voltage signal VDD2. The second terminal of the third switching unit 421 is connected to the first terminal of the duration control unit 422, and the first terminal of the duration control unit 422 is also used to receive the PWM data signal Data_PWM. The second terminal of the duration control unit 422 is connected to the control terminal of the first switching unit 411. The drive controller is also configured to:

[0085] During the data writing phase, the third switch unit 421 is turned on so that the first switch unit 411 is turned off by the second power supply voltage signal VDD2 connected to the second power supply voltage output terminal.

[0086] During the light-emitting stage, the control duration control unit 422 outputs a light-emitting duration control signal based on the PWM data signal Data_PWM to regulate the duration for which the drive current signal drives the light-emitting device LED.

[0087] In this embodiment, during the data writing phase, the third switching unit 421 is turned on to transmit the second power supply voltage signal VDD2 to the first switching unit 411 via the duration control unit 422, causing the first switching unit 411 to turn off. Therefore, when writing the PAM data signal Data_PAM to the driving unit 413, it is unaffected by the first power supply voltage signal VDD1, ensuring accurate writing of the PAM data signal Data_PAM and thus improving the reliability of the light emission control. During the light emission phase, the duration control unit 422 outputs a light emission duration control signal based on the PWM data signal Data_PWM, controlling the on-time of the first switching unit 411, thereby regulating the duration for which the driving current signal drives the LED light-emitting device, achieving precise control of the light emission brightness.

[0088] In some embodiments, the state control module 430 includes a state control transistor T0 and a storage capacitor C0. A first terminal of the storage capacitor C0 is connected to a first terminal of the first switching unit 411. A second terminal of the storage capacitor C0 is connected to both the control terminal of the first switching unit 411 and the first electrode of the state control transistor T0. The second electrode of the state control transistor T0 is connected to a state control signal output terminal. The control electrode of the state control transistor T0 is connected to a drive controller. The drive controller is configured to:

[0089] During the state control phase, the state control transistor T0 is turned on, and the state control signal Vref0 connected to the state control signal output terminal is transmitted to the control terminal of the first switching unit 411. The charge of the state control signal Vref0 is stored in the storage capacitor C0.

[0090] During the state control phase, the drive controller outputs a state control scan signal S4 to the control electrode of the state control transistor T0, turning on the state control transistor T0 and writing the state control signal Vref0 to node A. On one hand, the state control signal Vref0 controls the first switching unit 411 to turn on; on the other hand, the storage capacitor C0 charges according to the state control signal Vref0. The voltage magnitude of the state control signal Vref0 does not need to be limited and can be set according to factors such as the specific circuit structure of the first switching unit 411 during actual implementation.

[0091] In this embodiment, the state control transistor T0 forms the transmission path for the state control signal Vref0. During the state control phase, the state control signal Vref0 is precisely written into node A through a conduction operation, while simultaneously providing a charging path for the storage capacitor C0. The charge storage function of the storage capacitor C0 ensures that the potential of node A is stable in the early stage of the light-emitting phase. Even if the state control transistor T0 is turned off after entering the light-emitting phase (the state control scan signal S4 turns high), it ensures that the first switching unit 411 remains in the conducting state, thus conducting the output path. The first switching unit 411 is turned off, cutting off the output path, until the light-emitting duration control signal is written into node A. This state control module 430 includes a transistor and a capacitor, with a simple circuit structure that is easy to implement and control.

[0092] In some embodiments, the driving unit 413 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. The first terminal of the first transistor T1 is connected to the first switching unit 411 and the first terminal of the third transistor T3. The second terminal of the third transistor T3 is connected to the driving controller and is used to receive the PAM data signal Data_PAM. The control terminal of the third transistor T3 is used to receive the second scan signal S2. The second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is connected to the control terminal of the first transistor T1 and the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the first power supply voltage output terminal. The control terminal of the second transistor T2 is used to receive the second scan signal S2. The first terminal of the first transistor T1 serves as the first terminal of the driving unit 413, the second terminal of the first transistor T1 serves as the second terminal of the driving unit 413, and the control terminal of the first transistor T1 serves as the control terminal of the driving unit 413.

[0093] In some embodiments, the first switching unit 411 includes a fourth transistor T4. The first terminal of the fourth transistor T4 serves as the first terminal of the first switching unit 411 and is connected to the first power supply voltage output terminal. The second terminal of the fourth transistor T4 serves as the second terminal of the first switching unit 411 and is connected to the first terminal of the first transistor T1. The control terminal of the fourth transistor T4 serves as the control terminal of the first switching unit 411 and is connected to the state control module 430 and the light emission duration control module 420.

[0094] In some embodiments, the second switching unit 412 includes a fifth transistor T5. The first terminal of the fifth transistor T5 serves as the first terminal of the second switching unit 412 and is connected to the second terminal of the first transistor T1. The second terminal of the fifth transistor T5 serves as the second terminal of the second switching unit 412 and is connected to the anode of the light-emitting device LED. The cathode of the light-emitting device LED is connected to the ground signal VSS. The control terminal of the fifth transistor T5 serves as the control terminal of the second switching unit 412 and is used to receive the second light-emitting control signal EM2.

[0095] In some embodiments, the drive current control module 410 further includes a first reset transistor T6 and a second reset transistor T7. The first terminal of the first reset transistor T6 is connected to the anode of the LED, the second terminal of the first reset transistor T6 is used to receive a first initialization signal Vref1, and the control terminal of the first reset transistor T6 is used to receive a first scan signal S1. The first terminal of the second reset transistor T7 is connected to the control terminal of the first transistor T1, the second terminal of the second reset transistor T7 is used to receive a second initialization signal Vref2, and the control terminal of the second reset transistor T7 is used to receive the first scan signal S1.

[0096] In some embodiments, the duration control unit 422 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The first terminal of the eighth transistor T8 is connected to the third switching unit 421 and the first terminal of the ninth transistor T9. The second terminal of the ninth transistor T9 is connected to the drive controller and is used to receive the PWM data signal Data_PWM. The control terminal of the ninth transistor T9 is used to receive the third scan signal S3. The second terminal of the eighth transistor T8 is connected to the first terminal of the tenth transistor T10. The second terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the ramp signal output terminal. The control terminal of the tenth transistor T10 is used to receive the third scan signal S3. The first terminal of the eighth transistor T8 serves as the first terminal of the duration control unit 422, the second terminal of the eighth transistor T8 serves as the second terminal of the duration control unit 422, and the control terminal of the eighth transistor T8 serves as the control terminal of the duration control unit 422.

[0097] In some embodiments, the third switching unit 421 includes an eleventh transistor T11. The first terminal of the eleventh transistor T11 serves as the first terminal of the third switching unit 421 and is connected to the second power supply voltage output terminal. The second terminal of the eleventh transistor T11 serves as the second terminal of the third switching unit 421 and is connected to the first terminal of the eighth transistor T8. The control terminal of the eleventh transistor T11 serves as the control terminal of the third switching unit 421 and is used to receive the first light emission control signal EM1.

[0098] In some embodiments, the light emission duration control module 420 further includes a third reset transistor T12, the first terminal of the third reset transistor T12 is connected to the control terminal of the eighth transistor T8, the second terminal of the third reset transistor T12 is used to receive a third initialization signal Vref3, and the control terminal of the third reset transistor T12 is used to receive a first scan signal S1.

[0099] It should be noted that, for the sake of uniformity in manufacturing process and to simplify the subsequent method of driving the pixel circuit, the aforementioned transistors can all be P-type transistors or N-type transistors; no specific limitation is made here. Furthermore, those skilled in the art will understand that, since the signal levels in the pixel circuit differ in different implementation scenarios, for the same transistor, in one implementation scenario the control electrode may be the gate, the first electrode the source, and the second electrode the drain, while in another implementation scenario the control electrode may be the gate, the first electrode the drain, and the second electrode the source. In the embodiments of this application, the first and second electrodes are only used to distinguish the two pins of the transistor other than the gate, and are not otherwise limited. The other embodiments of this application and the accompanying drawings of other embodiments are similar and will not be described again.

[0100] The driving timing of the pixel circuit in the display device provided in the above embodiments will be described in detail below. Taking the example where all the transistors are P-type TFTs and the light-emitting device is a μLED, refer to... Figure 10 The timing diagrams of the signal lines shown are for example... Figure 9 The working principle of the pixel circuit shown is explained in detail. Figure 10 As shown, a display cycle T may include a reset phase (1), a first write phase (2), a second write phase (3), a state control phase (4), and an illumination phase (5) arranged from early to late in time. The data signal refers to the two data signals output by the drive controller in a time-division manner. The first write phase (2) corresponds to the PAM data signal Data_PAM, and the second write phase (3) corresponds to the PWM data signal Data_PWM.

[0101] Reset Phase (1): The first scan signal S1 is a low-level signal. At this time, the first reset transistor T6, the second reset transistor T7, and the third reset transistor T12 are all turned on. The first initial signal Vref1 is input to the anode of the LED through the first reset transistor T6. Since the first initial signal Vref1 is a low-level signal, it can be ensured that the LED is turned off, and the anode level is not affected by the previous cycle. The second initial signal Vref2 is input to node B through the second reset transistor T7. Since the second initial signal Vref2 is a low-level signal, it turns on the first transistor T1. The third initial signal Vref3 is input to node C through the third reset transistor T12. Since the third initial signal Vref3 is a low-level signal, it turns on the eighth transistor T8.

[0102] Since the first light-emitting control signal EM1 is low, the eleventh transistor T11 is turned on. The second power supply voltage signal VDD2 is written to node A through the eleventh transistor T11 and the eighth transistor T8, controlling the fourth transistor T4 to turn off. At this time, the Sweep signal is input to the first terminal of the second capacitor C2, charging the second capacitor C2.

[0103] First write stage (2): The second scan signal S2 is a low-level signal, and both the second transistor T2 and the third transistor T3 are turned on. The PAM data signal Data_PAM is written to node B through the third transistor T3, the first transistor T1, and the second transistor T2, and charges the first capacitor C1. This stage completes the writing of the PAM data signal Data_PAM and threshold voltage compensation.

[0104] In addition, during this stage, the first light-emitting control signal EM1 remains low, and the second power supply voltage signal VDD2 is written to node A via the eleventh transistor T11 and the eighth transistor T8, continuing to control the fourth transistor T4 to turn off, so that the first power supply voltage signal VDD1 does not affect the writing of the PAM data signal Data_PAM.

[0105] Second writing stage (3): The third scan signal S3 is a low-level signal, and both the ninth transistor T9 and the tenth transistor T10 are turned on. The PWM data signal Data_PWM is written to node C through the ninth transistor T9, the eighth transistor T8, and the tenth transistor T10, and charges the second capacitor C2. This stage completes the writing of the PWM data signal Data_PWM and threshold voltage compensation. Moreover, in this stage, the first light-emitting control signal EM1 is a high-level signal, which turns off the eleventh transistor T11, and the second power supply voltage signal VDD2 does not affect the writing of the PWM data signal Data_PWM.

[0106] State control stage (4): The fourth scan signal S4 is a low-level signal, the state control transistor T0 is turned on, and the state control signal Vref0 is written to node A. Since the state control signal Vref0 is a low-level signal, the fourth transistor T4 is turned on, and the storage capacitor C0 is charged. Since the second light-emitting control signal EM2 is a high-level signal in this stage, the fifth transistor T5 is turned off, so the output path of the drive current signal is disconnected, and the light-emitting device LED is still off.

[0107] Light-emitting stage (5): The first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both low-level signals. At this time, the first transistor T1 outputs a driving current based on the first power supply voltage signal VDD1 and the PAM data signal Data_PAM. The driving current flows to the light-emitting device LED through the fifth transistor T5, driving the light-emitting device LED to emit light.

[0108] At the beginning of the light-emitting stage, the eighth transistor T8 is turned off under the action of the PWM data signal Data_PWM. As the light-emitting stage progresses, the Sweep signal value gradually decreases and is coupled to node C through the second capacitor C2, causing the potential of node C to gradually decrease until the eighth transistor T8 turns on. At this time, the second power supply voltage signal VDD2 is written to node A through the eleventh transistor T11 and the eighth transistor T8, controlling the fourth transistor T4 to turn off, thereby stopping the generation of drive current and the light-emitting device LED stops emitting light.

[0109] In the aforementioned pixel circuit, when the second image grayscale of the LED is low, a fixed second PWM data signal keeps the light emission duration constant, while the second PAM data signal, based on the change in the second image grayscale, controls the magnitude of the drive current signal. Thus, while maintaining a constant duty cycle precision, the drive current output to the LED can be adjusted via the second PAM data signal, allowing for fine-tuning of the LED's brightness, resulting in smooth transitions in low grayscale levels and precise control. When the first image grayscale of the LED is medium to high, the first PWM data signal, adjusted according to the image grayscale, can adjust the duration of the output drive current signal, while a fixed first PAM data signal keeps the drive current constant, ensuring uniform light emission in medium to high grayscale levels. Therefore, the display device exhibits excellent image quality in both high and low brightness display modes.

[0110] In some embodiments, such as Figure 11 As shown, the pixel circuit includes a drive current control module 410, an emission duration control module 420, and a switching module 440 connected to the drive controller 300. The emission duration control module 420 is connected to the drive current control module 410 via the switching module 440, and the drive current control module 410 is also connected to the light-emitting device LED. The drive controller 300 is further configured to:

[0111] During the data writing stage, when the gray level of the first image corresponding to the light-emitting device LED is greater than or equal to the first preset gray level value, the preset first PAM data signal is output to the drive current control module 410, and the generated first PWM data signal is output to the light-emitting duration control module 420; when the gray level of the second image corresponding to the light-emitting device LED is less than the first preset gray level value, the generated second PAM data signal is output to the drive current control module 410, and the preset second PWM data signal is output to the light-emitting duration control module 420.

[0112] During the light-emitting stage, the drive current control module 410 outputs a drive current signal corresponding to the PAM data signal Data_PAM to drive the light-emitting device LED. The light-emitting duration control module 420 outputs a light-emitting duration control signal based on the PWM data signal Data_PWM, and controls the switch module 440 to turn on so as to transmit the light-emitting duration control signal to the drive current control module 410.

[0113] The light emission duration control signal is used to regulate the duration for which the drive current control module 410 outputs the drive current signal to drive the LED light-emitting device. The light emission stage is located after the data writing stage.

[0114] In this embodiment, when the image grayscale corresponding to the LED is a low grayscale value less than the first preset grayscale value, the drive controller 300 outputs a fixed PWM data signal Data_PWM to the drive current control module 410 to control the light emission time to be constant. The drive controller 300 also adjusts the PAM data signal Data_PAM according to the image grayscale. Thus, while maintaining the segmentation accuracy of the light emission duration control module 420, the drive current output to the LED can be adjusted by the drive current control module 410 to finely adjust the brightness of the LED, making the low grayscale transition smooth and achieving precise control of the low grayscale. When the image grayscale is a medium-high grayscale value greater than or equal to the first preset grayscale value, the drive controller 300 adjusts the PWM data signal Data_PWM output to the light emission duration control module 420 according to the image grayscale to adjust the light emission duration of the LED. At the same time, the drive controller 300 also outputs a fixed PAM data signal Data_PAM to the drive current control module 410 to make the LED a constant current drive, thereby ensuring the uniformity of light emission at medium-high grayscale.

[0115] Furthermore, a switch module 440 is positioned between the drive current control module 410 and the light emission duration control module 420. During the light emission phase, the connection between the two modules is established; during the non-light emission phase, the connection is disconnected, ensuring independent control of the drive current control module 410 and the light emission duration control module 420. During the data writing phase, PWM data signals Data_PWM and PAM data signals Data_PAM can be input simultaneously or time-divisionally, ensuring that the input of PWM data signal Data_PWM to the light emission duration control module 420 and PAM data signal Data_PAM to the drive current control module 410 do not interfere with each other. During the light emission phase, the connection between the light emission duration control module 420 and the drive current control module 410 is established, allowing the LED to emit light under the combined control of the PAM data signal Data_PAM and the PWM data signal Data_PWM.

[0116] In some embodiments, such as Figure 12 As shown, the switching module 440 includes a switching transistor T13. The first terminal of the switching transistor T13 is connected to the input light emission duration control module 420, the second terminal of the switching transistor T13 is connected to the drive current control module 410, and the control terminal of the switching transistor T13 is connected to the drive controller for receiving a first light emission control signal EM1. During the light emission phase, under the action of the first light emission control signal EM1, the switching transistor T13 is turned on to connect the light emission duration control module 420 and the drive current control module 410. During the non-light emission phase, the switching transistor T13 is turned off to disconnect the connection between the light emission duration control module 420 and the drive current control module 410.

[0117] In this embodiment, the switching module 440 is implemented using a single transistor (switching transistor T13), which has a simple circuit structure, is easy to implement, and is easy to control in terms of cost.

[0118] The structures of the drive current control module 410 and the light emission duration control module 420 can be set with reference to the above embodiments. The difference from the above embodiments is that the specific position of the light emission duration control module 420 connected to the drive current control module 410 via the switch module 440 is different. In this embodiment, the switch module 440 is connected to the control terminal of the drive current control module 410. Specifically, the drive current control module 410 includes a first switch unit 411, a second switch unit 412, and a drive unit 413. The control terminal of the first switch unit 411 is used to receive the second light emission control signal EM2. The first terminal of the first switch unit 411 is connected to the first power supply voltage output terminal to receive the first power supply voltage signal VDD1. The second terminal of the first switch unit 411 is connected to the first terminal of the drive unit 413. The first terminal of the drive unit 413 is also used to receive the PAM data signal Data_PAM. The second terminal of the drive unit 413 is connected to the first terminal of the second switch unit 412. The second terminal of the second switch unit 412 is connected to the light-emitting device LED. The control terminal of the second switch unit 412 is connected to the drive controller to receive the second light emission control signal EM2. The drive controller is specifically configured as follows:

[0119] During the data writing phase, the first switching unit 411 and the second switching unit 412 are turned off (via the second light emission control signal EM2). When the image grayscale is greater than or equal to the first preset grayscale value, a fixed PAM data signal Data_PAM is output to the driving unit 413, and a generated PWM data signal Data_PWM is output to the light emission duration control module 420. When the image grayscale is less than the first preset grayscale value, the generated PAM data signal Data_PAM is output to the driving unit 413, and a fixed PWM data signal Data_PWM is output to the light emission duration control module 420.

[0120] During the light-emitting stage, the first switching unit 411, the second switching unit 412, and the switching module 440 are respectively controlled to be turned on, so that the driving unit 413 outputs a driving current signal corresponding to the PAM data signal Data_PAM according to the first power supply voltage signal VDD1 connected to the first power supply voltage output terminal to drive the light-emitting device LED; and the light-emitting duration control module 420 is controlled to output a light-emitting duration control signal based on the PWM data signal Data_PWM to control the driving unit 413 to stop outputting the driving current signal.

[0121] In this embodiment, when the image grayscale corresponding to the light-emitting device LED is a low grayscale value less than the first preset grayscale value, the drive controller adjusts the PAM data signal Data_PAM according to the image grayscale so that the drive unit 413 outputs the corresponding drive current. Thus, while the segmentation accuracy of the light-emitting duration control module 420 remains unchanged, the drive current output to the light-emitting device LED can be adjusted by the drive unit 413 to finely adjust the brightness of the light-emitting device LED, making the low grayscale transition delicate and achieving precise control of the low grayscale.

[0122] The light emission duration control module 420 includes a third switching unit 421 and a duration control unit 422. The control terminal of the third switching unit 421 is connected to the drive controller and is used to receive the first light emission control signal EM1. The first terminal of the third switching unit 421 is connected to the second power supply voltage output terminal to receive the second power supply voltage signal VDD2. The second terminal of the third switching unit 421 is connected to the first terminal of the duration control unit 422, which is also used to receive the PWM data signal Data_PWM. The second terminal of the duration control unit 422 is connected to the switching module 440. The drive controller is also configured to:

[0123] During the data writing phase, the third switch unit 421 is turned off. During the light emission phase, the duration control unit 422 outputs a light emission duration control signal based on the PWM data signal Data_PWM. The light emission duration control signal is used by the switch module 440 to regulate the duration of the drive current signal output by the drive unit 413.

[0124] In some embodiments, the driving unit 413 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. The first terminal of the first transistor T1 is connected to the first switching unit 411 and the first terminal of the third transistor T3. The second terminal of the third transistor T3 is connected to the driving controller and is used to receive the PAM data signal Data_PAM. The control terminal of the third transistor T3 is used to receive the third scan signal S3. The second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is connected to the control terminal of the first transistor T1 and the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the first power supply voltage output terminal. The control terminal of the second transistor T2 is used to receive the third scan signal S3. The first terminal of the first transistor T1 serves as the first terminal of the driving unit 413, the second terminal of the first transistor T1 serves as the second terminal of the driving unit 413, and the control terminal of the first transistor T1 serves as the control terminal of the driving unit 413.

[0125] In some embodiments, the first switching unit 411 includes a fourth transistor T4. The first terminal of the fourth transistor T4 serves as the first terminal of the first switching unit 411 and is connected to the first power supply voltage output terminal. The second terminal of the fourth transistor T4 serves as the second terminal of the first switching unit 411 and is connected to the first terminal of the first transistor T1. The control terminal of the fourth transistor T4 is used to receive the second light emission control signal EM2.

[0126] In some embodiments, the second switching unit 412 includes a fifth transistor T5. The first terminal of the fifth transistor T5 serves as the first terminal of the second switching unit 412 and is connected to the second terminal of the first transistor T1. The second terminal of the fifth transistor T5 serves as the second terminal of the second switching unit 412 and is connected to the anode of the light-emitting device LED. The cathode of the light-emitting device LED is connected to the ground signal VSS. The control terminal of the fifth transistor T5 serves as the control terminal of the second switching unit 412 and is used to receive the second light-emitting control signal EM2.

[0127] In some embodiments, the drive current control module 410 further includes a first reset transistor T6 and a second reset transistor T7. The first terminal of the first reset transistor T6 is connected to the anode of the LED, the second terminal of the first reset transistor T6 is used to receive a first initialization signal Vref1, and the control terminal of the first reset transistor T6 is used to receive a first scan signal S1. The first terminal of the second reset transistor T7 is connected to the control terminal of the first transistor T1, the second terminal of the second reset transistor T7 is used to receive a second initialization signal Vref2, and the control terminal of the second reset transistor T7 is used to receive the first scan signal S1.

[0128] In some embodiments, the duration control unit 422 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The first terminal of the eighth transistor T8 is connected to the third switching unit 421 and the first terminal of the ninth transistor T9. The second terminal of the ninth transistor T9 is connected to the drive controller and is used to receive the PWM data signal Data_PWM. The control terminal of the ninth transistor T9 is used to receive the second scan signal S2. The second terminal of the eighth transistor T8 is connected to the first terminal of the tenth transistor T10. The second terminal of the tenth transistor T10 is connected to the control terminal of the eighth transistor T8 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the slope signal (Sweep) output terminal. The control terminal of the tenth transistor T10 is used to receive the second scan signal S2. The first terminal of the eighth transistor T8 serves as the first terminal of the duration control unit 422, the control terminal of the eighth transistor T8 serves as the control terminal of the duration control unit 422, and the second terminal of the eighth transistor T8 serves as the second terminal of the duration control unit 422 and is connected to the switching module 440.

[0129] In some embodiments, the third switching unit 421 includes an eleventh transistor T11. The first terminal of the eleventh transistor T11 serves as the first terminal of the third switching unit 421 and is connected to the second power supply voltage output terminal. The second terminal of the eleventh transistor T11 serves as the second terminal of the third switching unit 421 and is connected to the first terminal of the eighth transistor T8. The control terminal of the eleventh transistor T11 serves as the control terminal of the third switching unit 421 and is used to receive the first light emission control signal EM1.

[0130] In some embodiments, the light emission duration control module 420 further includes a third reset transistor T12, the first terminal of the third reset transistor T12 is connected to the control terminal of the eighth transistor T8, the second terminal of the third reset transistor T12 is used to receive a third initialization signal Vref3, and the control terminal of the third reset transistor T12 is used to receive a first scan signal S1.

[0131] It should be noted that the data writing stage includes a first writing stage and a second writing stage, with the second writing stage following the first writing stage. In some embodiments, the drive controller is configured to: output a PAM data signal Data_PAM to the drive current control module 410 in the first writing stage; and output a PWM data signal Data_PWM to the light emission duration control module 420 in the second writing stage. Because the capacitor in the drive current control module 410 has a larger capacitance, the leakage current of writing the PAM data signal Data_PAM first is smaller, resulting in a more precise drive current for the subsequent light emission stage and more reliable light emission control. In other embodiments, the PWM data signal Data_PWM can also be output to the light emission duration control module 420 in the first writing stage and the PAM data signal Data_PAM to the drive current control module 410 in the second writing stage. When the drive controller adjusts the timing of writing the PWM data signal Data_PWM and the PAM data signal Data_PAM in a time-division manner, this can be specifically achieved by adjusting the second scan signal S2 and the third scan signal S3. For example, in the scenario where the PWM data signal Data_PWM is output during the first write phase and the PAM data signal Data_PAM is output during the second write phase, the second scan signal S2 is effective before the third scan signal S3. In the scenario where the PAM data signal Data_PAM is output during the first write phase and the PWM data signal Data_PWM is output during the second write phase, the third scan signal S3 is effective before the second scan signal S2.

[0132] The following example uses P-type TFTs as all the transistors and μLEDs as the light-emitting device. Figures 13-14 The timing diagrams of the signal lines shown are for example... Figure 12 The working principle of the pixel circuit shown is explained in detail. A display cycle T may include a reset phase (1), a first write phase (2), a second write phase (3), and a light emission phase (4) arranged in order of time from early to late. Figure 13 The timing diagram is for the image grayscale corresponding to the light-emitting device LED when the grayscale is low. The data signal refers to the two data signals output by the drive controller in a time-division manner. The first writing stage (2) corresponds to the PWM data signal Data_PWM with preset voltage, and the second writing stage (3) corresponds to the PAM data signal Data_PAM with voltage value divided according to different grayscale (the dotted line in the figure indicates that the voltage value can be divided into different values). Figure 14The timing diagram is for the image grayscale corresponding to the light-emitting device LED when it is medium to high grayscale. The first writing stage (2) corresponds to the PWM data signal Data_PWM, which is divided into different grayscale values ​​according to the voltage value (the dotted line in the figure indicates that the voltage value can be divided into different values). The second writing stage (3) corresponds to the PAM data signal Data_PAM with preset voltage.

[0133] Reset Phase (1): The first scan signal S1 is a low-level signal. At this time, the first reset transistor T6, the second reset transistor T7, and the third reset transistor T12 are all turned on. The first initial signal Vref1 is input to the anode of the LED through the first reset transistor T6. Since the first initial signal Vref1 is a low-level signal, it can be ensured that the LED is turned off, and the anode level is not affected by the previous cycle. The second initial signal Vref2 is input to node B through the second reset transistor T7. Since the second initial signal Vref2 is a low-level signal, the first transistor T1 is turned on. The third initial signal Vref3 is input to node C through the third reset transistor T12. Since the third initial signal Vref3 is a low-level signal, the eighth transistor T8 is turned on. At this time, the Sweep signal is input to the first terminal of the second capacitor C2 to charge the second capacitor C2, preparing for the subsequent change of the potential of node C through capacitive coupling in the light-emitting phase.

[0134] First writing stage (2): The second scan signal S2 is a low-level signal, and both the ninth transistor T9 and the tenth transistor T10 are turned on. The PWM data signal Data_PWM is written to node C through the ninth transistor T9, the eighth transistor T8, and the tenth transistor T10, and charges the second capacitor C2. This process continues until the voltage of node C is VC = VData_PWM + Vth1, at which point the eighth transistor T8 will be turned off. Here, Vth1 represents the threshold voltage of the eighth transistor T8. This stage completes the writing of the PWM data signal Data_PWM and threshold voltage compensation. Moreover, during this stage, the first light-emitting control signal EM1 is a high-level signal, which turns off the eleventh transistor T11. The second power supply voltage signal VDD2 does not affect the writing of the PWM data signal Data_PWM.

[0135] Furthermore, under the action of the first light-emitting control signal EM1, the switching transistor T13 is turned off, and the duration control unit 422 and the driving unit 413 will not affect each other.

[0136] Second writing stage (3): The third scan signal S3 is a low-level signal, and both the second transistor T2 and the third transistor T3 are turned on. The PAM data signal Data_PAM is written to node B through the third transistor T3, the first transistor T1, and the second transistor T2, and charges the first capacitor C1. This process continues until the voltage of node B is VB = VData_PAM + Vth2, at which point the first transistor T1 will be turned off. Here, Vth2 represents the threshold voltage of the first transistor T1. This stage completes the writing of the PAM data signal Data_PAM and threshold voltage compensation. Moreover, during this stage, the second light emission control signal EM2 is a high-level signal, the fourth transistor T4 is turned off, and the first power supply voltage signal VDD1 does not affect the writing of the PAM data signal Data_PAM.

[0137] Furthermore, when the first light-emitting control signal EM1 is a high-level signal, the switching transistor T13 remains in the off state, and the duration control unit 422 and the driving unit 413 will not affect each other.

[0138] Light-emitting stage (4): Both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are low-level signals. At this time, the first transistor T1 outputs a drive current based on the first power supply voltage signal VDD1 and the PAM data signal Data_PAM. The drive current flows to the light-emitting device LED through the fifth transistor T5, driving the light-emitting device LED to emit light. Under the action of the first light-emitting control signal EM1, the switching transistor T13 is turned on.

[0139] When the light-emitting stage begins, the eighth transistor T8 is turned off under the action of the PWM data signal Data_PWM. As the light-emitting stage progresses, the Sweep signal value gradually decreases and is coupled to node C through the second capacitor C2, causing the potential of node C to gradually decrease until the eighth transistor T8 turns on. At this time, the first power supply voltage signal VDD1 is written to node B through the eleventh transistor T11, the eighth transistor T8, and the switching transistor T13, controlling the first transistor T1 to turn off, thereby stopping the output drive current, and the light-emitting device LED stops emitting light.

[0140] In the pixel circuit described above, when the image grayscale is low, a fixed PWM data signal (Data_PWM) keeps the light emission duration constant, while a PAM data signal (Data_PAM) that changes according to the image grayscale controls the magnitude of the drive current signal. Therefore, while maintaining a constant duty cycle precision, the drive current output to the LED can be adjusted via the PAM data signal (Data_PAM), allowing for fine-tuning of the LED's brightness and resulting in smooth transitions at low grayscale levels, achieving precise control. When the image grayscale is medium to high, the PWM data signal (Data_PWM) adjusted according to the image grayscale can regulate the duration of the output drive current signal, while the fixed PAM data signal (Data_PAM) keeps the drive current constant, ensuring uniform light emission at medium to high grayscale levels. Thus, the display device exhibits excellent image quality in both high and low brightness display scenarios.

[0141] It should be noted that, in the embodiments of this application, "display device" refers to any device with screen display and data processing capabilities. For example, display devices include, but are not limited to, smart TVs, mobile terminals, computers, monitors, advertising screens, wearable devices, virtual reality devices, and augmented reality devices.

[0142] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display device, characterized in that, The display device includes: The display panel includes light-emitting devices for constituting display pixels and pixel circuits connected to the light-emitting devices; A drive controller is connected to the pixel circuit; the drive controller is configured to: When the gray level of the first image corresponding to the light-emitting device is greater than or equal to a first preset gray level value, a corresponding first PWM data signal is generated according to the preset first PAM data signal and the first image gray level, so as to drive the pixel circuit according to the first PAM data signal and the generated first PWM data signal; wherein, the first PAM data signal corresponding to different first image gray levels is the same, the first image gray level corresponding to different first PWM data signals is different, and the same first PAM data signal indicates that the pixel circuit drives the light-emitting device with a constant driving current. When the gray level of the second image corresponding to the light-emitting device is less than the first preset gray level value, a corresponding second PAM data signal is generated according to the preset second PWM data signal and the gray level of the second image, so as to drive the pixel circuit according to the second PWM data signal and the generated second PAM data signal; wherein, the second PWM data signal corresponding to different gray levels of the second image is the same, the second image gray level corresponding to different second PAM data signals is different, and the same second PWM data signal indicates that the pixel circuit drives the light-emitting device with a constant driving duration.

2. The display device according to claim 1, characterized in that, When the gray level of the second image corresponding to the light-emitting device is less than the first preset gray level value and greater than or equal to the second preset gray level value, the voltage value of the second PWM data signal is the first preset PWM voltage value. The second preset grayscale value is less than the first preset grayscale value; When the grayscale of the second image is less than the second preset grayscale value, the voltage value of the second PWM data signal is the second preset PWM voltage value; wherein, when the second PWM data signal is the second preset PWM voltage value, the duration for which the pixel circuit outputs the drive current signal to drive the light-emitting device is less than the duration for which the pixel circuit outputs the drive current signal to drive the light-emitting device when the second PWM data signal is the first preset PWM voltage value.

3. The display device according to claim 1, characterized in that, When the gray level of the first image corresponding to the light-emitting device is greater than or equal to the first preset gray level value, the maximum voltage value of the generated first PWM data signal is the first PWM voltage limit value corresponding to the first preset gray level value, and the minimum voltage value of the first PWM data signal is the second PWM voltage limit value corresponding to the maximum value of the first image gray level. When the grayscale of the second image corresponding to the light-emitting device is less than the first preset grayscale value, the voltage value of the second PWM data signal is between the first PWM voltage limit and the second PWM voltage limit.

4. The display device according to claim 1, characterized in that, The voltage value of the first PAM data signal is a preset voltage value, which is less than the minimum voltage value of the second PAM data signal.

5. The display device according to claim 1, characterized in that, The pixel circuit includes a drive current control module, an emission duration control module, and a state control module connected to the drive controller. The drive current control module is connected to the emission duration control module, the state control module, and the light-emitting device. The drive controller is configured to: During the data writing stage, when the gray level of the first image corresponding to the light-emitting device is greater than or equal to the first preset gray level value, the first PAM data signal is output to the driving current control module, and the generated first PWM data signal is output to the light emission duration control module. When the grayscale of the second image corresponding to the light-emitting device is less than the first preset grayscale value, the generated second PAM data signal is output to the driving current control module, and the second PWM data signal is output to the light emission duration control module. During the state control phase, the state control module is controlled to conduct the output path of the drive current signal of the drive current control module according to the state control signal, and the state control module is controlled to store the amount of charge corresponding to the state control signal, so that the output path is kept on during the light emission phase based on the stored charge; the state control phase is after the data writing phase, and the light emission phase is after the state control phase. During the light-emitting stage, the drive current control module outputs a drive current signal corresponding to the PAM data signal to drive the light-emitting device, and the light-emitting duration control module outputs a light-emitting duration control signal based on the PWM data signal. The light-emitting duration control signal is used to control the output path to disconnect, so as to regulate the duration for which the drive current control module outputs the drive current signal to drive the light-emitting device. The PAM data signal and the PWM data signal are respectively the first PAM data signal and the first PWM data signal corresponding to the gray level of the first image, or the second PAM data signal and the second PWM data signal corresponding to the gray level of the second image.

6. The display device according to claim 5, characterized in that, The drive current control module includes: a first switching unit, a second switching unit, and a drive unit; the control terminal of the first switching unit is connected to the state control module and the light emission duration control module; the first terminal of the first switching unit is connected to the first power supply voltage output terminal; the second terminal of the first switching unit is connected to the first terminal of the drive unit; the first terminal of the drive unit is also used to receive the PAM data signal; the second terminal of the drive unit is connected to the first terminal of the second switching unit; the second terminal of the second switching unit is connected to the light-emitting device; the control terminal of the second switching unit is connected to the drive controller; the drive controller is configured to: During the data writing phase, the first switching unit is turned off by the light emission duration control module; and when the gray level of the first image corresponding to the light-emitting device is greater than or equal to the first preset gray level value, the first PAM data signal is output to the driving unit and the first PWM data signal is output to the light emission duration control module; when the gray level of the second image corresponding to the light-emitting device is less than the first preset gray level value, the generated second PAM data signal is output to the driving unit and the second PWM data signal is output to the light emission duration control module. During the state control phase, the state control module is controlled to turn on the first switching unit according to the state control signal. During the light emission phase, the state control module keeps the first switching unit in the on state based on the stored charge. During the light-emitting phase, the second switching unit is controlled to be turned on, so that the driving unit outputs a driving current signal corresponding to the PAM data signal according to the first power supply voltage signal connected to the first power supply voltage output terminal to drive the light-emitting device; and the light-emitting duration control module is controlled to output a light-emitting duration control signal based on the PWM data signal to control the first switching unit to be turned off.

7. The display device according to claim 6, characterized in that, The light emission duration control module includes: a third switching unit and a duration control unit; the control terminal of the third switching unit is connected to the drive controller, the first terminal of the third switching unit is connected to the second power supply voltage output terminal, the second terminal of the first switching unit is connected to the first terminal of the duration control unit, the first terminal of the duration control unit is also used to receive the PWM data signal, and the second terminal of the duration control unit is connected to the control terminal of the first switching unit; the drive controller is further configured to: During the data writing phase, the third switch unit is turned on so that the first switch unit is turned off by the second power supply voltage signal connected to the second power supply voltage output terminal. During the light-emitting phase, the duration control unit outputs a light-emitting duration control signal based on the PWM data signal to regulate the duration for which the driving current signal drives the light-emitting device.

8. The display device according to claim 6, characterized in that, The state control module includes a state control transistor and a storage capacitor. A first terminal of the storage capacitor is connected to a first terminal of the first switching unit. A second terminal of the storage capacitor is connected to both the control terminal of the first switching unit and the first electrode of the state control transistor. The second electrode of the state control transistor is connected to the state control signal output terminal. The control electrode of the state control transistor is connected to the drive controller. The drive controller is configured to: During the state control phase, the state control transistor is turned on, the state control signal input to the state control signal output terminal is transmitted to the control terminal of the first switching unit, and the charge of the state control signal is stored in the storage capacitor.

9. The display device according to claim 1, characterized in that, The pixel circuit includes a drive current control module, an emission duration control module, and a switching module connected to the drive controller. The emission duration control module is connected to the drive current control module via the switching module, and the drive current control module is also connected to the light-emitting device. The drive controller is further configured to: During the data writing stage, when the gray level of the first image corresponding to the light-emitting device is greater than or equal to the first preset gray level value, the first PAM data signal is output to the driving current control module, and the generated first PWM data signal is output to the light emission duration control module. When the grayscale of the second image corresponding to the light-emitting device is less than the first preset grayscale value, the generated second PAM data signal is output to the driving current control module, and the second PWM data signal is output to the light emission duration control module. During the light-emitting phase, the drive current control module outputs a drive current signal corresponding to the PAM data signal to drive the light-emitting device, and the light-emitting duration control module outputs a light-emitting duration control signal based on the PWM data signal. The switch module is then turned on to transmit the light-emitting duration control signal to the drive current control module. The light-emitting duration control signal is used to regulate the duration for which the drive current control module outputs the drive current signal to drive the light-emitting device. The light-emitting phase occurs after the data writing phase. The PAM data signal and the PWM data signal are respectively the first PAM data signal and the first PWM data signal corresponding to the grayscale of the first image, or respectively the second PAM data signal and the second PWM data signal corresponding to the grayscale of the second image.

10. The display device according to any one of claims 5 to 9, characterized in that, The data writing phase includes a first writing phase and a second writing phase, with the second writing phase following the first writing phase; the drive controller is configured to: In the first writing stage, the PAM data signal is output to the drive current control module; in the second writing stage, the PWM data signal is output to the light emission duration control module.

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