Display substrate and display device

Abstract

The present application relates to the technical field of display, especially to display substrate and display device, for avoiding color deviation and gray scale transition uneven phenomenon of low gray scale. The display substrate comprises pixel circuit, first scanning signal line, second scanning signal line and data line. The switch transistor is coupled with the data line and the first scanning signal line. The compensation transistor is coupled with the second scanning signal line and coupled with the drive transistor through the connecting line. The switch transistor and the drive transistor are P-type transistors, and the compensation transistor is N-type transistor; the connecting line and the first scanning signal line form the first capacitor, and the connecting line and the second scanning signal line form the second capacitor; the capacitance of the first capacitor of the first pixel circuit is smaller than the capacitance of the first capacitor of the second pixel circuit; and / or the capacitance of the second capacitor of the first pixel circuit is greater than the capacitance of the second capacitor of the second pixel circuit. The display substrate and the display device are used for image display.

Description

[0001] This application is a divisional application. The original application has the application number 202210169911.1 and the original application date is February 23, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diode (OLED) display technology is a technology that uses light-emitting materials to emit light when driven by an electric current to achieve display. OLED displays have advantages such as being ultra-lightweight, ultra-thin, high-brightness, wide viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing process, use of fewer raw materials, high luminous efficiency, and wide temperature range. Summary of the Invention

[0004] The purpose of this invention is to avoid color shift and uneven grayscale transition at low grayscale levels, thereby improving the display quality of the display substrate and display device.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions: This invention provides a display substrate comprising: multiple pixel circuits, multiple first scan signal lines, multiple second scan signal lines, and multiple data lines. Each pixel circuit includes: a connecting line, a switching transistor, a driving transistor, and a compensation transistor. The first terminal of the switching transistor is coupled to the data line, the gate of the switching transistor is coupled to the first scan signal line, the gate of the compensation transistor is coupled to the second scan signal line, and the second terminal of the compensation transistor is coupled to the gate of the driving transistor via the connecting line. The switching transistor and the driving transistor are P-type transistors, and the compensation transistor is an N-type transistor. The connecting line is partially opposite to the first scan signal line, and the two together form a first capacitor. The connecting line is partially opposite to the second scan signal line, and the two together form a second capacitor. Each pixel circuit includes: a first pixel circuit and a second pixel circuit. The capacitance of the first capacitor in the first pixel circuit is less than the capacitance of the first capacitor in the second pixel circuit; and / or, the capacitance of the second capacitor in the first pixel circuit is greater than the capacitance of the second capacitor in the second pixel circuit.

[0006] The display substrate provided in some embodiments of the present invention, by setting pixel circuits, first scan signal lines, second scan signal lines and data lines, and setting connecting lines in the pixel circuits such that the connecting lines are partially aligned with the first scan signal lines and the two form a first capacitor, and the connecting lines are partially aligned with the second scan signal lines and the two form a second capacitor, in order to increase the actual black state voltage required by the first pixel circuit coupled to the first light-emitting device, and decrease the difference between the actual black state required by the first pixel circuit coupled to the first light-emitting device and the actual black state required by the second pixel circuit coupled to the second light-emitting device, thereby reducing the difference between the actual black state voltage required by the first pixel circuit coupled to the first light-emitting device and the preset black state voltage provided by the display driver IC. Furthermore, after setting and calculating the white state voltage and the black state voltage, the color shift phenomenon and the uneven grayscale transition phenomenon of the display substrate at low grayscale levels can be weakened or even eliminated.

[0007] In some embodiments, when the capacitance of the first capacitor in the first pixel circuit is less than the capacitance of the first capacitor in the second pixel circuit, the area of ​​the opposite portion of the connecting line and the first scan signal line in the first pixel circuit is less than the area of ​​the opposite portion of the connecting line and the first scan signal line in the second pixel circuit.

[0008] In some embodiments, the area of ​​the opposite portion of the connecting line and the first scan signal line in the first pixel circuit is α, and the area of ​​the opposite portion of the connecting line and the first scan signal line in the second pixel circuit is 1:10≤α<1:1.

[0009] In some embodiments, when the capacitance of the second capacitor in the first pixel circuit is greater than the capacitance of the second capacitor in the second pixel circuit, the area of ​​the opposite portion of the connecting line and the second scan signal line in the first pixel circuit is greater than the area of ​​the opposite portion of the connecting line and the second scan signal line in the second pixel circuit.

[0010] In some embodiments, the ratio of the area of ​​the opposite portion of the connecting line and the second scan signal line in the first pixel circuit to the area of ​​the opposite portion of the connecting line and the second scan signal line in the second pixel circuit is β, where 1:1 < β ≤ 10:1.

[0011] In some embodiments, the display substrate further includes: a substrate, wherein a first conductive layer, a first active layer, a second conductive layer, a third conductive layer, and a fourth conductive layer are sequentially stacked on one side of the substrate; the connection line includes: a first connection line and a second connection line coupled to the first connection line; the first connection line is located in the first active layer, and the first scan signal line is located in the first conductive layer; the first connection line and the first scan signal line are partially opposite each other, and the two constitute the first parasitic capacitance; the second connection line is located in the fourth conductive layer, and the second scan signal line includes a first sub-scanning signal line and a second sub-scanning signal line; the first sub-scanning signal line is located in the second conductive layer, and the second sub-scanning signal line is located in the third conductive layer; the second connection line and the second scan signal line are partially opposite each other, and the two constitute the second parasitic capacitance.

[0012] In some embodiments, the first scan signal line extends along a first direction; when the capacitance of the first capacitor of the first pixel circuit is less than the capacitance of the first capacitor of the second pixel circuit, the portion of the first scan signal line facing the first connection line of the first pixel circuit has a dimension in a second direction that is smaller than the portion of the first connection line of the second pixel circuit facing the first connection line of the second pixel circuit in a second direction; the first direction and the second direction are perpendicular to each other.

[0013] In some embodiments, the first scan signal line extends along a first direction; when the capacitance of the first capacitor of the first pixel circuit is less than the capacitance of the first capacitor of the second pixel circuit, the size of the portion of the first connection line of the first pixel circuit facing the first scan signal line in the first direction is less than the size of the portion of the first connection line of the second pixel circuit facing the first scan signal line in the first direction; and / or, the size of the portion of the first connection line of the first pixel circuit facing the first scan signal line in the second direction is less than the size of the portion of the first connection line of the second pixel circuit facing the first scan signal line in the second direction; the first direction and the second direction are perpendicular to each other.

[0014] In some embodiments, the second scan signal line extends along a first direction; when the capacitance of the second capacitor of the first pixel circuit is greater than the capacitance of the second capacitor of the second pixel circuit, the size of the portion of the second connection line of the first pixel circuit that is directly opposite to the second scan signal line in the first direction is greater than the size of the portion of the second connection line of the second pixel circuit that is directly opposite to the second scan signal line in the first direction.

[0015] In some embodiments, the size of the portion of the second sub-scan signal line that is directly opposite the second connection line of the first pixel circuit in the second direction is equal to the size of the portion of the second connection line of the second pixel circuit in the second direction; the first direction and the second direction are perpendicular to each other.

[0016] In some embodiments, the second scan signal line extends along a first direction; when the capacitance of the second capacitor of the first pixel circuit is greater than the capacitance of the second capacitor of the second pixel circuit, the size of the portion of the second sub-scan signal line that is directly opposite the second connection line of the first pixel circuit in the first direction is greater than the size of the portion that is directly opposite the second connection line of the second pixel circuit in the first direction; the first direction and the second direction are perpendicular to each other.

[0017] In some embodiments, the display substrate further includes: a second active layer disposed between the substrate and the first conductive layer; the switching transistor includes a first active pattern and a first gate pattern, the driving transistor includes a second active pattern and a second gate pattern, and the compensation transistor includes a third active pattern, a third gate pattern, and a fourth gate pattern; the first active pattern and the second active pattern are located in the second active layer and are connected to each other to form an integral structure; the first gate pattern and the second gate pattern are located in the first conductive layer, and the first gate pattern is connected to the first scan signal line to form an integral structure; the third active pattern is located in the first active layer, the third gate pattern is located in the second conductive layer, and the third gate pattern is connected to the first sub-scan signal line to form an integral structure; the fourth gate pattern is located in the third conductive layer, and the fourth gate pattern is connected to the second sub-scan signal line to form an integral structure.

[0018] In some embodiments, the display substrate further includes: multiple reset signal lines, multiple voltage signal lines, multiple first initial signal lines, multiple second initial signal lines, and multiple enable signal lines; the pixel circuit further includes: a first reset transistor, a second reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a storage capacitor; the gate of the first reset transistor is coupled to the reset signal lines, the first electrode of the first reset transistor is coupled to the first initial signal lines, and the second electrode of the first reset transistor is coupled to the connection line; the gate of the first light-emitting control transistor is coupled to the enable signal lines, and the first electrode of the first light-emitting control transistor is coupled to the enable signal lines. The voltage signal line is coupled, the second terminal of the first light-emitting control transistor is coupled to the first terminal of the driving transistor; the gate of the second light-emitting control transistor is coupled to the enable signal line, the first terminal of the second light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is coupled to the first node; the gate of the second reset transistor is coupled to the first scan signal line, the first terminal of the second reset transistor is coupled to the second initial signal line, and the second terminal of the second reset transistor is coupled to the first node; the first plate of the storage capacitor is coupled to the voltage signal line, and the second plate of the storage capacitor is coupled to the connection line.

[0019] In some embodiments, the compensation transistor and the first reset transistor are both oxide transistors, and the switching transistor, the driving transistor, the second reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor are all low-temperature polycrystalline silicon transistors.

[0020] In some embodiments, the display substrate further includes a plurality of light-emitting devices; the plurality of light-emitting devices include: a first light-emitting device and a second light-emitting device; the first light-emitting device is coupled to the first pixel circuit and configured to emit green light under the action of the first pixel circuit; the second light-emitting device is coupled to the second pixel circuit and configured to emit red light or blue light under the action of the second pixel circuit.

[0021] In some embodiments, the second light-emitting device includes a first type of light-emitting device and a second type of light-emitting device, wherein the first type of light-emitting device is configured to emit red light and the second type of light-emitting device is configured to emit green light; the plurality of light-emitting devices are arranged in multiple rows and columns. Along a first direction, first light-emitting device columns and second light-emitting device columns are arranged alternately; along a second direction, first light-emitting device rows and second light-emitting device rows are arranged alternately. Specifically, each first light-emitting device column includes first light-emitting devices and first type of light-emitting devices arranged alternately in sequence; each first light-emitting device row includes first light-emitting devices and first type of light-emitting devices arranged alternately in sequence; each second light-emitting device column includes a plurality of second type of light-emitting devices arranged alternately in sequence; and each second light-emitting device row includes a plurality of second type of light-emitting devices arranged alternately in sequence. The first direction and the second direction are perpendicular to each other.

[0022] In some embodiments, the light-emitting device includes a light-emitting layer, and the orthographic projection shape of the light-emitting layer on the plane of the display substrate includes a polygon. At least one apex of the light-emitting layer of the first light-emitting device is an arc-shaped apex; along the direction from the first type of light-emitting device to the adjacent first light-emitting device, the arc-shaped apex of the light-emitting layer of the first light-emitting device is farther away from the first type of light-emitting device than the other apex angles; the shape of the area enclosed by the light-emitting layers of the plurality of first light-emitting devices adjacent to the first type of light-emitting device is a rounded quadrilateral.

[0023] This invention also provides a display device, which includes a display substrate as described in any of the above embodiments.

[0024] The beneficial effects that the display device provided in some embodiments of the present invention can achieve are the same as the beneficial effects that the display substrate provided in some embodiments above can achieve, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of this invention, the accompanying drawings used in some embodiments of this invention will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this invention, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this invention.

[0026] Figure 1 This is a structural diagram of a display device according to some embodiments of the present invention; Figure 2 This is a structural diagram of a display substrate according to some embodiments of the present invention; Figure 3This is an equivalent diagram of a pixel circuit and a light-emitting device according to some embodiments of the present invention; Figure 4a This is a structural diagram of a display substrate according to some embodiments of the present invention; Figure 4b This is a structural diagram of another display substrate according to some embodiments of the present invention; Figure 4c This is a structural diagram of another display substrate according to some embodiments of the present invention; Figure 5a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 5b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 5c This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 6a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 6b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 6c This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 7 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 8 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 9 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 10a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 10b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 11 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 12a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 12b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 13a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 13b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 14a This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 14b This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 15 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 16 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 17 This is a top view of some film layers in a display substrate according to some embodiments of the present invention; Figure 18 This is a top view of some film layers in a display substrate according to some embodiments of the present invention. Detailed Implementation

[0027] The technical solutions in some embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0029] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0030] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0031] The use of “configured as” in this article implies an open and inclusive language that does not preclude devices from being configured to perform additional tasks or steps.

[0032] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0033] In this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0034] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0035] In the circuit structure (e.g., pixel circuit) provided in the embodiments of the present invention, the transistor used in the circuit structure can be a thin film transistor (TFT), a metal oxidized semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of the present invention, thin film transistors are used as an example for illustration.

[0036] In the circuit structure provided in the embodiments of the present invention, the first electrode of each transistor is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistors in the embodiments of the present invention can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0037] In the circuit structure provided by the embodiments of the present invention, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0038] In this invention, the P-type transistor can be turned on under the control of a low-level signal, and the N-type transistor can be turned on under the control of a high-level signal.

[0039] like Figure 1 As shown, some embodiments of the present invention provide a display device 2000, which includes a display substrate 1000.

[0040] In some examples, the aforementioned display device 2000 may be, for example, an OLED (Organic Light Emitting Diode) display device.

[0041] For example, the display device 2000 also includes a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0042] For example, the aforementioned display device 2000 can be any display device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the display device of the described embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0043] In some examples, such as Figure 2 As shown, the display substrate 1000 includes: a substrate 100, a plurality of pixel circuits 200 disposed on one side of the substrate 100, and a plurality of light-emitting devices 300 disposed on the side of the plurality of pixel circuits 200 away from the substrate 100.

[0044] For example, the substrate 100 described above can be a flexible substrate or a rigid substrate.

[0045] For example, when the substrate 100 is a flexible substrate, the material of the substrate 100 can be a highly elastic material such as dimethylsiloxane, PI (polyimide), or PET (polyethylene terephthalate).

[0046] For example, when the substrate 100 is a rigid substrate, the material of the substrate 100 can be glass or the like.

[0047] In some examples, the plurality of pixel circuits 200 and the plurality of light-emitting devices 300 can be coupled one-to-one. In other examples, one pixel circuit 200 can be coupled to multiple light-emitting devices 300, or multiple pixel circuits 200 can be coupled to one light-emitting device 300.

[0048] The present invention will now illustrate the structure of the display substrate 1000 by taking the coupling of a pixel circuit 200 and a light-emitting device 300 as an example.

[0049] For example, in the display substrate 1000, each light-emitting device 300 can emit light under the driving action of the corresponding pixel circuit 200. The light emitted by multiple light-emitting devices 300 cooperates with each other, thereby enabling the display substrate 1000 to realize the display function.

[0050] In some examples, the pixel circuit 200 has various structures, which can be selected and set according to actual needs. For example, the structure of the pixel circuit 200 may include "6T1C", "7T1C", "6T2C" or "7T2C" etc. Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0051] For example, this invention uses a "7T1C" structure for the pixel circuit 200 as an example for explanation. Wherein, Figure 3 The equivalent circuit diagram of pixel circuit 200 is shown.

[0052] Understandably, during the operation of the pixel circuit 200, signal lines are required to provide corresponding electrical signals.

[0053] For example, such as Figures 4a-4cAs shown, the display substrate 1000 further includes: multiple first scan signal lines GateP, multiple second scan signal lines GateN, multiple data lines Data, multiple reset signal lines ResetN, multiple voltage signal lines VDD, multiple first initial signal lines Vinit1, multiple second initial signal lines Vinit2, and multiple enable signal lines EM. Specifically, the first scan signal line GateP is used to transmit a first scan signal, the second scan signal line GateN is used to transmit a second scan signal, the data line Data is used to transmit a data signal, the reset signal line ResetN is used to transmit a reset signal, the voltage signal line VDD is used to transmit a voltage signal, the first initial signal line Vinit1 is used to transmit a first initial signal, the second initial signal line Vinit2 is used to transmit a second initial signal, and the enable signal line EM is used to transmit an enable signal.

[0054] For example, the aforementioned multiple first scan signal lines GateP, multiple second scan signal lines GateN, multiple reset signal lines Reset, multiple voltage signal lines VDD, multiple first initial signal lines Vinit1, multiple second initial signal lines Vinit2, and multiple enable signal lines EM can all extend along the first direction X, and the aforementioned multiple data lines Data can extend along the second direction Y.

[0055] For example, the display substrate 1000 also includes multiple common voltage signal lines VSS, which are used to transmit a common voltage.

[0056] For example, the first direction X and the second direction Y are perpendicular to each other.

[0057] For example, such as Figure 3 As shown, the pixel circuit 200 includes: a first reset transistor T1, a second reset transistor T2, a switching transistor T3, a driving transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a storage capacitor Cst.

[0058] For example, such as Figure 3 As shown, the gate of the first reset transistor T1 is coupled to the reset signal line ResetN, the first terminal of the first reset transistor T1 is coupled to the first initial signal line Vinit1, and the second terminal of the first reset transistor T1 is coupled to the fourth node N4, which is also coupled to the second terminal of the compensation transistor T5. The first reset transistor T1 is configured to turn on under the control of the reset signal transmitted through the reset signal line ResetN, transmitting the first initial signal received at the first initial signal line Vinit1 to the fourth node N4, thus resetting the fourth node N4.

[0059] For example, such as Figure 3As shown, the gate of the second reset transistor T2 is coupled to the first scan signal line GateP, the first terminal of the second reset transistor T2 is coupled to the second initial signal line Vinit2, and the second terminal of the second reset transistor T2 is coupled to the first node N1, that is, coupled to the light-emitting device 300. The second reset transistor T2 is configured to be turned on under the control of the first scan signal transmitted by the first scan signal line Vinit1, transmitting the second initial signal received at the second initial signal line Vinit2 to the first node N1, thereby resetting the first node N1.

[0060] For example, such as Figure 3 As shown, the gate of switching transistor T3 is coupled to the first scan signal line GateP, the first terminal of switching transistor T3 is coupled to the data line Data, and the second terminal of switching transistor T3 is coupled to the second node N2, which is also coupled to the first terminal of driving transistor T4. Switching transistor T3 is configured to be turned on under the control of the first scan signal transmitted through the first scan signal line GateP, transmitting the data signal received at the data line Data to the second node N2.

[0061] For example, such as Figure 3 As shown, the gate of driving transistor T4 is coupled to the fourth node N4, the first terminal of driving transistor T4 is coupled to the second node N2, and the second terminal of driving transistor T4 is coupled to the third node N3. Driving transistor T4 is configured to conduct under the control of the voltage at the fourth node N4, transmitting a signal (e.g., a data signal) from the second node N2 to the third node N3.

[0062] For example, such as Figure 3 As shown, the gate of compensation transistor T5 is coupled to the second scan signal line GateN, the first terminal of compensation transistor T5 is coupled to the third node N3, which is also coupled to the second terminal of driving transistor T4, and the second terminal of compensation transistor T5 is coupled to the fourth node N4, which is also coupled to the gate of driving transistor T4. Compensation transistor T5 is configured to be turned on under the control of the second scan signal transmitted through the second scan signal line GateN, transmitting the electrical signal (e.g., a data signal) from the third node N3 to the fourth node N4.

[0063] For example, such as Figure 3 As shown, the gate of the first light-emitting control transistor T6 is coupled to the enable signal line EM, the first terminal of the first light-emitting control transistor T6 is coupled to the voltage signal line VDD, and the second terminal of the first light-emitting control transistor T6 is coupled to the second node N2. The first light-emitting control transistor T6 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, and transmit the voltage signal received at the voltage signal line VDD to the second node N2.

[0064] For example, such as Figure 3 As shown, the gate of the second light-emitting control transistor T7 is coupled to the enable signal line EM, the first terminal of the second light-emitting control transistor T7 is coupled to the third node N3, and the second terminal of the second light-emitting control transistor T7 is coupled to the first node N1. The second light-emitting control transistor T7 is configured to conduct under the control of the enable signal transmitted through the enable signal line EM, transmitting an electrical signal (e.g., a voltage signal) from the third node N3 to the first node N1.

[0065] For example, such as Figure 3 As shown, the first terminal of the storage capacitor Cst is coupled to the fourth node N4, and the second terminal of the storage capacitor Cst is coupled to the voltage signal line VDD.

[0066] For example, the operation of the pixel circuit 200 includes a reset phase, a data writing and compensation phase, and a light emission phase performed sequentially.

[0067] For example, during the reset phase, under the control of the reset signal, the first reset transistor T1 is turned on, transmitting the first initial signal to the fourth node N4 to reset the fourth node N4. Since the fourth node N4 is coupled to the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5, resetting the fourth node N4 can simultaneously reset the first terminal of the storage capacitor Cst, the gate of the driving transistor T4, and the second terminal of the compensation transistor T5. The driving transistor T4 can be turned on under the control of the first initial signal.

[0068] For example, during the data writing and compensation phase, the second reset transistor T2 and the switching transistor T3 are turned on under the control of the first scan signal, and the compensation transistor T5 is turned on under the control of the second scan signal. The second reset transistor T2 transmits the second start signal to the first node N1 to reset the first node N1. Since the first node N1 is coupled to the anode of the light-emitting device 300, the anode of the light-emitting device 300 can be reset simultaneously when the first node N1 is reset. The switching transistor T3 transmits the data signal to the second node N2, and the driving transistor T4 transmits the data signal from the second node N2 to the third node N3. The compensation transistor T5 transmits the data signal from the third node N3 to the fourth node N4 to charge the driving transistor T4 until the threshold voltage of the driving transistor T4 is compensated.

[0069] For example, during the light-emitting phase, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are simultaneously turned on under the control of the enable signal. The first light-emitting control transistor T6 transmits the voltage signal to the second node N2. The driving transistor T4 transmits the voltage signal from the second node N2 to the third node N3. The second light-emitting control transistor T7 transmits the voltage signal from the third node N3 to the first node N1.

[0070] The light-emitting device 300 emits light under the influence of the voltage signal from the first node N1 and the common voltage from the common voltage line VSS.

[0071] In some examples, such as Figure 2 As shown, the pixel circuit 200 includes a first pixel circuit 210 and a second pixel circuit 220. In the display substrate 1000, the light-emitting device 300 further includes a first light-emitting device 310 and a second light-emitting device 320.

[0072] For example, the second pixel circuit 220 may include a first type of pixel circuit 221 and a second type of pixel circuit 222. The second light-emitting device 320 may include a first type of light-emitting device 321 and a second type of light-emitting device 322.

[0073] For example, the first light-emitting device 310 is coupled to the first pixel circuit 210 and configured to emit blue light under the action of the first pixel circuit 210. The second light-emitting device 320 is coupled to the second pixel circuit 220 and configured to emit red or green light under the action of the second pixel circuit 220. For example, a first type of light-emitting device 321 is coupled to the first type of pixel circuit 221 and configured to emit red light under the action of the first type of pixel circuit 221, and a second type of light-emitting device 322 is coupled to the second type of pixel circuit 222 and configured to emit green light under the action of the second type of pixel circuit 222.

[0074] In some examples, the display driver IC in the display device 2000 is coupled to the data line Data in the display substrate 1000, providing a data signal to the data line Data and transmitting the data signal to the corresponding pixel circuit 200 through the data line Data. The data voltage in this data signal includes, for example, black state voltage and white state voltage.

[0075] For example, the aforementioned black-state voltage refers to the data voltage required by the pixel circuit 200 when the display substrate 1000 displays a black image (i.e., grayscale is 0). When the display substrate 1000 displays a black image, the data signal with the black-state voltage is sequentially transmitted through the switching transistor T3, the driving transistor T4, and the compensation transistor T5 to the gate of the driving transistor T4, causing the driving transistor T4 to turn off, thereby preventing the light-emitting device 300 from emitting light during the light-emitting phase. The aforementioned white-state voltage refers to the data voltage required by the pixel circuit 200 when the display substrate 1000 displays a white image (i.e., grayscale is 255). When the display substrate 1000 displays a white image, the data signal with the white-state voltage is sequentially transmitted through the switching transistor T3, the driving transistor T4, and the compensation transistor T5 to the gate of the driving transistor T4, causing the driving transistor T4 to be fully turned on, thereby causing the light-emitting device 300 to emit brighter light during the light-emitting phase.

[0076] It should be noted that the required black state voltage varies depending on the color of the light emitted by the light-emitting device.

[0077] In one implementation, the actual black-state voltage required by the pixel circuit to achieve a grayscale of 0 differs for light-emitting devices that emit different colors of light (e.g., a first light-emitting device and a second light-emitting device). For example, the first pixel circuit coupled to the first light-emitting device requires a black-state voltage of 5.8V; the first type of pixel circuit coupled to the first type of light-emitting device in the second light-emitting device requires a black-state voltage of 6.5V; and the second type of pixel circuit coupled to the second type of light-emitting device in the second light-emitting device requires a black-state voltage of 6.4V.

[0078] Currently, to meet the overall black screen requirements of the display substrate, the preset black state voltage in the data signal provided by the display driver IC needs to be the maximum black state voltage actually required by each pixel circuit in the display substrate; that is, the preset black state voltage of the display driver IC is set to 6.5V. However, this results in the first light-emitting device coupled to the first pixel circuit not emitting light when the data signal voltage is greater than 5.8V. When setting the binding point in the Gamma band, the white state voltage is set and calculated with the aforementioned preset black state voltage, which easily leads to color shift and uneven grayscale transitions at low grayscale levels.

[0079] One solution to the problems arising from the above implementation is to simultaneously reduce the capacitance of the capacitors between each second scan signal line and the fourth node, thereby reducing the actual required black-state voltage.

[0080] Another solution to the problems arising from the above implementation is to simultaneously increase the capacitance of the capacitors between each first scan signal line and the fourth node in order to reduce the actual black state voltage required by the light-emitting device.

[0081] For example, the present invention designs to increase the capacitance of the capacitor between each first scan signal line and the fourth node, and performs simulation calculations. The simulation results are shown in Table 1 below.

[0082] Table 1

[0083] As shown in Table 1, by increasing the capacitance of the capacitors between each first scan signal line and the fourth node N4, the actual black-state voltage required by the first pixel circuit increases from 5.8V to 6.22V, the actual black-state voltage required by the first type of pixel circuit increases from 6.5V to 6.51V, and the actual black-state voltage required by the second type of pixel circuit increases from 6.4V to 6.54V. To meet the overall black screen requirements of the display substrate, the preset black-state voltage of the display driver IC is set to 6.6V.

[0084] However, the difference between the preset black state voltage and the actual black state voltage required by different pixel circuits still varies significantly. In particular, the difference between the actual black state voltage required by the first pixel circuit and the preset black state voltage is still much larger than the difference between the actual black state voltage required by the second type of pixel circuit and the preset black state voltage. Therefore, when the preset black state voltage provided by the display driver IC is 6.6V, if the data signal voltage is greater than 6.22V, the first light-emitting devices coupled to the first pixel circuit will not emit light, which can still easily lead to color shift and uneven grayscale transitions at low grayscale levels.

[0085] Furthermore, the inventors of this invention have discovered that, due to the limited wiring space on the display substrate, it is virtually impossible to reduce the black-state voltage actually required by the second pixel circuit.

[0086] Based on this, such as Figure 4a , Figure 4b and Figure 4c As shown, the pixel circuit 200 in the display substrate 1000 provided in some embodiments of the present invention further includes: a connecting line 201.

[0087] In some examples, in the layout of pixel circuits, such as Figure 4a As shown, the connecting line 201 is... Figure 3 The physical line corresponding to the connection between the first terminal of the storage capacitor Cst and the second terminal of the first reset transistor T1, the second terminal of the compensation transistor T5, and the gate of the driving transistor T4 in the equivalent circuit diagram shown is the connection line 201. Figure 3This corresponds to the fourth node N4 in the diagram. Therefore, the second terminal of the first reset transistor T1, the second terminal of the compensation transistor T5, and the gate of the driving transistor T4 are all coupled to the aforementioned connection line 201. The second terminal of the compensation transistor T5 is coupled to the gate of the driving transistor T4 via the connection line 201.

[0088] In some examples, such as Figure 3 As shown, the switching transistor T3 and the driving transistor T4 are P-type transistors, and the compensation transistor T5 is an N-type transistor.

[0089] For example, when the level of the first scan signal provided by the first scan signal line GateP is low, the switching transistor T3 is turned on. When the voltage provided by the fourth node N4 is low, the driving transistor T4 is turned on. When the level of the second scan signal provided by the second scan signal line GateN is high, the compensation transistor T5 is turned on.

[0090] In some examples, such as Figure 5a , Figure 5b and Figure 5c As shown, the connecting line 201 is directly opposite the first scan signal line GateP, and the two together constitute the first capacitor Cp1. That is, the orthogonal projection of the connecting line 201 in the pixel circuit 200 onto the substrate partially overlaps with the orthogonal projection of the first scan signal line GateP onto the substrate, and this overlapping portion constitutes the first capacitor Cp1.

[0091] For example, the first scan signal line GateP is coupled to the pixel circuit to which the connection line 201 belongs.

[0092] For example, the first plate of the first capacitor Cp1 is located on the first scan signal line GateP, and is a part of the first scan signal line. The second plate of the first capacitor Cp1 is located on the connection line 201, and is a part of the connection line 201. When the voltage of the first scan signal changes, the voltage on the corresponding connection line 201 will also change due to the coupling effect of the first capacitor Cp1. For example, when the voltage of the first scan signal changes from a low level to a high level, that is, when the switching transistor T3 changes from being turned on to being turned off, the voltage of the first plate of the first capacitor Cp1 increases, and correspondingly, the voltage of the second plate of the first capacitor Cp1 will also increase under the coupling effect of the first parasitic capacitance Cp1, and the increase in the two values ​​is approximately the same.

[0093] In some examples, such as Figure 6aAs shown, the connecting line 201 is directly opposite the second scan signal line GateN, and the two together constitute the second capacitor Cp2. That is, the orthogonal projection of the connecting line 201 in the pixel circuit onto the substrate partially overlaps with the orthogonal projection of the second scan signal line GateN onto the substrate, and this overlapping portion constitutes the second capacitor Cp2.

[0094] For example, the second scan signal line GateN is coupled to the pixel circuit to which the connection line 201 belongs.

[0095] For example, the first plate Cp201 of the second capacitor Cp2 is located on the second scan signal line GateN, and is a part of the second scan signal line GateN. The second plate Cp202 of the second capacitor Cp2 is located on the connection line 201, and is a part of the connection line 201. When the voltage of the second scan signal GateN changes, the voltage on the corresponding connection line 201 will also change due to the coupling effect of the second capacitor Cp2. For example, when the voltage of the second scan signal changes from a high level to a low level, that is, when the compensation transistor T5 changes from being turned on to being turned off, the voltage of the first plate of the second capacitor Cp2 decreases, and the voltage of the second plate of the second capacitor Cp2 will also decrease due to the coupling effect of the second capacitor Cp2, and the decreases in both values ​​are approximately the same.

[0096] In some embodiments, the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is less than the capacitance of the first capacitor Cp12 of the second pixel circuit 220. And / or, the capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220.

[0097] It is understandable that the capacitance of the first capacitor Cp1 and the second capacitor Cp2 of the pixel circuit 200 can be set in multiple ways, and the various setting methods will be introduced in turn below.

[0098] In some examples, such as Figure 4a As shown, the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is smaller than the capacitance of the first capacitor Cp12 of the second pixel circuit 220.

[0099] During the process of the switching transistor T3 in the first pixel circuit 210 or the second pixel circuit 220 switching from on to off, the level (i.e., voltage) of the first scan signal line GateP coupled to it changes from low level (i.e., low voltage) to high level (i.e., high voltage). In other words, the voltage value of the first scan signal line GateP increases, and the voltage of the first plate of the first capacitor Cp1 increases. Since the capacitance of the first capacitor Cp12 in the first pixel circuit 210 is relatively small, its voltage coupling effect on the second plate of the first capacitor Cp11 in the connecting line 201 is relatively small. Figure 3 The potential coupling effect of the fourth node N4 shown is relatively small, resulting in a smaller potential rise in the fourth node N4 in the first pixel circuit 210. For example, the potential rise of the fourth node is ΔV. 11 However, the capacitance of the first capacitor Cp12 in the second pixel circuit 220 is relatively large, resulting in a smaller voltage coupling effect on the second plate of the first capacitor Cp12 in the connecting line 201. In other words, the voltage coupling effect on the second plate of the first capacitor Cp12 is smaller. Figure 3 The fourth node N4 shown has a large potential coupling effect, which causes the potential of the fourth node N4 in the second pixel circuit 220 to rise significantly, for example, by ΔV. 21 Wherein, ΔV 21 Greater than ΔV 11 This necessitates providing a data signal with a large voltage to the data line Data coupled to the first pixel circuit 210, ensuring that the driving transistor T4 in the first pixel circuit 210 can be turned off under the action of this large voltage data signal, and ensuring that the first light-emitting device 310 coupled to it can not emit light.

[0100] In other words, by adopting the above-mentioned configuration, the capacitance of the first capacitor Cp11 of the first pixel circuit 210 and the capacitance of the first capacitor Cp12 of the second pixel circuit 220 are designed differently. This increases the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310, thereby reducing the difference between the actual black state required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the actual black state required by the second pixel circuit 220 coupled to the second light-emitting device 320. As a result, the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC is reduced. Furthermore, after setting and calculating the white state voltage and the black state voltage, the color shift phenomenon of the display substrate at low gray levels and the phenomenon of uneven gray level transition can be weakened or even eliminated.

[0101] In other examples, such as Figure 4b As shown, the capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220.

[0102] During the process of the compensation transistor T5 in the first pixel circuit 210 or the second pixel circuit 220 turning off, the level (i.e., voltage) of the second scan signal line GateN coupled to it drops from high voltage to low voltage. In other words, the voltage of the second scan signal line GateN decreases, and the voltage of the first plate of the second capacitor Cp2 decreases. Since the capacitance of the second capacitor Cp21 in the first pixel circuit 210 is relatively large, the voltage coupling effect on the second plate of the second capacitor Cp21 in the connecting line 201 is significant. Figure 3 The fourth node N4 in the first pixel circuit 210 has a relatively large potential coupling effect, which causes the potential of the fourth node N4 in the first pixel circuit 210 to drop significantly. For example, the potential drop of the fourth node N4 is ΔV. 12 However, the capacitance of the second capacitor Cp22 in the second pixel circuit 220 is relatively small, resulting in a smaller voltage coupling effect on the second plate of the second capacitor Cp22 in the connecting line 201. In other words, it has a smaller effect on... Figure 3 The potential coupling effect of the fourth node N4 in the diagram is relatively large, resulting in a smaller potential decrease in the fourth node N4, for example, a potential decrease of ΔV. 22 ΔV 12 Greater than ΔV 22 This requires the data line Data coupled to the first pixel circuit 210 to provide a data signal with a large voltage to ensure that the driving transistor T4 in the first pixel circuit 210 can be turned off under the action of the data signal with a large voltage, and to ensure that the first light-emitting device 310 coupled to it can not emit light.

[0103] In other words, by adopting the above-mentioned configuration, the capacitance of the second capacitor Cp21 of the first pixel circuit 210 and the capacitance of the second capacitor Cp22 of the second pixel circuit 220 are designed differently. This increases the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310, and reduces the difference between the actual black state required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the actual black state required by the second pixel circuit 220 coupled to the second light-emitting device 320. As a result, the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC is reduced. Therefore, after setting and calculating the white state voltage and the black state voltage, the color shift phenomenon and the uneven gray level transition phenomenon of the display substrate 1000 at low gray levels can be weakened or even eliminated.

[0104] In some examples, such as Figure 4cAs shown, the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is less than the capacitance of the first capacitor Cp12 of the second pixel circuit 220. Furthermore, the capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220.

[0105] By adopting the above-described configuration, the capacitance of the second capacitor Cp21 of the first pixel circuit 210 and the capacitance of the second capacitor Cp22 of the second pixel circuit 220 are differentiated, as are the capacitances of the first capacitor Cp11 of the first pixel circuit 210 and the first capacitor Cp12 of the second pixel circuit 220. This can further increase the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310, and further reduce the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the actual black state voltage required by the second pixel circuit 220 coupled to the second light-emitting device 320. This can further reduce the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC, making the actual black state voltage required by the first light-emitting device 310 approximately equal to or equal to the preset black state voltage provided by the display driver IC. This can further reduce or even eliminate the color shift phenomenon and uneven grayscale transition phenomenon of the display substrate at low grayscale levels.

[0106] It should be noted that many factors affect the capacitance of a capacitor, such as the overlapping area of ​​the two plates and the distance between them. This invention does not impose any limitations on these factors.

[0107] It is understandable that the thickness of each insulating layer in the display substrate remains basically unchanged, which means that the spacing between the two plates of the first capacitor and the spacing between the two plates of the second capacitor in each pixel circuit remains basically unchanged.

[0108] The portion of the connecting line 201 and the first scan signal line GateP in the first pixel circuit 210 that faces each other constitutes the first capacitor Cp11 in the first pixel circuit 210. The portion of the connecting line 201 and the first scan signal line GateP in the second pixel circuit 200b that faces each other constitutes the first capacitor Cp12 in the second pixel circuit 200b. The portion of the connecting line 201 and the second scan signal line GateN in the first pixel circuit 210 that faces each other constitutes the second capacitor Cp21 in the first pixel circuit 210. The portion of the connecting line 201 and the second scan signal line GateN in the second pixel circuit 200b that faces each other constitutes the second capacitor Cp22 in the second pixel circuit 200b.

[0109] With the distance between the two plates of each capacitor (i.e., the first capacitor and the second capacitor) remaining constant, the size of the area of ​​the aforementioned facing portion essentially determines the capacitance of each capacitor. The larger the area of ​​the aforementioned facing portion, the larger the capacitance of the corresponding capacitor.

[0110] In some embodiments, such as Figure 4a , Figure 5a As shown, when the capacitance of the first capacitor Cp11 in the first pixel circuit 210 is less than the capacitance of the first capacitor Cp12 in the second pixel circuit 220, the area of ​​the opposite portion of the connecting line 201 and the first scan signal line GateP in the first pixel circuit 200b is less than the area of ​​the opposite portion of the connecting line 201 and the first scan signal line GateP in the second pixel circuit 200b.

[0111] This ensures that the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is less than the capacitance of the first capacitor Cp12 of the second pixel circuit 220, ensuring that the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 is increased, and that the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the actual black state voltage required by the second pixel circuit 220 coupled to the second light-emitting device 320 is reduced. This ensures that the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC is reduced, thereby ensuring that the color shift phenomenon and uneven gray level transition of the display substrate 1000 at low gray levels can be improved.

[0112] In some examples, the area of ​​the opposite portion of the connecting line 201 and the first scan signal line GateP in the first pixel circuit 210 is α, where 1:10 ≤ α < 1:1.

[0113] For example, the ratio α of the area of ​​the opposite portion of the connecting line 201 and the first scan signal line GateP in the first pixel circuit 210 to the area of ​​the opposite portion of the connecting line 201 and the first scan signal line GateP in the second pixel circuit 220 can be 1:10, 1:8, 1:6, 1:4, 1:2, etc.

[0114] By adopting the above configuration, the ratio of the capacitance of the first capacitor Cp11 of the first pixel circuit 210 to the capacitance of the first capacitor Cp12 of the second pixel circuit 220 can also be α. This increases the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310, thereby reducing or even eliminating the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC. This can weaken or even eliminate the color shift phenomenon and uneven gray level transition phenomenon of the display substrate 1000 at low gray levels, thereby improving the display quality of the display substrate 1000 and the display device 2000.

[0115] In this example, the capacitance of the second capacitor Cp21 in the first pixel circuit 210 and the capacitance of the second capacitor Cp22 in the second pixel circuit 220 can, for example, be equal.

[0116] After differentiating the design of the first parasitic capacitance Cp1 of different pixel circuits in the display substrate 1000, the black state voltage and capacitance were simulated and verified. The calculation results are shown in Table 2 below.

[0117] Table 2

[0118] In Table 2, during the simulation verification of this invention, the capacitance of the second capacitor Cp21 in the first pixel circuit 210, the capacitance of the second capacitor Cp22 in the first type pixel circuit 221, and the capacitance of the second capacitor Cp22 in the second type pixel circuit 222 are all set to the same value, which is 2.516 fF. The capacitances of the first capacitor Cp11 in the first pixel circuit 210, the capacitance of the first capacitor Cp12 in the first type pixel circuit 221, and the capacitance of the first capacitor Cp13 in the second type pixel circuit 222 are set to 3.864 fF, 5.864 fF, and 5.864 fF, respectively.

[0119] As shown in Table 2, the capacitance ratio α between the first capacitor Cp11 of the first pixel circuit 210 and the first capacitor Cp12 of the second pixel circuit 220 is 1:1.52, meaning the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is less than that of the first capacitor Cp12 of the second pixel circuit 220. Furthermore, the actual black-state voltage required by the first pixel circuit 210 has increased from 6.22V in Table 1 to 6.55V in Table 2 of this example. The difference between the actual black-state voltage required by the first pixel circuit 210 and the preset black-state voltage provided by the display driver IC has decreased from 0.38V in Table 1 to 0.05V in Table 2 of this example.

[0120] Therefore, by reducing the capacitance of the first capacitor Cp11 of the first pixel circuit 210, the present invention can reduce the coupling effect of the first capacitor Cp11 of the first pixel circuit 210 when the voltage of the first scan signal line GateP increases, reduce the amount of potential rise of the fourth node N4, increase the black state voltage actually required by the first pixel circuit 210, and thus reduce the color shift phenomenon of the display substrate 1000 at low gray levels and the phenomenon of uneven gray level transition.

[0121] In some embodiments, such as Figure 4b and Figure 6a As shown, when the capacitance of the second capacitor Cp21 in the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 in the second pixel circuit 220, the area of ​​the connecting line 201 and the opposite portion of the second scan signal line GateN in the first pixel circuit 210 is greater than the area of ​​the connecting line 201 and the opposite portion of the second scan signal line GateN in the second pixel circuit 220.

[0122] This ensures that the capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220, thereby increasing the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310. It also ensures that the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the actual black state voltage required by the second pixel circuit 220 coupled to the second light-emitting device 320 is reduced. This, in turn, ensures that the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC is reduced, thus improving the color shift phenomenon and uneven grayscale transition of the display substrate 1000 at low grayscale levels.

[0123] In some examples, the ratio of the area of ​​the connecting line 201 and the opposite portion of the second scan signal line GateN in the first pixel circuit 210 to the area of ​​the opposite portion of the connecting line 201 and the second scan signal line GateN in the second pixel circuit 220 is β, where 1:1 < β ≤ 10:1.

[0124] For example, the ratio β of the area of ​​the opposite portion of the connecting line 201 and the second scanning signal line GateN in the first pixel circuit 210 to the area of ​​the opposite portion of the connecting line 201 and the second scanning signal line GateN in the second pixel circuit 220 can be 2:1, 5:1, 7:1, 8:1, 9:1, or 10:1.

[0125] By adopting the above configuration, the ratio of the capacitance of the second capacitor Cp2 of the first pixel circuit 210 to the capacitance of the second capacitor Cp2 of the second pixel circuit 220 can also be β. This increases the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310, thereby reducing or even eliminating the difference between the actual black state voltage required by the first pixel circuit 210 coupled to the first light-emitting device 310 and the preset black state voltage provided by the display driver IC. This can weaken or even eliminate the color shift phenomenon and uneven gray level transition phenomenon of the display substrate 1000 at low gray levels, thereby improving the display quality of the display substrate 1000 and the display device 2000.

[0126] After differentiating the design of the second parasitic capacitance Cp2 of different pixel circuits in the display substrate 1000, the black state voltage and capacitance were simulated and verified. The calculation results are shown in Table 3 below.

[0127] Table 3

[0128] In Table 3, during the simulation verification of this invention, the capacitance of the first capacitor Cp11 in the first pixel circuit 210, the capacitance of the first capacitor Cp12 in the first type pixel circuit 221, and the capacitance of the first capacitor Cp13 in the second type pixel circuit 222 are the same, all being 5.864 fF. The capacitances of the second capacitor Cp21 in the first pixel circuit 210, the capacitance of the second capacitor Cp22 in the first type pixel circuit 221, and the capacitance of the second capacitor Cp23 in the second type pixel circuit 222 are 4.016 fF, 2.516 fF, and 2.516 fF, respectively.

[0129] As shown in Table 3, the ratio β of the capacitance of the second parasitic capacitor Cp21 of the first pixel circuit 210 to the capacitance of the second parasitic capacitor Cp22 of the second pixel circuit 220 is 1.60:1. The capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than that of the second capacitor Cp22 of the second pixel circuit 220. Furthermore, the actual black state voltage required by the first pixel circuit 210 has increased from 6.22V in Table 1 to 6.52V in Table 2 of this example. The difference between the actual black state voltage required by the first pixel circuit 210 and the preset black state voltage provided by the display driver IC has decreased from 0.38V in Table 1 to 0.08V in Table 2 of this example.

[0130] Therefore, it can be seen that by increasing the capacitance of the second capacitor Cp21 of the first pixel circuit 210, the present invention can increase the coupling effect of the second capacitor Cp21 of the first pixel circuit 210 when the voltage of the second scan signal line GateN decreases, increase the amount of potential decrease of the fourth node N4, improve the black state voltage actually required by the first pixel circuit 210, and thus reduce the color shift phenomenon of the display substrate 1000 at low gray levels and the phenomenon of uneven gray level transition.

[0131] In some embodiments, the compensation transistor T5 and the first reset transistor T1 are both oxide transistors, and the switching transistor T3, the driving transistor T4, the second reset transistor T2, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are all low-temperature polysilicon transistors.

[0132] For example, since oxide transistors have lower leakage current, setting the first reset transistor T1 to an oxide transistor can reduce the leakage current of the fourth node N4 in the first reset transistor T1 when it is in the off state after being reset by the first reset transistor T1, thereby improving the reset effect of the fourth node N4. Setting the compensation transistor T5 to an oxide transistor can reduce the leakage current of the compensation transistor T5 during the data writing and compensation stages, preventing leakage of the fourth node through the compensation transistor and the first reset transistor, thereby ensuring the compensation effect of the driving transistor T4, ensuring the stability of the voltage of the fourth node, and thus improving the display quality of the display substrate 1000. Furthermore, low-temperature polysilicon transistors have higher mobility; setting transistors such as the driving transistor T4 to low-temperature polysilicon transistors can accelerate the charging speed of the storage capacitor, thereby further improving the display quality of the display substrate 1000.

[0133] In some embodiments, such as Figures 8-18 As shown, the display substrate 1000 includes: a second active layer PL, a first conductive layer Gate1, a second conductive layer Gate2, a first active layer PO, a third conductive layer Gate3, a fourth conductive layer SD1, a fifth conductive layer SD2, an anode layer AND, and a light-emitting thin film EL, which are sequentially disposed on one side of the substrate 100.

[0134] in, Figures 4a-4c The diagram illustrates the top view of the stacked structure of the second active layer PL, the first conductive layer Gate1, the second conductive layer Gate2, the first active layer PO, the third conductive layer Gate3, the fourth conductive layer SD1, and the fifth conductive layer SD2. Figure 5a The diagram shows a top view of a stacked structure of a first active layer PO and a first conductive layer Gate1. Figure 5b This shows another top view of the stacked structure of the first active layer PO and the first conductive layer Gate1. Figure 5c This shows another top view of the stacked structure of the first active layer PO and the first conductive layer Gate1. Figure 6a The diagram shows a top view of a structure in which the third conductive layer Gate3 and the fourth conductive layer SD1 are stacked. Figure 6b This shows another top view of the stacked structure of the third conductive layer Gate3 and the fourth conductive layer SD1. Figure 6c This shows another top view of the stacked structure of the third conductive layer Gate3 and the fourth conductive layer SD1. Figure 7 The diagram shows a top view of the stacked structure of the first active layer PO and the fourth conductive layer SD1. Figure 9 The diagram shows the top view of the second active layer PL. Figure 10a The diagram illustrates a top view of the first conductive layer, Gate 1. Figure 10b This diagram illustrates a top view of another first conductive layer, Gate 1. Figure 11 The diagram shows the top view of the second conductive layer, Gate2. Figure 12a The diagram illustrates a top view of the first active layer PO. Figure 12b This illustrates a top view of another first active layer PO. Figure 13a The diagram illustrates a top view of a third conductive layer, Gate 3. Figure 13b This diagram illustrates a top view of another third conductive layer, Gate 3. Figure 14a The diagram illustrates a top view of a fourth conductive layer SD1. Figure 14b The diagram illustrates the top view of another fourth conductive layer, SD1. Figure 15 The diagram shows the top view of the fifth conductive layer SD2. Figure 16 The diagram illustrates the top view of the anode layer AND. Figure 17 The diagram illustrates the top view of the stacked structure of the anode layer AND and the light-emitting thin film EL. Figure 18 The diagram illustrates a top view of the stacked structure consisting of a second active layer PL, a first conductive layer Gate1, a second conductive layer Gate2, a first active layer PO, a third conductive layer Gate3, a fourth conductive layer SD1, a fifth conductive layer SD2, an anode layer AND, and a light-emitting thin film EL.

[0135] It is understood that an insulating layer (not shown in the figure) may be present between any two adjacent film layers mentioned above. A pixel delimiting layer is provided between the anode layer AND and the light-emitting thin film EL.

[0136] For example, the material of the second active layer PL may include semiconductor materials such as amorphous silicon, monocrystalline silicon, and polycrystalline silicon.

[0137] For example, the material of the first active layer PO may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0138] For example, the materials of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer Gate3, the fourth conductive layer SD1, and the fifth conductive layer SD2 are all conductive materials. The materials of the first conductive layer Gate1, the second conductive layer Gate2, and the third conductive layer Gate3 can be the same, for example, and the materials of the fourth conductive layer SD1 and the fifth conductive layer SD2 can be the same.

[0139] For example, the aforementioned conductive material can be a metallic material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.

[0140] In some examples, such as Figure 4a and Figure 8 As shown, the display substrate 1000 further includes a shielding layer BSM disposed between the substrate 100 and the second active layer PL.

[0141] in, Figure 8 The diagram shows the top view of the shielding layer BSM.

[0142] For example, the material of the shielding layer BSM may include a conductive material. The shielding layer BSM may be connected to a signal line that transmits a constant voltage signal (e.g., voltage signal line VDD, common voltage signal line VSS, first initial signal line Vinit1, or second initial signal line Vinit2), thereby improving the stability of the voltage signal of the film layer located on the side of the shielding layer BSM away from the substrate 100 (e.g., the film layer where the gate of the driving transistor T4 is located) and preventing the signal of the film layer from being interfered with.

[0143] It should be noted that the orthographic projection of the second active layer PL onto the substrate overlaps with the orthographic projection of the first conductive layer Gate1 onto the substrate. Specifically, after the first conductive layer Gate1 is formed on the side of the second active layer PL away from the substrate, it can be used as a mask to dope the second active layer PL. This results in the portion of the second active layer PL covered by the first conductive layer Gate1 forming the active pattern of a portion of the transistor, while the portion of the second active layer PL not covered by the first conductive layer Gate1 forms a conductor, which can form the first or second electrode of a portion of the transistor. The overlapping portion of the first conductive layer Gate1 and the second active layer PL forms the gate pattern of a portion of the transistor.

[0144] Furthermore, the orthographic projection of the first active layer PO onto the substrate has the same overlapping pattern as the orthographic projections of the third conductive layer Gate3 and the second conductive layer Gate2 onto the substrate. The portions of the third conductive layer Gate3 and the second conductive layer Gate2 located within the same overlapping pattern constitute the gate pattern of a portion of the transistor. The portion of the first active layer PO connected to the same overlapping pattern constitutes the first or second electrode of the portion of the transistor.

[0145] For example, the relative positional relationship between the transistors and storage capacitors included in the pixel circuit 200 is shown in Figure 4a. Along the first direction X, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are arranged in the same row, and the second reset transistor T2 and the switching transistor T3 are arranged in the same row. Along the second direction Y, the switching transistor T3 and the first light-emitting control transistor T6 are arranged in the same column, the second reset transistor T2 and the driving transistor T4 are arranged in the same column, and the compensation transistor T5 and the second light-emitting control transistor T7 are arranged in the same column. Along the first direction X, the first reset transistor T1 is located between the compensation transistor T5 and the second reset transistor T2, the second reset transistor T2 is located between the switching transistor T3 and the first reset transistor T1, and the driving transistor T4 is located between the first light-emitting control transistor T6 and the second light-emitting control transistor T7. Along the second direction Y, the switching transistor T3 and the compensation transistor T5 are located between the first reset transistor T1 and the second light-emitting control transistor T7. The storage capacitor Cst is located at the same position as the driving transistor T4, and the storage capacitor Cst is located on the side of the driving transistor T4 away from the substrate 100.

[0146] For example, each film layer included in the display substrate 1000, except for the portions corresponding to the first and second capacitors of each pixel circuit 200, can be mirrored about the boundary line between two adjacent pixel circuits 200. This helps to improve the regularity of the arrangement of the pixel circuits 200, improve the regularity of the wiring, and reduce the manufacturing difficulty of the display substrate 1000.

[0147] In some examples, such as Figure 9 , Figure 10a and Figure 10b As shown, the switching transistor T3 includes a first active pattern p31 and a first gate pattern g31, and the driving transistor T4 includes a second active pattern p41 and a second gate pattern g41.

[0148] For example, such as Figure 11 , Figure 12b , Figure 13a and Figure 13bAs shown, the compensation transistor T5 includes a third active pattern p51, a third gate pattern g51, and a fourth gate pattern g52.

[0149] For example, the first active pattern p31 and the second active pattern p41 may be located in the same active layer of the display substrate 1000, while the first active pattern p31, the second active pattern p41, and the third active pattern p51 may be located in different active layers of the display substrate 1000.

[0150] In some examples, such as Figure 9 As shown, the first active pattern p31 and the second active pattern p41 are located in the second active layer PL, and the two are connected and form an integral structure.

[0151] For example, "integrated structure" refers to two connected patterns disposed on the same layer, and the two patterns are continuous and not separated. That is, in this invention, the first active pattern p31 and the second active pattern p41 are located on the same film layer, and the first active pattern p31 and the second active pattern p41 are coupled to each other through a portion of doped semiconductor located between them.

[0152] For example, the term "same layer" as used in this invention refers to a layer structure formed using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This allows for the simultaneous fabrication of the first active pattern p41 and the second active pattern p31, which simplifies the fabrication process of the display substrate 1000.

[0153] In some examples, such as Figure 11 , Figure 12a and Figure 12b As shown, the third active pattern p51 is located in the first active layer PO.

[0154] By setting two active layers and setting the first active pattern p31, the second active pattern p41, and the third active pattern p51 in the manner described above, it is beneficial to ensure that the required type of transistor can be obtained.

[0155] In some examples, such as Figure 9 As shown, the first gate pattern g31 and the second gate pattern g41 are located in the first conductive layer Gate1, and the first gate pattern g31 and the first scan signal line GateP are connected and form an integral structure.

[0156] For example, in this invention, the first gate pattern g31 and the first scan signal line GateP are located in the same film layer, and the first gate pattern g31 and the first scan signal line GateP are coupled to each other, and are continuous and not separated. This simplifies the manufacturing process of the display substrate 1000.

[0157] In some examples, such as Figure 11 , Figure 13a and Figure 13b As shown, the third gate pattern g51 is located in the second conductive layer Gate2, and the third gate pattern g51 is connected to the first sub-scan signal line GateN1, forming an integral structure. The fourth gate pattern g52 is located in the third conductive layer Gate3, and the fourth gate pattern g52 is connected to the second sub-scan signal line GateN2, forming an integral structure.

[0158] This allows the compensation transistor T5 to have a bottom-top gate structure, giving it better leakage protection.

[0159] For example, in this invention, the third gate pattern g51 and the first sub-scan signal line GateN1 are located in the same film layer, and the third gate pattern g51 and the first sub-scan signal line GateN1 are coupled to each other, and are continuous and not separated. This simplifies the manufacturing process of the display substrate 1000.

[0160] For example, in this invention, the fourth gate pattern g52 and the second sub-scan signal line GateN2 are located in the same film layer, and the fourth gate pattern g52 and the second sub-scan signal line GateN2 are coupled to each other, and are continuous and not separated. This simplifies the manufacturing process of the display substrate 1000.

[0161] In some examples, the second scan signal line GateN includes a first sub-scan signal line GateN1 and a second sub-scan signal line GateN2. The second scan signal line GateN, including the first sub-scan signal line GateN1 and the second sub-scan signal line GateN2, transmits the same scan signal.

[0162] For example, such as Figure 11 As shown, the first sub-scan signal line GateN1 is located on the second conductive layer Gate2. For example, as... Figure 13a and Figure 11 As shown, there can also be two reset signal lines, ResetN, located on the second conductive layer Gate2 and the third conductive layer Gate3 respectively, and they transmit the same reset signal.

[0163] In some embodiments, such as Figure 7 , 12a , Figure 12b , Figure 13a , Figure 13b As shown, the above-mentioned connecting line 201 includes: a first connecting line 201a and a second connecting line 201b coupled to the first connecting line 201a.

[0164] In some examples, the first connection line 201a and the second connection line 201b described above may be located in the same film layer of the display substrate 1000 or in different film layers.

[0165] When the first connecting line 201a and the second connecting line 201b are located in different film layers of the display substrate 1000, such as Figure 7 As shown, the first connecting line 201a and the second connecting line 201b can be coupled through vias. Wherein, Figure 7 This is a stack diagram of the first active layer PO and the fourth conductive layer SD1.

[0166] For example, such as Figure 5a , Figure 5b , Figure 5c , Figure 6a , Figure 6b , Figure 6c , Figure 10a , Figure 10b , Figure 12a , Figure 12b , Figure 13a , Figure 13b , Figure 14a , Figure 14b As shown, the first connection line 201a is located in the first active layer PO, and the first scan signal line GateP is located in the first conductive layer Gate1; the first connection line 201a and the first scan signal line GateP are partially opposite each other, and the two together form the first capacitor Cp1. The second connection line 201b is located in the fourth conductive layer SD1, and the second sub-scan signal line GateN2 is located in the second conductive layer Gate3; the second connection line 201b and the second sub-scan signal line GateN2 are partially opposite each other, and the two together form the second capacitor Cp2.

[0167] By using the above configuration, placing the first connecting line 201a, the second connecting line 201b, the first scanning signal line GateP, and the second sub-scanning signal line GateN2 on different film layers, the design space of the display substrate 1000 can be optimized. This allows the areas of the first capacitor Cp1 and the second capacitor Cp2 to be set according to actual needs, avoiding significant space limitations. Consequently, the capacitance of the first capacitor Cp1 and the capacitance of the second capacitor Cp2 have a larger range of differentiated design, thereby improving the display quality of the display substrate 1000 and the display device 2000.

[0168] It should be noted that, taking the rectangular shape of the two plates of a capacitor as an example, there are many ways to set the areas of the two capacitors to be different. For example, the length of the first plate of one capacitor can be different from the length of the first plate of the other capacitor, or the width of the first plate of one capacitor can be different from the width of the first plate of the other capacitor, or the length of the second plate of one capacitor can be different from the length of the second plate of the other capacitor, or the width of the second plate of one capacitor can be different from the width of the second plate of the other capacitor, etc. This invention does not limit these possibilities.

[0169] In some embodiments, when the capacitance of the first capacitor Cp11 of the first pixel circuit 210 is less than the capacitance of the first capacitor Cp12 of the second pixel circuit 220, there are various arrangements between the two plates of the first capacitor of each pixel circuit.

[0170] In some examples, such as Figure 5a As shown, in the first scan signal line GateP, the portion of the part directly opposite the first connection line 201a of the first pixel circuit 210 in the second direction Y has a smaller size in the second direction Y than the portion of the part directly opposite the first connection line 201a of the second pixel circuit 220.

[0171] For example, let's take the case where the "opposite part" is a rectangle as an example. Figure 10b As shown, the width of the first opposing pattern Cp1101 formed by the portion of the first scanning signal line GateP that is directly opposite to the first connecting line 201a of the first pixel circuit 210 is its dimension in the second direction Y. Similarly, the width of the second opposing pattern Cp1102 formed by the portion of the first scanning signal line GateP that is directly opposite to the first connecting line 201a of the second pixel circuit 220 is its dimension in the second direction Y. The width of the first opposing pattern Cp1101 is smaller than the width of the second opposing pattern Cp1102, and the length of the first opposing pattern Cp1101 is equal to the length of the second opposing pattern Cp1102. Since the area of ​​a rectangle is the product of its length and width, the area of ​​the first opposing pattern Cp1101 is smaller than the area of ​​the second opposing pattern Cp1102. This results in the capacitance of the first capacitor Cp11 in the first pixel circuit 210 being smaller than the capacitance of the first capacitor Cp12 in the second pixel circuit 220.

[0172] In other examples, such as Figure 5c As shown, the size of the portion of the first connection line 201a of the first pixel circuit that is directly opposite the first scan signal line GateP in the first direction X is smaller than the size of the portion of the first connection line 201a of the second pixel circuit 220 that is directly opposite the first scan signal line 201a in the first direction X.

[0173] For example, let's take the case where the "opposite part" is a rectangle as an example. Figure 12b As shown, the length of the third opposing pattern Cp1103 formed by the portion of the first connection line 201a of the first pixel circuit that is directly opposite to the first scan signal line GateP is its dimension in the first direction X. Similarly, the length of the fourth opposing pattern Cp1104 formed by the portion of the first connection line 201a of the second pixel circuit that is directly opposite to the first scan signal line GateP is its dimension in the first direction X. The length of the third opposing pattern Cp1103 is less than the length of the fourth opposing pattern Cp1104, and the width of the third opposing pattern Cp1103 is equal to the width of the fourth opposing pattern Cp1104. Since the area of ​​a rectangle is the product of its length and width, the area of ​​the third opposing pattern Cp1103 is less than the area of ​​the fourth opposing pattern Cp1104. This results in the capacitance of the first capacitor Cp11 in the first pixel circuit 210 being less than the capacitance of the first capacitor Cp12 in the second pixel circuit 220.

[0174] In some other examples, such as Figure 5c As shown, the portion of the first connection line 201a of the first pixel circuit that is directly opposite the first scan signal line 201a has a smaller size in the second direction Y than the portion of the first connection line 201a of the second pixel circuit 220 that is directly opposite the first scan signal line GateP has a smaller size in the second direction Y.

[0175] For example, let's take the case where the "opposite part" is a rectangle as an example. Figure 12b As shown, the width of the fifth opposing pattern Cp1105 formed by the portion of the first connection line 201a of the first pixel circuit directly opposite the first scan signal line GateP is its dimension in the second direction Y. Similarly, the width of the sixth opposing pattern Cp1106 formed by the portion of the first connection line 201a of the second pixel circuit directly opposite the first scan signal line GateP is its dimension in the second direction Y. The width of the fifth opposing pattern Cp1105 is smaller than the width of the sixth opposing pattern Cp1106, and the length of the fifth opposing pattern Cp1105 is less than or equal to the length of the sixth opposing pattern Cp1106. Since the area of ​​a rectangle is the product of its length and width, the area of ​​the fifth opposing pattern Cp1105 is smaller than the area of ​​the sixth opposing pattern Cp1106. This results in the capacitance of the first capacitor Cp11 in the first pixel circuit 210 being smaller than the capacitance of the first capacitor Cp12 in the second pixel circuit 220.

[0176] By adopting the configuration method in the above embodiments, the area of ​​the two plates of the first capacitor Cp11 in the first pixel circuit 210 facing each other (i.e., the area of ​​the part of the first scan signal line GateP facing the first connection line 201a) is smaller than the effective area of ​​the first capacitor Cp12 in the second pixel circuit 220 (i.e., the area of ​​the part of the first scan signal line GateP facing the first connection line 201a). This ensures that the capacitance of the first capacitor Cp11 in the first pixel circuit 210 is smaller than the capacitance of the first capacitor Cp12 in the second pixel circuit 220. This reduces the coupling effect of the first capacitor Cp11 in the first pixel circuit 210 when the voltage of the first scan signal line GateP increases, reduces the potential rise of the fourth node N4, increases the black state voltage actually required by the first pixel circuit 210, and thus weakens the color shift phenomenon and uneven grayscale transition phenomenon of the display substrate 1000 at low grayscale.

[0177] In other embodiments, when the capacitance of the second capacitor Cp21 of the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220, there are various arrangements between the two plates of the first capacitor of each pixel circuit.

[0178] In some examples, such as Figure 6a As shown, the portion of the second connection line 201b of the first pixel circuit 210 that is directly opposite the second sub-scan signal line GateN2 has a larger size in the first direction X than the portion of the second connection line 201b of the second pixel circuit 220 that is directly opposite the second sub-scan signal line GateN2 in the first direction X.

[0179] For example, let's take the case where the "opposite part" is a rectangle as an example. Figure 14b As shown, the length of the seventh opposing pattern Cp2101 in the second connection line 201b of the first pixel circuit 210, which is directly opposite to the second sub-scan signal line Gate N2, is its size in the first direction X. Similarly, the length of the eighth opposing pattern Cp2102 formed in the second connection line 201b of the second pixel circuit 220, which is directly opposite to the second sub-scan signal line Gate N2, is its size in the first direction X. The length of the seventh opposing pattern Cp2101 is greater than the length of the eighth opposing pattern Cp2102.

[0180] For example, in the above configuration, the portion of the second sub-scan signal line GateN2 that faces the second connection line 201b of the first pixel circuit 210 in the second direction Y has a dimension equal to the portion of the second connection line 201b of the second pixel circuit 220 that faces the second connection line 201b in the second direction Y. For example, in Figure 14bIn the first pixel circuit 210, the length of the seventh facing pattern Cp1107 is greater than the length of the eighth facing pattern Cp1108, and the width of the seventh facing pattern Cp1107 is equal to the width of the eighth facing pattern Cp1108. The area of ​​the rectangle is the product of the length and the width. Therefore, the area of ​​the seventh facing pattern Cp1107 is greater than the area of ​​the eighth facing pattern Cp1108, which makes the capacitance of the second capacitor Cp21 of the first pixel circuit 210 greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220.

[0181] In other examples, such as Figure 6a As shown, in the second sub-scan signal line GateN2, the portion of the part directly opposite the second connection line 201b of the first pixel circuit 210 has a larger dimension in the second direction Y than the portion of the part directly opposite the second connection line 201b of the second pixel circuit 220 has a larger dimension in the second direction Y.

[0182] For example, let's take the case where the "opposite part" is a rectangle as an example. Figure 13b As shown, the width of the ninth opposing pattern Cp2103 formed by the portion of the second sub-scan signal line GateN2 that is directly opposite to the second connecting line 201b of the first pixel circuit 210 is its dimension in the second direction Y. Similarly, the width of the tenth opposing pattern Cp2104 formed by the portion of the second sub-scan signal line GateN2 that is directly opposite to the second sub-scan signal line GateN2 is its dimension in the second direction Y. The width of the ninth opposing pattern Cp2103 is greater than the width of the tenth opposing pattern Cp2104, and the length of the ninth opposing pattern Cp2103 is equal to the length of the tenth opposing pattern Cp2104. Since the area of ​​a rectangle is the product of its length and width, the area of ​​the ninth opposing pattern Cp2103 is greater than the area of ​​the tenth opposing pattern Cp2104. This results in the capacitance of the second capacitor Cp21 of the first pixel circuit 210 being greater than the capacitance of the second capacitor Cp22 of the second pixel circuit 220.

[0183] By adopting the configuration method in the above embodiment, the effective area of ​​the second capacitor Cp21 in the first pixel circuit 210 (i.e., the area of ​​the part directly opposite the second scan signal line GateN and the second connection line 201b) can be greater than the effective area of ​​the second capacitor Cp22 in the second pixel circuit 220 (i.e., the area of ​​the part directly opposite the second scan signal line GateN and the second connection line 201b). This ensures that the capacitance of the second capacitor Cp21 in the first pixel circuit 210 is greater than the capacitance of the second capacitor Cp22 in the second pixel circuit 220. Consequently, the actual black state voltage required by the first light-emitting device 310 increases, thereby reducing the difference between the actual black state voltage required by the first light-emitting device 310 and the black state voltage VGMP preset by the display driver IC. This can further reduce the color shift phenomenon of the first light-emitting device 310 and the second light-emitting device 320 at low gray levels, as well as the uneven transition phenomenon of the first light-emitting device 310 between gray levels.

[0184] In some embodiments, such as Figure 16 As shown, the anode layer AND includes multiple independent anodes. The light-emitting device 300 may include an anode.

[0185] In some examples, such as Figure 17 As shown, the light-emitting thin film EL is disposed on one side of the anode layer AND and includes multiple independent light-emitting layers. The light-emitting device 300 may also include a light-emitting layer disposed on the anode side. For example, the light-emitting device 300 may also include a cathode disposed on the side of the light-emitting layer away from the anode.

[0186] For example, such as Figure 18 As shown, the light-emitting thin film EL can be disposed on the side of the anode layer AND away from the fifth conductive layer SD2.

[0187] For example, there are various ways to arrange the multiple light-emitting devices in this invention, which can be set according to actual needs, and this invention does not limit them.

[0188] It should be noted that because the cathodes of different light-emitting devices are interconnected in a single structure, and the anodes and light-emitting layers of different light-emitting devices are set independently, the arrangement of the light-emitting devices is the same as the arrangement of the anodes or light-emitting layers. Figure 17 In this invention, the arrangement of the anode or the light-emitting layer is used to represent the arrangement of the light-emitting devices, and the anode and the light-emitting layer belonging to the same light-emitting device are identified as light-emitting devices.

[0189] In some embodiments, such as Figure 17As shown, multiple light-emitting devices 300 are arranged in multiple rows and columns. Along the first direction X, first light-emitting device columns 301a and second light-emitting device columns 301b are arranged alternately; along the second direction Y, first light-emitting device rows 302a and second light-emitting device rows 302b are arranged alternately. Specifically, the first light-emitting device column 301a includes first light-emitting devices 310 and first-type light-emitting devices 321 arranged alternately in sequence; the first light-emitting device row 302a includes first light-emitting devices 310 and first-type light-emitting devices 321 arranged alternately in sequence; the second light-emitting device column 301b includes multiple second-type light-emitting devices 322 arranged alternately in sequence; and the second light-emitting device row 302b includes multiple second-type light-emitting devices 322 arranged alternately in sequence. The first direction X and the second direction Y are perpendicular to each other.

[0190] By arranging the light-emitting devices 300 in the above manner, a reasonable spatial layout of the first light-emitting device 310, the first type of light-emitting device 321, and the second type of light-emitting device 322 can be ensured, thereby improving the display quality of the display substrate 1000 and effectively utilizing the space of the display substrate 1000.

[0191] The shape of the light-emitting layer in the light-emitting device 300 can be varied and can be set according to actual needs. This invention does not impose any restrictions on this.

[0192] For example, the shape of the light-emitting layer of the first light-emitting device 310, the shape of the light-emitting layer of the first type of light-emitting device 321, and the shape of the light-emitting layer of the second type of light-emitting device 322 can be the same or different.

[0193] In some embodiments, such as Figure 17 As shown, the orthographic projection shape of the light-emitting layer on the plane of the display substrate 1000 includes polygons.

[0194] For example, the polygon mentioned above can be a rectangle, or it can be a pentagon, hexagon, etc.

[0195] In some examples, at least one apex corner of the light-emitting layer of the first light-emitting device 310 is an arc-shaped apex corner.

[0196] For example, such as Figure 17 and Figure 18 As shown, the shape of the light-emitting layer of the first light-emitting device 310 is approximately rectangular, and one of the vertices of the approximately rectangular shape is an arc-shaped vertices.

[0197] For example, the shape of the light-emitting layer of the first light-emitting device 310 is approximately rectangular, and the two vertices of the approximately rectangular shape are both arc-shaped vertices.

[0198] In some examples, such as Figure 17As shown, along the direction from the first type of light-emitting device 321 to the adjacent first light-emitting device 310, the arc-shaped apex angle of the light-emitting layer of the first light-emitting device 310 is farther away from the first type of light-emitting device 321 than the other apex angles; the area enclosed by the light-emitting layers of the multiple first light-emitting devices 310 adjacent to the first type of light-emitting device 321 (such as...) Figure 17 (As shown in the dashed box) It has a rounded quadrilateral shape.

[0199] For example, the rounded quadrilateral can be a rounded rectangle, which can save the arrangement space of the light-emitting devices 300 on the display substrate 1000, facilitate the regular design of the relative positions of the light-emitting devices 300, and help simplify the manufacturing process of the display substrate 1000.

[0200] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate includes: multiple pixel circuits, multiple first scan signal lines, multiple light-emitting devices, multiple voltage signal lines, multiple second scan signal lines, and multiple data lines; The pixel circuit includes: a connecting line, a switching transistor, a driving transistor, a storage capacitor, and a compensation transistor; the first terminal of the switching transistor is coupled to the data line, the gate of the switching transistor is coupled to the first scan signal line, the gate of the compensation transistor is coupled to the second scan signal line, and the second terminal of the compensation transistor is coupled to the gate of the driving transistor through the connecting line; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the voltage signal line. The connecting line includes: a first connecting line, which is partially aligned with the first scan signal line, and the two together form a first capacitor; The pixel circuit includes a first pixel circuit and a second pixel circuit; the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device; the first light-emitting device is coupled to the first pixel circuit, the second light-emitting device is coupled to the second pixel circuit, and the first light-emitting device and the second light-emitting device are configured to emit light of different colors; Wherein, the capacitance of the first capacitor in the first pixel circuit is smaller than the capacitance of the first capacitor in the second pixel circuit; the orthographic projection of the voltage signal line on the substrate of the display substrate overlaps with the orthographic projection of the first capacitor on the substrate.

2. The display substrate according to claim 1, characterized in that, The area of ​​the directly opposite portion of the first connecting line and the first scanning signal line in the first pixel circuit is smaller than the area of ​​the directly opposite portion of the first connecting line and the first scanning signal line in the second pixel circuit.

3. The display substrate according to claim 1, characterized in that, The switching transistor and the driving transistor are P-type transistors, and the compensation transistor is an N-type transistor.

4. The display substrate according to claim 1, characterized in that, The connecting line further includes: a second connecting line coupled to the first connecting line; the second connecting line is partially opposite to the second scan signal line, and the two together form a second capacitor; The capacitance of the second capacitor in the first pixel circuit is greater than the capacitance of the second capacitor in the second pixel circuit; the orthographic projection of the voltage signal line on the substrate overlaps with the orthographic projection of the second capacitor on the substrate.

5. The display substrate according to claim 4, characterized in that, The area of ​​the opposite portion of the second connecting line and the second scanning signal line in the first pixel circuit is greater than the area of ​​the opposite portion of the second connecting line and the second scanning signal line in the second pixel circuit.

6. The display substrate according to claim 1, characterized in that, The connecting line further includes: a second connecting line coupled to the first connecting line; The display substrate further includes: a first conductive layer, a first active layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on one side of the substrate; The first connection line is located in the first active layer; the first scan signal line is located in the first conductive layer; the second connection line is located in the fourth conductive layer; and the voltage signal line is located in the fifth conductive layer. The second scan signal line includes a first sub-scan signal line and a second sub-scan signal line; the first sub-scan signal line is located in the second conductive layer, and the second sub-scan signal line is located in the third conductive layer; the second connecting line is partially opposite to the second sub-scan signal line, and the two together constitute the second capacitor.

7. The display substrate according to claim 6, characterized in that, The first scan signal line extends along a first direction; The capacitance of the first capacitor in the first pixel circuit is smaller than the capacitance of the first capacitor in the second pixel circuit. In the first scan signal line, the portion of the line directly opposite the first connection line of the first pixel circuit has a smaller size in the second direction than the portion of the line directly opposite the first connection line of the second pixel circuit. The first direction and the second direction are perpendicular to each other.

8. The display substrate according to claim 6 or 7, characterized in that, The first scan signal line extends along a first direction; The capacitance of the first capacitor in the first pixel circuit is smaller than the capacitance of the first capacitor in the second pixel circuit. In the first connection line of the first pixel circuit, the portion of the part directly opposite the first scan signal line in the first direction is smaller than the portion of the first connection line of the second pixel circuit that is directly opposite the first scan signal line in the first direction. And / or, In the first connection line of the first pixel circuit, the portion of the part directly opposite the first scan signal line has a smaller size in the second direction than the portion of the first connection line of the second pixel circuit that is directly opposite the first scan signal line in the second direction. The first direction and the second direction are perpendicular to each other.

9. The display substrate according to claim 6, characterized in that, The second scan signal line extends along the first direction; The capacitance of the second capacitor in the first pixel circuit is greater than the capacitance of the second capacitor in the second pixel circuit. The size of the portion of the second connection line of the first pixel circuit that is directly opposite the second scan signal line in the first direction is greater than the size of the portion of the second connection line of the second pixel circuit that is directly opposite the second scan signal line in the first direction.

10. The display substrate according to claim 9, characterized in that, In the second sub-scan signal line, the size of the portion directly opposite the second connection line of the first pixel circuit in the second direction is equal to the size of the portion directly opposite the second connection line of the second pixel circuit in the second direction. The first direction and the second direction are perpendicular to each other.

11. The display substrate according to claim 6 or 9, characterized in that, The second scan signal line extends along the first direction; The capacitance of the second capacitor in the first pixel circuit is greater than the capacitance of the second capacitor in the second pixel circuit. In the second sub-scan signal line, the size of the portion directly opposite the second connection line of the first pixel circuit in the first direction is greater than the size of the portion directly opposite the second connection line of the second pixel circuit in the first direction.

12. The display substrate according to claim 6, characterized in that, The display substrate further includes: a second active layer disposed between the substrate and the first conductive layer; The switching transistor includes a first active pattern and a first gate pattern, the driving transistor includes a second active pattern and a second gate pattern, and the compensation transistor includes a third active pattern, a third gate pattern, and a fourth gate pattern. The first active pattern and the second active pattern are located in the second active layer, and the two are connected and form an integral structure; The first gate pattern and the second gate pattern are located in the first conductive layer, and the first gate pattern and the first scan signal line are connected and form an integral structure; The third active pattern is located in the first active layer, the third gate pattern is located in the second conductive layer, and the third gate pattern is connected to the first sub-scan signal line to form an integral structure. The fourth gate pattern is located in the third conductive layer, and the fourth gate pattern is connected to the second sub-scan signal line to form an integral structure.

13. The display substrate according to claim 1, characterized in that, The display substrate further includes: multiple reset signal lines, multiple first initial signal lines, multiple second initial signal lines, and multiple enable signal lines; The pixel circuit further includes: a first reset transistor, a second reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The gate of the first reset transistor is coupled to the reset signal line, the first terminal of the first reset transistor is coupled to the first initial signal line, and the second terminal of the first reset transistor is coupled to the connection line. The gate of the first light-emitting control transistor is coupled to the enable signal line, the first terminal of the first light-emitting control transistor is coupled to the voltage signal line, and the second terminal of the first light-emitting control transistor is coupled to the first terminal of the driving transistor. The gate of the second light-emitting control transistor is coupled to the enable signal line, the first terminal of the second light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is coupled to the first node; The gate of the second reset transistor is coupled to the first scan signal line, the first terminal of the second reset transistor is coupled to the second initial signal line, and the second terminal of the second reset transistor is coupled to the first node; The second plate of the storage capacitor is also coupled to the connecting line.

14. The display substrate according to claim 13, characterized in that, The compensation transistor and the first reset transistor are both oxide transistors, and the switching transistor, the driving transistor, the second reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor are all low-temperature polycrystalline silicon transistors.

15. The display substrate according to claim 1, characterized in that, The first light-emitting device is configured to emit blue light under the action of the first pixel circuit; The second light-emitting device is configured to emit red or green light under the action of the second pixel circuit.

16. The display substrate according to claim 15, characterized in that, The second light-emitting device includes a first type of light-emitting device and a second type of light-emitting device, wherein the first type of light-emitting device is configured to emit red light and the second type of light-emitting device is configured to emit green light; The multiple light-emitting devices are arranged in multiple rows and columns; Along the first direction, the first column of light-emitting devices and the second column of light-emitting devices are arranged alternately; along the second direction, the first row of light-emitting devices and the second row of light-emitting devices are arranged alternately. Wherein, the first light-emitting device column includes the first light-emitting device and the first type of light-emitting device arranged alternately in sequence, the first light-emitting device row includes the first light-emitting device and the first type of light-emitting device arranged alternately in sequence, the second light-emitting device column includes a plurality of second type of light-emitting devices arranged in sequence, and the second light-emitting device row includes a plurality of second type of light-emitting devices arranged in sequence; The first direction and the second direction are perpendicular to each other.

17. A display device, characterized in that, The display device includes: a display substrate as described in any one of claims 1 to 16.

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