Semiconductor device and method of operation thereof, system

Abstract

The present disclosure provides semiconductor devices and methods of operating the same. A semiconductor device includes an array of memory cells, a word line coupled with the array of memory cells, and a peripheral circuit coupled with the word line, the peripheral circuit configured to: perform a first program operation on a target set of memory cells in a plurality of sets of memory cells coupled with the selected word line, the first program operation including a plurality of first program loops; the target set of memory cells including a plurality of memory cells in a target threshold voltage distribution corresponding to a threshold voltage to be programmed to one of a plurality of states; perform a second program operation on the target set of memory cells, the second program operation including at least one second program loop, the second program loop including a verify phase and a program phase following the verify phase, wherein at least a portion of the target set of memory cells are verified during the verify phase of the second program loop and program is performed on memory cells that fail verification during the program phase of the second program loop.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and their operating methods and systems. Background Technology

[0002] As the parameters of large AIGC (Artificial Intelligence Generated Content) models continue to grow, the traditional von Neumann architecture faces the "memory wall" and "power wall" problems. The bandwidth between the CPU (Central Processing Unit) and memory has become a bottleneck restricting the performance of AI (Artificial Intelligence) chips. Inspired by the working mode of the human brain, in-memory computing architecture has flourished in recent years. By embedding computing functions in memory, it avoids data transfer back and forth, reducing the impact of the "memory wall" and "power wall," thus promising to build high-performance, high-bandwidth, and high-energy-efficiency computing systems. Improving the accuracy of in-memory operations and data read / write operations has been a long-term research focus in this field. Summary of the Invention

[0003] This disclosure provides semiconductor devices and their operating methods and systems.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including: a memory cell array, word lines coupled to the memory cell array, and peripheral circuitry coupled to the word lines, wherein the peripheral circuitry is configured to:

[0005] A first programming operation is performed on a target set of multiple memory cells coupled to a select word line, the first programming operation including multiple first programming loops; the target set of memory cells includes multiple memory cells in a target threshold voltage distribution corresponding to a state of multiple states to be programmed with a threshold voltage.

[0006] A second programming operation is performed on the target storage cell set. The second programming operation includes at least one second programming loop. The second programming loop includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the storage cells in the target storage cell set are verified. In the programming phase of the second programming loop, the storage cells that fail verification are programmed.

[0007] Secondly, embodiments of this disclosure provide yet another semiconductor device, including: a memory cell array, word lines coupled to the memory cell array, and peripheral circuitry coupled to the word lines, wherein the peripheral circuitry is configured to:

[0008] A first programming operation is performed on at least one set of memory cells corresponding to a programming state of a plurality of memory cells coupled to a select word line; the set of memory cells includes a plurality of memory cells in a target threshold voltage distribution corresponding to the same programming state or erase state, to which a threshold voltage will be programmed.

[0009] A second programming operation is performed on the set of memory cells corresponding to the erased state. The second programming operation includes at least one second programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified, and in the programming phase of the second programming loop, the memory cells that fail verification are programmed.

[0010] Thirdly, embodiments of this disclosure provide a system comprising: one or more semiconductor devices as described in any one of the first and second aspects of this disclosure; and,

[0011] A memory controller is coupled to the semiconductor device and configured to control the semiconductor device.

[0012] Fourthly, embodiments of this disclosure provide a method for operating a semiconductor device, the method comprising:

[0013] A first programming operation is performed on a target set of multiple memory cells coupled to a select word line, the first programming operation including multiple first programming loops; the target set of memory cells includes multiple memory cells in a target threshold voltage distribution corresponding to a state of multiple states to be programmed with a threshold voltage.

[0014] A second programming operation is performed on the target storage cell set. The second programming operation includes at least one second programming loop. The second programming loop includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the storage cells in the target storage cell set are verified. In the programming phase of the second programming loop, the storage cells that fail verification are programmed.

[0015] Fifthly, embodiments of this disclosure provide a method for operating a semiconductor device, the method comprising:

[0016] A first programming operation is performed on at least one set of memory cells corresponding to a programming state of a plurality of memory cells coupled to a select word line; the set of memory cells includes a plurality of memory cells in a target threshold voltage distribution corresponding to the same programming state or erase state, to which a threshold voltage will be programmed.

[0017] A second programming operation is performed on the set of memory cells corresponding to the erased state. The second programming operation includes at least one second programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified, and in the programming phase of the second programming loop, the memory cells that fail verification are programmed.

[0018] In the technical solution provided in this disclosure, during the data storage write operation phase, the target storage cell set can be the storage cell set corresponding to the programmed state. Performing a first programming operation on the target storage cell set can create an intermediate threshold voltage distribution. In the first second programming loop of the second programming operation, verification is performed to select a portion of storage cells near the lower tail from the intermediate threshold voltage distribution. These selected storage cells are then programmed, while other storage cells in the intermediate threshold voltage distribution are not programmed. By appropriately increasing the threshold voltage of the storage cells in the lower tail, the threshold voltage distribution can be effectively narrowed, thereby improving data read / write accuracy and effectively reducing the impact of the IVS effect on data storage accuracy.

[0019] During the write operation phase of in-memory operations, the target memory cell set can be the memory cell set corresponding to the erase state. After performing the first programming operation and the second programming operation on the target memory cell set, the threshold voltage distribution corresponding to the erase state can be narrowed, thereby narrowing the magnitude of each current during the operation phase and improving the accuracy of in-memory operations. Attached Figure Description

[0020] Figure 1 A schematic diagram of a semiconductor device including peripheral circuitry provided for embodiments of this disclosure.

[0021] Figure 2a A schematic diagram of a semiconductor device including peripheral circuitry and a memory cell array provided for embodiments of this disclosure. Figure 1 .

[0022] Figure 2b Schematic diagram 2 of a semiconductor device including peripheral circuits and a memory cell array provided for embodiments of this disclosure.

[0023] Figure 3 This is a schematic diagram of a first programming operation and a second programming operation performed on a semiconductor device provided in an embodiment of this disclosure.

[0024] Figure 4 This diagram illustrates the threshold voltage change of a select-word-line-coupled memory cell during the write operation phase of data storage, as provided in an embodiment of this disclosure.

[0025] Figure 5A schematic diagram of the threshold voltage change of the memory cell set corresponding to the programming state provided in the embodiments of this disclosure. Figure 1 .

[0026] Figure 6 Schematic diagram 2 showing the threshold voltage change of the memory cell corresponding to the programming state provided in the embodiments of this disclosure.

[0027] Figure 7 This is a schematic diagram of an embodiment of the present disclosure where an input voltage is input to a memory block via a top selection line.

[0028] Figure 8 This is a schematic diagram illustrating the in-memory operation performed by a storage cell array including a single-level storage cell, as provided in an embodiment of this disclosure.

[0029] Figure 9 A schematic diagram of the threshold voltage distribution during the write operation phase of a select-word-line coupled memory cell provided in this embodiment of the present disclosure. Figure 1 .

[0030] Figure 10 Schematic diagram 2 showing the threshold voltage distribution of a word-line coupled memory cell during the write operation phase of memory operations, as provided in an embodiment of this disclosure.

[0031] Figure 11 A schematic diagram of the threshold voltage distribution during the write operation phase of a select-word-line coupled memory cell provided in this embodiment of the present disclosure. Figure 3 .

[0032] Figure 12 A schematic diagram of the first programming operation provided for embodiments of this disclosure. Figure 1 .

[0033] Figure 13 Schematic diagram two of the first programming operation provided in the embodiments of this disclosure.

[0034] Figure 14 This is a schematic diagram of a threshold voltage distribution provided in an embodiment of the present disclosure.

[0035] Figure 15 Illustration of the second programming operation provided for embodiments of this disclosure Figure 1 .

[0036] Figure 16 Schematic diagram two of the second programming operation provided in the embodiments of this disclosure.

[0037] Figure 17 Illustration of the second programming operation provided for embodiments of this disclosure Figure 3 .

[0038] Figure 18This is a schematic flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure.

[0039] Figure 19 This is a flowchart illustrating another method of operating a semiconductor device provided in an embodiment of this disclosure.

[0040] Figure 20 A schematic diagram of the system provided in an embodiment of this disclosure Figure 1 .

[0041] Figure 21 This is a schematic diagram of the system provided in one embodiment of the present disclosure.

[0042] Figure 22 This is a schematic diagram of an exemplary memory card with a memory system provided according to an embodiment of the present disclosure.

[0043] Figure 23 This is a schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of the present disclosure. Detailed Implementation

[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0047] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0050] In-memory computing chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory is a non-volatile memory with a large capacity, making it a focus of attention in in-memory computing chips. The following will provide a related introduction to NAND flash memory.

[0051] Figure 1 This is a schematic diagram of a semiconductor device including peripheral circuitry provided for embodiments of the present disclosure. The semiconductor device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. Taking a three-dimensional NAND-type memory array as an example, the memory cells 106 are NAND memory cells, provided in the form of an array of memory strings (also referred to as memory cell strings) 108, each memory string 108 extending vertically. In some embodiments, each memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0052] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0053] like Figure 1As shown, each memory string 108 may include a bottom select gate (BSG) 110 at its source terminal and a top select gate (TSG) 112 at its drain terminal. The bottom select gate 110 and top select gate 112 can be configured to activate the selected memory string 108 during read and program operations. In some embodiments, the sources of memory strings 108 within the same memory block 104 can be coupled via a common source line (CSL) 114. In other words, all memory strings 108 within the same memory block 104 have a common source (ACS). According to some embodiments, the top select gate 112 of each memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written. Each memory string 108 has a top select transistor 112 coupled to a corresponding top select line (TSL) 113, and a bottom select transistor 110 coupled to a corresponding bottom select line (BSL) 115. In some embodiments, each memory string 108 is configured to be selected or deselected by applying a select voltage (e.g., a voltage higher than a threshold voltage of the top select transistor 112) or a deselect voltage (e.g., 0V) to the corresponding top select transistor 112 via one or more top select lines 113 and / or by applying a select voltage (e.g., a voltage higher than a threshold voltage of the bottom select transistor 110) or a deselect voltage (e.g., 0V) to the corresponding bottom select transistor 110 via one or more bottom select lines (BSL) 115. Memory cells 106 of adjacent memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations.

[0054] Continue to refer to Figure 1 The peripheral circuitry 102 can be coupled to the memory array 101 via bit line 116, word line 118, source line 114, bottom select line 115, and top select line 113. The peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 101 by applying voltage and / or current signals to each memory cell 106 and sensing voltage and / or current signals from each memory cell 106 via bit line 116, word line 118, source line 114, bottom select line 115, and top select line 113. The peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0055] Figure 2a A schematic diagram of a semiconductor device including peripheral circuitry and a memory cell array provided for embodiments of this disclosure. Figure 1 Combined with reference Figure 1 and Figure 2a The peripheral circuitry 102 may include control logic 212, a digital-to-analog converter (DAC) 201 coupled to the control logic 212 and the memory cell array 101, and an analog-to-digital converter (ADC) 202 coupled to the memory cell array 101 and the control logic 212. During in-memory computation using semiconductor devices, the DAC 201 can convert digital signals into voltage signals required by the memory cell array 101 in the in-memory computing chip. The ADC 202 can convert the current signals output by the memory cell array 101 into digital signals. The control logic 212 may be coupled to the peripheral circuitry and configured to control the operation of the peripheral circuitry. The control logic 212 can also be used to receive input data sent by the controller and send the computation results to the controller.

[0056] Figure 2b Schematic diagram two of a semiconductor device including peripheral circuitry and a memory cell array provided for embodiments of this disclosure, except... Figure 2a In addition to the circuit structure shown, such as Figure 2b As shown, the peripheral circuitry may also include a page buffer / sensor amplifier 204, a column decoder / bit line (BL) driver 206, a row decoder / word line (WL) driver 208, a voltage generator 210, a register 214, an interface 216, and a data bus 218. It should be understood that in some examples, it may also include... Figure 2a and Figure 2b Additional peripheral circuitry not shown.

[0057] Page buffer / sensor amplifier 204 can be configured to read data from and program (write) data to memory cell array 101 according to control signals from control logic 212. In one example, page buffer / sensor amplifier 204 can store a page of programming data to be programmed into a page of memory cell array 101. In another example, page buffer / sensor amplifier 204 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 204 can also sense a low-power signal from bit line 116 representing a data bit stored in memory cell 106 and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 206 can be configured to be controlled by control logic 212 and select one or more memory strings 108 by applying a bit line voltage generated from voltage generator 210.

[0058] The row decoder / word line driver 208 can be configured to be controlled by control logic 212 and to select / deselect memory blocks 104 of the memory cell array 101 and to select / deselect word lines 118 of memory blocks 104. The row decoder / word line driver 208 can also be configured to drive word lines 118 using word line voltages generated from voltage generator 210. In some embodiments, the row decoder / word line driver 208 can also select / deselect and drive BSL 115 and TSL 113. As described in detail below, the row decoder / word line driver 208 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 118. The voltage generator 210 can be configured to be controlled by control logic 212 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, select voltage, programming verification voltage, etc., input voltage), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0059] Register 214 can be coupled to control logic 212 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 216 can be coupled to control logic 212 and acts as a control buffer to buffer control commands received from the host device and relay them to control logic 212, as well as to buffer status information received from control logic 212 and relay it to the host device. Interface 216 can also be coupled to column decoder / bit line driver 206 via data bus 218 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 101.

[0060] In some embodiments, such as Figure 2b As shown, the analog-to-digital converter (ADC) 201 can be specifically connected to the control logic 212 and the voltage generator 210, and the analog-to-digital converter (ADC) 202 can be specifically connected to the control logic 212 and the column decoder / bit line driver 206. During the computation phase using the three-dimensional NAND memory, the control logic receives input data sent by the controller. The ADC converts the input data into voltage signals that need to be applied to the word lines or bit lines. The voltage generator generates the corresponding voltages that need to be applied to the word lines or bit lines. The row decoder / word line driver is configured to drive the selected word line using the word line voltage generated by the voltage generator, or the column decoder / bit line driver is configured to drive the selected bit line using the bit line voltage generated by the voltage generator. The analog computation result is transmitted to the ADC through the page buffer and the column decoder. The ADC converts the analog computation result into a digital computation result and transmits the final digital computation result to the control logic.

[0061] In in-memory computing (IMC) systems, narrowing the threshold voltage distribution can improve the accuracy of data reading and writing, as well as the accuracy and computing power of in-memory computing. This disclosure provides a semiconductor device capable of high-precision programming and narrowing the threshold voltage distribution. Figure 3 This diagram illustrates a first programming operation and a second programming operation performed by a semiconductor device provided in an embodiment of this disclosure. The semiconductor device includes: a memory cell array, word lines coupled to the memory cell array, and peripheral circuitry coupled to the word lines, such as... Figure 3 As shown, the peripheral circuit is configured as follows:

[0062] A first programming operation is performed on a target set of multiple memory cells coupled to a select word line. The first programming operation includes multiple first programming loops. The target set of memory cells includes multiple memory cells in a target threshold voltage distribution corresponding to a state where a threshold voltage will be programmed.

[0063] A second programming operation is performed on a target set of storage cells. The second programming operation includes at least one second programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the storage cells in the target set of storage cells are verified, and in the programming phase of the second programming loop, the storage cells that fail verification are programmed.

[0064] For example, in the verification phase of the first second programming loop, the target memory set (i.e., all memory units in the target memory set) is verified. In the verification phases of each of the other second programming loops, at least a portion of the memory units in the target memory set is verified. In the programming phase of each second programming loop, the memory units that failed verification in the verification phase within the same second programming loop are programmed.

[0065] The memory cell array and peripheral circuitry can be Figures 1 to 2b The memory cell array 101 and peripheral circuitry 102 shown in either example. Word lines can be... Figure 1 The character line 118 is shown in the image.

[0066] In this embodiment, the memory cell can be a single-level memory cell (SLC) with two possible memory states: an erase state (also called an erase state) E and a programmable state (also called a programmable state) P. Correspondingly, multiple memory cells coupled to the select word line can be divided into two memory cell sets A and B. In one memory cell set, all memory cells store the same data, meaning the threshold voltage of all memory cells in that set will fall within the same target threshold voltage distribution corresponding to the same state. Different memory cell sets store different data, meaning different memory cell sets correspond to different target threshold voltage distributions. For example, memory cells in memory cell set A all store data 0, and the memory cells in memory cell set A will fall within the target threshold voltage distribution corresponding to the erase state. Memory cells in memory cell set B all store data 1, and the memory cells in memory cell set B will be programmed into the target threshold voltage distribution corresponding to the programmable state. The target memory cell set can be any one of multiple memory cell sets. That is, the target memory cell set can be memory cell set A or memory cell set B.

[0067] It should be understood that the storage cells in a storage cell set do not necessarily have to be adjacent or continuously distributed. Whether each storage cell on a word line stores data 0 or data 1 depends on the data being written, and multiple storage cells that typically store the same data are not continuously distributed.

[0068] Furthermore, a memory cell can also be a multi-level memory cell with more than two possible memory states. For example, a memory cell can be a multi-level memory cell (MLC) with four possible memory states: erase state E and programmed states P1, P2, and P3. Correspondingly, the multiple memory cells coupled to the select word line can be divided into at most four memory cell sets A, B, C, and D. The threshold voltage of all memory cells in memory cell set A will be within the target threshold voltage distribution corresponding to erase state E; the threshold voltage of all memory cells in memory cell set B will be programmed into the target threshold voltage distribution corresponding to state P1; the threshold voltage of all memory cells in memory cell set C will be programmed into the target threshold voltage distribution corresponding to state P2; and the threshold voltage of all memory cells in memory cell set D will be programmed into the target threshold voltage distribution corresponding to state P3. The target memory cell set can be any one of the multiple memory cell sets. That is, the target memory cell set can be memory cell set A, memory cell set B, memory cell set C, or memory cell set D.

[0069] For example, a memory cell can also be a three-level memory cell (TLC) with eight possible memory states. Correspondingly, multiple memory cells coupled to the select word line can be divided into at most eight sets of memory cells, with the target set being any one of the eight sets. A memory cell can also have more memory states, and multiple memory cells coupled to the select word line can be divided into at most the same number of sets of memory cells as the number of memory states, with the target set being any one of the sets.

[0070] This disclosure is illustrated using the example of a memory cell having two possible memory states, namely erase state E and programmed state P. Figure 4 This is a schematic diagram illustrating the threshold voltage change of a word-line coupled memory cell during the write operation phase of data storage, provided in an embodiment of this disclosure. The vertical axis represents the number of memory cells, and the horizontal axis represents the threshold voltage Vth. Figure 5 A schematic diagram of the threshold voltage change of the memory cell set corresponding to the programming state provided in the embodiments of this disclosure. Figure 1 , Figure 6 Schematic diagram two illustrating the threshold voltage change of the memory cell corresponding to the programming state provided in this embodiment of the disclosure. The following is in conjunction with... Figures 4 to 6 A programming method provided by an embodiment of this disclosure is described in detail.

[0071] The memory provided in this disclosure supports data storage and in-memory operations. In some embodiments, during the data storage write operation phase, the target memory cell set is the memory cell set corresponding to the programmed state P. The first programming operation, also known as a coarse programming operation, can program the threshold voltage of the memory cell into an intermediate threshold voltage distribution.

[0072] For a single-level memory unit, there is only one programmed state P. For example... Figure 4 As shown, the first programming operation can be performed only on the memory cell set B corresponding to the programming state P, so that the threshold voltage of the memory cells in memory cell set B is formed. Figure 4 The intermediate threshold voltage distribution M 12 The threshold voltages of the unprogrammed memory cells in set A form an intermediate threshold voltage distribution M. 11 .

[0073] It should be noted that for multi-level memory cells, there are multiple programming states, so the first programming operation can be performed simultaneously on the memory cell sets corresponding to all programming states. For example, if an MLC has three programming states, the first programming operation can be performed simultaneously on the memory cell sets corresponding to these three programming states, resulting in three intermediate threshold voltage distributions after the first programming operation. The memory cell sets corresponding to the unprogrammed erase state also form one intermediate threshold voltage distribution.

[0074] See Figure 5 Taking the set of memory cells corresponding to one of the programming states P as an example, after the first programming operation, due to the Initial Voltage Shift (IVS) effect, the threshold voltage of some memory cells in the set will decrease, and the degree of decrease may be different for memory cells with different threshold voltages. This will cause the threshold voltage distribution corresponding to the programming state to widen and shift towards lower threshold voltages (i.e., Figure 5 (Move left in the middle).

[0075] Based on this, the present disclosure proposes that in the first second programming loop of the second programming operation, the set of storage units corresponding to the programming state P is first verified, and the storage units that fail to be verified are selected. Then, in the programming phase of the first second programming loop, only the storage units that fail to be verified are programmed.

[0076] Here, verification failure means that the threshold voltage of the storage cell is less than the first preset threshold voltage Vth_1, which is related to the target threshold voltage distribution corresponding to the target storage cell set.

[0077] For example, the process of verifying the set of memory cells corresponding to the programming state in the first second programming loop can be implemented as follows: a verification pulse is applied to the select word line, and the page buffer coupled to each memory cell in the set of memory cells corresponding to the programming state P senses the voltage change on the bit line, and determines whether the verification is successful based on the voltage change on the bit line.

[0078] The voltage magnitude and sensing time of the verification pulse are related to the position of the first preset threshold voltage Vth_1. By controlling the voltage magnitude and sensing time of the verification pulse, memory cells with threshold voltages lower than the first preset threshold voltage Vth_1 can be selected.

[0079] The first preset threshold voltage Vth_1 is related to the intermediate threshold voltage distribution after IVS. The first preset threshold voltage is located within the intermediate threshold voltage distribution after IVS, allowing for the selection of a subset of memory cells for reprogramming. This embodiment does not limit the specific position of the first preset threshold voltage Vth_1 within the intermediate threshold voltage distribution after IVS, that is, it does not limit the number of memory cells selected that failed verification. In practical applications, an appropriate number of memory cells that failed verification can be selected based on parameters such as the intermediate threshold voltage distribution after IVS, the target threshold voltage distribution, the number of programming operations, and the programming and verification voltages in the next programming operation.

[0080] The first preset threshold voltage Vth_1 is related to the target threshold voltage distribution, meaning that the first preset threshold voltage Vth_1 is related to the intermediate threshold voltage distribution after IVS, and the intermediate threshold voltage distribution after IVS is related to the target threshold voltage distribution. The first preset threshold voltage Vth_1 can be less than or equal to the lower limit of the target threshold voltage distribution.

[0081] Furthermore, the first preset threshold voltage Vth_1 can be less than, equal to, or greater than the lower limit of the intermediate threshold voltage distribution after the first programming operation. Figure 5 This illustrates the case where the first preset threshold voltage Vth_1 equals the lower limit of the intermediate threshold voltage distribution after the first programming operation. And... Figure 6 This illustrates a scenario where the first preset threshold voltage is less than the lower limit of the intermediate threshold voltage distribution after the first programming operation. It should be understood that in different embodiments, for different purposes, the intermediate threshold voltage distribution after the first programming operation may be lower than, equal to, or higher than the target threshold voltage distribution. For example, such as... Figure 5 As shown, if the lower limit of the intermediate threshold voltage distribution after the first programming operation is equal to the lower limit of the target threshold voltage distribution, but the IVS effect causes the intermediate threshold voltage distribution to shift to the left, and the first preset threshold voltage Vth_1 used in the second programming operation can be the lower limit of the target threshold voltage distribution, then the first preset threshold voltage Vth_1 is equal to the lower limit of the intermediate threshold voltage distribution after the first programming operation. Also, for example, as... Figure 6 As shown, if the IVS effect is considered, the intermediate threshold voltage distribution after the first programming operation is higher than the target threshold voltage distribution, and the first preset threshold voltage Vth_1 used in the second programming operation is the lower limit of the target threshold voltage distribution, then the first preset threshold voltage Vth_1 is less than the lower limit of the intermediate threshold voltage distribution after the first programming operation. As another example, the first preset threshold voltage Vth_1 can be any value between the lower limit of the target threshold voltage distribution and the lower limit of the intermediate threshold voltage distribution after IVS, with the aim of making the threshold voltage distribution closer to the target threshold voltage distribution after programming the selected memory cells that failed verification.

[0082] In summary, the second programming operation can set a first preset threshold voltage Vth_1 for the purpose of gradually narrowing the threshold voltage distribution, and in subsequent programming operations, program the threshold voltage distribution of the memory cell set to the target threshold voltage distribution. Alternatively, the second programming operation can set the first preset threshold voltage Vth_1 for the purpose of programming the threshold voltage distribution of the memory cell set to the target threshold voltage distribution.

[0083] like Figure 5 and Figure 6As shown, in the first second programming loop of the second programming operation, after programming the selected memory cells that failed verification, the threshold voltage of the failed memory cells shifts in the direction of increasing threshold voltage (i.e., to the right in the figure), which can narrow the threshold voltage distribution of the memory cell set. In the other second programming loops after the first second programming loop, only the memory cells that failed verification are programmed, thus ultimately making the threshold voltage distribution of the programmed state after the second programming operation narrower than the threshold voltage distribution after the first programming operation. For example, the second programming operation is also called the fine programming operation.

[0084] For example, such as Figure 4 As shown, during the write operation phase of data storage, the set of memory cells corresponding to the erase state E can be left unprogrammed. After the second programming operation, the threshold voltage of the set of memory cells corresponding to the erase state E still forms the intermediate threshold voltage distribution M. 11 .

[0085] For example, the second programming operation can be performed separately on the memory cell set corresponding to each programming state P. Also for example, the second programming operation can be performed simultaneously on the memory cell sets corresponding to multiple programming states P.

[0086] In this embodiment of the present disclosure, during the write operation phase of data storage, a first programming operation is performed on the target storage cell set, which can cause the threshold voltage of the target storage cell set to form an intermediate threshold voltage distribution. In the first second programming loop of the second programming operation, verification is performed first to select a portion of storage cells near the low tail from the intermediate threshold voltage distribution, and then the selected storage cells are programmed, while the other storage cells in the intermediate threshold voltage distribution are not programmed. By appropriately increasing the threshold voltage of the storage cells in the low tail, the threshold voltage distribution can be effectively narrowed, thereby improving the accuracy of data read and write and effectively reducing the impact of the IVS effect on the accuracy of data storage.

[0087] In some embodiments, the memory can perform in-memory operations. In-memory operations refer to performing multiplication operations between the input data and the weight matrix within the memory to obtain the corresponding elements in the output data. The input data can be an input matrix or an input vector consisting of multiple elements.

[0088] During the in-memory operation phase, the memory cell array can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the memory cell array according to a certain mapping rule, and each memory cell in the array can be configured to store one weight. During the operation phase, the memory can receive input data from the controller. The input data can be an input matrix consisting of multiple elements, and each element in the input data can be processed... Figure 2a or Figure 2bThe output digital-to-analog converter circuit converts the input voltage to... Figure 1 The bit lines, word lines, or select lines shown are input to the memory cell array. The select line can be one of the top select line 113 and the bottom select line 115.

[0089] Figure 7 This is a schematic diagram illustrating an embodiment of the present disclosure where an input voltage is input to a memory block via a top selection line. (See diagram below.) Figure 7 As shown, multiple memory cells coupled to the select word line WLn can be configured as multiple weights in a storage weight matrix. Specifically, the memory state corresponding to the threshold voltage of a memory cell can correspond to a weight.

[0090] The values ​​of multiple elements in the input data are mapped to multiple input voltages, which are applied to the storage block by corresponding top-select lines. Each element in the output matrix is ​​mapped to a current I on a bit line, and the current on the bit line corresponds to the sum of the products of multiple input voltages multiplied by their corresponding weights. Figure 7 For example, when the corresponding input voltage V is applied to multiple top selection lines TSL0, TSL1, and TSL2 respectively... in0 V in1 and V in2 At that time, the current I0 on the bit line BL0 corresponds to V in0 ×w 00 +V in1 ×w 10 +V in2 ×w 20 As a result, the current I1 on bit line BL1 corresponds to V in0 ×w 01 +V in1 ×w 11 +V in2 ×w 21 As a result, the current I2 on bit line BL2 corresponds to V in0 ×w 02 +V in1 ×w 12 +V in2 ×w 22 The result.

[0091] Figure 8 This is a schematic diagram illustrating the in-memory operation performed by a storage cell array including a single-level storage cell, as provided in an embodiment of this disclosure. Figure 8 This explanation will only consider a string of memory cells coupled to the same bit line BL0 as an example. For example... Figure 8 As shown, the value of any weight in the weight matrix is ​​either "1" or "0". The memory cell has erase and program states; for example, erase state E corresponds to a weight value of "1", and program state P corresponds to a weight value of "0".

[0092] The input values ​​in the input data are mapped to the input voltage V. in The input data is applied to the memory cell array via the top select line. The input value in the input data is either "1" or "0", which can be mapped to a high-level input voltage and a low-level input voltage. A high-level input voltage is greater than the threshold voltage of the top select transistor (TSG), causing the TSG to be in the on state; a low-level input voltage is less than the threshold voltage of the TSG, causing the TSG to be in the off state. For example, a high-level input voltage corresponds to the input value "1", and a low-level input voltage corresponds to the input value "0".

[0093] During the computation phase, a read voltage V is applied to the select word line WLn. rd Apply a turn-on voltage V to the non-selection word lines WL0~WLn-1 and WLn+1~WL_end pass For the gates of multiple top select lines, i.e., multiple top select transistors TSG0-TSGn, respectively, the corresponding input voltage V is applied. in0 -V inn And sense the current on bit line BL0.

[0094] Read voltage V rd The read voltage V is greater than the threshold voltage of the memory cell in the erase state E, and less than the threshold voltage of the memory cell in the programmable state P. In other words, the read voltage V... rd Located between the target threshold voltage distribution range corresponding to the erase state E and the target threshold voltage distribution range corresponding to the programming state P, it is possible to distinguish whether a memory cell is in erase state E or programming state P. An on-state voltage V is applied to the non-select word line coupled to the same memory block. pass This allows all memory cells coupled to the non-select word line to be in the on state. In this case, the current in each memory string is only related to the threshold voltage of the memory cell coupled to the select word line WLn, i.e., the memory state.

[0095] like Figure 9 As shown, when a high-level input voltage (corresponding to input value "1") is applied to the top select line, causing the top select transistor TSG to conduct, if the memory cell has an erase state E, then the threshold voltage of the memory cell is less than the read voltage V. rd This causes the memory string to be connected and generate a significant current; if the memory cell has a programmed state P, then the threshold voltage of the memory cell is greater than the read voltage V. rdThis turns off the memory string to which the memory cell belongs, preventing the generation of a significant current. Corresponding to the input and weight values, this can be understood as follows: when the input value is 1, if the weight value stored in the memory cell is 1 (corresponding to the erase state E), then the memory string will generate current; when the input value is 1, if the weight value stored in the memory cell is 0 (corresponding to the programming state P), then the memory string will not generate current.

[0096] Similarly, applying a low-level input voltage (corresponding to an input value of "0") to the top select line turns off the top select transistor. At this time, no current is generated in the memory string, regardless of whether the memory cell is in erase state E or programmed state P. Corresponding to the input value and weight value, this can be understood as follows: when the input value is 0, regardless of whether the weight value is 1 (corresponding to erase state E) or 0 (corresponding to programmed state P), no current is generated in the memory string. Based on this, we can define the output value as 1 when the memory string generates current, and 0 when the memory string does not generate current. Therefore, we can obtain the following: when the input value is 1 and the weight value is 1, the output value is 1; when the input value is 1 and the weight value is 0, the output value is 0; when the input value is 0 and the weight value is 1, the output value is 0; when the input value is 0 and the weight value is 0, the output value is 0. This is consistent with the rules of multiplication. Therefore, the input voltage can be applied to the memory cell array through the top select line, the weight value can be stored in the memory cells, and the output value can be obtained through the current in the bit line, thus using the memory array to realize the multiplication operation between the input vector and the weight matrix.

[0097] See also Figure 9 When a corresponding input voltage V is applied to the gate of multiple top select lines, i.e., multiple top select transistors TSG0, TSG1... to TSGn, respectively... in0 V in1 …V inn The current obtained on bit line BL0 is the sum of the currents of multiple memory strings, corresponding to multiple input values ​​V. in0 V in1 …V inn With the corresponding weight w 00 w 10 w 20 …w n1 The result of multiplying and then summing the products. That is, the value I corresponding to the current on the voltage line. D0 =V in0 ×w 00 +V in1 ×w 10 +…+V inn ×w n0 In this embodiment, the current I on the bit line D0 = 1×1+1×0+0×1...+1×0+0×0.

[0098] As mentioned above, during the in-memory operation phase, when a memory cell is in the erase state E, a memory string may output a single current, while multiple currents from multiple memory strings converge on the bit line. With increasing demands on memory computing power, the number of memory strings coupled to the bit line continues to increase. If the distribution of each current is wide, calculation errors may occur. For example, if the magnitude of N currents may be greater than the magnitude of N+1 currents, the sum of N values ​​may equal the sum of N+1 values, leading to a calculation error. Therefore, this disclosure proposes to tighten the threshold voltage distribution in the erase state E to tighten the distribution of each current and improve calculation accuracy.

[0099] In some embodiments, during the write operation phase of the memory performing in-memory operations, the target set of memory cells is the set of memory cells corresponding to the erase state E. First, a first programming operation is performed on the set of memory cells corresponding to the erase state E to adjust the threshold voltage of the memory cells in the set of memory cells corresponding to the erase state E.

[0100] It is understandable that, within the memory cell set corresponding to erase state E, the threshold voltage of the memory cell affects the magnitude of a current output by the memory string during the in-memory operation phase. Therefore, in this embodiment, performing a first programming operation on the memory cell set corresponding to erase state E can change the threshold voltage of the memory cell in erase state E, thereby changing the magnitude of a current output by the memory string during the operation phase. In other words, a suitable threshold voltage can be obtained by performing a first programming operation on the memory cell corresponding to erase state E according to the desired magnitude of each current.

[0101] After the first programming operation, the threshold voltages of each memory cell in the erase state E form the intermediate threshold voltage distribution of the erase state. Then, a second programming operation is performed on the memory cell set corresponding to erase state E. In the first second programming loop of the second programming operation, the memory cell set corresponding to erase state E is first verified to select memory cells that fail verification. Then, the failed-verification memory cells are programmed to shift their threshold voltages in the direction of increasing threshold voltage (i.e., to the right in the figure). This narrows the threshold voltage distribution of the memory cell set, resulting in a narrower threshold voltage distribution in erase state E after the second programming operation compared to after the first programming operation. This narrows the magnitude of each current during the computation phase, thereby improving the accuracy of in-memory computation.

[0102] It should be noted that, typically, the set of memory cells corresponding to erase state E does not require programming when the memory performs data storage. However, in this embodiment, the threshold voltage distribution corresponding to erase state E affects the accuracy of the calculation results when the memory performs the aforementioned in-memory operations. Therefore, it is proposed to program erase state E to narrow its threshold voltage distribution. Finally, through multiple programming operations, the threshold voltages of the memory cells in the set of memory cells corresponding to erase state E are programmed into the target threshold voltage distribution corresponding to erase state E. The target threshold voltage distribution corresponding to erase state E is the desired narrowed final threshold voltage distribution of the set of memory cells corresponding to erase state E.

[0103] In some embodiments, the first programming operation may only program the set of memory cells corresponding to the erase state E. In other embodiments, the first programming operation may be performed on both the set of memory cells corresponding to the erase state E and the set of memory cells corresponding to the programming state P.

[0104] Figure 9 A schematic diagram of the threshold voltage distribution during the write operation phase of a select-word-line coupled memory cell provided in this embodiment of the present disclosure. Figure 1 In some embodiments, such as Figure 9 As shown, a first programming operation can be performed on the set of memory cells corresponding to the erase state E, causing the threshold voltage of the memory cells in the set of memory cells to form Figure 9 The intermediate threshold voltage distribution M corresponding to the programmed state E 13 Furthermore, a first programming operation is performed on the set of memory cells corresponding to the programming state P, causing the threshold voltage distribution of the memory cells in the set to form... Figure 9 The intermediate threshold voltage distribution M corresponding to the programmed state P 12 .

[0105] Next, a second programming operation is performed on the set of memory cells corresponding to erase state E. Specifically, in the first second programming loop, verification is first performed on the set of memory cells corresponding to erase state E, and then programming is performed on the memory cells that fail verification to tighten the threshold voltage distribution. Here, the memory cells that fail verification are those memory cells in the set of memory cells corresponding to the erase state whose threshold voltage is less than a first preset threshold voltage. The first preset threshold voltage is related to the target threshold voltage distribution corresponding to the erase state.

[0106] For example, the first preset threshold voltage can be less than or equal to the lower limit of the target threshold voltage distribution corresponding to the erase state. The second programming operation may, for different purposes, set the first preset threshold voltage to the intermediate threshold voltage distribution M of the erase state E. 13 Any position between the lower limit of the target threshold voltage distribution of the erase state E and the lower limit of the target threshold voltage distribution of the erase state E.

[0107] Combination Figure 4 and Figure 9 It is understood that, in different embodiments, the target storage unit set can be different storage unit sets, for example in Figure 4 In the illustrated embodiment, the target memory cell set is the memory cell set corresponding to the programming state, while in this embodiment, the target memory cell set is the memory cell set corresponding to the erase state. When the memory cell sets are different, the corresponding first preset threshold voltage is different. It can be understood that the first preset threshold voltage is related to the target threshold voltage distribution of the state corresponding to the target memory cell set. Figure 4 In the illustrated embodiment, the first preset threshold voltage is related to the target threshold voltage distribution in the programming state, while in this embodiment, the first preset threshold voltage is related to the target threshold voltage distribution in the erase state. Therefore... Figure 4 The first preset threshold voltage in the illustrated embodiment is different from the first preset threshold voltage in this embodiment.

[0108] like Figure 9 As shown, after the second programming operation, the intermediate threshold voltage distribution M corresponding to the erase state E is... 23 Compared to the intermediate threshold voltage distribution M after the first programming operation 13 Narrower widths allow for tighter current distribution across each current segment during in-memory operations, improving the accuracy of in-memory calculations.

[0109] In some embodiments, such as Figure 9 As shown, during the write operation phase of in-memory computation, a second programming operation can be omitted from the memory cell set corresponding to the programmed state P. The threshold voltage of the memory cells in the memory cell set corresponding to the programmed state P still forms an intermediate threshold voltage distribution M. 12 .

[0110] Figure 10 This is a schematic diagram (2) illustrating the threshold voltage distribution during the write operation phase of a word-line coupled memory cell in memory, as provided in an embodiment of this disclosure. Figure 10 As shown, in some embodiments, the peripheral circuit can be configured to: perform a second programming operation on each set of memory cells, wherein the second programming operation on each set of memory cells includes at least one second programming loop; wherein the second programming operation performed on any set of memory cells includes: in the verification phase of the second programming loop, performing corresponding verification on at least a portion of the memory cells in the set of memory cells, and in the programming phase of the second programming loop, performing corresponding programming on the memory cells that failed verification.

[0111] For example, in the verification phase of the first second programming loop, the set of memory cells (i.e., all memory cells in the set) is verified. In the verification phases of each of the other second programming loops, at least a portion of the memory cells in the set are verified. In the programming phase of each second programming loop, the memory cells that failed verification in the verification phase within the same second programming loop are programmed.

[0112] Understandably, when performing corresponding verifications on different sets of memory cells, the voltage of the verification pulse used is different, and the voltage of the verification pulse is related to the corresponding first preset threshold voltage. When performing corresponding programming loops on different sets of memory cells, the number of programming loops can be the same or different. For example, the voltage magnitude of the programming pulse used in the programming loops corresponding to different sets of memory cells is different.

[0113] Compared to Figure 9 In the embodiment shown, in addition to performing a second programming operation on the memory cell set corresponding to the erase state E, a second programming operation can also be performed on the memory cell set corresponding to the programming state P to tighten the intermediate threshold voltage distribution of the memory cell set corresponding to the programming state P, resulting in a narrowed intermediate threshold voltage distribution M. 22 This increases the reading window during the computation phase, which helps improve the accuracy of the reading results.

[0114] This disclosure also provides an in-memory operation method, wherein peripheral circuitry is configured to execute the in-memory operation method. Specifically, the peripheral circuitry is configured to: perform a first programming operation on at least one or more memory cell sets corresponding to programming states of a plurality of memory cell sets coupled to a select word line; the memory cell set includes a plurality of memory cells whose threshold voltages will be programmed to a target threshold voltage distribution corresponding to the same programming state or erase state; and perform a second programming operation on the memory cell set corresponding to the erase state, the second programming operation including: at least one second programming loop, the second programming loop including a verification phase and a programming phase following the verification phase, wherein at least a portion of the memory cells in the memory cell set corresponding to the erase state are verified in the verification phase of the second programming loop, and the memory cells that fail verification are programmed in the programming phase of the second programming loop.

[0115] For example, in the verification phase of the first second programming loop, the set of memory cells corresponding to the erased state (i.e., all memory cells in the set of memory cells corresponding to the erased state) is verified. In the verification phase of each of the other second programming loops, at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified. In the programming phase of each second programming loop, the memory cells that failed verification in the verification phase within the same second programming loop are programmed.

[0116] Figure 11 A schematic diagram of the threshold voltage distribution during the write operation phase of a select-word-line coupled memory cell provided in this embodiment of the present disclosure. Figure 3 .like Figure 11 As shown, firstly, a first programming operation is performed on the memory cell set corresponding to the programming state P, so that the memory cells in the memory cell set form Figure 11 The intermediate threshold voltage distribution M corresponding to the programmed state P 12 The memory cells in the erase state E are not programmed, and their threshold voltages form the intermediate threshold voltage distribution M corresponding to the erase state E. 11 .

[0117] It should be noted that if there are multiple programming states, the first programming operation can be performed on multiple sets of memory units corresponding to multiple programming states simultaneously.

[0118] For example, a larger programming voltage can be used to program the set of memory cells corresponding to the programming state P, thereby increasing the intermediate threshold voltage distribution M corresponding to the programming state P. 12 The initial threshold voltage distribution M corresponding to the erase state E 11 The read window between them ensures that even if the memory units corresponding to the programmed state are concentrated in the memory units, the initial threshold distribution M is affected by the IVS effect. 12 Even when shifted to the left, the reading window still meets the requirements.

[0119] Next, a second programming operation is performed on the set of memory cells corresponding to the erased state E. For example... Figure 11 As shown, after performing the second programming operation on the memory cell set corresponding to the erase state E, the threshold voltage distribution M corresponding to the erase state is... 21 Compared to the intermediate threshold voltage distribution M after the first programming operation 11 Narrower.

[0120] In this embodiment, during the write operation phase of in-memory computation, a first programming operation is performed on the set of memory cells in the programming state to form intermediate threshold voltage distributions for both the set of memory cells in the programming state and the set of memory cells in the erase state. Then, a second programming operation is performed on the set of memory cells in the erase state. In the first second programming loop of the second programming operation, verification is performed first, and then the memory cells that fail verification are programmed to appropriately increase the threshold voltage of the failed verification memory cells. This helps to narrow the threshold voltage distribution in the erase state, thereby tightening the current distribution of each current during the in-memory computation phase and improving the accuracy of in-memory computation.

[0121] In some embodiments, a second programming operation may be performed on the memory cell corresponding to the programming state P to tighten the threshold voltage distribution of the programming state.

[0122] In some embodiments, the peripheral circuitry is configured to prohibit programming of verified memory cells during the programming phase of each second programming cycle.

[0123] Here, a verified memory cell refers to a memory cell whose threshold voltage is greater than or equal to a first preset threshold voltage. In this embodiment, during the programming phase of each second programming cycle, programming is prohibited for verified large memory cells. This prevents the threshold voltage of these memory cells from becoming larger, causing the upper limit of the threshold voltage distribution to shift towards higher threshold voltages and resulting in a wider threshold voltage distribution. It also reduces the occurrence of overprogramming of memory cells and improves programming accuracy.

[0124] The following detailed description of the specific processes of the first and second programming operations, in conjunction with several specific embodiments, will now be presented.

[0125] Figure 12 A schematic diagram of the first programming operation provided for embodiments of this disclosure. Figure 1 In some embodiments, such as Figure 12 As shown, in the first programming operation, multiple first programming cycles can be executed using Incremental Step Pulse Programming (ISPP). In each first programming cycle, a programming pulse and a verification pulse are applied sequentially to the select word line, with the verification pulse following the programming pulse.

[0126] The specific operations for executing multiple first programming loops using ISPP can be referenced to conventional ISPP operations in the art, and this disclosure does not impose any limitations. This disclosure is based on... Figure 4 In the illustrated embodiment, the use of ISPP to perform multiple first programming cycles on the memory unit set corresponding to programming state P is taken as an example for illustrative purposes. Figure 3 As shown, the first programming cycle can be divided into a programming phase and a verification phase that follows the programming phase.

[0127] During the programming phase, a programming pulse is applied to the select word line, and the voltage of the programming pulse is the programming voltage. A programming pass voltage is applied to the non-select word line, a programming enable voltage is applied to the bit lines coupled to the set of memory cells that can be programmed, and a programming disable voltage is applied to the bit lines coupled to the set of memory cells that cannot be programmed. Specifically, for the first programming cycle, the programmable memory cells are all memory cells in the set of memory cells corresponding to the programming state P. In other programming cycles, the programmable memory cells are those memory cells that were not verified in the previous programming cycle. The programmable memory cells include all memory cells in the set of memory cells corresponding to the erase state E and the memory cells that were verified in the previous programming cycle.

[0128] For example, during the verification phase, a verification pulse is applied to the select word line. The page buffers coupled to all memory cells in the memory cell set corresponding to the programming state P sense the voltage change on the bit lines, thereby verifying whether all memory cells in the memory cell set corresponding to the programming state P have been successfully programmed in this programming loop. For example, after a preset number of first programming loops, the first programming operation ends. Alternatively, the first programming operation ends after all memory cells in the memory cell set corresponding to the programming state P have passed verification.

[0129] like Figure 12 As shown, the voltage of the programming pulses used in multiple first programming cycles gradually increases, while the voltage of the verification pulses used can be the same for each other.

[0130] In some embodiments, the specific steps of performing the first programming operation on the memory cell sets corresponding to the erase state E and the programming state P using ISPP can be referred to the process of using ISPP programming in multi-level memory cells in the art, and will not be repeated here.

[0131] In some embodiments, when performing a first programming operation on the set of memory cells corresponding to the erase state E, the first programming cycle includes a verification phase and a programming phase within the verification phase. Specifically, the target set of memory cells is verified during the verification phase of the first first programming cycle, and memory cells that fail verification are programmed during the programming phase of the first programming cycle. In each of the other first programming cycles besides the first programming cycle, at least a portion of the memory cells in the target set are verified, and memory cells that fail verification are programmed during the programming phase.

[0132] For example, such as Figure 13 As shown, a verification pulse is applied to the select word line during the verification phase of each first programming cycle, and a programming pulse is applied to the select word line during the programming phase of each first programming cycle.

[0133] In this embodiment, the steps of the first programming operation and the second programming operation performed on the memory cell set corresponding to the erase state E are the same. However, in the first programming cycle, memory cells with a threshold voltage lower than a second preset threshold voltage can be selected. The second preset threshold voltage is related to the target threshold voltage distribution corresponding to the erase state, and the second preset threshold voltage is different from the first preset threshold voltage. For example, memory cells with a threshold voltage lower than the second preset threshold voltage can be selected by setting the voltage or sensing time of the verification pulse used in the first programming cycle.

[0134] In the first programming loop of the first programming operation, verifying the erase state E before programming it tightens the threshold voltage distribution corresponding to the erase state, while ensuring that the threshold voltage distribution of the erase state is at a low position, which is beneficial for increasing the read window between the threshold voltage distribution of the programming state and the programmable state. It also helps to reduce the read voltage applied to the select word line during the operation phase, thereby reducing operation power consumption.

[0135] In some embodiments, in each subsequent first programming cycle after the first first programming cycle, all memory cells in the memory cell set corresponding to the erased state E can be verified during the verification phase, and memory cells that failed verification can be programmed during the programming phase. The voltages of the verification pulses used in multiple first programming cycles can be equal or unequal. The voltages of the programming pulses used in multiple first programming cycles can be gradually increased.

[0136] In other embodiments, in each subsequent first programming cycle after the first first programming cycle, the memory cells that were programmed in the previous first programming cycle can be verified during the verification phase, and the memory cells that failed verification can be programmed during the programming phase. In this way, in the first programming operation, only the memory cells that failed verification in the first first programming cycle are programmed, verified, and reprogrammed, while the memory cells that passed verification in the first first programming cycle are not programmed. By programming the threshold voltage of the memory cells that failed verification to an appropriate size, the threshold voltage distribution can be narrowed.

[0137] In some embodiments, at least during the verification phase of the first programming cycle, the memory cells in the memory cell set corresponding to the erase state E are verified to divide the memory cells in the memory cell set into multiple subsets according to the threshold voltage of the memory cells; during the programming phase of the first programming cycle, different subsets are programmed to different degrees.

[0138] For example, different degrees of programming can be applied to different subsets, including applying the same bit line voltage to the bit lines coupled to memory cells in the same subset, while applying different bit line voltages to the bit lines coupled to memory cells in different subsets.

[0139] like Figure 14 As shown, when the threshold voltage of a certain memory cell in the memory cell set is verified to be greater than or equal to the first threshold voltage Vry_f1, that is, when the threshold voltage of the memory cell is within the range d in the current threshold voltage distribution, it indicates that the current threshold voltage of the memory cell is large. Therefore, programming of the memory cell is prohibited, that is, a programming prohibition voltage (e.g., VDD voltage) is applied to the bit line coupled to the memory cell.

[0140] When the threshold voltage of a memory cell is verified to be greater than or equal to the second threshold voltage Vry_f2 and less than the first threshold voltage Vry_f1, meaning the threshold voltage of the memory cell is within the range c of the current threshold voltage distribution, considering that the threshold voltage distribution of this set of memory cells is expected to converge to a larger and narrower range of the desired threshold voltage distribution, the memory cells whose threshold voltage distribution is within the range c still need to be programmed. However, the programming step size needs to be shortened this time to prevent the threshold voltage of the memory cell after the next programming from exceeding the range of the desired threshold voltage distribution. To shorten the step size of the next programming, a first bit line forced voltage Vmid1 is applied to the bit line coupled to the memory cell. The voltage value of Vmid1 is less than the VDD voltage and greater than the allowed programming voltage. Here, the desired threshold voltage distribution is the threshold voltage distribution expected to be obtained after the programming phase in this programming loop.

[0141] When the threshold voltage of a memory cell is verified to be greater than or equal to the third threshold voltage Vry_f3 and less than the second threshold voltage Vry_f2, it indicates that the threshold voltage of the memory cell has been programmed into the range b of the current threshold voltage distribution. Considering that the threshold voltage distribution of this memory cell is expected to converge within the desired threshold voltage distribution range, memory cells with threshold voltage distributions within the b range still need to be programmed. However, the programming step size needs to be shortened this time to prevent the programming step size from being too long (e.g., overprogramming) and causing the threshold voltage of the memory cell to exceed the desired threshold voltage distribution range after the next programming. It will be understood that the programming step size this time can be slightly larger than the programming step size for memory cells with current threshold voltages within the c range. To shorten the next programming step size, a second bit line forced voltage Vmid2 is applied to the bit line coupled to the memory cell. The voltage value of Vmid2 is less than the voltage of Vmid1 and greater than the allowed programming voltage.

[0142] When the threshold voltage of a memory cell is verified to be less than the third threshold voltage Vry_f3, it indicates that the threshold voltage of that memory cell has been programmed into the range 'a' of the current threshold voltage distribution, which is far from the desired threshold voltage distribution. This means there is still a considerable distance from the desired threshold voltage distribution range where convergence is expected. In this case, using Vmid2 or Vmid1 to program the memory cell, although the programming step size can be controlled, will increase the programming time and affect memory performance. Therefore, for cases where the threshold voltage is within the range 'a' of the current threshold voltage distribution or has not yet reached the range 'a', a ground voltage, i.e., a programming-enabled voltage, can be applied to the bit line of the memory cell.

[0143] In summary, during the verification phase, the memory cells in the set of memory cells corresponding to the erased state are divided into multiple subsets. For example, these subsets include a first subset, a second subset, a third subset, and a fourth subset, corresponding to the memory cells within the ranges a, b, c, and d mentioned above, respectively. During the programming phase, a programming enable voltage, a second bit line forced voltage, a first bit line forced voltage, and a programming disable voltage are sequentially applied to the bit lines coupled to the memory cells in the first, second, third, and fourth subsets to program different subsets to varying degrees, thereby better narrowing the threshold voltage distribution.

[0144] For example, during the verification phase, three successively increasing verification voltages can be used to verify the memory cells in the memory cell set corresponding to the erase state E. Alternatively, a single verification voltage can be used, and verification can be performed using three different sensing times to divide the memory cell set into the aforementioned subsets.

[0145] Next, the execution process of the second programming loop in the second programming operation will be described in detail.

[0146] In some embodiments, the second programming operation includes a plurality of second programming cycles, each second programming cycle including a verification phase and a programming phase following the verification phase. For example, in the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line, the programming pulse following the verification pulse.

[0147] This application is based on Figure 4 In the illustrated embodiment, multiple second programming cycles are performed on the memory cell set corresponding to programming state P as an example. During the verification phase of the first second programming cycle, a verification pulse is applied to the select word line. The page buffers coupled to all memory cells in the memory cell set corresponding to programming state P sense voltage changes on the bit lines to determine whether the memory cell verification is successful. During the programming phase of the first second programming cycle, a programming pulse is applied to the select word line, a programming pass voltage is applied to the non-select word line, a programming enable voltage is applied to the bit lines coupled to the memory cell set that failed verification, and a programming disable voltage is applied to the bit lines coupled to the memory cell set that passed verification.

[0148] In some embodiments, in each of the other second programming cycles after the first second programming cycle, all memory cells in the memory cell set corresponding to the programming state P can be verified during the verification phase, and memory cells that fail verification can be programmed during the programming phase.

[0149] In other embodiments, in each subsequent second programming cycle after the first second programming cycle, the memory cells that were programmed in the previous second programming cycle can be verified during the verification phase, and the memory cells that failed verification can be programmed during the programming phase. That is, in the second programming operation, the verification phase of the first second programming cycle is to select a portion of memory cells, while the subsequent second programming cycles are to program the threshold voltage of these memory cells to the appropriate position, and the memory cells that passed verification in the first second programming cycle are not programmed, thereby narrowing the threshold voltage distribution.

[0150] The process of performing the second programming operation on the memory cell set corresponding to the erased state E is the same as above, so it will not be described again.

[0151] Figure 15 Illustration of the second programming operation provided for embodiments of this disclosure Figure 1 In some embodiments, such as Figure 15 As shown, in the second programming operation, the voltage of the programming pulses used in multiple second programming cycles gradually increases, while the voltage of the verification pulses used can be the same for each other. In this disclosure, the voltage of the programming pulse is simply referred to as the programming voltage Vpgm, and the voltage of the verification pulse is simply referred to as the verification voltage Vpv.

[0152] For example, at least one of the following parameters can be adjusted: the programming voltage (Vpgminit) in the first second programming cycle, the increment of the programming voltage between two adjacent second programming cycles (ispp step), the number of second programming cycles, and the verification voltage. In one specific embodiment, the control logic inside the memory can adjust these parameters. For example, the control logic can adjust these parameters based on the verification result in the previous second programming cycle, the environmental parameters during the second programming operation, the number of read / write operations of the memory cell during the current second programming operation, etc. Of course, in another embodiment, these parameters can also be fixed and not adjustable after the memory leaves the factory.

[0153] For example, in different implementations, at least one of the following may be different: the programming voltage (Vpgm init) in the first second programming cycle, the increment of the programming voltage (ispp step) in two adjacent second programming cycles, the number of second programming cycles, and the verification voltage.

[0154] Figure 16 A second schematic diagram illustrating a second programming operation provided for an embodiment of this disclosure. In some embodiments, such as Figure 16As shown, the second programming operation includes multiple second programming cycles; in the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltage of the programming pulses in the multiple second programming cycles is equal.

[0155] With the above Figure 15 Compared to the illustrated embodiment, the difference lies in that the programming voltage used in the multiple second programming cycles is fixed, but the verification voltage is not entirely the same. For example, the programming voltage can be set to a smaller value, and the threshold voltage of the selected memory cell can be programmed to the desired threshold voltage by increasing the number of programming cycles. This method can reduce the probability of overprogramming.

[0156] For example, in two adjacent second programming cycles, the verification voltage in the later second programming cycle can be greater than or less than the verification voltage in the previous second programming cycle. The control logic inside the memory can adjust the verification voltage in the next second programming cycle based on the verification result of the previous second programming cycle.

[0157] For example, at least one of the programming voltage in the second programming cycle, the number of second programming cycles, and the verification voltage in each second programming cycle can be adjusted. For instance, the control logic inside the memory can adjust these parameters based on the verification result of the previous second programming cycle, environmental parameters during the second programming operation, and the number of read / write operations on the memory cell during the current second programming operation. Of course, in another embodiment, these parameters can be fixed and not adjustable after the memory leaves the factory.

[0158] Figure 17 Illustration of the second programming operation provided for embodiments of this disclosure Figure 3 In some embodiments, such as Figure 17 As shown, the second programming operation includes multiple second programming cycles; in the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltages of the programming pulses in two adjacent second programming cycles are different, and / or the voltages of the verification pulses in two adjacent second programming cycles are different.

[0159] In other words, in any two adjacent second programming cycles, the programming voltage in the latter second programming cycle may be different from the programming voltage in the former second programming cycle, or the verification voltage in the latter second programming cycle may be different from the verification voltage in the former second programming cycle, or both the programming voltage and the verification voltage in the latter second programming cycle may be different from both the programming voltage and the verification voltage in the former second programming cycle.

[0160] In this embodiment, during the second programming cycle, the programming voltage and / or verification voltage can be adjusted based on the results of the previous second programming cycle. Through this high-precision, dynamic adjustment, the threshold voltage distribution can be tightened to the greatest extent.

[0161] In summary, this disclosure does not limit the specific process of multiple second programming cycles, as long as the threshold voltage of the selected memory cells can be appropriately increased to narrow the threshold voltage distribution. In some embodiments, at least in the first second programming cycle, the threshold voltage distribution can be narrowed by applying the above-described method of applying an enable programming voltage, a first bit line forced voltage, a second bit line forced voltage, and an disable programming voltage to the bit lines coupled to different subsets.

[0162] In some embodiments, the second programming operation further includes a verification step following a plurality of second programming cycles, for verifying whether the threshold voltage distribution of the memory cells in the memory cell set after the second programming operation reaches the desired threshold voltage distribution.

[0163] For example, the verification step can verify all memory cells in the target memory cell set. Also for example, if each of the second programming loops (except the first) verifies memory cells programmed in the previous second programming loop, then the final verification step can also verify memory cells programmed in the last second programming loop.

[0164] In some embodiments, the peripheral circuitry is further configured to perform a third programming operation on the target memory cell set, the third programming operation including at least one third programming cycle, the third programming cycle including a verification phase and a programming phase following the verification phase, wherein at least a portion of the memory cells in the target memory cell set are verified in the verification phase of the third programming cycle, and the memory cells that fail verification are programmed in the programming phase of the third programming cycle.

[0165] For example, in the verification phase of the first third programming loop, the target memory set (i.e., all memory units in the target memory set) is verified. In the verification phases of each of the other third programming loops, at least a portion of the memory units in the target memory set is verified. In the programming phase of each third programming loop, the memory units that failed verification in the verification phase within the same third programming loop are programmed.

[0166] The steps for performing the third programming operation and the second programming operation on the target memory cell set are the same. However, in the first third programming cycle, memory cells with a threshold voltage lower than a third preset threshold voltage can be selected. The third preset threshold voltage is related to the target threshold voltage distribution corresponding to the erase state, and the third preset threshold voltage is different from the first preset threshold voltage and the second preset threshold voltage. For example, memory cells with a threshold voltage lower than the third preset threshold voltage can be selected by setting the voltage of the verification pulse or the sensing time used in the first third programming cycle.

[0167] The third programming operation is the same as the second programming operation, and will not be described again in this disclosure. However, it should be noted that the programming voltage and verification voltage used in the third programming operation are not exactly the same as those in the second programming operation. The third programming operation enables the threshold voltage distribution of the target memory cell set to be closer to the target threshold voltage distribution.

[0168] In some embodiments, the peripheral circuitry is configured to: during the first programming operation phase of the target memory cell set, prohibit the execution of the first programming operation on other memory cell sets in the plurality of memory cell sets; and during the second programming operation phase of the target memory cell set, prohibit the execution of the second programming operation on other memory cell sets.

[0169] In this embodiment, the first programming operation is performed on only one set of memory cells in the multiple memory cell sets coupled to the select word line at a time. If multiple sets of memory cells need to be programmed, the first programming operation is performed on one set of memory cells before the first programming operation is performed on another set of memory cells. Similarly, the second programming operation is performed on only one set of memory cells in the multiple memory cell sets at a time.

[0170] In some embodiments, the peripheral circuitry is configured to perform a corresponding first programming operation on each of the memory cell sets other than the target memory cell set in the plurality of memory cell sets coupled to the select word line;

[0171] Perform the corresponding second programming operation on each of the other memory cell sets.

[0172] For example, the first programming operation is performed on the set of memory cells requiring the first programming operation within the multiple memory cell sets coupled to the select word line, before the second programming operation is performed on the set of memory cells requiring the second programming operation. For instance, during the write operation phase of in-memory operations, the first programming operation can be performed consecutively on the set of memory cells corresponding to erase state E and the set of memory cells corresponding to programming state P. Then, the second programming operation is performed consecutively on the set of memory cells corresponding to erase state E and the set of memory cells corresponding to programming state P. By completing the first programming operation on the set of memory cells requiring the first programming operation within the multiple memory cell sets coupled to the select word line, and completing the second programming operation on the set of memory cells requiring the second programming operation, the programming of all memory cells coupled to the select word line is completed.

[0173] In some embodiments, after all first programming operations are performed consecutively on the plurality of memory cell sets coupled to the select word line WLn+1, all second programming operations are performed consecutively on the plurality of memory cell sets coupled to the previous word line WLn, and all first programming operations are performed consecutively on the plurality of memory cell sets coupled to the next word line WLn+2. Here, n is a positive integer greater than or equal to 0.

[0174] For example, after all the first programming operations are performed on the multiple sets of memory cells coupled to the first word line WL0, all the first programming operations are performed on the multiple sets of memory cells coupled to the second word line WL1, all the second programming operations are performed on the multiple sets of memory cells coupled to the first word line WL0, all the first programming operations are performed on the multiple sets of memory cells coupled to the third word line WL2, all the second programming operations are performed on the multiple sets of memory cells coupled to the second word line WL1, and so on, until all the data is written.

[0175] Here, performing all first programming operations consecutively on multiple sets of memory cells coupled to the same word line means performing the corresponding first programming operations consecutively on the sets of memory cells for which the first programming operations need to be performed. Performing all second programming operations consecutively on multiple sets of memory cells coupled to the same word line means performing the corresponding second programming operations consecutively on the sets of memory cells for which the second programming operations need to be performed.

[0176] In some embodiments, the semiconductor device in the above embodiments includes a three-dimensional NAND type memory.

[0177] In some embodiments, the semiconductor device described above includes a first semiconductor structure and a second semiconductor structure. The memory cell array is located in the first semiconductor structure, and the peripheral circuitry is located in the second semiconductor structure. The first and second semiconductor structures are stacked along the thickness direction of the semiconductor device and coupled to each other. For example, the first and second semiconductor structures are bonded together to achieve electrical connection.

[0178] In this embodiment of the disclosure, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on one wafer and the second semiconductor structure can be formed on another wafer. The two wafers are then bonded together. The first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. Such a structural architecture can save more area of ​​the semiconductor device and shorten the process cycle.

[0179] Based on a concept similar to the semiconductor devices described above, this disclosure also provides a method for operating a semiconductor device, which can be executed using a semiconductor device from any of the above embodiments. Figure 18 This is a schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 18 As shown, the operation method includes:

[0180] S110: Perform a first programming operation on a target memory cell set of a plurality of memory cell sets coupled to the select word line. The first programming operation includes a plurality of first programming loops. The target memory cell set includes a plurality of memory cells in a target threshold voltage distribution corresponding to a state in a plurality of states to which the threshold voltage will be programmed.

[0181] S210: Perform a second programming operation on the target storage cell set. The second programming operation includes at least one second programming loop. The second programming loop includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the storage cells in the target storage cell set are verified. In the programming phase of the second programming loop, the storage cells that fail verification are programmed.

[0182] In some embodiments, step S210 further includes: during the programming phase of the second programming cycle, prohibiting programming of the verified storage unit.

[0183] In some embodiments, step S110 can be implemented by performing multiple first programming cycles on the target memory cell set using incremental step pulse programming (ISPP).

[0184] In some embodiments, step S210 may be implemented as follows: performing multiple second programming cycles on the target memory cell set, applying a verification pulse to the select word line during the verification phase of each second programming cycle, and applying a programming pulse to the select word line during the programming phase of each second programming cycle; wherein the voltage of the programming pulses in the multiple second programming cycles increases incrementally.

[0185] In some embodiments, step S210 may be implemented as follows: performing multiple second programming cycles on the target memory cell set, applying a verification pulse to the select word line during the verification phase of each second programming cycle, and applying a programming pulse to the select word line during the programming phase of each second programming cycle; wherein the voltages of the programming pulses in the multiple second programming cycles are equal.

[0186] In some embodiments, step S210 may be implemented as follows: performing multiple second programming cycles on the target memory cell set, applying a verification pulse to the select word line during the verification phase of each second programming cycle, and applying a programming pulse to the select word line during the programming phase of each second programming cycle; wherein the voltages of the programming pulses in two adjacent second programming cycles are different, and / or the voltages of the verification pulses in two adjacent second programming cycles are different.

[0187] In some embodiments, the target storage cell set is the storage cell set corresponding to the erase state, and step S110 can be implemented as follows: multiple first programming cycles are executed on the target storage cell set, each first programming cycle including a verification phase and a programming phase located in the verification phase, wherein at least some storage cells in the target storage cell set are verified in the verification phase of the first programming cycle, and the storage cells that fail verification are programmed in the programming phase of the programming cycle.

[0188] In some embodiments, the target memory cell set is the memory cell set corresponding to the erase state. The first programming cycle includes a verification phase and a programming phase following the verification phase. Step S110 can be implemented as follows: the target memory cell set is verified in the verification phase of the first programming cycle to divide the memory cells in the target memory cell set into multiple subsets according to the threshold voltage of the memory cells; in the programming phase of the first programming cycle, different subsets are programmed to different degrees.

[0189] In some embodiments, the method further includes performing a third programming operation on a target set of storage cells, the third programming operation including at least one third programming loop, the third programming loop including a verification phase and a programming phase following the verification phase, wherein at least a portion of the storage cells in the target set of storage cells are verified in the verification phase of the third programming loop, and the storage cells that fail verification are programmed in the programming phase of the third programming loop.

[0190] In some embodiments, the operation method further includes: during the first programming operation phase of the target storage cell set, prohibiting the execution of the first programming operation on other storage cell sets in the plurality of storage cell sets; and during the second programming operation phase of the target storage cell set, prohibiting the execution of the second programming operation on other storage cell sets.

[0191] In some embodiments, the method further includes performing a corresponding first programming operation and a second programming operation on each of the other memory cell sets in the plurality of memory cell sets coupled to the select word line.

[0192] In the semiconductor device operation method provided in this disclosure, during the data storage write operation phase, the target memory cell set can be the memory cell set corresponding to the programmed state. Performing a first programming operation on the target memory cell set can create an intermediate threshold voltage distribution for its threshold voltage. In the first second programming loop of the second programming operation, verification is performed to select a portion of memory cells near the low tail of the intermediate threshold voltage distribution. These selected memory cells are then programmed, while other memory cells in the intermediate threshold voltage distribution are not programmed. By appropriately increasing the threshold voltage of the low-tail memory cells, the threshold voltage distribution can be effectively narrowed. In other second programming loops, the verification-then-programming approach is also adopted, ultimately narrowing the threshold voltage distribution of the target memory cell set, thereby improving data read / write accuracy and effectively reducing the impact of the IVS effect on data storage accuracy.

[0193] During the write operation phase of in-memory operations, the target memory cell set can be the memory cell set corresponding to the erase state. After performing the first programming operation and the second programming operation on the target memory cell set, the threshold voltage distribution corresponding to the erase state can be narrowed, thereby narrowing the magnitude of each current during the operation phase and improving the accuracy of in-memory operations.

[0194] This disclosure also discloses a method for operating a semiconductor device. Figure 19 A flowchart illustrating another method of operating a semiconductor device provided in this disclosure is shown below. Figure 19 As shown, the operation method includes:

[0195] S120: Perform a first programming operation on at least one set of memory cells corresponding to a programming state of a set of memory cells coupled to the select word line; the set of memory cells includes multiple memory cells in a target threshold voltage distribution corresponding to the same programming state or erase state, to which threshold voltages will be programmed.

[0196] S220: Perform a second programming operation on the set of memory cells corresponding to the erased state, the second programming operation including: at least one second programming loop, the second programming loop including a verification phase and a programming phase following the verification phase, wherein at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified in the verification phase of the second programming loop, and the memory cells that fail verification are programmed in the programming phase of the second programming loop.

[0197] In this embodiment, after performing a second programming operation on the set of memory cells corresponding to the erase state during the write operation phase of in-memory operation, the threshold voltage distribution corresponding to the erase state can be narrowed, thereby narrowing the magnitude of each current during the operation phase and improving the accuracy of in-memory operation.

[0198] Based on a concept similar to the semiconductor devices described above, this disclosure also provides a system comprising: at least one semiconductor device as described in any of the above embodiments and a controller coupled to the semiconductor device, wherein the memory controller is configured to control the semiconductor device.

[0199] In some embodiments, the memory controller is configured to send a weight matrix and an input matrix to the semiconductor device and receive the computation results from the semiconductor device. Here, the computation results from the semiconductor device are the computation results after analog-to-digital conversion.

[0200] In some embodiments, the system described above may be as follows: Figure 20 The memory system 302 shown includes a memory controller 306 and a memory device 304 coupled to the memory controller 306. In the above embodiment, the controller can be the memory controller 306, and the semiconductor device can be the memory device 304. The memory controller 306 is coupled to the memory device 304 and the host 308 and is configured to control the operation of the memory device 304, such as read, erase, program, and compute operations. The memory controller 306 can manage the data stored in the memory device 304 and communicate with the host 308.

[0201] In other embodiments, the system described in the above embodiments can be as follows: Figure 21 The system 400 shown includes a host 308 and a memory device 304 coupled to the host 308. The controller in the above embodiment may be a CPU in the host device. The semiconductor device in the above embodiment may be the memory device 304.

[0202] In such Figure 22In one example, the system can be integrated into a memory card 402. The semiconductor device in the system can be the memory device 304 within the memory card 402, and the controller in the system can be the memory controller 306 within the memory card 402. The memory card 402 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 402 may also include a memory card connector 403 that couples the memory card 402 to a host computer. Figure 23 In another example shown, the system can be integrated into a solid-state disk (SSD) 406. The semiconductor device in the system can be the memory device 304 within the SSD 406, and the memory controller in the system can be the memory controller 306 within the SSD 406. The SSD 406 may also include a solid-state disk connector 408 that couples the SSD 406 to a host device. In some embodiments, the storage capacity and / or operating speed of the SSD 406 is greater than the storage capacity and / or operating speed of the memory card 402.

[0203] In other embodiments, the system can be integrated into the terminal device, and the memory controller can be the central processing unit (CPU) of the terminal device. Here, the terminal device can be, but is not limited to, any terminal device or portable terminal device such as mobile phone, smart TV, smart speaker, wearable device, tablet computer, desktop computer, all-in-one computer, handheld computer, laptop computer, server, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), laptop computer, mobile computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, etc.

[0204] It should be understood that the system includes, but is not limited to, a memory system. For example, the system may include a memory system and a memory computing system, such as a memory computing system and a processor, where the processor includes at least one of a CPU, GPU, or NPU. In one specific implementation, the system may be a system-on-a-chip (SoC).

[0205] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0206] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0207] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A memory cell array, word lines coupled to the memory cell array, and peripheral circuitry coupled to the word lines, wherein the peripheral circuitry is configured as follows: A first programming operation is performed on a target set of multiple memory cells coupled to a select word line, the first programming operation comprising multiple first programming loops; The target storage cell set includes multiple storage cells in the target threshold voltage distribution corresponding to one of multiple states to which the threshold voltage will be programmed. A second programming operation is performed on the target storage cell set. The second programming operation includes at least one second programming loop. The second programming loop includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the storage cells in the target storage cell set are verified. In the programming phase of the second programming loop, the storage cells that fail verification are programmed.

2. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is configured as follows: During the programming phase of the second programming loop, programming is prohibited on verified memory cells.

3. The semiconductor device according to claim 1 or 2, characterized in that, The plurality of states includes an erase state and at least one programming state; Specifically, the threshold voltage of the storage cells in the target storage cell set will be programmed into the target threshold voltage distribution corresponding to the erase state.

4. The semiconductor device according to claim 1, characterized in that, In the first programming operation, the plurality of first programming loops are executed using Incremental Step Pulse Programming (ISPP).

5. The semiconductor device according to claim 1, characterized in that, The second programming operation includes multiple second programming loops; In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltage of the programming pulses in the plurality of second programming cycles increases.

6. The semiconductor device according to claim 1, characterized in that, The second programming operation includes multiple second programming loops; In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltage of the programming pulses in the plurality of second programming cycles is equal.

7. The semiconductor device according to claim 1, characterized in that, The second programming operation includes multiple second programming loops; In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltages of the programming pulses in two adjacent second programming cycles are different, and / or the voltages of the verification pulses in two adjacent second programming cycles are different.

8. The semiconductor device according to claim 1, characterized in that, The threshold voltage of the target storage unit centralized storage unit will be programmed into the target threshold voltage distribution corresponding to the erase state; The first programming cycle includes a verification phase and a programming phase following the verification phase. The peripheral circuit is configured to: verify at least a portion of the memory cells in the target memory cell set during the verification phase of the first programming cycle, and to perform programming on the memory cells that fail verification during the programming phase of the first programming cycle.

9. The semiconductor device according to claim 1, characterized in that, The threshold voltage of the target storage unit centralized storage unit will be programmed into the target threshold voltage distribution corresponding to the erase state; The first programming cycle includes a verification phase and a programming phase following the verification phase. The peripheral circuit is configured to: verify the target memory cell set during the verification phase of the first programming cycle to divide the memory cells in the target memory cell set into multiple subsets based on the threshold voltage of the memory cells; and program the different subsets to different degrees during the programming phase of the first programming cycle.

10. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is configured as follows: A third programming operation is performed on the target storage cell set. The third programming operation includes at least one third programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the third programming loop, at least a portion of the storage cells in the target storage cell set are verified, and in the programming phase of the third programming loop, the storage cells that fail verification are programmed.

11. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is configured as follows: During the first programming operation phase of the target storage cell set, the corresponding first programming operation is prohibited from being performed on other storage cell sets in the plurality of storage cell sets; During the second programming operation phase on the target storage unit set, the corresponding second programming operation is prohibited on the other storage unit sets.

12. The semiconductor device according to claim 11, characterized in that, The peripheral circuit is configured as follows: Perform the corresponding first programming operation on each of the multiple memory cell sets coupled to the select word line, excluding the target memory cell set; Perform the corresponding second programming operation on each of the other sets of storage units.

13. The semiconductor device according to claim 1, characterized in that, The second programming operation also includes a verification step following a plurality of second programming loops; The peripheral circuit is configured to verify at least a portion of the storage cells in the target storage cell set during the verification step.

14. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: bit lines coupled to the memory cell array; The peripheral circuit includes: control logic, analog-to-digital conversion circuit, digital-to-analog conversion circuit, and digital circuit. The analog-to-digital conversion circuit is coupled to the bit line. The digital circuit is coupled to the control logic through the digital-to-analog conversion circuit, and the digital circuit is also coupled to the analog-to-digital conversion circuit.

15. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a three-dimensional NAND flash memory.

16. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a first semiconductor structure and a second semiconductor structure; the memory cell array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are co-bonded.

17. A semiconductor device, characterized in that, include: A memory cell array, word lines coupled to the memory cell array, and peripheral circuitry coupled to the word lines, wherein the peripheral circuitry is configured as follows: A first programming operation is performed on at least one set of memory cells corresponding to a programming state of a plurality of memory cells coupled to a select word line; the set of memory cells includes a plurality of memory cells in a target threshold voltage distribution corresponding to the same programming state or erase state, to which a threshold voltage will be programmed. A second programming operation is performed on the set of memory cells corresponding to the erased state. The second programming operation includes at least one second programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified, and in the programming phase of the second programming loop, the memory cells that fail verification are programmed.

18. A system, characterized in that, include: One or more semiconductor devices as described in any one of claims 1 to 17; as well as, A memory controller is coupled to the semiconductor device and configured to control the semiconductor device.

19. A method of operating a semiconductor device, characterized in that, The operation method includes: A first programming operation is performed on a target set of multiple memory cells coupled to a select word line, the first programming operation including multiple first programming loops; the target set of memory cells includes multiple memory cells in a target threshold voltage distribution corresponding to a state of multiple states to be programmed with a threshold voltage. A second programming operation is performed on the target storage cell set. The second programming operation includes at least one second programming loop. The second programming loop includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least some storage cells in the target storage cell set are verified. In the programming phase of the second programming loop, the storage cells that fail verification are programmed.

20. The operating method according to claim 19, characterized in that, The second programming operation performed on the target storage unit set includes: During the programming phase of the second programming loop, programming is prohibited on verified memory cells.

21. The operating method according to claim 19, characterized in that, Perform a first programming operation on a target set of multiple memory cells coupled to a select word line, the first programming operation comprising multiple first programming loops, including: The target memory cell set is executed with the plurality of first programming loops using Incremental Step Pulse Programming (ISPP).

22. The operating method according to claim 19, characterized in that, The second programming operation performed on the target storage unit set includes: Multiple second programming cycles are executed on the target memory cell set. In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltage of the programming pulse in the multiple second programming cycles increases.

23. The operating method according to claim 19, characterized in that, The second programming operation performed on the target storage unit set includes: Multiple second programming cycles are executed on the target memory cell set. In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line; wherein the voltage of the programming pulses in the multiple second programming cycles is equal.

24. The operating method according to claim 19, characterized in that, The second programming operation performed on the target storage unit set includes: Multiple second programming cycles are executed on the target memory cell set. In the verification phase of each second programming cycle, a verification pulse is applied to the select word line, and in the programming phase of each second programming cycle, a programming pulse is applied to the select word line. The voltages of the programming pulses in two adjacent second programming cycles are different, and / or the voltages of the verification pulses in two adjacent second programming cycles are different.

25. The operating method according to claim 19, characterized in that, The threshold voltage of the target memory cell set will be programmed into the target threshold voltage distribution corresponding to the erase state; the first programming operation performed on the target memory cell set of multiple memory cell sets coupled to the select word line includes: Multiple first programming loops are executed on the target storage cell set, each first programming loop including a verification phase and a programming phase following the verification phase, wherein at least a portion of the storage cells in the target storage cell set are verified in the verification phase of the first programming loop, and the storage cells that fail verification are programmed in the programming phase of the first programming loop.

26. The operating method according to claim 19, characterized in that, The operation method further includes: A third programming operation is performed on the target storage cell set. The third programming operation includes at least one third programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the third programming loop, at least a portion of the storage cells in the target storage cell set are verified, and in the programming phase of the third programming loop, the storage cells that fail verification are programmed.

27. The operating method according to claim 19, characterized in that, The operation method further includes: During the first programming operation phase of the target storage cell set, the corresponding first programming operation is prohibited from being performed on other storage cell sets in the plurality of storage cell sets; During the second programming operation phase on the target storage unit set, the corresponding second programming operation is prohibited on the other storage unit sets.

28. The operating method according to claim 19, characterized in that, The operation method further includes: Perform the corresponding first programming operation on each of the multiple memory cell sets coupled to the select word line, excluding the target memory cell set; Perform the corresponding second programming operation on each of the other sets of storage units.

29. A method of operating a semiconductor device, characterized in that, The operation method includes: A first programming operation is performed on at least one set of memory cells corresponding to a programming state of a plurality of memory cells coupled to a select word line; the set of memory cells includes a plurality of memory cells in a target threshold voltage distribution corresponding to the same programming state or erase state, to which a threshold voltage will be programmed. A second programming operation is performed on the set of memory cells corresponding to the erased state. The second programming operation includes at least one second programming loop, which includes a verification phase and a programming phase following the verification phase. In the verification phase of the second programming loop, at least a portion of the memory cells in the set of memory cells corresponding to the erased state are verified, and in the programming phase of the second programming loop, the memory cells that fail verification are programmed.

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