SRAM in-memory computing architecture and its multi-operant xor method

Abstract

The application discloses an SRAM in-memory computing architecture, comprising an SRAM storage array and an in-memory computing control module, wherein the SRAM storage array comprises a voltage translation XOR computing module, the SRAM storage array is used for storing data to be processed, redundancy check information and temporarily storing intermediate results of multi-operand XOR operation and check sub-computing results; the in-memory computing control module is used for controlling sub-lines, bit lines and read-write timing, providing clock signals and read word line activation signals for the multi-operand XOR operation; the voltage translation XOR computing module is used for realizing the multi-operand XOR operation by adopting a two-stage voltage conversion strategy and a capacitor charge sharing mechanism inside the storage array, and obtaining an XOR computing result. By setting the voltage translation XOR computing module, the energy consumption and delay of the multi-operand XOR operation are reduced.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, specifically to an SRAM in-memory computing architecture and its multi-operand XOR method. Background Technology

[0002] With the continuous development of integrated circuit technology, the "memory wall" problem caused by the separation of computing and storage units in the traditional von Neumann architecture has become increasingly prominent. In this architecture, data is frequently moved between memory and processor, which not only causes significant energy consumption but also limits the overall system performance, especially in data-intensive and real-time applications.

[0003] To address these issues, in-memory computing architecture emerged. This architecture performs some computational operations directly within the memory array, enabling computation to be completed during data retrieval, thereby significantly reducing data movement overhead and improving energy efficiency. Static Random Access Memory (SRAM), due to its mature CMOS process compatibility, high speed, and good stability, has become one of the important carriers for realizing in-memory computing.

[0004] On the other hand, in safety-critical applications such as aerospace, aviation, autonomous driving, and industrial control, systems not only require high performance and low power consumption but also high reliability. However, as process dimensions continue to shrink, SRAM memory cells become increasingly sensitive to external factors such as radiation and electrical noise, making them prone to soft errors that can cause data flipping and thus affect system correctness. Therefore, error correction coding technology is widely used in storage systems. Error correction coding refers to a coding technique that adds specific redundant information to the original data input to form anti-interference codewords, and then identifies and corrects errors occurring during transmission or storage through the decoding process. Common types include Hamming codes, LDPC codes, Turbo codes, and BCH codes. This coding technique requires two core characteristics: error correction capability and coding efficiency. Error correction capability means that even after bit flips or symbol distortions occur due to noise interference, channel attenuation, storage loss, etc., the codeword can still accurately identify the error location and recover the original data through the decoding algorithm. Depending on the design, it can support the correction of single-bit, multi-bit, and even burst errors. Coding efficiency means that the proportion of added redundant information in the total codeword should be as low as possible, maximizing the transmission or storage bandwidth of effective data while ensuring the target error correction performance, and reducing hardware resource overhead and energy consumption. Among them, Hamming code is widely used to solve single-bit flip errors due to its simple hardware implementation.

[0005] In existing technologies, error correction coding is typically performed externally to memory using separate encoding and decoding circuits. Introducing this approach into in-memory computing architectures reintroduces significant data movement and additional logical operations, diminishing the energy efficiency advantages of in-memory computing. Therefore, existing research has attempted to directly implement the Boolean logic operations required for error correction coding within in-memory computing architectures, particularly the XOR operation.

[0006] However, existing XOR and error correction coding schemes based on SRAM in-memory computation still have significant shortcomings: First, in the hardware implementation of multi-operand XOR operations, as the number of operands increases, the number of circuit flips increases significantly, leading to a rapid increase in power consumption and latency; Second, some schemes rely on sensing amplifiers or complex comparison circuits, resulting in large hardware overhead and sensitivity to process fluctuations and noise; Third, most schemes only support error correction codes with shorter code lengths, such as (7,4) Hamming codes, and are difficult to extend to more commonly used code types such as (21,16) and (38,32).

[0007] Therefore, there is an urgent need for a way to implement multi-operand XOR operations in an SRAM in-memory computing architecture with low power consumption, low latency, and good scalability. Summary of the Invention

[0008] The purpose of this invention is to provide an SRAM in-memory computing architecture and its multi-operand XOR method, which has the advantages of being lightweight, energy efficient, and low-latency.

[0009] This invention is achieved through the following technical solution:

[0010] In a first aspect, the first embodiment of the present invention provides an SRAM in-memory computing architecture, including an SRAM storage array and an in-memory computing control module. The SRAM storage array includes a voltage-shifting XOR calculation module. The SRAM storage array is used to store data to be processed, redundancy check information, and temporarily store intermediate results of multi-operand XOR operations and check sub-calculation results.

[0011] The in-memory computing control module is used to control the sub-line, bit line and read / write timing, and provides clock signals and read word line activation signals for multi-operand XOR operations;

[0012] The voltage-shifting XOR calculation module is used to perform multi-operand XOR operations within the storage array using a two-stage voltage conversion strategy and a capacitor charge sharing mechanism, and to obtain the XOR calculation result.

[0013] Furthermore, the SRAM storage array also includes an error correction coding module, which is used to perform parallel processing of multi-operand XOR operations, combine and schedule the XOR calculation results, and complete the encoding or decoding process of different Hamming codes.

[0014] Furthermore, the voltage-shifting XOR calculation module includes a voltage comparison unit, a result storage unit, and a logic combination unit. The voltage comparison unit uses skewed inverters with different flip thresholds to determine the voltage range at different stages and obtain intermediate results.

[0015] The result storage unit uses the parasitic capacitance of the XOR gate input port to store the intermediate results of each stage.

[0016] The combinational logic unit generates the final XOR calculation result based on the intermediate results.

[0017] Furthermore, the voltage comparison unit includes a first comparison unit and a second comparison unit. The first comparison unit is used to precharge the read bit line to the supply voltage in the first stage, and then discharge the read bit line by applying short pulses to the read word lines of several rows involved in the calculation, and obtain a first intermediate result through a deflection inverter. The second comparison unit is used to perform charge sharing shift of the voltage space through capacitor voltage division in the second stage, and obtain a second intermediate result through a deflection inverter while keeping the comparison threshold unchanged.

[0018] Furthermore, the error correction coding module includes a column sorting check matrix and a pipeline control unit. The column sorting check matrix is ​​used to group the check matrix by column, with each group corresponding to an independent voltage-shift XOR operation module. The pipeline control unit is used to achieve parallel processing of XOR calculations at different stages through pipeline scheduling.

[0019] Secondly, another embodiment of the present invention provides a multi-operand XOR method based on the SRAM in-memory computing architecture described in the above embodiments, comprising:

[0020] The read word lines of multiple memory cells in the same column of the memory array are activated simultaneously, causing the read bit lines to discharge. The voltage value after discharge is related to the number of logic "1"s involved in the operation.

[0021] A two-stage voltage conversion strategy is used inside the storage array to perform multi-operand XOR operations and obtain the XOR calculation result.

[0022] Furthermore, the method also includes:

[0023] Parallel processing of multi-operand XOR operations, combination and scheduling of XOR calculation results, and completion of encoding or decoding processes for different Hamming codes.

[0024] Furthermore, the specific method for using a two-stage voltage conversion strategy within the storage array to perform multi-operand XOR operations and obtain the XOR calculation result includes:

[0025] By using skewed inverters with different flip thresholds, intermediate results are obtained by determining the voltage range at different stages.

[0026] The parasitic capacitance of the XOR gate input port is used to store the intermediate results of each stage;

[0027] The final XOR calculation result is generated based on the intermediate results.

[0028] Furthermore, the specific method for using skew inverters with different flip thresholds to determine the voltage range at different stages and obtain intermediate results includes:

[0029] The stage includes a first stage and a second stage. In the first stage, the read bit line is precharged to the supply voltage, and then the read bit line is discharged by applying short pulses to the read word lines of several rows involved in the operation, and the first intermediate result is obtained through the deflection inverter.

[0030] In the second stage, the voltage space is shifted by charge sharing through capacitive voltage division, and the second intermediate result is obtained through a skew inverter while keeping the comparison threshold unchanged.

[0031] Furthermore, the specific method for parallel processing of multi-operand XOR operations is as follows: parallel execution of multi-operand XOR operations is achieved through pipeline scheduling.

[0032] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0033] This invention provides an SRAM in-memory computing architecture and its multi-operand XOR method. By setting up a voltage-shifted XOR calculation module, the energy consumption and latency of multi-operand XOR operations are reduced. Through the optimization of the column sorting parity matrix by setting up an error correction coding module and the use of a pipeline control unit for multi-stage pipeline scheduling and parallel processing, it supports Hamming codes of arbitrary size without increasing the number of core units, and significantly reduces encoding and decoding latency. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0035] Figure 1 This is a schematic diagram of an SRAM in-memory computing architecture provided in the first embodiment of the present invention;

[0036] Figure 2 for Figure 1 The circuit diagram of the 8T circuit;

[0037] Figure 3 This is a block diagram of the voltage-shifting XOR calculation module;

[0038] Figure 4 This is the circuit diagram of the voltage-shifting XOR calculation module;

[0039] Figure 5 A schematic diagram of a column-sorted verification matrix;

[0040] Figure 6 This is a schematic diagram of the pipeline division in the error correction coding module;

[0041] Figure 7 A flowchart of a multi-operand XOR method for an SRAM in-memory computing architecture provided in another embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0043] like Figure 1 As shown, the first embodiment of the present invention provides an SRAM in-memory computing architecture, which includes: an SRAM storage array, a row decoder, a column decoder, an in-memory computing control module, and a 4-bit XOR unit. The SRAM storage array includes a voltage-shift XOR computing module, which is used to store data to be processed, redundancy check information, and temporarily store intermediate results and checksum calculation results of multi-operand XOR operations. The in-memory computing control module is used to control the sub-lines, bit lines, and read / write timing, and provides clock signals and read word line activation signals for multi-operand XOR operations. The voltage-shift XOR computing module is used to implement multi-operand XOR operations within the storage array using a two-stage voltage conversion strategy and a capacitor charge sharing mechanism to obtain the XOR calculation result. The SRAM storage array also includes an error correction coding module, which is used to perform parallel processing of multi-operand XOR operations, combine and schedule the XOR calculation results, and complete the encoding or decoding process of different Hamming codes.

[0044] like Figure 2 As shown, a classic 8T SRAM memory cell with an independent read / write port is used as the basic computing unit, i.e. Figure 1 The 8T in the model describes a method that activates the read word lines of multiple memory cells simultaneously in the same column, causing voltage changes on the read bit lines of these cells within the same time period. This voltage change is related to the number of logic "1"s in the memory cells involved in the calculation, thus enabling Boolean operations that satisfy both commutative and associative laws.

[0045] The voltage-shifting XOR calculation module employs a two-stage voltage conversion strategy and a capacitor charge-sharing mechanism to achieve multi-operand XOR operations. The bitwise XOR operation is decomposed into two... In the bit operation stage, the number of circuit flip paths is significantly reduced, lowering energy consumption and latency. Voltage shifting is achieved through capacitor charge sharing, eliminating the need for a large number of additional transistors, balancing area efficiency and computational performance, and supporting flexible expansion of operand bits. To reduce the number of circuit node flips during multi-operand XOR operations, the voltage-shifting XOR calculation module performs voltage-shifting calculations as follows: In the first stage, the read bit lines ( Figure 1 and Figure 2 Each column of RBL is precharged to the supply voltage. Then, through the reading lines of several lines involved in the calculation ( Figure 1 and Figure 2 The duration is applied to each row of the RWL. A short pulse discharges the read line and through a The bit XOR subunit makes a preliminary judgment on the range of the voltage of the final read bit line, roughly dividing the number of logic "1"s involved in the operation into several intervals. Specifically, let the number of "1"s in all input operands be... Then the voltage on the read line will become ,in, The on-resistance of the 8T-SRAM cell is... This is the parasitic capacitance of the read bit line. If If the value is odd, the output of the first stage should be 1; otherwise, it should be 0. In the second stage, the voltage space is shifted using capacitor voltage division, and the same comparison threshold is maintained. The bit XOR sub-unit performs another judgment to obtain another set of interval information. The parameters of the capacitors involved in the voltage divider are carefully adjusted so that the voltage after voltage division becomes the same as before voltage division. times, if If the value is even, the output of the second stage should be 1; otherwise, it should be 0. Finally, by combining and interpreting the results of the two stages, the outputs of the two stages are XORed to determine the exact parity of the logic "1" involved in the operation, thus obtaining the XOR result. The truth table for the two stages is shown in Table 1. Compared with the traditional one-time multi-threshold comparison method, this method significantly reduces the number of voltage flips at critical nodes, fundamentally reducing dynamic power consumption and latency.

[0046] Table 1 Truth Tables for the Two Calculation Stages (in words) (For example)

[0047] (The number of 1s in the operand) Phase 1 output Phase 2 output XOR result 0 0 0 0 1 0 1 1 2 1 1 0 3 1 0 1 4 0 0 0

[0048] like Figure 3 As shown, the voltage-shifting XOR calculation module includes a voltage comparison unit, a result storage unit, and a logic combination unit. The voltage comparison unit uses skewed inverters or equivalent structures with different flip thresholds to determine the voltage range at different stages and obtain intermediate results. The result storage unit uses the parasitic capacitance of the XOR gate input port to store the intermediate results at each stage. The combinational logic unit generates the final XOR calculation result based on the intermediate results. Figure 4 The diagram shows a circuit diagram of a voltage-shifting XOR calculation module. In the first stage, the clock signal... and At this time, the read word line of the response row participating in the operation is activated by a short pulse, and the read bit line, along with the capacitor... Together from pre-charged Discharge to The intermediate result of the first stage is obtained by using two skew inverters with different flip thresholds, and stored in the parasitic capacitance of the XOR gate input port. In the second stage, the clock signal... and ,capacitance and Charge sharing occurs between them. Because the parameters of the two capacitors are carefully selected, the voltage across the two capacitors will become [different value] after charge sharing. The intermediate result of the second stage is obtained through the same two skew inverters and latched onto the parasitic capacitance. The intermediate results of the first stage are XORed to obtain the final 4-bit XOR result.

[0049] In error correction coding applications, multiple XOR operations often need to be performed in a specific order. The error correction coding module includes a column sorting parity check matrix and a pipeline control unit. The column sorting parity check matrix is ​​used to group the parity check matrix by columns, with each group corresponding to an independent voltage-shift XOR operation module. The pipeline control unit is used to achieve parallel processing of XOR calculations at different stages through pipeline scheduling. A schematic diagram of the column sorting parity check matrix is ​​shown below. Figure 5 As shown, the error correction coding module optimizes the column sorting check matrix and uses a pipelined control unit for multi-stage pipeline scheduling and parallel processing, supporting Hamming codes of arbitrary size without increasing the number of core units, and significantly reducing encoding and decoding latency.

[0050] according to Figure 4As shown in the upper and lower circuits, each column in the memory implements two voltage-shift XOR calculation circuits as described above, implementing the two stages of the error correction coding process in a two-stage pipeline. Each stage completes a partial XOR calculation or stores intermediate results. Through pipeline scheduling, the calculations of different stages are performed in parallel, shortening the single encoding or decoding delay without reducing the overall throughput. This method is particularly suitable for error correction coding with large code lengths, such as (38,32) Hamming codes, and can significantly improve overall energy efficiency.

[0051] For the decoding process of (38,32) Hamming code, each calculation of the checksum involves three 19-bit XOR calculations, two 16-bit XOR calculations, and one 7-bit XOR calculation. Its pipeline can be designed according to... Figure 6 The process is divided into 30 stages, totaling 31 pipeline cycles. For each... To achieve the bit XOR operation requirement, this embodiment first performs a 4-bit XOR operation in the initial calculation. Then, the results are continuously written back to the storage array and used in subsequent calculations to achieve several subsequent 3-bit XOR operations, ultimately realizing the complete XOR operation. The bitwise XOR operation. Furthermore, this embodiment employs... The intermediate calculation result of the bit XOR operation is written back to the row of the original storage array where redundant bits are stored to store the intermediate calculation result. This eliminates the need for additional storage resources to store the intermediate calculation result and further reduces hardware overhead.

[0052] This invention provides an SRAM in-memory computing architecture that optimizes the energy consumption and latency of multi-operand XOR operations from both the operational principle and hardware structure perspectives through a two-stage voltage conversion strategy and a shared XOR circuit design. Compared to traditional skewed inverter-type XOR units (4-bit operation latency ≥ 0.24ns, energy consumption ≥ 9.9fJ) and sense amplifier-type XOR units (4-bit operation latency ≥ 2.2ns, energy consumption ≥ 294.0fJ), this invention controls the latency of 4-bit XOR operations to ≤ 0.17ns and reduces energy consumption to ≤ 5.2fJ, achieving an overall performance improvement of over 47.5% compared to the best existing solutions.

[0053] By grouping the parity check matrix by columns, with each group corresponding to an independent voltage-shift XOR calculation module, adding a new code type only requires adjusting the number of groups and the timing coordination between modules, without needing to reconstruct the core operation unit. Furthermore, the voltage-shift XOR calculation module supports dynamic adjustment of the operand bit length (configurable from 2 bits to 16 bits) via control signals. Combined with the flexible scheduling of the pipeline control module, it can adapt to the varying requirements of different Hamming code types regarding the number of XOR operands. Especially for mainstream applications with 32-bit data widths, this embodiment can efficiently adapt to (38,32) Hamming codes (6 redundant bits, 32 data bits), achieving efficient execution of parity bit generation and parity calculation through pipelined parallel operation of 19 groups of 4-bit XOR units. Simultaneously, this architecture can be seamlessly extended to larger Hamming code sizes.

[0054] like Figure 7 As shown, another embodiment of the present invention provides a multi-operand XOR method based on the SRAM in-memory computing architecture described in the above embodiments, comprising:

[0055] The read word lines of multiple memory cells in the same column of the memory array are activated simultaneously, causing the read bit lines to discharge. The voltage value after discharge is related to the number of logic "1"s involved in the operation.

[0056] A two-stage voltage conversion strategy is used inside the storage array to perform multi-operand XOR operations and obtain the XOR calculation result.

[0057] In this embodiment, the method further includes:

[0058] Parallel processing of multi-operand XOR operations, combination and scheduling of XOR calculation results, and completion of encoding or decoding processes for different Hamming codes.

[0059] Specific methods for achieving XOR calculation results using a two-stage voltage conversion strategy within a storage array include:

[0060] By using skewed inverters with different flip thresholds, intermediate results are obtained by determining the voltage range at different stages.

[0061] The parasitic capacitance of the XOR gate input port is used to store the intermediate results of each stage;

[0062] The final XOR calculation result is generated based on the intermediate results.

[0063] The specific methods for determining the voltage range at different stages and obtaining intermediate results using skewed inverters with different flip thresholds include:

[0064] The stage includes a first stage and a second stage. In the first stage, the read bit line is precharged to the supply voltage, and then the read bit line is discharged by applying short pulses to the read word lines of several rows involved in the operation, and the first intermediate result is obtained through the deflection inverter.

[0065] In the second stage, the voltage space is shifted by charge sharing through capacitive voltage division, and the second intermediate result is obtained through a skew inverter while keeping the comparison threshold unchanged.

[0066] The specific method for parallel processing of multi-operand XOR operations is to achieve parallel execution of multi-operand XOR operations through pipeline scheduling.

[0067] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An SRAM in-memory computing architecture, characterized in that, include: SRAM storage array and in-memory calculation control module, wherein the SRAM storage array includes a voltage-shifting XOR calculation module, and the SRAM storage array is used to store data to be processed, redundancy check information, and temporarily store intermediate results of multi-operand XOR operations and check sub-calculation results; The in-memory computing control module is used to control the sub-line, bit line and read / write timing, and provides clock signals and read word line activation signals for multi-operand XOR operations; The voltage-shifting XOR calculation module is used to perform multi-operand XOR operations within the storage array using a two-stage voltage conversion strategy and a capacitor charge sharing mechanism, and to obtain the XOR calculation result.

2. The architecture as described in claim 1, characterized in that, The SRAM storage array also includes an error correction coding module, which is used to perform parallel processing of multi-operand XOR operations, combine and schedule the XOR calculation results, and complete the encoding or decoding process of different Hamming codes.

3. The architecture as described in claim 2, characterized in that, The voltage-shifting XOR calculation module includes a voltage comparison unit, a result storage unit, and a logic combination unit. The voltage comparison unit uses skewed inverters with different flip thresholds to determine the voltage range at different stages and obtain intermediate results. The result storage unit uses the parasitic capacitance of the XOR gate input port to store the intermediate results of each stage. The combinational logic unit generates the final XOR calculation result based on the intermediate results.

4. The architecture as described in claim 3, characterized in that, The voltage comparison unit includes a first comparison unit and a second comparison unit. The first comparison unit is used to precharge the read bit line to the supply voltage in the first stage, and then discharge the read bit line by applying short pulses to the read word lines of several rows involved in the calculation, and obtain a first intermediate result through a deflection inverter. The second comparison unit is used to perform charge sharing shift of the voltage space through capacitor voltage division in the second stage, and obtain a second intermediate result through a deflection inverter while keeping the comparison threshold unchanged.

5. The architecture as described in claim 4, characterized in that, The error correction coding module includes a column sorting check matrix and a pipeline control unit. The column sorting check matrix is ​​used to group the check matrix by column, with each group corresponding to an independent voltage-shifting XOR operation module. The pipeline control unit is used to achieve parallel processing of XOR calculations at different stages through pipeline scheduling.

6. A multi-operand XOR method based on the SRAM in-memory computing architecture as described in any one of claims 1-5, characterized in that, include: The read word lines of multiple memory cells in the same column of the memory array are activated simultaneously, causing the read bit lines to discharge. The voltage value after discharge is related to the number of logic "1"s involved in the operation. A two-stage voltage conversion strategy is used inside the storage array to perform multi-operand XOR operations and obtain the XOR calculation result.

7. The method as described in claim 6, characterized in that, Also includes: Parallel processing of multi-operand XOR operations, combination and scheduling of XOR calculation results, and completion of encoding or decoding processes for different Hamming codes.

8. The method as described in claim 7, characterized in that, The specific method for using a two-stage voltage conversion strategy within the storage array to perform multi-operand XOR operations and obtain the XOR calculation result includes: By using skewed inverters with different flip thresholds, intermediate results are obtained by determining the voltage range at different stages. The parasitic capacitance of the XOR gate input port is used to store the intermediate results of each stage; The final XOR calculation result is generated based on the intermediate results.

9. The method as described in claim 8, characterized in that, The specific method for determining the voltage range at different stages and obtaining intermediate results using skew inverters with different flip thresholds includes: The stage includes a first stage and a second stage. In the first stage, the read bit line is precharged to the supply voltage, and then the read bit line is discharged by applying short pulses to the read word lines of several rows involved in the operation, and the first intermediate result is obtained through the deflection inverter. In the second stage, the voltage space is shifted by charge sharing through capacitive voltage division, and the second intermediate result is obtained through a skew inverter while keeping the comparison threshold unchanged.

10. The method as described in claim 9, characterized in that, The specific method for parallel processing of multi-operand XOR operations is as follows: parallel execution of multi-operand XOR operations is achieved through pipeline scheduling.

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