Memory circuit and method of programming the same

Abstract

A memory circuit and a programming method thereof, the memory circuit including memory cells each from one of first to fourth cells. A transistor of the first cell has a gate coupled to a first word line, a source / drain coupled to a first interconnect carrying a ground voltage, and a drain / source coupled to the first interconnect. A transistor of the second cell has a gate coupled to a second word line, a source / drain coupled to a second interconnect serving as a bit line, and a drain / source coupled to the second interconnect. A transistor of the third cell has a gate coupled to a third word line, a source / drain coupled to the first interconnect, and a drain / source coupled to the second interconnect. A transistor of the fourth cell has a gate coupled to a fourth word line, a drain / source coupled to the second interconnect, and a drain / source coupled to the first interconnect.

Description

Technical Field

[0001] One embodiment disclosed herein relates to a memory circuit and a method for programming the same, and more particularly to a memory circuit and a method for programming the same that allows for a reduction in additional area. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As IC dimensions continue to shrink, more devices are integrated into a single chip. This scaling-down process typically yields benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory array comprising a plurality of memory cells. Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes a first transistor having: a gate coupled to a first word line; a first source / drain coupled to a first interconnect structure carrying a ground voltage; and a second source / drain coupled to the first interconnect structure. The second memory cell includes a second transistor having: a gate coupled to a second word line; a first source / drain coupled to a second interconnect structure serving as a bit line; and a second source / drain coupled to the second interconnect structure. The third memory cell includes a third transistor having: a gate coupled to a third word line; a first source / drain coupled to the first interconnect structure; and a second source / drain coupled to the second interconnect structure. The fourth memory cell includes a fourth transistor having: a gate terminal coupled to a fourth word line; a first source / drain terminal coupled to a second interconnect structure; and a second source / drain terminal coupled to a first interconnect structure.

[0004] Another embodiment of this disclosure provides a memory circuit comprising a memory array. The memory array includes a plurality of memory cells. These memory cells are arranged above a plurality of word lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines extending along the second lateral direction. Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first source / drain terminals and the second source / drain terminals of the first memory cell are both connected to corresponding terminals of the reference lines. The first source / drain terminals and the second source / drain terminals of the second memory cell are both connected to corresponding terminals of the signal lines. The first source / drain terminals and the second source / drain terminals of the third memory cell are respectively connected to corresponding terminals of the signal lines and corresponding terminals of the reference lines. The first source / drain terminals and the second source / drain terminals of the fourth memory cell are respectively connected to corresponding terminals of the reference lines and corresponding terminals of the signal lines.

[0005] Another embodiment of this disclosure provides a programming method for a memory circuit, comprising the following steps: An initial memory cell among a plurality of memory cells is formed as one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first source / drain terminals and the second source / drain terminals of the first memory cell are both connected to a reference line. The first source / drain terminals and the second source / drain terminals of the second memory cell are both connected to a signal line. The first source / drain terminals and the second source / drain terminals of the third memory cell are respectively connected to a signal line and a reference line. The first source / drain terminals and the second source / drain terminals of the fourth memory cell are respectively connected to a reference line and a signal line. Based on the initial memory cell being formed as the first memory cell, the next immediately following memory cell is formed as either the first memory cell or the third memory cell. Based on the initial memory cell being formed as the second memory cell, the next immediately following memory cell is formed as either the second memory cell or the fourth memory cell. The initial memory unit is used to form the third memory unit, and the next memory unit is used to form the second or fourth memory unit. The initial memory unit is used to form the fourth memory unit, and the next memory unit is used to form the first or third memory unit. Attached Figure Description

[0006] The various aspects of one embodiment of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A block diagram illustrating an exemplary memory device (or circuit) according to some embodiments;

[0008] Figure 2 Descriptions according to some embodiments may include in Figure 1 A circuit diagram of an exemplary memory array in a memory device;

[0009] Figure 3 Descriptions according to some embodiments may include in Figure 1 A schematic diagram and layout of an exemplary memory array in a memory device;

[0010] Figure 4 Descriptions according to some embodiments may include in Figure 1 A circuit diagram of an exemplary memory array in memory device 100;

[0011] Figure 5 Descriptions according to some embodiments may include in Figure 1 A schematic diagram and layout of an exemplary memory array in a memory device;

[0012] Figure 6 A block diagram illustrating an exemplary memory device (or circuit) according to some embodiments;

[0013] Figure 7A and Figure 7B A schematic diagram illustrating an exemplary memory array according to some embodiments;

[0014] Figure 8 A block diagram illustrating an exemplary memory device (or circuit) according to some embodiments;

[0015] Figure 9 A flowchart illustrating an exemplary method for a programmable memory circuit according to some embodiments;

[0016] Figure 10 A flowchart illustrating an exemplary method for a programmable memory circuit according to some embodiments;

[0017] Figure 11 A flowchart illustrating an exemplary method for a programmable memory circuit according to some embodiments;

[0018] Figure 12 A flowchart illustrating an exemplary method for a programmable memory circuit according to some embodiments;

[0019] Figure 13 A flowchart illustrating an exemplary method for a programmable memory circuit according to some embodiments;

[0020] Figure 14 According to some embodiments, it can be used as Figure 13 A flowchart illustrating an exemplary method executed as part of the method;

[0021] Figure 15 According to some embodiments, it can be used as Figure 13 A flowchart illustrating an exemplary method executed as part of the method;

[0022] Figure 16 According to some embodiments, it can be used as Figure 13 A flowchart of an exemplary method executed as part of the method.

[0023] [Symbol Explanation]

[0024] 100, 600, 800: Memory devices

[0025] 105: Memory Controller

[0026] 112: BL Controller

[0027] 114: WL Controller

[0028] 120, 220, 320, 420, 520, 700A, 700B: Memory Array

[0029] 125: Memory Unit

[0030] 231, 331, 431, 531: First transistor

[0031] 232, 332, 432, 532: Second transistor

[0032] 233, 333, 433, 533: Third transistor

[0033] 234, 334, 434, 534: Fourth transistor

[0034] 241, 341, 441, 541: First interconnection structure

[0035] 251, 351, 451, 551: Second interconnection structure

[0036] 625: Additional Memory Unit

[0037] 650: Symbol Decoder

[0038] 709: Unit

[0039] 710: Select Unit

[0040] 825: Complementary Memory Unit

[0041] 860: Differential Symbolic I / O

[0042] 870: Control signal

[0043] 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600: Method

[0044] 910, 920, 930, 940, 950, 1010, 1020, 1030, 1040, 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, 1330, 1410, 1420, 1430, 1440, 1510, 1520, 1530, 1540, 1610, 1620, 1630: Operation

[0045] 0A: First memory unit

[0046] 0B: Second memory unit

[0047] 1A: Third Memory Unit

[0048] 1B: Fourth memory unit

[0049] BL, BL0~BL2, BLB, BLN-1: Bit lines

[0050] VDD: Power supply voltage

[0051] VIA1: A pair of first through-hole structures

[0052] VIA2: A pair of second through-hole structures

[0053] VIA3: A pair of third through-hole structures

[0054] VIA4: A pair of fourth through-hole structures

[0055] VSS: Grounding voltage

[0056] WL, WL0~WL4, WLB1~WLB4, WLM-1: Character lines

[0057] X, Y: Direction Detailed Implementation

[0058] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0059] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” “top,” and “bottom” may be used herein to describe the relationship between one element or feature and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0060] In advanced memory technologies, binary data can be embedded into the memory cell layout, where each binary bit corresponds to a specific memory cell. To improve layout and functionality, isolation dummy cells are typically inserted between subarrays of memory cells. While this approach simplifies conversion processes and helps manage variations, it introduces significant area costs and increases the overall footprint of the memory design. Eliminating isolation dummy cells can reduce area costs, but this introduces challenges related to layout redundancy. For example, the expanded design phase space can cause changes in characteristics such as cell stability, bit line load, and read margin, thereby sacrificing the efficiency of the mapped rows for finding memory circuitry.

[0061] This disclosure provides a technique for an efficient conversion method. By eliminating isolated dummy cells and embedding the original data using only a limited number of memory cells, area costs can be reduced while maintaining consistent performance. Therefore, this allows binary data to be embedded in the memory cell layout, improving efficiency and minimizing variation. The efficient conversion method disclosed herein simplifies the process of generating schematics and layouts, thereby significantly reducing design time. Furthermore, the introduction of additional sign rows and the method of generating sign bits effectively suppress bitline load variations, ensuring enhanced stability and reliability of the entire memory array.

[0062] According to one embodiment of this disclosure, in some embodiments, the memory circuit includes a memory array comprising a plurality of memory cells, each memory cell being selected from a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes a first transistor having: a gate coupled to a first word line; a first source / drain coupled to a first interconnect structure carrying a ground voltage; and a second source / drain coupled to the first interconnect structure. The second memory cell includes a second transistor having: a gate coupled to a second word line; a first source / drain coupled to a second interconnect structure serving as a bit line; and a second source / drain coupled to the second interconnect structure. The third memory cell includes a third transistor having: a gate coupled to a third word line; a first source / drain coupled to the first interconnect structure; and a second source / drain coupled to the second interconnect structure. The fourth memory cell includes a fourth transistor having: a gate terminal coupled to a fourth word line; a first source / drain terminal coupled to a second interconnect structure; and a second source / drain terminal coupled to a first interconnect structure.

[0063] Figure 1 This diagram illustrates a block diagram of an exemplary memory device (or circuit) 100 according to some embodiments. The memory device 100 includes a memory controller 105 and a memory array 120. In one embodiment, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 includes word lines WL0, WL1…WL M-1 Each character line extends along a direction (e.g., the X direction), and the bit lines BL0, BL1...BL N-1 Each bit line extends in another direction (e.g., the Y direction). The word line WL and bit line BL may each be a conductive metal or a conductive rail. In some embodiments, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and can operate according to a voltage or current via the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB coupled to one or more memory cells 125 arranged in a direction (e.g., the Y direction). Bit lines BL, BLB can receive and / or provide differential signals.

[0064] Each memory cell 125 may include a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell 125 may be embodied as a static random access memory (SRAM) cell, etc. However, it should be understood that the memory cell 125 may be implemented as any of a variety of other non-volatile memory cells, such as a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase-change random access memory (PCRAM) cell, an electrically programmable fuse, an antifuse, a read-only memory (ROM) (e.g., a ROM compiler), etc., while still within the scope of one embodiment disclosed herein. For example, each memory cell 125 may include a ROM cell.

[0065] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line (BL) controller 112, a word line (WL) controller 114, etc. The BL controller 112 and the WL controller 114 may be embodied as logic circuitry, analog circuitry, or a combination thereof. In one configuration, the WL controller 114 may be a circuit that provides voltage or current to one or more word lines WL of the memory array 120. The BL controller 112 may be a circuit that provides or senses voltage or current to one or more bit lines BL of the memory array 120. The BL controller 112 may be coupled to the bit lines BL of the memory array 120, while the WL controller 114 may be coupled to the word lines WL of the memory array 120.

[0066] In some embodiments, memory circuitry 120 includes a plurality of memory cells (e.g., memory cell 125), each memory cell being selected from a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes a first transistor having: a gate coupled to a first word line; a first source / drain coupled to a first interconnect structure carrying a ground voltage; and a second source / drain coupled to the first interconnect structure. The second memory cell includes a second transistor having: a gate coupled to a second word line; a first source / drain coupled to a second interconnect structure serving as a bit line; and a second source / drain coupled to the second interconnect structure. The third memory cell includes a third transistor having: a gate coupled to a third word line; a first source / drain coupled to the first interconnect structure; and a second source / drain coupled to the second interconnect structure. The fourth memory cell includes a fourth transistor having: a gate terminal coupled to a fourth word line; a first source / drain terminal coupled to a second interconnect structure; and a second source / drain terminal coupled to a first interconnect structure.

[0067] In some embodiments, the memory array 120 includes a plurality of memory cells (e.g., memory cells 125) disposed above a plurality of word lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines (e.g., bit lines, data lines, etc.) extending along the second lateral direction. Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes first and second source / drain terminals, both connected to corresponding lines among the reference lines. The second memory cell includes first and second source / drain terminals, both connected to corresponding lines among the signal lines (e.g., bit lines, data lines, etc.). The third memory cell includes first and second source / drain terminals, respectively connected to corresponding lines among the signal lines (e.g., bit lines, data lines, etc.) and corresponding lines among the reference lines. The fourth memory cell includes first and second source / drain terminals, respectively connected to corresponding lines among the reference lines and corresponding lines among the signal lines (e.g., bit lines, data lines, etc.).

[0068] Figure 2 Descriptions according to some embodiments may include in Figure 1 A circuit diagram of an exemplary memory array 220 in the memory device 100. In some embodiments, the memory array 220 may be substantially similar to or incorporate features of the memory array 120. It should be understood that... Figure 2The memory array 220 is simplified for illustrative purposes, and therefore, the memory array 220 can be implemented in any of a variety of other configurations, while still remaining within the scope of one embodiment disclosed herein.

[0069] Memory array 220 includes a first memory cell 0A, a second memory cell 0B, a third memory cell 1A, and a fourth memory cell 1B. In some embodiments, each memory cell in memory array 220 may be selected from one of the first memory cell 0A, the second memory cell 0B, the third memory cell 1A, or the fourth memory cell 1B. In some embodiments, the first memory cell 0A includes a first transistor 231. The first transistor 231 may have: a gate terminal coupled to a first word line WL1; a first source / drain terminal coupled to a first interconnect structure 241 carrying a ground voltage VSS; and a second source / drain terminal coupled to the first interconnect structure 241. In some embodiments, the second memory cell 0B includes a second transistor 232. The second transistor 232 may have: a gate terminal coupled to a second word line WL2; a first source / drain terminal coupled to a second interconnect structure 251 serving as a bit line; and a second source / drain terminal coupled to the second interconnect structure 251. In some embodiments, the third memory cell 1A includes a third transistor 233. The third transistor 233 may have: a gate terminal coupled to a third word line WL3; a first source / drain terminal coupled to a first interconnect structure 241; and a second source / drain terminal coupled to a second interconnect structure 251. In some embodiments, the fourth memory cell 1B includes a fourth transistor 234. The fourth transistor 234 may have: a gate terminal coupled to a fourth word line WL4; a first source / drain terminal coupled to a second interconnect structure 251; and a second source / drain terminal coupled to a first interconnect structure 241. In some embodiments, the first memory cell 0A and the second memory cell 0B are operably oriented to a first logic state (e.g., "1"), and the third memory cell 1A and the fourth memory cell 1B are operably oriented to a second logic state (e.g., "0"). In some embodiments, at least one of the first transistor 231, the second transistor 232, the third transistor 233, and the fourth transistor 234 may be an NMOS transistor. For example, each of the first transistor 231, the second transistor 232, the third transistor 233, and the fourth transistor 234 may be an NMOS transistor.

[0070] In some embodiments, the first interconnect structure 241 may be a reference line. In some embodiments, the second interconnect structure 251 may be a signal line (e.g., a bit line, a data line, etc.). In some embodiments, the memory cells of the memory array 220 may be disposed above a plurality of word lines (e.g., word lines WL1, WL2, WL3, WL4, etc.) extending along a first lateral direction, a plurality of reference lines (e.g., the first interconnect structure 241) extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines (e.g., the second interconnect structure 251, bit lines, data lines, etc.) extending along the second lateral direction. In some embodiments, word lines WL1, WL2, WL3, and WL4 may physically extend along the first lateral direction, and the first interconnect structure 241 and the second interconnect structure 251 may extend along a second lateral direction perpendicular to the first lateral direction.

[0071] In some embodiments, the first memory cell 0A may connect its first and second source / drain terminals to corresponding lines in these reference lines (e.g., the first interconnect structure 241). The second memory cell 0B may connect its first and second source / drain terminals to corresponding lines in these signal lines (e.g., the second interconnect structure 251, bit lines, data lines, etc.). The third memory cell 1A may connect its first and second source / drain terminals to corresponding lines in these signal lines (e.g., the second interconnect structure 251, bit lines, data lines, etc.) and corresponding lines in these reference lines (e.g., the first interconnect structure 241), respectively. The fourth memory cell 1B may connect its first and second source / drain terminals to corresponding lines in these reference lines (e.g., the first interconnect structure 241) and corresponding lines in these signal lines (e.g., the second interconnect structure 251, bit lines, data lines, etc.), respectively.

[0072] As disclosed herein, by using a predetermined number of memory units (e.g., such as...) Figure 2 The four cells shown embed data, and memory array 220 allows for a reduction in additional area while maintaining consistent performance and reliability, as discussed in more detail below. For example, the original data row d m =[d0,…,d N-1 ], where d i ∈{1,0}(2 N (a combination), which can be encoded as a mapping row with a memory array 220, c m =[c0,…,c N-1 ], where c i ∈{1A,1B,0A,0B}(2 N+1 (a number of combinations). In some embodiments, in addition to the factor 2, the number of possible combinations of the memory array (2^3) N+1 (10 combinations) and the number of possible combinations of the original data (2) NThis involves matching a combination of elements. This reduces the phase space of the memory array and decreases resources (e.g., time, computation, etc.) to find a c that reduces any given original data d. m Furthermore, minimizing redundancy in the memory array reduces variability, thereby improving timing specifications, reliability, and yield.

[0073] Figure 3 Descriptions according to some embodiments may include in Figure 1 A schematic diagram and layout of an exemplary memory array 320 in the memory device 100. Specifically, in the memory array 320, the original data row d is shown. m =[d0,…,d N-1 (m = 0, ..., M-1; M is the number of rows in the original data matrix) can be embedded in the ROM cell chain c m (This can be equivalently called a through-hole array v) m =[v0,…,v N ], where v i ∈{–1(on VSS),1(on BLB)}). In some embodiments, memory array 320 may be substantially similar to or incorporate features of memory array 220. It should be understood that Figure 3 The schematic diagrams and layouts shown are simplified for illustrative purposes and can therefore be implemented in any of a variety of other configurations while still remaining within the scope of one embodiment disclosed herein.

[0074] Referring to the schematic diagram and layout diagram, the memory array 320 may include multiple via structures. In some embodiments, the memory array 320 includes a pair of first via structures VIA1 for connecting the first and second source / drain terminals of the first transistor 331 to the first interconnect structure 341 (e.g., VSS). In some embodiments, the memory array 320 includes a pair of second via structures VIA2 for connecting the first and second source / drain terminals of the second transistor 332 to the second interconnect structure 351 (e.g., BLB). In some embodiments, the memory array 320 includes a pair of third via structures VIA3 for connecting the first and second source / drain terminals of the third transistor 333 to the first interconnect structure 341 and the second interconnect structure 351, respectively. In some embodiments, the memory array 320 includes a pair of fourth via structures VIA4 for connecting the first and second source / drain terminals of the fourth transistor 334 to the second interconnect structure 351 and the first interconnect structure 341, respectively.

[0075] The memory cells of the memory array disclosed herein can be selected, set, or configured based on a first type of memory cell (e.g., first memory cell 0A), a second type of memory cell (e.g., second memory cell 0B), a third type of memory cell (e.g., third memory cell 1A), or a fourth type of memory cell (e.g., fourth memory cell 1B).

[0076] In some embodiments, the plurality of memory cells of the memory array 320 may be physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a first memory cell 0A, and the next memory cell among these memory cells (e.g., one of the adjacent cells in the processing direction; for example) Figure 3 The adjacent unit on the right is either the first memory unit 0A or the third memory unit 1A. In some embodiments, the plurality of memory units of the memory array 320 may be physically arranged in a horizontal direction, wherein the initial memory unit among these memory units is the second memory unit 0B, and the next memory unit among these memory units is either the second memory unit 0B or the fourth memory unit 1B. In some embodiments, the plurality of memory units of the memory array 320 may be physically arranged in a horizontal direction, wherein the initial memory unit among these memory units is the third memory unit 1A, and the next memory unit among these memory units is either the second memory unit 0B or the fourth memory unit 1B. In some embodiments, the plurality of memory units of the memory array 320 may be physically arranged in a horizontal direction, wherein the initial memory unit among these memory units is the fourth memory unit 1B, and the next memory unit among these memory units is either the first memory unit 0A or the third memory unit 1A.

[0077] Table 1 shows each data point d0, ..., d N-1 Initial unit (c) n-1 ) and the next unit (c n ) are illustrative relationships between them.

[0078] Table 1

[0079]

[0080]

[0081] See Figure 3The initial unit (c0) can be the fourth unit 1B, and d0 = 1 is provided. According to Table 1, with the fourth unit 1B (c0) as the initial unit, the next unit (c1) can be the first unit 0A when d1 = 0. Similarly, with the first unit 0A (c1) as the initial unit, the next unit (c2) can be the first unit 0A when d2 = 0. With the first unit 0A (c2) as the initial unit, the next unit (c3) can be the third unit 1A when d3 = 1. With the third unit 1A (c3) as the initial unit, the next unit (c4) can be the fourth unit 1B when d4 = 1. With the fourth unit 1B (c4) as the initial unit, the next unit (c5) can be the third unit 1A when d5 = 1. With the third unit 1A (c5) as the initial unit, the next unit (c6) can be the second unit 0B when d6 = 0.

[0082] In some embodiments, the number of these memory cells may be equal to N, and the number of the first via structure VIA1 or the number of the second via structure VIA2 may be equal to or less than N / 2. For example, the number of memory cells arranged (or selected) in the memory array may be equal to N, and the number of connections on the first interconnect structure 341 or the second interconnect structure 351 may be equal to or less than N / 2. As a non-limiting example, in Figure 3 In the first interconnect structure 341, four connections are formed, wherein the number of memory cells arranged (or selected) is seven; and four connections are formed on the second interconnect structure 351, wherein the number of memory cells arranged (or selected) is seven.

[0083] Figure 4 Descriptions according to some embodiments may include in Figure 1 A circuit diagram of an exemplary memory array 420 in the memory device 100. In some embodiments, the memory array 420 may be substantially similar to or incorporate features of the memory array 120. It should be understood that... Figure 4 The memory array 420 is simplified for illustrative purposes, and therefore, the memory array 420 can be implemented in any of a variety of other configurations, while still remaining within the scope of one embodiment disclosed herein.

[0084] Memory array 420 includes a first memory cell 0A, a second memory cell 0B, a third memory cell 1A, and a fourth memory cell 1B. In some embodiments, each memory cell in memory array 420 may be selected from one of the first memory cell 0A, the second memory cell 0B, the third memory cell 1A, or the fourth memory cell 1B. In some embodiments, the first memory cell 0A includes a first transistor 431. The first transistor 431 may have: a gate terminal coupled to a first word line WLB1; a first source / drain terminal coupled to a first interconnect structure 441 carrying a power supply voltage VDD; and a second source / drain terminal coupled to the first interconnect structure 441. In some embodiments, the second memory cell 0B includes a second transistor 432. The second transistor 432 may have: a gate terminal coupled to a second word line WLB2; a first source / drain terminal coupled to a second interconnect structure 451 serving as a bit line; and a second source / drain terminal coupled to the second interconnect structure 451. In some embodiments, the third memory cell 1A includes a third transistor 433. The third transistor 433 may have: a gate terminal coupled to a third word line WLB3; a first source / drain terminal coupled to a first interconnect structure 441; and a second source / drain terminal coupled to a second interconnect structure 451. In some embodiments, the fourth memory cell 1B includes a fourth transistor 434. The fourth transistor 434 may have: a gate terminal coupled to a fourth word line WLB4; a first source / drain terminal coupled to a second interconnect structure 451; and a second source / drain terminal coupled to a first interconnect structure 441. In some embodiments, the first memory cell 0A and the second memory cell 0B are operably oriented to a first logic state (e.g., "0"), and the third memory cell 1A and the fourth memory cell 1B are operably oriented to a second logic state (e.g., "1"). In some embodiments, at least one of the first transistor 431, the second transistor 432, the third transistor 433, and the fourth transistor 434 may be a PMOS transistor. For example, each of the first transistor 431, the second transistor 432, the third transistor 433, and the fourth transistor 434 may be a PMOS transistor.

[0085] In some embodiments, the first interconnect structure 441 may be a reference line. In some embodiments, the second interconnect structure 451 may be a signal line (e.g., a bit line, a data line, etc.). In some embodiments, the memory cells of the memory array 420 may be disposed above a plurality of word lines (e.g., word lines WLB1, WLB2, WLB3, WLB4, etc.) extending along a first lateral direction, a plurality of reference lines (e.g., the first interconnect structure 441) extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines (e.g., the second interconnect structure 451, bit lines, data lines, etc.) extending along the second lateral direction. In some embodiments, word lines WLB1, WLB2, WLB3, and WLB4 may physically extend along the first lateral direction, and the first interconnect structure 441 and the second interconnect structure 451 may extend along a second lateral direction perpendicular to the first lateral direction.

[0086] In some embodiments, the first memory cell 0A may connect its first and second source / drain terminals to corresponding lines in these reference lines (e.g., the first interconnect structure 441). The second memory cell 0B may connect its first and second source / drain terminals to corresponding lines in these signal lines (e.g., the second interconnect structure 451, bit lines, data lines, etc.). The third memory cell 1A may connect its first and second source / drain terminals to corresponding lines in these signal lines (e.g., the second interconnect structure 451, bit lines, data lines, etc.) and corresponding lines in these reference lines (e.g., the first interconnect structure 441), respectively. The fourth memory cell 1B may connect its first and second source / drain terminals to corresponding lines in these reference lines (e.g., the first interconnect structure 441) and corresponding lines in these signal lines (e.g., the second interconnect structure 451, bit lines, data lines, etc.), respectively.

[0087] As disclosed herein, by using a predetermined number of memory units (e.g., such as...) Figure 4 The four cells shown embed data, and the memory array 420 allows for a reduction in additional area while maintaining consistent performance and reliability, as discussed in more detail below. For example, the original data row d m =[d0,…,d N-1 ], where d i ∈{1,0}(2 N (a combination), can be encoded as a mapping row with a memory array of 420, c m =[c0,…,c N-1 ], where c i ∈{1A,1B,0A,0B}(2 N+1 (a number of combinations). In some embodiments, in addition to the factor 2, the number of possible combinations of the memory array (2^3) N+1 (10 combinations) and the number of possible combinations of the original data (2) NThis involves matching a combination of elements. This reduces the phase space of the memory array and decreases resources (e.g., time, computation, etc.) to find a c that reduces any given original data d. m Furthermore, minimizing redundancy in the memory array reduces variability, thereby improving timing specifications, reliability, and yield.

[0088] Figure 5 Descriptions according to some embodiments may include in Figure 1 A schematic diagram and layout diagram of an exemplary memory array 520 in the memory device 100. Specifically, in the memory array 520, the original data row d is shown. m =[d0,…,d N-1 (m = 0, ..., M-1; M is the number of rows in the original data matrix) can be embedded in the ROM cell chain c m (This can be equivalently called a through-hole array v) m =[v0,…,v N ], where v i ∈{–1(on VDD),1(on BL)}). In some embodiments, memory array 520 may be substantially similar to or combine with the features of memory array 420. It should be understood that Figure 5 The schematic diagrams and layouts shown are simplified for illustrative purposes and can therefore be implemented in any of a variety of other configurations while still remaining within the scope of one embodiment disclosed herein.

[0089] Referring to the schematic diagram and layout diagram, the memory array 520 may include multiple via structures. In some embodiments, the memory array 520 includes a pair of first via structures VIA1 for connecting the first and second source / drain terminals of the first transistor 531 to the first interconnect structure 541 (e.g., VDD). In some embodiments, the memory array 520 includes a pair of second via structures VIA2 for connecting the first and second source / drain terminals of the second transistor 532 to the second interconnect structure 551 (e.g., BL). In some embodiments, the memory array 520 includes a pair of third via structures VIA3 for connecting the first and second source / drain terminals of the third transistor 533 to the first interconnect structure 541 and the second interconnect structure 551, respectively. In some embodiments, the memory array 520 includes a pair of fourth via structures VIA4 for connecting the first and second source / drain terminals of the fourth transistor 534 to the second interconnect structure 551 and the first interconnect structure 541, respectively.

[0090] The memory cells of the memory array disclosed herein can be selected, set, or configured based on a first type of memory cell (e.g., first memory cell 0A), a second type of memory cell (e.g., second memory cell 0B), a third type of memory cell (e.g., third memory cell 1A), or a fourth type of memory cell (e.g., fourth memory cell 1B).

[0091] In some embodiments, the plurality of memory cells of the memory array 520 may be physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a first memory cell 0A, and the next memory cell among these memory cells is either the first memory cell 0A or the third memory cell 1A. In some embodiments, the plurality of memory cells of the memory array 520 may be physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a second memory cell 0B, and the next memory cell among these memory cells is either the second memory cell 0B or the fourth memory cell 1B. In some embodiments, the plurality of memory cells of the memory array 520 may be physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a third memory cell 1A, and the next memory cell among these memory cells is either the second memory cell 0B or the fourth memory cell 1B. In some embodiments, the memory array 520 may be physically arranged in a lateral direction, wherein the initial memory unit among these memory units is the fourth memory unit 1B, and the next memory unit among these memory units is the first memory unit 0A or the third memory unit 1A.

[0092] See Figure 5 The initial unit (c0) can be the fourth unit 1B, and d0 = 1 is provided. According to Table 1, with the fourth unit 1B (c0) as the initial unit, the next unit (c1) can be the first unit 0A when d1 = 0. Similarly, with the first unit 0A (c1) as the initial unit, the next unit (c2) can be the first unit 0A when d2 = 0. With the first unit 0A (c2) as the initial unit, the next unit (c3) can be the third unit 1A when d3 = 1. With the third unit 1A (c3) as the initial unit, the next unit (c4) can be the fourth unit 1B when d4 = 1. With the fourth unit 1B (c4) as the initial unit, the next unit (c5) can be the third unit 1A when d5 = 1. With the third unit 1A (c5) as the initial unit, the next unit (c6) can be the second unit 0B when d6 = 0.

[0093] In some embodiments, the number of these memory cells may be equal to N, and the number of the first via structure VIA1 or the number of the second via structure VIA2 may be equal to or less than N / 2. For example, the number of memory cells arranged (or selected) in the memory array may be equal to N, and the number of connections on the first interconnect structure 541 or the second interconnect structure 551 may be equal to or less than N / 2. As a non-limiting example, in Figure 5 In the first interconnect structure 541, four connections are formed, wherein the number of memory cells arranged (or selected) is seven; and four connections are formed on the second interconnect structure 551, wherein the number of memory cells arranged (or selected) is seven.

[0094] According to one embodiment of the present disclosure, in some embodiments, the memory circuit (e.g., memory circuit 100) may include additional memory units to reduce variations in BL load. Figure 6 A block diagram illustrating an exemplary memory device (or circuitry) 600 according to some embodiments is provided. In some embodiments, memory device 600 may be substantially similar to or incorporate features of memory device 100. Unlike memory device 100, memory device 600 further includes an additional memory unit 625 and a symbol decoder 650. It should be understood that... Figure 6 The memory device 600 shown is simplified for illustrative purposes and can therefore be implemented in any of a variety of other configurations while remaining within the scope of one embodiment disclosed herein.

[0095] The memory unit 125 of the memory device 600 is disposed above a plurality of word lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines (e.g., bit lines, data lines, etc.) extending along the second lateral direction. An additional memory unit 625 may extend along the second lateral direction. The additional memory unit 625 is operatively corresponding to the sign of a corresponding subset of the memory unit 125 disposed along the first lateral direction. As discussed in more detail below, the additional memory unit 625 may be used as a sign bit unit to suppress variations in the BL load of the memory unit. Figure 7A The illustration depicts an exemplary memory array 700A according to some embodiments. In some embodiments, memory array 700A may be substantially similar to or incorporate features of memory array 120. It should be understood that memory array 700A is shown for illustrative purposes, for example, to show exemplary raw binary data (e.g., in the appendix as shown). Figure 7B (Previously shown as additional memory unit 625). Figure 7BThe illustration shows a schematic diagram of an exemplary memory array 700B according to some embodiments. In some embodiments, the memory array 700B may be substantially similar to or incorporate features of memory arrays 120, 700A, etc. Unlike memory array 700A, memory array 700B includes memory cells 125 and additional memory cells 625. It should be understood that... Figure 7B The memory array 700B shown is simplified for illustrative purposes and can therefore be implemented in any of a variety of other configurations while still remaining within the scope of one embodiment disclosed herein.

[0096] In some embodiments, the additional unit 625 may be used to provide sign bits. For example, for a selected unit 710 of the additional unit 625, a first logic state (e.g., "1") may be included. The additional unit 625 and the memory unit 125 may be used such that, based on the sign bits, data in a corresponding subset of the memory unit 125 is compared with the original data (e.g., Figure 7A The corresponding unit 709 is displayed as "0" and inverted (e.g., from "0" to "1"; from "1" to "0"). In the first row (BLB[0]), the first memory unit in memory unit 125 can be inverted from "0" to "1", in the second row (BLB[1]), the second memory unit in memory unit 125 can be inverted from "1" to "0", and in the Mth row (BLB[M-1]), the Mth memory unit in memory unit 125 can be inverted from "0" to "1". In the absence of an additional unit 625 for providing the sign bit, the BL load L of the mth BL is... m The function of the number of vias on the BLB Here, L m It can vary from 0 to N+1. The limit L can be restricted by the additional unit 625 used to provide the sign bit. m The upper and lower limits are set to suppress BL load variations, because in an N*M array with signed rows, L... m The mathematical limit of width can be defined as follows: in For cumulative binomial distribution The inverse function. These inverted bits can be decoded in the symbol decoder 650, thus providing the same output as the original data.

[0097] Figure 8A block diagram illustrating an exemplary memory device (or circuitry) 800 according to some embodiments is provided. In some embodiments, memory device 800 may be substantially similar to or incorporate features of memory devices 100, 600, etc. Unlike memory device 600, memory device 800 further includes complementary memory cells 825 and differential symbol I / O. It should be understood that... Figure 8 The memory device 800 shown is simplified for illustrative purposes and can therefore be implemented in any of a variety of other configurations while still remaining within the scope of one embodiment disclosed herein. In some embodiments, the complementary memory cell 825 may extend along a second lateral direction. The complementary memory cell 825 and the differential symbol I / O 860 may be used to allow the control signal 870 of the symbol decoder 650 to arrive earlier than the signal BLx.

[0098] Figure 9 This is a flowchart illustrating an exemplary method 900 for programming memory circuitry according to some embodiments. Method 900 may be performed by one or more components of the circuitry disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 900 is performed by other entities. In some embodiments, method 900 includes... Figure 9 The more, fewer, or different operations shown.

[0099] In brief, method 900 may begin with operation 910: forming an initial memory unit among a plurality of memory units into one of a first, second, third, or fourth memory units. Method 900 may continue to operation 920: based on the initial memory unit being formed as the first memory unit, forming the next immediately following memory unit among these memory units into a first or third memory unit. Method 900 may continue to operation 930: based on the initial memory unit being formed as the second memory unit, forming the next immediately following memory unit into a second or fourth memory unit. Method 900 may continue to operation 940: based on the initial memory unit being formed as the third memory unit, forming the next immediately following memory unit into a second or fourth memory unit. Method 900 may continue to operation 950: based on the initial memory unit being formed as the fourth memory unit, forming the next immediately following memory unit into a first or third memory unit.

[0100] At operation 910, the initial memory unit (e.g., memory unit 125) among the plurality of memory units is formed as a first, second, third, or fourth memory unit (e.g., memory units 0A, 0B, 1A, 1B, etc.). Figure 2One of the following is shown. The first and second source / drain terminals of the first memory cell are both connected to a reference line (e.g., the first interconnect structure 241). The first and second source / drain terminals of the second memory cell are both connected to a signal line (e.g., the second interconnect structure 251, a bit line, a data line, etc.). The first and second source / drain terminals of the third memory cell are connected to a signal line and a reference line, respectively. The first and second source / drain terminals of the fourth memory cell are connected to a reference line and a signal line, respectively.

[0101] At operation 920, a first memory unit is formed based on the initial memory unit, and the next memory unit immediately following this memory unit can be formed as either a first or a third memory unit. At operation 930, a second memory unit is formed based on the initial memory unit, and the next memory unit immediately following this memory unit can be formed as either a second or a fourth memory unit. At operation 940, a third memory unit is formed based on the initial memory unit, and the next memory unit immediately following this memory unit can be formed as either a second or a fourth memory unit. At operation 950, a fourth memory unit is formed based on the initial memory unit, and the next memory unit immediately following this memory unit can be formed as either a first or a third memory unit.

[0102] For example, such as Figure 3 As shown, the initial unit (c0) can be formed as the fourth unit. Using the fourth unit as the initial unit, the next unit (c1) can be formed as the first unit (e.g., for d1 = 0). Using the first unit 0A (c1) as the initial unit, the next unit (c2) can be formed as the first unit (e.g., for d2 = 0). Using the first unit (c2) as the initial unit, the next unit (c3) can be formed as the third unit (e.g., for d3 = 1). Using the third unit (c3) as the initial unit, the next unit (c4) can be formed as the fourth unit (e.g., for d4 = 1). Using the fourth unit (c4) as the initial unit, the next unit (c5) can be formed as the third unit (e.g., for d5 = 1). Using the third unit (c5) as the initial unit, the next unit (c6) can be formed as the second unit (e.g., for d6 = 0).

[0103] Figure 10 This is a flowchart illustrating an exemplary method 1000 for programming memory circuitry according to some embodiments. Method 1000 may be performed by one or more components of the circuitry disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 1000 is performed by other entities. In some embodiments, method 1000 includes... Figure 10 The more, fewer, or different operations shown.

[0104] In some embodiments, method 1000 can be executed to convert the original data d m =[d0,…,d N-1](d i ∈{1,0}) Embedded memory unit c m =[c0,…,c N-1 ](c i In the range {1A, 1B, 0A, 0B} (e.g., memory arrays 220, 420, etc.). At operation 1010, in response to d0 being "0", the initial memory cell c0 can be formed as the first memory cell (e.g., ...). Figure 2 Memory cell 0A). In response to d0 being "1", the initial memory cell c0 can be formed into a third memory cell (e.g., Figure 2 (Memory unit 1A). At operation 1020, in response to the current number n being less than or equal to N-1, method 1000 may continue to operation 1030. At operation 1020, in response to n being greater than N-1 (e.g., all original data are embedded), method 1000 may terminate. At operation 1030, based on the nth data (d... n ) and the previous memory unit (c n-1 ), the nth memory unit (c n It can be formed as one of the first, second, third or fourth memory units.

[0105] In response to c n-1 0A and d n c is "0" n This can be formed into the first memory unit (0A). Responding to c n-1 0A and d n c is "1" n It can be formed as a third memory unit (1A). Responding to c n-1 0B and d n c is "0" n It can be formed as a second memory unit (0B). Responding to c n-1 0B and d n c is "1" n It can be formed as a fourth memory unit (1B). Responding to c n-1 For 1A and d n c is "0" n It can be formed as a second memory unit (0B). Responding to c n-1 For 1A and d n c is "1" n It can be formed as a fourth memory unit (1B). Responding to c n-1 For 1B and d n c is "0" n This can be formed into the first memory unit (0A). Responding to c n-1 For 1B and d n c is "1" nIt can be formed into a third memory unit (1A).

[0106] Figure 11 This is a flowchart illustrating an exemplary method 1100 for programming memory circuitry according to some embodiments. Method 1100 may be performed by one or more components of the circuitry disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 1100 is performed by other entities. In some embodiments, method 1100 includes... Figure 11 The more, fewer, or different operations shown.

[0107] In some embodiments, method 1100 can be executed to convert the original data d m =[d0,…,d N-1 ](d i ∈{1,0}) Embedded memory unit c m =[c0,…,c N-1 ](c i In the range {1A, 1B, 0A, 0B} (e.g., memory arrays 220, 420, etc.). At operation 1110, in response to d0 being "0", the initial memory cell c0 can be formed into a second memory cell (e.g., ...). Figure 2 Memory cell 0B). In response to d0 being "1", the initial memory cell c0 can be formed into a fourth memory cell (e.g., Figure 2 (Memory cell 1B). At operation 1120, in response to the current number n being less than or equal to N-1, method 1100 may continue to operation 1130. At operation 1120, in response to n being greater than N-1 (e.g., all original data are embedded), method 1100 may terminate. At operation 1130, based on the nth data (d... n ) and the previous memory unit (c n-1 ), the nth memory unit (c n It can be formed as one of the first, second, third or fourth memory units.

[0108] In response to c n-1 0A and d n c is "0" n This can be formed into the first memory unit (0A). Responding to c n-1 0A and d n c is "1" n It can be formed as a third memory unit (1A). Responding to c n-1 0B and d n c is "0" n It can be formed as a second memory unit (0B). Responding to c n-1 0B and d n c is "1" nIt can be formed as a fourth memory unit (1B). Responding to c n-1 For 1A and d n c is "0" n It can be formed as a second memory unit (0B). Responding to c n-1 For 1A and d n c is "1" n It can be formed as a fourth memory unit (1B). Responding to c n-1 For 1B and d n c is "0" n This can be formed into the first memory unit (0A). Responding to c n-1 For 1B and d n c is "1" n It can be formed into a third memory unit (1A).

[0109] Figure 12 This is a flowchart illustrating an exemplary method 1200 for programming memory circuitry according to some embodiments. Method 1200 may be performed by one or more components of the circuitry disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 1200 is performed by other entities. In some embodiments, method 1200 includes... Figure 12 The more, fewer, or different operations shown.

[0110] At operation 1210, the given original data d with the first initial unit c0 can be used. m Generate c m The first initial unit c0 may be formed as a first memory unit (e.g., first memory unit 0A) or a third memory unit (e.g., third memory unit 1A). In some embodiments, method 1200 may execute method 1000 at operation 1210 to generate c m For example, the initial unit c0 can be formed as a first memory unit (e.g., first memory unit 0A) or a third memory unit (e.g., third memory unit 1A), and then c is generated based on operations 1020 to 1040. m .

[0111] At operation 1220, the BL load L can be calculated. m And it is compared with N / / 2 (as used in this paper, " / / " is used as a down division operator). In response to L m If N is less than or equal to 2, method 1200 can end at operation 1220. (Response to L) m If the value is greater than N / / 2, method 1200 can continue to operation 1230. At operation 1230, the given original data d with the second initial unit c0 can be used. m Generate c mThe second initial unit c0 may be formed as a second memory unit (e.g., second memory unit 1B) or a fourth memory unit (e.g., fourth memory unit 1B). In some embodiments, method 1200 may execute method 1100 at operation 1230 to generate c m For example, the initial unit c0 can be formed as a second memory unit (e.g., second memory unit 0B) or a fourth memory unit (e.g., fourth memory unit 1B), and then c is generated based on operations 1120 to 1140. m .

[0112] In some embodiments, method 1200 is executable at operation 1210 to produce c m For example, the initial unit c0 can be formed as a second memory unit (e.g., second memory unit 0B) or a fourth memory unit (e.g., fourth memory unit 1B), and then c is generated based on operations 1120 to 1140. m Method 1200 can execute method 1000 at operation 1230 to produce c. m For example, the initial unit c0 can be formed as a first memory unit (e.g., first memory unit 0A) or a third memory unit (e.g., third memory unit 1A), and then c is generated based on operations 1020 to 1040. m .

[0113] Figure 13 This is a flowchart illustrating an exemplary method 1300 for programming memory circuitry according to some embodiments. Method 1300 may be performed by one or more components of the circuitry disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 1300 is performed by other entities. In some embodiments, method 1300 includes... Figure 13 The more, fewer, or different operations shown.

[0114] At operation 1310, the original data d 0 d 1 、……、d M-1 Can be converted to v 0 v 1 ... v M-1 In some embodiments, at operation 1310, method 1300 may perform any of methods 1000, 1100, 1200, etc., to convert the original data d 0 d 1 、……、d M-1 Convert to v 0 v 1 ... v M-1 .

[0115] In operation 1320, it can be based on the via array set {v 0 ,v 1 ,…,v M-1} Generates symbolic lines s = [s0, s1, ..., s N This can generate symbol rows, resulting in converted through-hole rows. satisfy in For v m v in i The relevant load can be calculated as follows:

[0116]

[0117] In some embodiments, at operation 1320, the converted via row can be reversed based on the load. For example, in response to Greater than (N+1) / 2, through hole Reversible This allows BL load. It is distributed between [N+1-ΔL(N,M)] / 2 and (N+1) / 2.

[0118] At operation 1330, the converted through-hole row and symbol row. Transferable to form memory cells with sign rows (e.g., such as...) Figure 7B (As shown).

[0119] This will be discussed further below (e.g., regarding...). Figures 14 to 16 In some embodiments, method 1300 may include performing various operations at operation 1320. Figure 14 This is a flowchart illustrating an exemplary method 1400 that can be performed as part of operation 1320 of method 1300 according to some embodiments. In some embodiments, method 1400 can be performed to find the optimal vector for symbol row s. Method 1400 can be performed by one or more components of the circuit disclosed herein (e.g., memory circuitry 100, etc.). In some embodiments, method 1400 is performed by other entities. In some embodiments, method 1400 includes a comparison... Figure 14 The more, fewer, or different operations shown.

[0120] At operation 1410, the initial symbol vector s = [s0, s1, ..., s2] can be generated for the symbol row. N ] T As a simplified example, based on through-hole rows It can generate an initial vector At operation 1420, a vector b representing the number of vias on the bitline can be generated based on the via row and the initial symbol vector. In a simplified example, this can be based on the exemplary via row [v 0 ,v1 ] T and initial vector Generate vector b as Using vector b, we can base it on #argmax i |b i The expression `|→q` finds the exponent `q` of the row. In the simplified example, the exponent `q` can be 1 or 2. At operation 1430, in response to `|b`... q If |b| is less than or equal to ΔL(N,M), method 1400 may terminate and update the symbol row. In some embodiments, method 1400 may continue at operation 1430 to operation 1330 of method 1300. At operation 1430, in response to |b| q If |b| is greater than ΔL(N,M), method 1400 can continue to operation 1440. At operation 1440, the symbol line s can be updated such that |b| is greater than ΔL(N,M). q | Decrease, then continue with operation 1420. Method 1400 continues with operations 1420 to 1440 until |b is found. q | Less than or equal to ΔL(N,M).

[0121] Figure 15 This is a flowchart illustrating an exemplary method 1500 that can be performed as part of operation 1320 of method 1300 according to some embodiments. In some embodiments, method 1500 may be substantially similar to or incorporate features of method 1400. For example, operation 1510 may be performed at operation 1440 to update symbol line s. In some embodiments, method 1500 is performed by other entities. In some embodiments, method 1500 includes more than Figure 15 The more, fewer, or different operations shown.

[0122] At operation 1510, when updating symbol line s, method 1500 may include the following steps: based on b q Invert bits. At operation 1520, method 1500 includes the following steps: determine b q Is it greater than 0? (Response to b) q If the value is greater than 0, method 1500 can continue with operation 1530, where the condition will be met. Invert any bit. In response to b q If the value is less than or equal to 0, method 1500 can continue with operation 1540, where the condition will be met. Any bit inversion. In some embodiments, method 1500 may end at operation 1510, and then operation 1420 of method 1400 may continue.

[0123] Figure 16This is a flowchart illustrating an exemplary method 1600 that can be performed as part of operation 1320 of method 1300 according to some embodiments. In some embodiments, method 1600 may be substantially similar to or incorporate features of method 1500. For example, operation 1610 may be performed in response to operation 1510 to update symbol line s. In some embodiments, method 1600 is performed by other entities. In some embodiments, method 1600 includes more than Figure 16 The more, fewer, or different operations shown.

[0124] In some embodiments, at operation 1620, in response to operation 1510 of method 1500, method 1600 may continue to operation 1610. If variable k is assigned to the initial vector s at operation 1620, variable k may be incremented by 1 for each update operation. At operation 1630, method 1600 includes the step of determining whether variable k is less than a predetermined limit. In response to k being less than the predetermined limit, method 1600 may continue to operation 1420 of method 1400. In response to k being greater than or equal to the predetermined limit, method 1600 may continue to operation 1410 of method 1400. By iterating over variable k, method 1600 can prevent the update operation from getting trapped in a local minimum.

[0125] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a plurality of memory cells. Each memory cell is selected from a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes a first transistor having: a gate coupled to a first word line; a first source / drain coupled to a first interconnect structure carrying a ground voltage; and a second source / drain coupled to the first interconnect structure. The second memory cell includes a second transistor having: a gate coupled to a second word line; a first source / drain coupled to a second interconnect structure serving as a bit line; and a second source / drain coupled to the second interconnect structure. The third memory cell includes a third transistor having: a gate coupled to a third word line; a first source / drain coupled to the first interconnect structure; and a second source / drain coupled to the second interconnect structure. The fourth memory cell includes a fourth transistor having: a gate terminal coupled to a fourth word line; a first source / drain terminal coupled to a second interconnect structure; and a second source / drain terminal coupled to a first interconnect structure.

[0126] In some embodiments, each of these memory units includes a read-only memory unit.

[0127] In some embodiments, the first and second memory cells are operationally corresponding to a first logical state, and the third and fourth memory cells are operationally corresponding to a second logical state.

[0128] In some embodiments, the first to fourth character lines physically extend along a first lateral direction, and the first and second interconnect structures extend along a second lateral direction, which is perpendicular to the first lateral direction.

[0129] In some embodiments, the memory circuit further includes a pair of first via structures, a pair of second via structures, a pair of third via structures, and a pair of fourth via structures. The pair of first via structures connects the first and second source / drain terminals of a first transistor to a first interconnect structure. The pair of second via structures connects the first and second source / drain terminals of a second transistor to a second interconnect structure. The pair of third via structures connects the first and second source / drain terminals of a third transistor to both the first and second interconnect structures. The pair of fourth via structures connects the first and second source / drain terminals of a fourth transistor to both the second and first interconnect structures.

[0130] In some embodiments, the number of these memory cells is equal to N, and the number of these first via structures or the number of these second via structures is equal to or less than N / 2.

[0131] In some embodiments, these memory cells are physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a first memory cell, and the next memory cell among these memory cells is a first or third memory cell.

[0132] In some embodiments, these memory cells are physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is a second memory cell, and the next memory cell among these memory cells is a second or fourth memory cell.

[0133] In some embodiments, these memory cells are physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is the third memory cell, and the next memory cell among these memory cells is the second or fourth memory cell.

[0134] In some embodiments, these memory cells are physically arranged in a lateral direction, wherein the initial memory cell among these memory cells is the fourth memory cell, and the next memory cell among these memory cells is the first or third memory cell.

[0135] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a plurality of memory cells disposed above a plurality of word lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines extending along the second lateral direction. Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first memory cell includes first and second source / drain terminals, both connected to corresponding terminals of the reference lines. The second memory cell includes first and second source / drain terminals, both connected to corresponding terminals of the signal lines. The third memory cell includes first and second source / drain terminals, respectively connected to corresponding terminals of the signal lines and corresponding terminals of the reference lines. The fourth memory cell includes first and second source / drain terminals, respectively connected to corresponding terminals of the reference lines and corresponding terminals of the signal lines.

[0136] In some embodiments, each subset of these memory cells extending along a second lateral direction is physically arranged, wherein the initial memory cell among these memory cells is a first memory cell, and the next memory cell among these memory cells is a first or third memory cell.

[0137] In some embodiments, each subset of these memory cells extending along a second lateral direction is physically arranged, wherein the initial memory cell among these memory cells is a second memory cell, and the next memory cell among these memory cells is a second or fourth memory cell.

[0138] In some embodiments, each subset of these memory cells extending along a second lateral direction is physically arranged, wherein the initial memory cell among these memory cells is the third memory cell, and the next memory cell among these memory cells is the second or fourth memory cell.

[0139] In some embodiments, each subset of these memory cells extending along a second lateral direction is physically arranged, wherein the initial memory cell among these memory cells is a fourth memory cell, and the next memory cell among these memory cells is a first or third memory cell.

[0140] In some embodiments, the memory circuitry further includes a plurality of additional memory cells extending along a second lateral direction, wherein each of these additional memory cells operatively corresponds to a symbol of a corresponding subset of the memory cells arranged along a first lateral direction.

[0141] In some embodiments, the first and second memory cells operably correspond to a first logic state, and the third and fourth memory cells operably correspond to a second logic state.

[0142] In another embodiment of the present disclosure, a method for programming memory circuitry is provided. The method includes the following steps: forming an initial memory cell from a plurality of memory cells into one of a first, second, third, or fourth memory cells, wherein the first and second source / drain terminals of the first memory cell are both connected to a reference line, the first and second source / drain terminals of the second memory cell are both connected to a signal line, the first and second source / drain terminals of the third memory cell are respectively connected to the signal line and the reference line, and the first and second source / drain terminals of the fourth memory cell are respectively connected to the reference line and the signal line; based on the initial memory cell being formed as the first memory cell, forming the next memory cell immediately following this memory cell into a first or third memory cell; based on the initial memory cell being formed as the second memory cell, forming the next memory cell immediately following this memory cell into a second or fourth memory cell; based on the initial memory cell being formed as the third memory cell, forming the next memory cell immediately following this memory cell into a second or fourth memory cell; and based on the initial memory cell being formed as the fourth memory cell, forming the next memory cell immediately following this memory cell into a first or third memory cell.

[0143] In some embodiments, each of these memory units includes a read-only memory unit.

[0144] In some embodiments, these memory cells are arranged in a lateral direction.

[0145] As used herein, the terms “about” and “approximately” generally refer to a given quantity value that can vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity value that varies within, for example, 10-30% of that value (e.g., +10%, ±20%, or ±30% of the value).

[0146] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of the embodiments disclosed herein. Those skilled in the art should understand that they can readily use the embodiments disclosed herein as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A memory circuit, characterized in that, Include: A memory array containing multiple memory cells; Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell; The first memory cell includes a first transistor having: a gate terminal coupled to a first word line; a first source / drain terminal coupled to a first interconnect structure carrying a ground voltage; and a second source / drain terminal coupled to the first interconnect structure. The second memory cell includes a second transistor having: a gate terminal coupled to a second word line; a first source / drain terminal coupled to a second interconnect structure serving as a bit line; and a second source / drain terminal coupled to the second interconnect structure. The third memory cell includes a third transistor having: a gate terminal coupled to a third word line; a first source / drain terminal coupled to the first interconnect structure; and a second source / drain terminal coupled to the second interconnect structure; and The fourth memory cell includes a fourth transistor having: a gate terminal coupled to a fourth word line; a first source / drain terminal coupled to the second interconnect structure; and a second source / drain terminal coupled to the first interconnect structure.

2. The memory circuit as described in claim 1, characterized in that, Each of the plurality of memory units includes a read memory unit.

3. The memory circuit as described in claim 1, characterized in that, The first memory unit and the second memory unit are operationally corresponding to a first logical state, and the third memory unit and the fourth memory unit are operationally corresponding to a second logical state.

4. The memory circuit as described in claim 1, characterized in that, The first character line to the fourth character line physically extends along a first lateral direction, and the first interconnect structure and the second interconnect structure extend along a second lateral direction, which is perpendicular to the first lateral direction.

5. The memory circuit as described in claim 1, characterized in that, Further includes: A pair of first via structures are used to connect the first source / drain terminal and the second source / drain terminal of the first transistor to the first interconnect structure; A pair of second via structures are used to connect the first source / drain terminal and the second source / drain terminal of the second transistor to the second interconnect structure; A pair of third via structures are used to connect the first source / drain terminal and the second source / drain terminal of the third transistor to the first interconnect structure and the second interconnect structure, respectively; and A pair of fourth via structures are used to connect the first source / drain terminal and the second source / drain terminal of the fourth transistor to the second interconnect structure and the first interconnect structure, respectively.

6. The memory circuit as described in claim 5, characterized in that, The number of the plurality of memory cells is equal to N, and the number of the first through-hole structure or the number of the second through-hole structure is equal to or less than N / 2.

7. A memory circuit, characterized in that, Include: A memory array comprising a plurality of memory cells arranged above a plurality of character lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines extending along the second lateral direction. Each memory cell is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell; The first source / drain terminal and the second source / drain terminal of the first memory cell are both connected to a corresponding one of the plurality of reference lines; The first source / drain terminal and the second source / drain terminal of the second memory cell are both connected to a corresponding one of the plurality of signal lines; The first source / drain terminal and the second source / drain terminal of the third memory cell are respectively connected to a corresponding one of the plurality of signal lines and a corresponding one of the plurality of reference lines; and The first source / drain terminal and the second source / drain terminal of the fourth memory cell are respectively connected to a corresponding one of the plurality of reference lines and a corresponding one of the plurality of signal lines.

8. The memory circuit as described in claim 7, characterized in that, The memory circuit further includes a plurality of additional memory cells extending along the second lateral direction, wherein each of the plurality of additional memory cells operatively corresponds to a symbol of a corresponding subset of the plurality of memory cells arranged along the first lateral direction.

9. A method for programming a memory circuit, characterized in that, Includes the following steps: An initial memory cell among a plurality of memory cells is formed into one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell. The first source / drain terminal and the second source / drain terminal of the first memory cell are both connected to a reference line. The first source / drain terminal and the second source / drain terminal of the second memory cell are both connected to a signal line. The first source / drain terminal and the second source / drain terminal of the third memory cell are respectively connected to the signal line and the reference line. The first source / drain terminal and the second source / drain terminal of the fourth memory cell are respectively connected to the reference line and the signal line. Based on the initial memory unit, the first memory unit is formed, and the next memory unit in the plurality of memory units is formed as the first memory unit or the third memory unit; Based on the initial memory cell, the second memory cell is formed, and the next memory cell that follows is formed as the second memory cell or the fourth memory cell; Based on the initial memory unit formed as the third memory unit, the immediately following memory unit is formed as the second memory unit or the fourth memory unit; and Based on the initial memory unit, the fourth memory unit is formed, and the next memory unit that follows is formed as the first memory unit or the third memory unit.

10. The method as described in claim 9, characterized in that, The plurality of memory cells are arranged in a horizontal direction.

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