Method for performing a programming process and related memory device

Abstract

A method of performing a program process on a three-dimensional (3D) NAND memory device is disclosed. The method causes residual electrons trapped in a storage region of a dummy cell in the middle of an unselected string of the 3D NAND memory device during a pre-charge phase to be removed, thereby reducing program disturbance to a selected string adjacent to the unselected string.

Description

Divisional Application Instructions

[0001] This application is a divisional application of Chinese Patent Application No. 201980100813.9, filed on November 14, 2019, entitled "Method for Performing a Programming Process and Related Storage Device". Technical Field

[0002] The present invention relates to a method for performing a programming process, and more particularly to a method for performing a programming process on a three-dimensional (3D) NAND storage device. Background Technology

[0003] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memories allow information to be stored and retained. Examples of non-volatile memories include flash memory (e.g., NAND and NOR flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0004] In some NAND architectures, memory cells have a charging storage region that remains charged to program the cell. An example of a charging storage region is a floating gate. When programming an EEPROM or flash memory device, such as a NAND flash memory device, a programming voltage is typically applied to the control gate (or selected word line), and the bit line is grounded. Electrons from the channel are injected into the charging storage region. As electrons accumulate in the charging storage region, it becomes negatively charged, and the threshold voltage of the memory cell rises, putting the cell into a programmed state.

[0005] The applicant noted that during the pre-charge phase, residual electrons may be trapped in the storage region of virtual cells in unselected strings, causing programming interference to the selected memory cells of selected strings adjacent to the unselected strings. For example, during the boost / programming phase, residual electrons trapped in unselected strings may lower the channel potential corresponding to the selected memory cells of selected strings, thus causing programming interference.

[0006] Therefore, there is a need to provide a method and storage device for reducing program interference. Summary of the Invention

[0007] Therefore, the object of the present invention is to provide a method for reducing program interference and related storage devices.

[0008] This invention discloses a method for performing a programming process on a three-dimensional (3D) NAND memory device. The method includes: during a pre-charge phase of the programming process, applying a first voltage to a plurality of word lines of the 3D NAND memory device, wherein the plurality of word lines are vertically located above a plurality of virtual word lines; during the pre-charge phase, applying a second voltage to a second adjacent word line of the 3D NAND memory device, wherein the second adjacent word line is one of the plurality of word lines and is vertically located above a selected word line among the plurality of word lines; and during a boost phase of the programming process, applying the second voltage to the second adjacent word line and a plurality of first word lines among the plurality of word lines, and applying a third voltage to a first adjacent word line of the 3D NAND memory device, wherein the first adjacent word line is one of the plurality of word lines and not included among the plurality of first word lines, and is vertically located below the second adjacent word line and above the selected word line.

[0009] The present invention also discloses a three-dimensional (3D) NAND memory device, the three-dimensional (3D) NAND memory device comprising: a memory array including a plurality of bit lines, a plurality of word lines and a plurality of strings; a word line driver coupled to the memory array and configured to generate a plurality of voltages applied to the plurality of word lines of the memory array according to a plurality of control signals; and a control circuit configured to generate the plurality of control signals according to a process for performing a programming process, wherein the process includes the steps of the method for performing a programming process on the three-dimensional (3D) NAND memory device as described above.

[0010] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of preferred embodiments illustrated in the various accompanying drawings and figures. Attached Figure Description

[0011] Figure 1 The diagram shows the remaining electrons in the channel of the unselected string adjacent to the selected string.

[0012] Figure 2 It is aimed at Figure 1 Signal diagram of the programming process of strings.

[0013] Figure 3 The illustration shows the movement of residual electrons in the channel of an unselected string adjacent to the selected string, according to an embodiment of the invention.

[0014] Figure 4 It is aimed at Figure 3 Signal diagram of the programming process of strings.

[0015] Figure 5 This is a functional block diagram of a storage device according to an embodiment of the present invention.

[0016] Figure 6 According to an embodiment of the present invention, for Figure 3 The flowchart shows the process of programming strings. Detailed Implementation

[0017] Figure 1 The diagram shows the remaining electrons in the channel of an unselected string 12 adjacent to the selected string 10. The memory array may include the selected string 10 and the unselected string 12. The memory array may be a three-dimensional NAND flash memory array comprising multiple bit lines, multiple word lines, and multiple strings, wherein each of the strings extends vertically and includes multiple memory cells formed in multiple horizontal layers.

[0018] Strings 10 and 12 are structurally identical; for example, each of strings 10 and 12 may include a top selection unit, multiple top virtual units, multiple top storage units, multiple intermediate virtual units, multiple bottom storage units, multiple bottom virtual units, and a bottom selection unit, wherein the units included in the string are connected in series. The multiple top virtual units include i units, the multiple top storage units include j units, the multiple intermediate virtual units include k units, the multiple bottom storage units include m units, and the multiple bottom virtual units include n units, where i, j, k, m, and n are integers greater than 1.

[0019] Word line WL_TSG is connected to the gate of the top selected cell of strings 10 and 12. Multiple word lines WL_TD_1 to WL_TD_i are connected to multiple gates of multiple top virtual cells. Multiple word lines WL_1 to WL_j are connected to multiple gates of multiple top memory cells of strings 10 and 12. One of the multiple word lines WL_1 to WL_j is the selected word line WL_x, which is connected to the selected memory cell of the selected string 10 and the memory cell horizontally adjacent to the selected memory cell. Another of the multiple word lines WL_1 to WL_j is a first adjacent word line WL_x+1 connected to a first adjacent memory cell, which is vertically adjacent to the selected memory cell of the selected string 10. A third of the multiple word lines WL_1 to WL_j is a second adjacent word line WL_x+2 connected to a second adjacent memory cell, which is vertically adjacent to the first adjacent memory cell of the selected string 10.

[0020] Multiple word lines WL_MD_1 to WL_MD_k are connected to multiple gates of multiple intermediate dummy cells in strings 10 and 12. Multiple word lines WL_B_1 to WL_B_m are connected to multiple gates of multiple bottom memory cells in strings 10 and 12. Multiple word lines WL_BD_1 to WL_BD_n are connected to multiple gates of multiple bottom dummy cells in strings 10 and 12. Word line WL_BSG is connected to the gate of the bottom select cell in strings 10 and 12.

[0021] The drain of the top selection cell is connected to the bit line (BL), and during the programming process, the bit line of the selected string 10 is always applied with a zero (ground) voltage, while during the pre-charge phase of the programming process, the unselected string 12 is applied with a system voltage pulse Vcc. During the pre-charge phase of the programming process, a certain amount of residual electrons may be trapped in the memory region of multiple intermediate virtual cells corresponding to multiple word lines WL_MD_1 to WL_MD_k of the unselected string 12, thereby causing programming interference to the adjacent selected string 10.

[0022] Figure 2 It is aimed at Figure 1 The signal diagram illustrates the programming process for strings 10 and 12. During the precharge phase, the voltage of the unselected bit line of string 12 increases from zero volts at time T0 to Vcc at time T1. The voltage of word line WL_TSG increases from zero volts at time T0 to Vtsg at time T1, and decreases from Vtsg at time T3 to zero volts at time T4. During the precharge phase, word lines WL_BSG, WL_BD_1 to WL_BD_n, WL_B_1 to WL_B_m, WL_MD_1 to WL_MD_k, WL_1 to WL_j, and WL_TD_1 to WL_TD_i are at zero volts. One of the multiple word lines WL_1 to WL_j is the selected word line WL_x.

[0023] During time T1 to time T2, a certain number of residual electrons may be trapped in the memory regions of multiple intermediate virtual cells corresponding to the multiple word lines WL_MD_1 to WL_MD_k of the unselected string 12, thereby causing programming interference to the adjacent selected string 10. For example, during the boost phase of the unselected string 12 and the programming phase of the selected string 10, particularly from time T9 to time T10, voltage Vpass is applied to the word lines WL_B_1 to WL_B_m and WL_1 to WL_j corresponding to the memory cells to increase the channel potential of the memory cells, and voltage Vbias is applied to the word lines WL_BD_1 to WL_BD_n, WL_MD_1 to WL_MD_k and WL_TD_1 to WL_TD_i corresponding to the virtual cells to increase the channel potential of the virtual cells. During time T10 to time T11, programming voltage Vpgm is applied to the selected word line WL_x. However, residual electrons at the intermediate virtual cells of the unselected string 12 can induce a transverse field on the adjacent selected string 10, causing programming interference. For example, due to the transverse field induced by the residual electrons, the channel potential corresponding to the selected memory cell of the selected string 10 decreases.

[0024] To reduce programming interference, refer to Figure 3 , Figure 3 The illustration shows the movement of residual electrons in the channel of an unselected string 12, adjacent to a selected string 10, according to an embodiment of the invention. To reduce residual electrons and avoid programming interference, during the precharge phase, a voltage Von is applied to all word lines WL_T_1 to WL_T_j corresponding to all of the plurality of top memory cells to partially open the channel of the unselected string 12, allowing residual electrons to move along the partially open channel from intermediate virtual cells to the plurality of top memory cells. Furthermore, during the precharge phase, zero volts are applied to word lines WL_T_1 to WL_T_x+1 and WL_T_x+3 to WL_T_j to partially close the channel of the unselected string 12. Finally, during the boost / programming phase, a voltage Vcut (e.g., Von) is applied to word line WL_T_x+1 to weakly cut off the top memory cell corresponding to word line WL_T_x+1. This partially cuts off the channel of the unselected string 12, preventing residual electrons from moving back to the top memory cell below the top memory cell corresponding to word line WL_T_x+1. As a result, residual electrons can be removed from multiple intermediate virtual cells to avoid programming interference.

[0025] Figure 4 yes Figure 3The signal diagram for the programming process of strings 10 and 12 is shown below. Specifically, the precharge phase begins at time T0 and ends at time T7. The voltage of the unselected string 12 bit line increases from zero volts at time T0 to voltage Vcc at time T1. Voltage Vcc is applied to the unselected string 12 bit line from time T1 to time T6, and the voltage of the unselected string 12 bit line decreases from voltage Vcc at time T6 to zero volts at time T7. During the programming process, the selected string 10 bit line is always applied with zero volts. The voltage of word line WL_TSG increases from zero volts at time T0 to voltage Vtsg at time T1. Voltage Vtsg is applied to word line WL_TSG from time T1 to time T5, and the voltage of word line WL_TSG decreases from voltage Vtsg at time T5 to zero volts at time T6 just before the end of the precharge phase. During the pre-charge phase of the programming process, the voltages on word lines WL_B_1 to WL_B_m, WL_TD_1 to WL_TD_i, WL_MD_1 to WL_MD_k, and WL_BD_1 to WL_BD_n are always applied to zero volts.

[0026] From time T1 to time T2, voltage Von is applied to word lines WL_T_1 to WL_T_j to partially open the channels at multiple top memory cells. Therefore, residual electrons trapped in the memory regions of multiple intermediate virtual cells of the unselected string 12 are attracted by the voltage potential provided by voltage Von and can move towards the top memory cells corresponding to word lines WL_T_1 to WL_T_j. From time T2 to time T3, the voltage of word lines WL_T_1 to WL_T_j decreases from voltage Von to zero volts to close the channels of the unselected string 12 at the multiple top memory cells corresponding to word lines WL_T_1 to WL_T_j. Note that the circuit area of ​​the control circuit configured to control the memory array depends on the complexity of the programming process; for example, the control circuit requires a larger area to perform a more complex programming process. By applying voltage Von to all word lines WL_T_1 to WL_T_j corresponding to all multiple top memory cells during the precharge phase, and... Figure 2 Compared to the complexity of the programming process in [the other context], the complexity of this programming process is acceptable.

[0027] The voltage of word line WL_T_x+2 corresponding to the second adjacent memory cell increases from zero volts at time T4 to voltage Vpass at time T5, partially turning on the channel at the second adjacent memory cell of the unselected string 12. Therefore, residual electrons at the top memory cells corresponding to word lines WL_T_1 to WL_T_x+1 can move to the second adjacent memory cell corresponding to word line WL_T_x+2 when attracted by the voltage potential provided by voltage Vpass. Note that voltage Vpass is applied to word line WL_T_x+2 from time T5 during the pre-charge phase to time T11 during the boost phase; from another perspective, the second adjacent memory cell corresponding to word line WL_T_x+2 is turned on before the remainder of multiple word lines WL_T_1 to WL_T_x+1 and WL_T_x+3 to WL_T_j, to boost the channel potential corresponding to word line WL_T_x+2 before entering the boost / programming phase.

[0028] Notice, Figure 2 The pre-charging phase begins at time T0 and ends at time T4, while Figure 4 The pre-charge phase begins at time T0 and ends at time T7. The pre-charge phase of the present invention is extended to allow residual electrons to discharge from the bit line during the pre-charge phase.

[0029] exist Figure 4 In the process, the pre-charging phase ends at time T7, while the boost phase of the unselected string 12 and the programming phase of the selected string 10 begin at time T7 and end at time T12.

[0030] In detail, the voltage of word line WL_T_x+1 corresponding to the first adjacent memory cell increases from zero volts at time T7 to voltage Vcut at time T8, voltage Vcut is applied to word line WL_T_x+1 from time T8 to T11, and the voltage of word line WL_T_x+1 decreases from voltage Vcut at time T11 to zero volts at time T12. The voltages of word lines WL_T_1 to WL_T_x-1, WL_x+3 to WL_T_j, and WL_B_1 to WL_B_m increase from zero volts at time T7 to voltage Vpass at time T8. Voltage Vpass is applied to word lines WL_T_1 to WL_T_x-1, WL_x+3 to WL_T_j, and WL_B_1 to WL_B_m from time T8 to time T11. The voltages of word lines WL_T_1 to WL_T_x-1, WL_x+3 to WL_T_j, and WL_B_1 to WL_B_m decrease from voltage Vpass at time T11 to zero volts at time T12. The voltages of word lines WL_TD_1 to WL_TD_i, WL_MD_1 to WL_MD_k, and WL_BD_1 to WL_BD_n increase from zero volts at time T7 to voltage Vbias at time T8. Voltage Vbias is applied to word lines WL_TD_1 to WL_TD_i, WL_MD_1 to WL_MD_k, and WL_BD_1 to WL_BD_n from time T8 to time T11. The voltages of word lines WL_TD_1 to WL_TD_i, WL_MD_1 to WL_MD_k, and WL_BD_1 to WL_BD_n decrease from voltage Vbias at time T11 to zero volts at time T12.

[0031] During the boost phase of the unselected string 12, a voltage Vpass (T5 to T11) is applied to the word line WL_T_x+2 corresponding to the second adjacent memory cell, a voltage Vcut (T8 to T11) is applied to the word line WL_T_x+1 corresponding to the first adjacent memory cell, and a voltage Vpass (T8 to T9) and a voltage Vpgm (T10 to T11) are applied to the word line WL_T_x corresponding to the selected memory cell, wherein the voltage Vcut is less than the voltages Vpass and Vpgm. Therefore, the first adjacent memory cell is weakly cut off by the voltage Vcut, thereby cutting off the channel of the unselected string 12, and isolating the memory cell above the first adjacent memory cell from the memory cell below the first adjacent memory cell. As a result, residual electrons can discharge from the bit line of the selected string 12 through the first adjacent memory cell, wherein the first adjacent memory cell is weakly cut off to prevent residual electrons from being attracted by the voltage potential provided by the voltages Vpass or Vpgm.

[0032] During the boost phase (T8 to T11) of the unselected string 12, the channel potential of the unselected string 12 is increased by applying voltage Vpass to word lines WL_T_1 to WL_T_x-1, WL_T_x+3 to WL_T_j, WL_B_1 to WL_B_m and voltage Vbias to the word line corresponding to the virtual cell. This prevents the memory cell of the unselected string 12 corresponding to the selected word line WL_T_x from being unintentionally programmed by voltage Vpgm.

[0033] During the programming phase of the selected string 10, the channel potential corresponding to the selected memory cell is increased by applying a voltage Vpass from time T8 to time T9. A voltage Vpgm is applied to the selected word line WL_x corresponding to the selected memory cell of the selected string 10 to perform the programming operation from time T10 to time T11.

[0034] Finally, the boost and programming phases will end at time T11, and when the boost and programming phases end, all bit lines and all word lines will decrease to zero volts at time T12.

[0035] As a result, residual electrons in unselected string 12 can be removed during the pre-charge phase, reducing programming interference to adjacent selected string 10 during the boost / programming phase. Furthermore, by applying voltage Von to all word lines WL_T_1 to WL_T_j corresponding to all the multiple top memory cells to turn them on, and... Figure 2 Compared to the complexity of the programming process in [the other context], the complexity of this programming process is acceptable.

[0036] Figure 5 This is a functional block diagram of a storage device 5 according to an embodiment of the present invention. The storage device 5 includes a storage array 50, a word line driver 52, and a control circuit 54. The storage device 5 may be a three-dimensional NAND flash memory device. The storage array 50 includes multiple bit lines (BLs), multiple word lines, and multiple strings (e.g., ...). Figure 3 (Strings 10 and 12 in the array). Each string includes multiple memory cells and multiple virtual cells, wherein the multiple memory cells and multiple virtual cells are connected in series and extend vertically above a substrate (not shown). Control circuitry 54 is configured to generate multiple control signals to word line driver 52 to perform a programming process. Word line driver 52 is coupled to control circuitry 54 and memory array 50 and is configured to generate multiple voltages applied to multiple word lines of memory array 50 according to the multiple control signals generated by control circuitry 54.

[0037] Figure 6 According to an embodiment of the present invention, for Figure 3The flowchart for process 6, which involves programming the string, is shown below. Process 6 can be executed by control circuit 54 and includes the following steps.

[0038] Step 61: During the pre-charge phase of the programming process, a first voltage is applied to multiple word lines, wherein the multiple word lines are vertically positioned above multiple virtual word lines.

[0039] Step 62: During the pre-charge phase, a second voltage is applied to a second adjacent word line, wherein the second adjacent word line is one of a plurality of word lines and is located vertically above the selected word line among the plurality of word lines.

[0040] Step 63: During the boost phase of the programming process, a second voltage is applied to the second adjacent word line and the plurality of first word lines among the plurality of word lines, and a third voltage is applied to the first adjacent word line, wherein the first adjacent word line is one of the plurality of word lines but not included in the plurality of first word lines, and is located vertically below the second adjacent word line and above the selected word line.

[0041] In step 61, during the pre-charge phase of the programming process, control circuit 54 is configured to apply a first voltage (e.g., Von) to multiple word lines (e.g., WL_T_1 to WL_T_j), wherein the multiple word lines (e.g., WL_T_1 to WL_T_1) are vertically positioned above multiple virtual word lines (e.g., WL_MD_1 to WL_MD_k). Therefore, residual electrons captured in the memory regions of the multiple intermediate virtual cells can move upwards to the top memory cells corresponding to word lines WL_T_1 to WL_T_j.

[0042] In step 62, during the pre-charge phase, the control circuit 54 is configured to apply a second voltage (e.g., Vpass) to a second adjacent word line (e.g., WL_T_x+2), wherein the second adjacent word line (e.g., WL_T_x+2) is one of a plurality of word lines (e.g., WL_T_1 to WL_T_j) and is located vertically above the selected word line (e.g., WL_T_x) among the plurality of word lines.

[0043] In step 63, during the boost phase of the programming process, control circuit 54 is configured to apply a second voltage (e.g., Vpass) to the second adjacent word line (e.g., WL_T_x+2) and multiple first word lines, and to apply a third voltage (e.g., Vcut) to the first adjacent word line (e.g., WL_T_x+1), wherein the first adjacent word line (e.g., WL_T_x+1) is one of the multiple word lines but not included in the multiple first word lines, and is vertically located below the second adjacent word line (e.g., WL_T_x+2) and above the selected word line (e.g., WL_T_x). Therefore, since the third voltage Vcut is less than the second voltage Vpass, the channel of the unselected string 12 is partially cut off to prevent residual electrons from moving back to the top memory cell below the top memory cell corresponding to word line WL_T_x+1. As a result, residual electrons can be removed from the unselected string 12 to reduce programming interference to the adjacent selected string 10.

[0044] In summary, the present invention provides a method for a programming process to remove residual electrons captured in the storage region of intermediate virtual memory cells of an unselected string during the precharge phase, thereby reducing programming interference to selected strings adjacent to the unselected strings. Furthermore, this is achieved by applying a voltage Von to all word lines WL_T_1 to WL_T_j corresponding to all the plurality of top memory cells during the precharge phase, and... Figure 2 Compared to the complexity of the programming process in [the other context], the complexity of this programming process is acceptable.

[0045] Those skilled in the art will readily observe that various modifications and alterations can be made to the devices and methods while maintaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the scope of the appended claims.

Claims

1. A method for programming a three-dimensional (3D) NAND memory device, the 3D NAND memory device comprising a plurality of memory strings, each of the memory strings comprising a plurality of top memory cells, a plurality of bottom memory cells, and a plurality of virtual memory cells located between the plurality of top memory cells and the plurality of bottom memory cells, the method comprising: During the first time period of the pre-charge phase, a first voltage is applied to a plurality of first word lines, which are located between a selected word line and a plurality of virtual word lines. The virtual word lines are coupled one-to-one with a plurality of virtual memory cells, and the selected word line is coupled with a selected memory cell among the plurality of top memory cells. During the second time period of the pre-charging phase and the boost phase following the pre-charging phase, a second voltage is applied to a second adjacent word line, wherein the second adjacent word line is located above the selected word line.

2. The method according to claim 1, further comprising: During the boost phase, a third voltage is applied to a first adjacent word line, wherein the first adjacent word line is located between the second adjacent word line and the selected word line.

3. The method according to claim 2, wherein, The first adjacent word line is the word line closest to the selected word line, and the second voltage is greater than the third voltage.

4. The method according to claim 1, further comprising: During the second time period of the pre-charging phase, a zero-volt voltage is applied to the plurality of first word lines.

5. The method according to claim 2, further comprising: During a first time period of the pre-charging phase, the first voltage is applied to the second adjacent word line, the first voltage being equal to the third voltage.

6. The method according to claim 1, wherein the 3D NAND memory device further comprises a plurality of bit lines coupled to the plurality of memory strings, the plurality of top memory cells being located between the plurality of bit lines and the plurality of virtual memory cells, the method further comprising: During the boost phase, the third voltage is provided to the unselected word lines, wherein the unselected word lines are located between the second adjacent word lines and the plurality of bit lines.

7. The method according to claim 6, wherein, The plurality of bit lines includes a first bit line coupled to a selected memory string among the plurality of memory strings and a second bit line coupled to an unselected memory string among the plurality of memory strings. The method further includes: During the first and second time periods of the pre-charging phase, a fourth voltage, greater than zero volts, is provided to the second bit line.

8. The method of claim 7, wherein each of the memory strings further comprises a top select transistor located between the plurality of top memory cells and the plurality of bit lines, the method further comprising: During the first time period and part of the second time period of the pre-charge phase, a fifth voltage is provided to the top select word line coupled to the top select transistor.

9. The method according to claim 8, wherein, The fifth voltage drops earlier than the fourth voltage.

10. The method according to claim 1, further comprising: During the first time period of the pre-charging phase, a zero-volt voltage is provided to the multiple word lines coupled to the plurality of bottom memory cells.

11. A three-dimensional (3D) NAND storage device, comprising: A storage array comprising multiple storage strings, each of the storage strings comprising multiple top storage units, multiple bottom storage units, and multiple virtual storage units located between the multiple top storage units and the multiple bottom storage units; A word line driver, coupled to the memory array, is configured as follows: During the first time period of the pre-charge phase, a first voltage is applied to a plurality of first word lines, which are located between a selected word line and a plurality of virtual word lines. The virtual word lines are coupled one-to-one with a plurality of virtual memory cells, and the selected word line is coupled with a selected memory cell among the plurality of top memory cells. During the second time period of the pre-charging phase and the boost phase following the pre-charging phase, a second voltage is applied to a second adjacent word line, wherein the second adjacent word line is located above the selected word line.

12. The 3D NAND storage device according to claim 11, wherein, The word line driver is also configured to: During the boost phase, a third voltage is applied to a first adjacent word line, wherein the first adjacent word line is located between the second adjacent word line and the selected word line.

13. The 3D NAND storage device according to claim 12, wherein, The first adjacent word line is the word line closest to the selected word line, and the second voltage is greater than the third voltage.

14. The 3D NAND memory device of claim 11, wherein the word line driver is further configured to: During the second time period of the pre-charging phase, a zero-volt voltage is applied to the plurality of first word lines.

15. The 3D NAND memory device of claim 12, wherein the word line driver is further configured to: During a first time period of the pre-charging phase, the first voltage is applied to the second adjacent word line, the first voltage being equal to the third voltage.

16. The 3D NAND memory device of claim 11, further comprising a plurality of bit lines coupled to the plurality of memory strings, the plurality of top memory cells located between the plurality of bit lines and the plurality of virtual memory cells, and the word line driver further configured to: During the boost phase, the third voltage is provided to the unselected word lines, wherein, The unselected word line is located between the second adjacent word line and the plurality of bit lines.

17. The 3D NAND storage device according to claim 16, wherein, The plurality of bit lines includes a first bit line coupled to a selected memory string among the plurality of memory strings and a second bit line coupled to an unselected memory string among the plurality of memory strings, and the word line driver is further configured to: During the first and second time periods of the pre-charging phase, a fourth voltage, greater than zero volts, is provided to the second bit line.

18. The 3D NAND memory device of claim 17, wherein each of the memory strings further comprises a top select transistor located between the plurality of top memory cells and the plurality of bit lines, and the word line driver is further configured to: During the first time period and part of the second time period of the pre-charge phase, a fifth voltage is provided to the top select word line coupled to the top select transistor.

19. The 3D NAND memory device according to claim 18, wherein, The fifth voltage drops earlier than the fourth voltage.

20. The 3D NAND memory device of claim 11, wherein the word line driver is further configured to: During the first time period of the pre-charging phase, a zero-volt voltage is provided to the multiple word lines coupled to the plurality of bottom memory cells.

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